Module Definition
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Module Instance : tb.dut.u_reg_core.u_reg_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.44 100.00 97.78 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.97 97.14 98.75 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.69 100.00 94.75 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00
u_rsp_intg_gen 83.33 66.67 100.00



Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_reg_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.44 100.00 97.78 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.97 97.14 98.75 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00
u_rsp_intg_gen 83.33 66.67 100.00

Line Coverage for Module : tlul_adapter_reg
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS14166100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00

76 77 1/1 assign a_ack = tl_i.a_valid & tl_o.a_ready; Tests: T1 T2 T3  78 1/1 assign d_ack = tl_o.d_valid & tl_i.d_ready; Tests: T1 T2 T3  79 // Request signal 80 1/1 assign wr_req = a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)); Tests: T1 T2 T3  81 1/1 assign rd_req = a_ack & (tl_i.a_opcode == Get); Tests: T1 T2 T3  82 83 1/1 assign we_o = wr_req & ~err_internal; Tests: T1 T2 T3  84 1/1 assign re_o = rd_req & ~err_internal; Tests: T1 T2 T3  85 1/1 assign wdata_o = tl_i.a_data; Tests: T1 T2 T3  86 1/1 assign be_o = tl_i.a_mask; Tests: T1 T2 T3  87 88 if (RegAw <= 2) begin : gen_only_one_reg 89 assign addr_o = '0; 90 end else begin : gen_more_regs 91 1/1 assign addr_o = {tl_i.a_address[RegAw-1:2], 2'b00}; // generate always word-align Tests: T1 T2 T3  92 end 93 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 2/2 if (!rst_ni) outstanding_q <= 1'b0; Tests: T1 T2 T3  | T1 T2 T3  96 2/2 else if (a_ack) outstanding_q <= 1'b1; Tests: T1 T2 T3  | T1 T2 T3  97 2/2 else if (d_ack) outstanding_q <= 1'b0; Tests: T1 T2 T3  | T1 T2 T3  MISSING_ELSE 98 end 99 100 always_ff @(posedge clk_i or negedge rst_ni) begin 101 1/1 if (!rst_ni) begin Tests: T1 T2 T3  102 1/1 reqid_q <= '0; Tests: T1 T2 T3  103 1/1 reqsz_q <= '0; Tests: T1 T2 T3  104 1/1 rspop_q <= AccessAck; Tests: T1 T2 T3  105 1/1 end else if (a_ack) begin Tests: T1 T2 T3  106 1/1 reqid_q <= tl_i.a_source; Tests: T1 T2 T3  107 1/1 reqsz_q <= tl_i.a_size; Tests: T1 T2 T3  108 // Return AccessAckData regardless of error 109 1/1 rspop_q <= (rd_req) ? AccessAckData : AccessAck ; Tests: T1 T2 T3  110 end MISSING_ELSE 111 end 112 113 if (AccessLatency == 1) begin : gen_access_latency1 114 logic wr_req_q, rd_req_q; 115 always_ff @(posedge clk_i or negedge rst_ni) begin 116 if (!rst_ni) begin 117 rdata_q <= '0; 118 error_q <= 1'b0; 119 wr_req_q <= 1'b0; 120 rd_req_q <= 1'b0; 121 end else begin 122 rd_req_q <= rd_req; 123 wr_req_q <= wr_req; 124 // Addressing phase 125 if (a_ack) begin 126 error_q <= err_internal; 127 // Response phase 128 end else begin 129 error_q <= error; 130 rdata_q <= rdata; 131 end 132 end 133 end 134 assign rdata = (error_i || error_q || wr_req_q) ? '1 : 135 (rd_req_q) ? rdata_i : 136 rdata_q; // backpressure case 137 assign error = (rd_req_q || wr_req_q) ? (error_q || error_i) : 138 error_q; // backpressure case 139 end else begin : gen_access_latency0 140 always_ff @(posedge clk_i or negedge rst_ni) begin 141 1/1 if (!rst_ni) begin Tests: T1 T2 T3  142 1/1 rdata_q <= '0; Tests: T1 T2 T3  143 1/1 error_q <= 1'b0; Tests: T1 T2 T3  144 1/1 end else if (a_ack) begin Tests: T1 T2 T3  145 1/1 rdata_q <= (error_i || err_internal || wr_req) ? '1 : rdata_i; Tests: T1 T2 T3  146 1/1 error_q <= error_i || err_internal; Tests: T1 T2 T3  147 end MISSING_ELSE 148 end 149 1/1 assign rdata = rdata_q; Tests: T1 T2 T3  150 1/1 assign error = error_q; Tests: T1 T2 T3  151 end 152 153 tlul_pkg::tl_d2h_t tl_o_pre; 154 1/1 assign tl_o_pre = '{ Tests: T1 T2 T3  155 // busy is selected based on address 156 // thus if there is no valid transaction, we should ignore busy 157 a_ready: ~(outstanding_q | tl_i.a_valid & busy_i), 158 d_valid: outstanding_q, 159 d_opcode: rspop_q, 160 d_param: '0, 161 d_size: reqsz_q, 162 d_source: reqid_q, 163 d_sink: '0, 164 d_data: rdata, 165 d_user: '0, 166 d_error: error 167 }; 168 169 // outgoing integrity generation 170 tlul_rsp_intg_gen #( 171 .EnableRspIntgGen(EnableRspIntgGen), 172 .EnableDataIntgGen(EnableDataIntgGen) 173 ) u_rsp_intg_gen ( 174 .tl_i(tl_o_pre), 175 .tl_o(tl_o) 176 ); 177 178 if (CmdIntgCheck) begin : gen_cmd_intg_check 179 logic intg_error_q; 180 tlul_cmd_intg_chk u_cmd_intg_chk ( 181 .tl_i(tl_i), 182 .err_o(intg_error) 183 ); 184 // permanently latch integrity error until reset 185 always_ff @(posedge clk_i or negedge rst_ni) begin 186 if (!rst_ni) begin 187 intg_error_q <= 1'b0; 188 end else if (intg_error) begin 189 intg_error_q <= 1'b1; 190 end 191 end 192 assign intg_error_o = intg_error_q; 193 end else begin : gen_no_cmd_intg_check 194 assign intg_error = 1'b0; 195 assign intg_error_o = 1'b0; 196 end 197 198 //////////////////// 199 // Error Handling // 200 //////////////////// 201 202 // An instruction type transaction is only valid if en_ifetch is enabled 203 // If the instruction type is completely invalid, also considered an instruction error 204 1/1 assign instr_error = prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type) | Tests: T1 T2 T3  205 (prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) & 206 prim_mubi_pkg::mubi4_test_false_loose(en_ifetch_i)); 207 208 1/1 assign err_internal = addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error; Tests: T1 T2 T3  209 210 // Don't allow unsupported values. 211 1/1 assign malformed_meta_err = tl_a_user_chk(tl_i.a_user); Tests: T1 T2 T3  212 213 // addr_align_err 214 // Raised if addr isn't aligned with the size 215 // Read size error is checked in tlul_assert.sv 216 // Here is it added due to the limitation of register interface. 217 always_comb begin 218 1/1 if (wr_req) begin Tests: T1 T2 T3  219 // Only word-align is accepted based on comportability spec 220 1/1 addr_align_err = |tl_i.a_address[1:0]; Tests: T1 T2 T3  221 end else begin 222 // No request 223 1/1 addr_align_err = 1'b0; Tests: T1 T2 T3 

Cond Coverage for Module : tlul_adapter_reg
TotalCoveredPercent
Conditions464495.65
Logical464495.65
Non-Logical00
Event00

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T15,T16
11CoveredT1,T2,T3

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T15,T16
11CoveredT1,T2,T3

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       145
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       145
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT14,T15,T16
100CoveredT14,T15,T16

 LINE       146
 EXPRESSION (error_i || err_internal)
             ---1---    ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T15,T16
10CoveredT14,T15,T16

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Unreachable
00010Not Covered
00100CoveredT1,T2,T3
01000Not Covered
10000CoveredT14,T15,T16

Branch Coverage for Module : tlul_adapter_reg
Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 141 4 4 100.00


95 if (!rst_ni) outstanding_q <= 1'b0; -1- ==> 96 else if (a_ack) outstanding_q <= 1'b1; -2- ==> 97 else if (d_ack) outstanding_q <= 1'b0; -3- ==> MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


101 if (!rst_ni) begin -1- 102 reqid_q <= '0; ==> 103 reqsz_q <= '0; 104 rspop_q <= AccessAck; 105 end else if (a_ack) begin -2- 106 reqid_q <= tl_i.a_source; 107 reqsz_q <= tl_i.a_size; 108 // Return AccessAckData regardless of error 109 rspop_q <= (rd_req) ? AccessAckData : AccessAck ; -3- ==> ==> 110 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T2,T3
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


218 if (wr_req) begin -1- 219 // Only word-align is accepted based on comportability spec 220 addr_align_err = |tl_i.a_address[1:0]; ==> 221 end else begin 222 // No request 223 addr_align_err = 1'b0; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


141 if (!rst_ni) begin -1- 142 rdata_q <= '0; ==> 143 error_q <= 1'b0; 144 end else if (a_ack) begin -2- 145 rdata_q <= (error_i || err_internal || wr_req) ? '1 : rdata_i; -3- ==> ==> 146 error_q <= error_i || err_internal; 147 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T2,T3
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AllowedLatency_A 2582 2582 0 0
MatchedWidthAssert 2582 2582 0 0


AllowedLatency_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2582 2582 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T11 2 2 0 0
T12 2 2 0 0
T13 2 2 0 0

MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 2582 2582 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T11 2 2 0 0
T12 2 2 0 0
T13 2 2 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_reg_if
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS14166100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00

76 77 1/1 assign a_ack = tl_i.a_valid & tl_o.a_ready; Tests: T1 T2 T3  78 1/1 assign d_ack = tl_o.d_valid & tl_i.d_ready; Tests: T1 T2 T3  79 // Request signal 80 1/1 assign wr_req = a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)); Tests: T1 T2 T3  81 1/1 assign rd_req = a_ack & (tl_i.a_opcode == Get); Tests: T1 T2 T3  82 83 1/1 assign we_o = wr_req & ~err_internal; Tests: T1 T2 T3  84 1/1 assign re_o = rd_req & ~err_internal; Tests: T1 T2 T3  85 1/1 assign wdata_o = tl_i.a_data; Tests: T1 T2 T3  86 1/1 assign be_o = tl_i.a_mask; Tests: T1 T2 T3  87 88 if (RegAw <= 2) begin : gen_only_one_reg 89 assign addr_o = '0; 90 end else begin : gen_more_regs 91 1/1 assign addr_o = {tl_i.a_address[RegAw-1:2], 2'b00}; // generate always word-align Tests: T1 T2 T3  92 end 93 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 2/2 if (!rst_ni) outstanding_q <= 1'b0; Tests: T1 T2 T3  | T1 T2 T3  96 2/2 else if (a_ack) outstanding_q <= 1'b1; Tests: T1 T2 T3  | T1 T2 T3  97 2/2 else if (d_ack) outstanding_q <= 1'b0; Tests: T1 T2 T3  | T1 T2 T3  MISSING_ELSE 98 end 99 100 always_ff @(posedge clk_i or negedge rst_ni) begin 101 1/1 if (!rst_ni) begin Tests: T1 T2 T3  102 1/1 reqid_q <= '0; Tests: T1 T2 T3  103 1/1 reqsz_q <= '0; Tests: T1 T2 T3  104 1/1 rspop_q <= AccessAck; Tests: T1 T2 T3  105 1/1 end else if (a_ack) begin Tests: T1 T2 T3  106 1/1 reqid_q <= tl_i.a_source; Tests: T1 T2 T3  107 1/1 reqsz_q <= tl_i.a_size; Tests: T1 T2 T3  108 // Return AccessAckData regardless of error 109 1/1 rspop_q <= (rd_req) ? AccessAckData : AccessAck ; Tests: T1 T2 T3  110 end MISSING_ELSE 111 end 112 113 if (AccessLatency == 1) begin : gen_access_latency1 114 logic wr_req_q, rd_req_q; 115 always_ff @(posedge clk_i or negedge rst_ni) begin 116 if (!rst_ni) begin 117 rdata_q <= '0; 118 error_q <= 1'b0; 119 wr_req_q <= 1'b0; 120 rd_req_q <= 1'b0; 121 end else begin 122 rd_req_q <= rd_req; 123 wr_req_q <= wr_req; 124 // Addressing phase 125 if (a_ack) begin 126 error_q <= err_internal; 127 // Response phase 128 end else begin 129 error_q <= error; 130 rdata_q <= rdata; 131 end 132 end 133 end 134 assign rdata = (error_i || error_q || wr_req_q) ? '1 : 135 (rd_req_q) ? rdata_i : 136 rdata_q; // backpressure case 137 assign error = (rd_req_q || wr_req_q) ? (error_q || error_i) : 138 error_q; // backpressure case 139 end else begin : gen_access_latency0 140 always_ff @(posedge clk_i or negedge rst_ni) begin 141 1/1 if (!rst_ni) begin Tests: T1 T2 T3  142 1/1 rdata_q <= '0; Tests: T1 T2 T3  143 1/1 error_q <= 1'b0; Tests: T1 T2 T3  144 1/1 end else if (a_ack) begin Tests: T1 T2 T3  145 1/1 rdata_q <= (error_i || err_internal || wr_req) ? '1 : rdata_i; Tests: T1 T2 T3  146 1/1 error_q <= error_i || err_internal; Tests: T1 T2 T3  147 end MISSING_ELSE 148 end 149 1/1 assign rdata = rdata_q; Tests: T1 T2 T3  150 1/1 assign error = error_q; Tests: T1 T2 T3  151 end 152 153 tlul_pkg::tl_d2h_t tl_o_pre; 154 1/1 assign tl_o_pre = '{ Tests: T1 T2 T3  155 // busy is selected based on address 156 // thus if there is no valid transaction, we should ignore busy 157 a_ready: ~(outstanding_q | tl_i.a_valid & busy_i), 158 d_valid: outstanding_q, 159 d_opcode: rspop_q, 160 d_param: '0, 161 d_size: reqsz_q, 162 d_source: reqid_q, 163 d_sink: '0, 164 d_data: rdata, 165 d_user: '0, 166 d_error: error 167 }; 168 169 // outgoing integrity generation 170 tlul_rsp_intg_gen #( 171 .EnableRspIntgGen(EnableRspIntgGen), 172 .EnableDataIntgGen(EnableDataIntgGen) 173 ) u_rsp_intg_gen ( 174 .tl_i(tl_o_pre), 175 .tl_o(tl_o) 176 ); 177 178 if (CmdIntgCheck) begin : gen_cmd_intg_check 179 logic intg_error_q; 180 tlul_cmd_intg_chk u_cmd_intg_chk ( 181 .tl_i(tl_i), 182 .err_o(intg_error) 183 ); 184 // permanently latch integrity error until reset 185 always_ff @(posedge clk_i or negedge rst_ni) begin 186 if (!rst_ni) begin 187 intg_error_q <= 1'b0; 188 end else if (intg_error) begin 189 intg_error_q <= 1'b1; 190 end 191 end 192 assign intg_error_o = intg_error_q; 193 end else begin : gen_no_cmd_intg_check 194 assign intg_error = 1'b0; 195 assign intg_error_o = 1'b0; 196 end 197 198 //////////////////// 199 // Error Handling // 200 //////////////////// 201 202 // An instruction type transaction is only valid if en_ifetch is enabled 203 // If the instruction type is completely invalid, also considered an instruction error 204 1/1 assign instr_error = prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type) | Tests: T1 T2 T3  205 (prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) & 206 prim_mubi_pkg::mubi4_test_false_loose(en_ifetch_i)); 207 208 1/1 assign err_internal = addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error; Tests: T1 T2 T3  209 210 // Don't allow unsupported values. 211 1/1 assign malformed_meta_err = tl_a_user_chk(tl_i.a_user); Tests: T1 T2 T3  212 213 // addr_align_err 214 // Raised if addr isn't aligned with the size 215 // Read size error is checked in tlul_assert.sv 216 // Here is it added due to the limitation of register interface. 217 always_comb begin 218 1/1 if (wr_req) begin Tests: T1 T2 T3  219 // Only word-align is accepted based on comportability spec 220 1/1 addr_align_err = |tl_i.a_address[1:0]; Tests: T1 T2 T3  221 end else begin 222 // No request 223 1/1 addr_align_err = 1'b0; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_core.u_reg_if
TotalCoveredPercent
Conditions454497.78
Logical454497.78
Non-Logical00
Event00

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T15,T16
11CoveredT1,T2,T3

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T15,T16
11CoveredT1,T2,T3

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       145
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       145
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT14,T15,T16
100CoveredT14,T15,T16

 LINE       146
 EXPRESSION (error_i || err_internal)
             ---1---    ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T15,T16
10CoveredT14,T15,T16

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----
-1--2--3--4--5-StatusTestsExclude Annotation
00000CoveredT1,T2,T3
00001Unreachable
00010Not Covered
00100CoveredT1,T2,T4
01000Excluded VC_COV_UNR
10000CoveredT14,T15,T16

Branch Coverage for Instance : tb.dut.u_reg_core.u_reg_if
Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 141 4 4 100.00


95 if (!rst_ni) outstanding_q <= 1'b0; -1- ==> 96 else if (a_ack) outstanding_q <= 1'b1; -2- ==> 97 else if (d_ack) outstanding_q <= 1'b0; -3- ==> MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


101 if (!rst_ni) begin -1- 102 reqid_q <= '0; ==> 103 reqsz_q <= '0; 104 rspop_q <= AccessAck; 105 end else if (a_ack) begin -2- 106 reqid_q <= tl_i.a_source; 107 reqsz_q <= tl_i.a_size; 108 // Return AccessAckData regardless of error 109 rspop_q <= (rd_req) ? AccessAckData : AccessAck ; -3- ==> ==> 110 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T2,T3
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


218 if (wr_req) begin -1- 219 // Only word-align is accepted based on comportability spec 220 addr_align_err = |tl_i.a_address[1:0]; ==> 221 end else begin 222 // No request 223 addr_align_err = 1'b0; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


141 if (!rst_ni) begin -1- 142 rdata_q <= '0; ==> 143 error_q <= 1'b0; 144 end else if (a_ack) begin -2- 145 rdata_q <= (error_i || err_internal || wr_req) ? '1 : rdata_i; -3- ==> ==> 146 error_q <= error_i || err_internal; 147 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T2,T3
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg_core.u_reg_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AllowedLatency_A 1291 1291 0 0
MatchedWidthAssert 1291 1291 0 0


AllowedLatency_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291 1291 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291 1291 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_reg_if
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS14166100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00

76 77 1/1 assign a_ack = tl_i.a_valid & tl_o.a_ready; Tests: T1 T2 T3  78 1/1 assign d_ack = tl_o.d_valid & tl_i.d_ready; Tests: T1 T2 T3  79 // Request signal 80 1/1 assign wr_req = a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)); Tests: T1 T2 T3  81 1/1 assign rd_req = a_ack & (tl_i.a_opcode == Get); Tests: T1 T2 T3  82 83 1/1 assign we_o = wr_req & ~err_internal; Tests: T1 T2 T3  84 1/1 assign re_o = rd_req & ~err_internal; Tests: T1 T2 T3  85 1/1 assign wdata_o = tl_i.a_data; Tests: T1 T2 T3  86 1/1 assign be_o = tl_i.a_mask; Tests: T1 T2 T3  87 88 if (RegAw <= 2) begin : gen_only_one_reg 89 assign addr_o = '0; 90 end else begin : gen_more_regs 91 1/1 assign addr_o = {tl_i.a_address[RegAw-1:2], 2'b00}; // generate always word-align Tests: T1 T2 T3  92 end 93 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 2/2 if (!rst_ni) outstanding_q <= 1'b0; Tests: T1 T2 T3  | T1 T2 T3  96 2/2 else if (a_ack) outstanding_q <= 1'b1; Tests: T1 T2 T3  | T18 T19 T20  97 2/2 else if (d_ack) outstanding_q <= 1'b0; Tests: T1 T2 T3  | T18 T19 T20  MISSING_ELSE 98 end 99 100 always_ff @(posedge clk_i or negedge rst_ni) begin 101 1/1 if (!rst_ni) begin Tests: T1 T2 T3  102 1/1 reqid_q <= '0; Tests: T1 T2 T3  103 1/1 reqsz_q <= '0; Tests: T1 T2 T3  104 1/1 rspop_q <= AccessAck; Tests: T1 T2 T3  105 1/1 end else if (a_ack) begin Tests: T1 T2 T3  106 1/1 reqid_q <= tl_i.a_source; Tests: T18 T19 T20  107 1/1 reqsz_q <= tl_i.a_size; Tests: T18 T19 T20  108 // Return AccessAckData regardless of error 109 1/1 rspop_q <= (rd_req) ? AccessAckData : AccessAck ; Tests: T18 T19 T20  110 end MISSING_ELSE 111 end 112 113 if (AccessLatency == 1) begin : gen_access_latency1 114 logic wr_req_q, rd_req_q; 115 always_ff @(posedge clk_i or negedge rst_ni) begin 116 if (!rst_ni) begin 117 rdata_q <= '0; 118 error_q <= 1'b0; 119 wr_req_q <= 1'b0; 120 rd_req_q <= 1'b0; 121 end else begin 122 rd_req_q <= rd_req; 123 wr_req_q <= wr_req; 124 // Addressing phase 125 if (a_ack) begin 126 error_q <= err_internal; 127 // Response phase 128 end else begin 129 error_q <= error; 130 rdata_q <= rdata; 131 end 132 end 133 end 134 assign rdata = (error_i || error_q || wr_req_q) ? '1 : 135 (rd_req_q) ? rdata_i : 136 rdata_q; // backpressure case 137 assign error = (rd_req_q || wr_req_q) ? (error_q || error_i) : 138 error_q; // backpressure case 139 end else begin : gen_access_latency0 140 always_ff @(posedge clk_i or negedge rst_ni) begin 141 1/1 if (!rst_ni) begin Tests: T1 T2 T3  142 1/1 rdata_q <= '0; Tests: T1 T2 T3  143 1/1 error_q <= 1'b0; Tests: T1 T2 T3  144 1/1 end else if (a_ack) begin Tests: T1 T2 T3  145 1/1 rdata_q <= (error_i || err_internal || wr_req) ? '1 : rdata_i; Tests: T18 T19 T20  146 1/1 error_q <= error_i || err_internal; Tests: T18 T19 T20  147 end MISSING_ELSE 148 end 149 1/1 assign rdata = rdata_q; Tests: T1 T2 T3  150 1/1 assign error = error_q; Tests: T1 T2 T3  151 end 152 153 tlul_pkg::tl_d2h_t tl_o_pre; 154 1/1 assign tl_o_pre = '{ Tests: T1 T2 T3  155 // busy is selected based on address 156 // thus if there is no valid transaction, we should ignore busy 157 a_ready: ~(outstanding_q | tl_i.a_valid & busy_i), 158 d_valid: outstanding_q, 159 d_opcode: rspop_q, 160 d_param: '0, 161 d_size: reqsz_q, 162 d_source: reqid_q, 163 d_sink: '0, 164 d_data: rdata, 165 d_user: '0, 166 d_error: error 167 }; 168 169 // outgoing integrity generation 170 tlul_rsp_intg_gen #( 171 .EnableRspIntgGen(EnableRspIntgGen), 172 .EnableDataIntgGen(EnableDataIntgGen) 173 ) u_rsp_intg_gen ( 174 .tl_i(tl_o_pre), 175 .tl_o(tl_o) 176 ); 177 178 if (CmdIntgCheck) begin : gen_cmd_intg_check 179 logic intg_error_q; 180 tlul_cmd_intg_chk u_cmd_intg_chk ( 181 .tl_i(tl_i), 182 .err_o(intg_error) 183 ); 184 // permanently latch integrity error until reset 185 always_ff @(posedge clk_i or negedge rst_ni) begin 186 if (!rst_ni) begin 187 intg_error_q <= 1'b0; 188 end else if (intg_error) begin 189 intg_error_q <= 1'b1; 190 end 191 end 192 assign intg_error_o = intg_error_q; 193 end else begin : gen_no_cmd_intg_check 194 assign intg_error = 1'b0; 195 assign intg_error_o = 1'b0; 196 end 197 198 //////////////////// 199 // Error Handling // 200 //////////////////// 201 202 // An instruction type transaction is only valid if en_ifetch is enabled 203 // If the instruction type is completely invalid, also considered an instruction error 204 1/1 assign instr_error = prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type) | Tests: T1 T2 T3  205 (prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) & 206 prim_mubi_pkg::mubi4_test_false_loose(en_ifetch_i)); 207 208 1/1 assign err_internal = addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error; Tests: T1 T2 T3  209 210 // Don't allow unsupported values. 211 1/1 assign malformed_meta_err = tl_a_user_chk(tl_i.a_user); Tests: T1 T2 T3  212 213 // addr_align_err 214 // Raised if addr isn't aligned with the size 215 // Read size error is checked in tlul_assert.sv 216 // Here is it added due to the limitation of register interface. 217 always_comb begin 218 1/1 if (wr_req) begin Tests: T1 T2 T3  219 // Only word-align is accepted based on comportability spec 220 1/1 addr_align_err = |tl_i.a_address[1:0]; Tests: T18 T19 T20  221 end else begin 222 // No request 223 1/1 addr_align_err = 1'b0; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_reg_if
TotalCoveredPercent
Conditions454497.78
Logical454497.78
Non-Logical00
Event00

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT18,T19,T20
11CoveredT18,T19,T20

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT3,T17,T18
10CoveredT19,T20,T134
11CoveredT18,T19,T20

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT18,T19,T20
11CoveredT18,T19,T20

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT18,T19,T20
01CoveredT18,T19,T20
10CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T19,T20

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------
-1--2-StatusTests
01CoveredT18,T19,T20
10CoveredT18,T19,T20
11CoveredT18,T19,T20

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T19,T20

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT18,T19,T20
10CoveredT14,T15,T16
11CoveredT18,T19,T20

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT18,T19,T20
10CoveredT14,T15,T16
11CoveredT18,T19,T20

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT18,T19,T20
1CoveredT18,T19,T20

 LINE       145
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------
-1-StatusTests
0CoveredT18,T19,T20
1CoveredT18,T19,T20

 LINE       145
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--
-1--2--3-StatusTests
000CoveredT18,T19,T20
001CoveredT18,T19,T20
010CoveredT14,T15,T16
100CoveredT297,T298,T299

 LINE       146
 EXPRESSION (error_i || err_internal)
             ---1---    ------2-----
-1--2-StatusTests
00CoveredT18,T19,T20
01CoveredT14,T15,T16
10CoveredT14,T15,T16

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT18,T19,T20

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT18,T19,T20
11Unreachable

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----
-1--2--3--4--5-StatusTestsExclude Annotation
00000CoveredT18,T19,T20
00001Unreachable
00010Not Covered
00100CoveredT3,T19,T134
01000Excluded VC_COV_UNR
10000CoveredT297,T305,T309

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_reg_if
Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 141 4 4 100.00


95 if (!rst_ni) outstanding_q <= 1'b0; -1- ==> 96 else if (a_ack) outstanding_q <= 1'b1; -2- ==> 97 else if (d_ack) outstanding_q <= 1'b0; -3- ==> MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T18,T19,T20
0 0 1 Covered T18,T19,T20
0 0 0 Covered T1,T2,T3


101 if (!rst_ni) begin -1- 102 reqid_q <= '0; ==> 103 reqsz_q <= '0; 104 rspop_q <= AccessAck; 105 end else if (a_ack) begin -2- 106 reqid_q <= tl_i.a_source; 107 reqsz_q <= tl_i.a_size; 108 // Return AccessAckData regardless of error 109 rspop_q <= (rd_req) ? AccessAckData : AccessAck ; -3- ==> ==> 110 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T18,T19,T20
0 1 0 Covered T18,T19,T20
0 0 - Covered T1,T2,T3


218 if (wr_req) begin -1- 219 // Only word-align is accepted based on comportability spec 220 addr_align_err = |tl_i.a_address[1:0]; ==> 221 end else begin 222 // No request 223 addr_align_err = 1'b0; ==>

Branches:
-1-StatusTests
1 Covered T18,T19,T20
0 Covered T1,T2,T3


141 if (!rst_ni) begin -1- 142 rdata_q <= '0; ==> 143 error_q <= 1'b0; 144 end else if (a_ack) begin -2- 145 rdata_q <= (error_i || err_internal || wr_req) ? '1 : rdata_i; -3- ==> ==> 146 error_q <= error_i || err_internal; 147 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T18,T19,T20
0 1 0 Covered T18,T19,T20
0 0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_reg_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AllowedLatency_A 1291 1291 0 0
MatchedWidthAssert 1291 1291 0 0


AllowedLatency_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291 1291 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291 1291 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0