Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_unbuf_err_code_cg_wrap::unbuf_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_unbuf_err_code_cg_wrap::unbuf_err_code_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
85.71	80.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

5 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]	57.14	1	100	1	64	64
unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]	85.71	1	100	1	64	64
unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]	85.71	1	100	1	64	64
unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]	85.71	1	100	1	64	64
unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]	85.71	1	100	1	64	64

---

Group Instance : unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
57.14	1	100	1	64	64

---

Summary for Group Instance unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	3	4	57.14

Variables for Group Instance unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	3	4	57.14	100	1	1	0

---

Group Instance : unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

---

Summary for Group Instance unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	1	6	85.71

Variables for Group Instance unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0

---

Group Instance : unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

---

Summary for Group Instance unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	1	6	85.71

Variables for Group Instance unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0

---

Group Instance : unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

---

Summary for Group Instance unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	1	6	85.71

Variables for Group Instance unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0

---

Group Instance : unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

---

Summary for Group Instance unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	1	6	85.71

Variables for Group Instance unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	3	4	57.14

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
ecc_uncorr_err	0	1	1
ecc_corr_err	0	1	1
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	89767	1			T5	22		T130	76		T8	269
check_fail	1	1			T149	1		-	-		-	-
access_err	28409	1			T11	38		T86	98		T88	33
no_err	89090	1			T5	20		T7	70		T6	61

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	89395	1			T4	1		T5	22		T130	76
check_fail	2	1			T102	1		T149	1		-	-
access_err	29239	1			T11	43		T130	10		T86	126
ecc_uncorr_err	506	1			T132	1		T153	46		T109	34
ecc_corr_err	1024	1			T5	20		T130	8		T152	8
no_err	87185	1			T7	70		T6	61		T11	21

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	89490	1			T4	1		T5	22		T130	76
check_fail	1	1			T149	1		-	-		-	-
access_err	28369	1			T5	16		T11	59		T86	55
ecc_uncorr_err	393	1			T93	1		T157	2		T155	1
ecc_corr_err	913	1			T130	1		T152	9		T37	49
no_err	88116	1			T5	4		T7	70		T6	61

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	89530	1			T4	1		T5	22		T130	76
check_fail	2	1			T102	1		T149	1		-	-
access_err	28656	1			T8	7		T86	89		T88	39
ecc_uncorr_err	349	1			T152	29		T94	1		T163	51
ecc_corr_err	1185	1			T5	18		T37	10		T153	3
no_err	87500	1			T5	2		T7	70		T6	61

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	89530	1			T4	1		T5	22		T130	76
check_fail	2	1			T102	1		T149	1		-	-
access_err	28859	1			T86	133		T88	7		T66	15
ecc_uncorr_err	345	1			T153	33		T167	104		T164	18
ecc_corr_err	909	1			T66	11		T37	27		T129	5
no_err	87521	1			T5	20		T7	70		T6	61