Unified Coverage Report :: Group :: push_pull_agent_pkg::req_ack_cg

Group : push_pull_agent_pkg::req_ack_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_push_pull_agent_0.1/push_pull_agent_cov.sv

9 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
push_pull_agent_pkg.uvm_test_top.env.m_edn_pull_agent[0].cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_flash_addr_pull_agent.cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_flash_data_pull_agent.cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_lc_prog_pull_agent.cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_otbn_pull_agent.cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[0].cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[1].cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[2].cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[3].cov::m_req_ack_cg	100.00	1	100	1	64	64

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_edn_pull_agent[0].cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_edn_pull_agent[0].cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_edn_pull_agent[0].cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_flash_addr_pull_agent.cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_flash_addr_pull_agent.cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_flash_addr_pull_agent.cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_flash_data_pull_agent.cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_flash_data_pull_agent.cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_flash_data_pull_agent.cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_lc_prog_pull_agent.cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_lc_prog_pull_agent.cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_lc_prog_pull_agent.cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_otbn_pull_agent.cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_otbn_pull_agent.cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_otbn_pull_agent.cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[0].cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[0].cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[0].cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[1].cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[1].cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[1].cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[2].cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[2].cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[2].cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[3].cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[3].cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[3].cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	394012	1			T5	66		T7	90		T6	144
auto[2]	394344	1			T5	66		T7	90		T6	144
auto[3]	394063	1			T5	66		T7	90		T6	144

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4412	1			T5	1		T7	1		T6	2
auto[2]	4982	1			T5	1		T7	1		T6	2
auto[3]	4413	1			T5	1		T7	1		T6	2

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4333	1			T5	1		T7	1		T6	2
auto[2]	4992	1			T5	1		T7	1		T6	2
auto[3]	4333	1			T5	1		T7	1		T6	2

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	7154	1			T5	2		T7	1		T6	2
auto[2]	7820	1			T5	2		T7	1		T6	3
auto[3]	7201	1			T5	2		T7	1		T6	3

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4385	1			T5	1		T7	1		T6	2
auto[2]	5065	1			T5	1		T7	1		T6	2
auto[3]	4385	1			T5	1		T7	1		T6	2

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4399	1			T5	1		T7	1		T6	2
auto[2]	5044	1			T5	1		T7	1		T6	2
auto[3]	4400	1			T5	1		T7	1		T6	2

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4367	1			T5	1		T7	1		T6	2
auto[2]	4982	1			T5	1		T7	1		T6	2
auto[3]	4368	1			T5	1		T7	1		T6	2

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4344	1			T5	1		T7	1		T6	2
auto[2]	4928	1			T5	1		T7	1		T6	2
auto[3]	4344	1			T5	1		T7	1		T6	2

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4294	1			T5	1		T7	1		T6	2
auto[2]	5091	1			T5	1		T7	1		T6	2
auto[3]	4379	1			T5	1		T7	1		T6	2