Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4178229	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2321284

1

T1

6

T2

176

T3

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5461373	1			T1	4		T2	511		T3	1
values[0x0]	489459	1			T1	11		T2	114		T3	46
values[0x1]	548681	1			T1	4		T2	107		T3	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3076339	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3423174

1

T1

6

T2

326

T3

24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20264	1			T2	4		T3	1		T4	5
valid_sources[0x01]	32347	1			T4	4		T7	7		T6	2
valid_sources[0x02]	20908	1			T2	2		T4	1		T7	22
valid_sources[0x03]	27796	1			T2	5		T3	2		T4	1
valid_sources[0x04]	29613	1			T2	2		T4	1		T7	11
valid_sources[0x05]	21159	1			T2	6		T4	4		T7	10
valid_sources[0x06]	20455	1			T2	3		T4	9		T7	21
valid_sources[0x07]	28951	1			T4	1		T7	12		T6	5
valid_sources[0x08]	21177	1			T2	3		T4	1		T7	5
valid_sources[0x09]	20080	1			T2	2		T3	1		T4	1
valid_sources[0x0a]	20904	1			T4	2		T7	22		T6	6
valid_sources[0x0b]	23561	1			T4	2		T7	10		T11	3
valid_sources[0x0c]	19623	1			T2	3		T4	5		T7	9
valid_sources[0x0d]	22282	1			T2	2		T7	9		T6	4
valid_sources[0x0e]	49416	1			T2	7		T4	3		T7	10
valid_sources[0x0f]	20642	1			T2	6		T4	1		T7	9
valid_sources[0x10]	19773	1			T2	9		T7	15		T6	3
valid_sources[0x11]	21171	1			T2	1		T4	7		T7	9
valid_sources[0x12]	20811	1			T2	1		T3	2		T4	3
valid_sources[0x13]	23611	1			T2	2		T7	5		T6	4
valid_sources[0x14]	38959	1			T2	1		T3	1		T4	2
valid_sources[0x15]	23374	1			T2	3		T4	3		T7	14
valid_sources[0x16]	28456	1			T2	5		T3	1		T4	6
valid_sources[0x17]	29349	1			T2	3		T4	4		T7	6
valid_sources[0x18]	22263	1			T2	6		T4	3		T7	22
valid_sources[0x19]	36984	1			T4	4		T7	22		T6	7
valid_sources[0x1a]	25932	1			T2	5		T7	17		T6	6
valid_sources[0x1b]	20727	1			T2	5		T4	2		T7	8
valid_sources[0x1c]	119381	1			T2	3		T3	1		T4	1
valid_sources[0x1d]	20493	1			T7	8		T6	6		T11	8
valid_sources[0x1e]	21547	1			T2	5		T4	2		T7	15
valid_sources[0x1f]	21202	1			T2	2		T4	7		T7	8
valid_sources[0x20]	21927	1			T2	1		T4	1		T7	17
valid_sources[0x21]	26774	1			T2	3		T7	16		T6	12
valid_sources[0x22]	21907	1			T2	5		T4	2		T7	16
valid_sources[0x23]	19842	1			T2	2		T7	8		T6	5
valid_sources[0x24]	91938	1			T4	2		T7	21		T6	6
valid_sources[0x25]	20624	1			T2	3		T7	11		T6	9
valid_sources[0x26]	21808	1			T7	10		T6	6		T11	4
valid_sources[0x27]	20221	1			T2	2		T4	2		T7	6
valid_sources[0x28]	29252	1			T2	3		T7	13		T6	4
valid_sources[0x29]	30657	1			T7	5		T6	3		T11	12
valid_sources[0x2a]	22118	1			T2	4		T3	1		T7	13
valid_sources[0x2b]	19873	1			T2	3		T3	1		T4	3
valid_sources[0x2c]	19916	1			T2	3		T4	6		T7	8
valid_sources[0x2d]	36276	1			T2	1		T7	10		T6	8
valid_sources[0x2e]	19734	1			T2	3		T3	1		T7	4
valid_sources[0x2f]	27038	1			T2	2		T4	6		T7	6
valid_sources[0x30]	24744	1			T4	2		T7	11		T6	7
valid_sources[0x31]	20845	1			T2	5		T4	3		T7	13
valid_sources[0x32]	23603	1			T2	1		T4	1		T7	12
valid_sources[0x33]	23905	1			T2	5		T4	2		T7	15
valid_sources[0x34]	40631	1			T2	1		T4	2		T7	13
valid_sources[0x35]	20622	1			T2	3		T4	5		T7	18
valid_sources[0x36]	21649	1			T2	2		T4	2		T7	19
valid_sources[0x37]	20879	1			T2	7		T4	5		T7	7
valid_sources[0x38]	21979	1			T2	2		T7	9		T6	4
valid_sources[0x39]	23490	1			T3	1		T4	4		T7	19
valid_sources[0x3a]	22846	1			T2	4		T4	5		T7	16
valid_sources[0x3b]	23226	1			T2	2		T4	4		T7	9
valid_sources[0x3c]	20797	1			T2	2		T4	1		T7	7
valid_sources[0x3d]	20402	1			T2	6		T7	13		T6	5
valid_sources[0x3e]	20591	1			T2	4		T4	2		T7	8
valid_sources[0x3f]	25854	1			T2	3		T4	2		T7	20
valid_sources[0x40]	21778	1			T2	1		T7	5		T6	4
valid_sources[0x41]	25139	1			T4	5		T7	15		T6	2
valid_sources[0x42]	27978	1			T2	2		T7	16		T6	3
valid_sources[0x43]	22883	1			T2	2		T4	3		T7	4
valid_sources[0x44]	22302	1			T2	4		T4	1		T7	16
valid_sources[0x45]	22591	1			T2	1		T3	1		T4	1
valid_sources[0x46]	21799	1			T2	3		T4	1		T7	7
valid_sources[0x47]	20480	1			T2	4		T3	1		T4	12
valid_sources[0x48]	20324	1			T2	1		T4	1		T7	8
valid_sources[0x49]	20784	1			T2	6		T3	2		T4	1
valid_sources[0x4a]	21235	1			T2	5		T4	3		T7	9
valid_sources[0x4b]	23161	1			T2	5		T3	2		T4	2
valid_sources[0x4c]	23192	1			T2	4		T4	2		T7	10
valid_sources[0x4d]	21739	1			T2	1		T4	8		T7	8
valid_sources[0x4e]	20018	1			T2	5		T3	2		T4	12
valid_sources[0x4f]	20981	1			T2	3		T4	1		T7	12
valid_sources[0x50]	20613	1			T2	4		T7	9		T6	2
valid_sources[0x51]	19939	1			T2	8		T4	1		T7	10
valid_sources[0x52]	19870	1			T2	4		T3	1		T4	2
valid_sources[0x53]	20175	1			T2	2		T3	1		T4	3
valid_sources[0x54]	21519	1			T2	1		T4	3		T7	13
valid_sources[0x55]	20350	1			T2	4		T7	13		T6	7
valid_sources[0x56]	20657	1			T2	3		T4	1		T7	5
valid_sources[0x57]	20556	1			T1	3		T2	3		T4	1
valid_sources[0x58]	24869	1			T2	4		T3	1		T4	5
valid_sources[0x59]	20366	1			T7	17		T6	4		T11	22
valid_sources[0x5a]	20248	1			T2	1		T4	2		T7	10
valid_sources[0x5b]	29272	1			T2	3		T4	7		T7	10
valid_sources[0x5c]	20451	1			T2	2		T4	1		T7	9
valid_sources[0x5d]	29567	1			T2	2		T4	2		T7	7
valid_sources[0x5e]	20458	1			T2	3		T3	1		T7	6
valid_sources[0x5f]	20087	1			T2	3		T4	1		T7	12
valid_sources[0x60]	22350	1			T2	4		T4	5		T7	15
valid_sources[0x61]	23174	1			T2	3		T4	1		T7	16
valid_sources[0x62]	32708	1			T2	3		T7	11		T6	3
valid_sources[0x63]	21043	1			T2	1		T4	2		T7	19
valid_sources[0x64]	36784	1			T2	2		T7	7		T6	6
valid_sources[0x65]	28842	1			T2	1		T4	4		T7	8
valid_sources[0x66]	21606	1			T2	4		T3	2		T4	2
valid_sources[0x67]	21987	1			T2	2		T4	3		T7	16
valid_sources[0x68]	20009	1			T2	4		T3	1		T4	4
valid_sources[0x69]	21211	1			T2	7		T4	4		T7	14
valid_sources[0x6a]	20440	1			T2	2		T4	5		T7	9
valid_sources[0x6b]	20253	1			T2	3		T7	12		T6	3
valid_sources[0x6c]	20375	1			T2	7		T7	11		T6	5
valid_sources[0x6d]	23195	1			T2	1		T4	4		T7	10
valid_sources[0x6e]	22605	1			T2	2		T7	7		T6	11
valid_sources[0x6f]	24129	1			T2	3		T4	3		T7	15
valid_sources[0x70]	23117	1			T2	7		T4	1		T7	9
valid_sources[0x71]	30716	1			T2	1		T4	1		T7	17
valid_sources[0x72]	19703	1			T2	3		T4	2		T7	6
valid_sources[0x73]	55079	1			T2	4		T7	8		T6	3
valid_sources[0x74]	22791	1			T2	7		T3	1		T4	1
valid_sources[0x75]	19652	1			T2	4		T4	3		T7	11
valid_sources[0x76]	22225	1			T2	3		T3	1		T7	9
valid_sources[0x77]	23232	1			T2	2		T3	1		T4	3
valid_sources[0x78]	19933	1			T2	2		T4	3		T7	28
valid_sources[0x79]	28192	1			T2	7		T4	1		T7	10
valid_sources[0x7a]	21397	1			T2	3		T4	6		T7	5
valid_sources[0x7b]	20471	1			T2	3		T3	3		T4	10
valid_sources[0x7c]	20609	1			T2	1		T4	1		T7	16
valid_sources[0x7d]	20729	1			T2	7		T4	4		T7	12
valid_sources[0x7e]	22937	1			T2	3		T4	2		T7	11
valid_sources[0x7f]	27583	1			T2	3		T4	2		T7	24
valid_sources[0x80]	20521	1			T2	4		T7	13		T6	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1830007

1

T1

2

T2

78

T3

1

values[0x0]

all_enables

biggest_size

276110

1

T1

4

T2

58

T3

15

values[0x1]

all_enables

biggest_size

215167

1

T2

40

T3

1

T4

55

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25219	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

486681

1

T5

40

T7

40

T6

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	164045	1			T5	20		T7	20		T6	20
values[0x0]	169366	1			T5	14		T7	11		T6	12
values[0x1]	178489	1			T5	6		T7	9		T6	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14008	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

497892

1

T5

40

T7

40

T6

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2104	1			T7	1		T87	1		T119	1
valid_sources[0x01]	1961	1			T18	1		T116	2		T194	1
valid_sources[0x02]	2077	1			T7	2		T8	2		T18	1
valid_sources[0x03]	1850	1			T87	2		T124	1		T116	3
valid_sources[0x04]	2057	1			T87	1		T119	1		T199	1
valid_sources[0x05]	1876	1			T7	2		T87	2		T18	2
valid_sources[0x06]	1829	1			T87	2		T124	1		T119	1
valid_sources[0x07]	3270	1			T18	2		T127	3		T129	1
valid_sources[0x08]	1994	1			T87	1		T37	1		T122	140
valid_sources[0x09]	2206	1			T87	1		T124	1		T119	2
valid_sources[0x0a]	2498	1			T129	1		T135	1		T212	2
valid_sources[0x0b]	2187	1			T87	1		T116	8		T118	1
valid_sources[0x0c]	1946	1			T87	1		T119	1		T92	4
valid_sources[0x0d]	2551	1			T87	1		T66	28		T37	1
valid_sources[0x0e]	2239	1			T117	1		T92	1		T127	1
valid_sources[0x0f]	2210	1			T12	2		T124	1		T118	2
valid_sources[0x10]	1820	1			T87	2		T118	1		T128	2
valid_sources[0x11]	1552	1			T66	9		T116	3		T119	2
valid_sources[0x12]	1613	1			T117	2		T119	1		T37	1
valid_sources[0x13]	2227	1			T117	2		T119	1		T37	2
valid_sources[0x14]	2079	1			T37	1		T14	16		T311	1
valid_sources[0x15]	1918	1			T119	2		T127	1		T37	1
valid_sources[0x16]	1905	1			T87	1		T119	1		T127	1
valid_sources[0x17]	2170	1			T118	4		T119	2		T127	1
valid_sources[0x18]	1832	1			T18	1		T117	1		T210	4
valid_sources[0x19]	1777	1			T13	2		T118	3		T119	2
valid_sources[0x1a]	2007	1			T7	2		T127	1		T218	160
valid_sources[0x1b]	1991	1			T7	1		T130	2		T220	1
valid_sources[0x1c]	1554	1			T120	5		T128	1		T129	1
valid_sources[0x1d]	1766	1			T8	1		T124	1		T37	3
valid_sources[0x1e]	1749	1			T119	2		T9	1		T153	1
valid_sources[0x1f]	1938	1			T116	2		T117	2		T128	1
valid_sources[0x20]	2185	1			T119	2		T127	1		T120	1
valid_sources[0x21]	1735	1			T87	1		T119	2		T92	2
valid_sources[0x22]	1681	1			T87	1		T37	1		T128	1
valid_sources[0x23]	2148	1			T8	1		T127	1		T37	1
valid_sources[0x24]	2049	1			T121	3		T37	1		T128	1
valid_sources[0x25]	2032	1			T87	1		T116	1		T127	1
valid_sources[0x26]	1719	1			T87	1		T119	1		T194	1
valid_sources[0x27]	2290	1			T87	2		T124	1		T119	1
valid_sources[0x28]	1860	1			T87	1		T124	1		T116	5
valid_sources[0x29]	2020	1			T130	1		T87	1		T117	2
valid_sources[0x2a]	1754	1			T117	1		T119	1		T197	1
valid_sources[0x2b]	2105	1			T87	1		T119	1		T121	2
valid_sources[0x2c]	2165	1			T12	2		T119	1		T37	1
valid_sources[0x2d]	2176	1			T18	1		T37	2		T128	2
valid_sources[0x2e]	2261	1			T117	1		T119	1		T127	1
valid_sources[0x2f]	1877	1			T7	1		T87	5		T18	1
valid_sources[0x30]	1885	1			T125	20		T92	5		T152	3
valid_sources[0x31]	1781	1			T12	2		T87	1		T117	2
valid_sources[0x32]	2051	1			T127	2		T120	1		T440	1
valid_sources[0x33]	1814	1			T87	1		T121	4		T37	1
valid_sources[0x34]	1881	1			T118	1		T128	1		T153	1
valid_sources[0x35]	2122	1			T87	1		T128	3		T14	17
valid_sources[0x36]	1827	1			T87	3		T117	1		T119	1
valid_sources[0x37]	2217	1			T12	1		T87	1		T118	2
valid_sources[0x38]	1776	1			T37	1		T153	4		T135	1
valid_sources[0x39]	1954	1			T18	2		T119	1		T128	3
valid_sources[0x3a]	1812	1			T6	40		T12	1		T87	1
valid_sources[0x3b]	2492	1			T124	1		T118	1		T120	3
valid_sources[0x3c]	2229	1			T13	1		T118	1		T119	1
valid_sources[0x3d]	1777	1			T116	4		T120	1		T220	1
valid_sources[0x3e]	1765	1			T87	1		T124	1		T116	2
valid_sources[0x3f]	2027	1			T18	3		T124	1		T116	1
valid_sources[0x40]	2005	1			T130	1		T87	1		T117	2
valid_sources[0x41]	2246	1			T87	2		T18	3		T117	2
valid_sources[0x42]	1772	1			T7	1		T116	3		T119	1
valid_sources[0x43]	1892	1			T12	1		T92	1		T127	2
valid_sources[0x44]	2780	1			T7	1		T87	1		T120	2
valid_sources[0x45]	1766	1			T119	1		T194	1		T210	6
valid_sources[0x46]	1942	1			T87	1		T66	3		T194	1
valid_sources[0x47]	1856	1			T124	1		T117	4		T118	1
valid_sources[0x48]	1822	1			T87	3		T66	15		T195	20
valid_sources[0x49]	2256	1			T87	1		T92	2		T127	2
valid_sources[0x4a]	1959	1			T7	2		T117	3		T119	1
valid_sources[0x4b]	2460	1			T124	1		T116	3		T119	1
valid_sources[0x4c]	1878	1			T118	3		T194	1		T127	1
valid_sources[0x4d]	1890	1			T119	1		T199	1		T153	1
valid_sources[0x4e]	1666	1			T87	1		T117	2		T119	1
valid_sources[0x4f]	1956	1			T87	1		T37	1		T440	1
valid_sources[0x50]	3220	1			T87	1		T118	2		T119	1
valid_sources[0x51]	2398	1			T116	1		T121	3		T37	1
valid_sources[0x52]	1958	1			T118	5		T119	1		T127	1
valid_sources[0x53]	1927	1			T87	1		T119	1		T127	1
valid_sources[0x54]	1919	1			T7	1		T124	1		T118	2
valid_sources[0x55]	1997	1			T7	1		T18	3		T194	2
valid_sources[0x56]	1708	1			T117	1		T128	1		T129	2
valid_sources[0x57]	1770	1			T87	2		T92	2		T37	1
valid_sources[0x58]	2232	1			T7	1		T127	1		T153	1
valid_sources[0x59]	1730	1			T130	2		T116	4		T145	8
valid_sources[0x5a]	1806	1			T87	1		T124	1		T118	1
valid_sources[0x5b]	2102	1			T5	40		T119	1		T37	1
valid_sources[0x5c]	2039	1			T8	2		T119	1		T37	1
valid_sources[0x5d]	1708	1			T7	1		T87	2		T127	1
valid_sources[0x5e]	2548	1			T130	2		T8	1		T119	1
valid_sources[0x5f]	2412	1			T12	1		T119	1		T127	1
valid_sources[0x60]	1984	1			T119	1		T121	1		T37	1
valid_sources[0x61]	1648	1			T87	1		T119	3		T92	1
valid_sources[0x62]	1855	1			T124	2		T119	1		T92	4
valid_sources[0x63]	2115	1			T87	4		T121	4		T37	2
valid_sources[0x64]	1902	1			T87	1		T117	1		T119	1
valid_sources[0x65]	1917	1			T119	3		T369	1		T135	2
valid_sources[0x66]	1766	1			T124	1		T118	1		T119	1
valid_sources[0x67]	1956	1			T87	3		T124	1		T127	3
valid_sources[0x68]	1776	1			T119	1		T37	2		T220	1
valid_sources[0x69]	1830	1			T117	1		T118	1		T119	1
valid_sources[0x6a]	1661	1			T118	3		T92	1		T127	2
valid_sources[0x6b]	2225	1			T13	1		T18	1		T124	1
valid_sources[0x6c]	1934	1			T87	2		T127	1		T120	2
valid_sources[0x6d]	2319	1			T7	1		T117	1		T119	1
valid_sources[0x6e]	1976	1			T87	2		T118	3		T194	1
valid_sources[0x6f]	1963	1			T87	1		T119	1		T199	5
valid_sources[0x70]	1932	1			T7	1		T116	1		T152	3
valid_sources[0x71]	1989	1			T119	1		T199	1		T9	1
valid_sources[0x72]	1759	1			T130	1		T124	1		T117	2
valid_sources[0x73]	1498	1			T18	3		T116	1		T117	1
valid_sources[0x74]	2371	1			T8	1		T119	1		T120	2
valid_sources[0x75]	1574	1			T8	1		T18	1		T92	1
valid_sources[0x76]	1951	1			T13	8		T117	2		T118	1
valid_sources[0x77]	2254	1			T12	1		T8	1		T87	1
valid_sources[0x78]	1895	1			T7	1		T124	1		T197	1
valid_sources[0x79]	2304	1			T119	1		T127	1		T120	2
valid_sources[0x7a]	1750	1			T87	1		T118	2		T127	1
valid_sources[0x7b]	1656	1			T12	1		T87	1		T124	2
valid_sources[0x7c]	1845	1			T7	1		T12	1		T87	1
valid_sources[0x7d]	2325	1			T127	1		T129	2		T202	1
valid_sources[0x7e]	2612	1			T87	2		T119	2		T127	1
valid_sources[0x7f]	1838	1			T130	1		T87	1		T118	6
valid_sources[0x80]	1860	1			T8	1		T87	1		T124	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

151250

1

T5

20

T7

20

T6

20

values[0x0]

all_enables

biggest_size

167831

1

T5

14

T7

11

T6

12

values[0x1]

all_enables

biggest_size

167600

1

T5

6

T7

9

T6

8