Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4914510

1

T1

13

T2

556

T3

66

full_word

2365846

1

T1

6

T2

176

T3

17

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7280066	1			T1	19		T2	732		T3	83
auto[TlIntgErrCmd]	112	1			T297	2		T298	6		T299	3
auto[TlIntgErrData]	90	1			T297	8		T299	3		T305	6
auto[TlIntgErrBoth]	88	1			T298	4		T299	4		T305	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5515552

1

T1

4

T2

511

T3

1

auto[1]

1764804

1

T1

15

T2

221

T3

82

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3679995	1			T1	2		T2	433		T4	314
auto[TlIntgErrNone]	partial	auto[1]	1234248	1			T1	11		T2	123		T3	66
auto[TlIntgErrNone]	full_word	auto[0]	1835424	1			T1	2		T2	78		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	530399	1			T1	4		T2	98		T3	16
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T297	1		T298	1		T305	5
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T297	1		T298	5		T299	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T379	2		T383	1		T304	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T305	1		T383	1		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1			T297	4		T299	1		T305	2
auto[TlIntgErrData]	partial	auto[1]	41	1			T297	3		T299	1		T305	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T297	1		T299	1		T380	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T381	1		T384	1		T308	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T298	3		T299	2		T309	3
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T298	1		T299	2		T305	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T305	1		T382	1		T385	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T304	1		-	-		-	-