Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	94.16	95.24	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	80837848	341054	0	0
check_regwen_rd_A	80837848	1525	0	0
check_timeout_rd_A	80837848	970	0	0
check_trigger_regwen_rd_A	80837848	1374	0	0
consistency_check_period_rd_A	80837848	1546	0	0
creator_sw_cfg_read_lock_rd_A	80837848	1046	0	0
direct_access_address_rd_A	80837848	319	0	0
direct_access_wdata_0_rd_A	80837848	64	0	0
direct_access_wdata_1_rd_A	80837848	41	0	0
integrity_check_period_rd_A	80837848	1472	0	0
intr_enable_rd_A	80837848	2144	0	0
owner_sw_cfg_read_lock_rd_A	80837848	1112	0	0
rot_creator_auth_codesign_read_lock_rd_A	80837848	1097	0	0
rot_creator_auth_state_read_lock_rd_A	80837848	1033	0	0
vendor_test_read_lock_rd_A	80837848	1099	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80837848	341054	0	0
T14	182725	4434	0	0
T15	0	4470	0	0
T16	0	4587	0	0
T21	0	4404	0	0
T22	0	12809	0	0
T24	0	3445	0	0
T46	9352	0	0	0
T98	46830	0	0	0
T205	48575	0	0	0
T236	0	13279	0	0
T248	0	7248	0	0
T259	273752	0	0	0
T282	0	4915	0	0
T311	133493	0	0	0
T313	0	8038	0	0
T314	16267	0	0	0
T315	15408	0	0	0
T316	67722	0	0	0
T317	20295	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80837848	1525	0	0
T16	268908	19	0	0
T21	0	17	0	0
T23	0	60	0	0
T133	0	12	0	0
T150	10210	0	0	0
T154	55993	0	0	0
T160	8408	0	0	0
T257	176863	0	0	0
T282	0	16	0	0
T286	51430	0	0	0
T347	0	28	0	0
T348	0	15	0	0
T349	0	15	0	0
T350	0	48	0	0
T351	0	13	0	0
T352	81875	0	0	0
T353	66940	0	0	0
T354	20166	0	0	0
T355	5284	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80837848	970	0	0
T16	268908	16	0	0
T21	0	28	0	0
T23	0	35	0	0
T133	0	23	0	0
T150	10210	0	0	0
T154	55993	0	0	0
T160	8408	0	0	0
T257	176863	0	0	0
T282	0	25	0	0
T286	51430	0	0	0
T300	0	6	0	0
T347	0	18	0	0
T349	0	10	0	0
T350	0	59	0	0
T351	0	28	0	0
T352	81875	0	0	0
T353	66940	0	0	0
T354	20166	0	0	0
T355	5284	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80837848	1374	0	0
T16	268908	26	0	0
T21	0	15	0	0
T23	0	38	0	0
T133	0	15	0	0
T150	10210	0	0	0
T154	55993	0	0	0
T160	8408	0	0	0
T257	176863	0	0	0
T282	0	10	0	0
T286	51430	0	0	0
T347	0	16	0	0
T348	0	10	0	0
T349	0	14	0	0
T350	0	51	0	0
T351	0	17	0	0
T352	81875	0	0	0
T353	66940	0	0	0
T354	20166	0	0	0
T355	5284	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80837848	1546	0	0
T16	268908	35	0	0
T21	0	19	0	0
T23	0	48	0	0
T133	0	22	0	0
T150	10210	0	0	0
T154	55993	0	0	0
T160	8408	0	0	0
T257	176863	0	0	0
T282	0	12	0	0
T286	51430	0	0	0
T347	0	36	0	0
T348	0	12	0	0
T349	0	10	0	0
T350	0	38	0	0
T351	0	32	0	0
T352	81875	0	0	0
T353	66940	0	0	0
T354	20166	0	0	0
T355	5284	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80837848	1046	0	0
T16	268908	38	0	0
T21	0	23	0	0
T23	0	43	0	0
T133	0	43	0	0
T150	10210	0	0	0
T154	55993	0	0	0
T160	8408	0	0	0
T257	176863	0	0	0
T282	0	21	0	0
T286	51430	0	0	0
T347	0	29	0	0
T348	0	7	0	0
T349	0	20	0	0
T350	0	42	0	0
T351	0	24	0	0
T352	81875	0	0	0
T353	66940	0	0	0
T354	20166	0	0	0
T355	5284	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80837848	319	0	0
T16	268908	39	0	0
T21	0	38	0	0
T23	0	54	0	0
T133	0	26	0	0
T150	10210	0	0	0
T154	55993	0	0	0
T160	8408	0	0	0
T257	176863	0	0	0
T282	0	12	0	0
T286	51430	0	0	0
T347	0	20	0	0
T348	0	13	0	0
T349	0	14	0	0
T350	0	47	0	0
T351	0	11	0	0
T352	81875	0	0	0
T353	66940	0	0	0
T354	20166	0	0	0
T355	5284	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80837848	64	0	0
T16	268908	8	0	0
T21	0	24	0	0
T133	0	10	0	0
T150	10210	0	0	0
T154	55993	0	0	0
T160	8408	0	0	0
T257	176863	0	0	0
T282	0	1	0	0
T286	51430	0	0	0
T347	0	1	0	0
T350	0	14	0	0
T351	0	6	0	0
T352	81875	0	0	0
T353	66940	0	0	0
T354	20166	0	0	0
T355	5284	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80837848	41	0	0
T16	268908	5	0	0
T21	0	15	0	0
T150	10210	0	0	0
T154	55993	0	0	0
T160	8408	0	0	0
T257	176863	0	0	0
T282	0	1	0	0
T286	51430	0	0	0
T347	0	5	0	0
T350	0	15	0	0
T352	81875	0	0	0
T353	66940	0	0	0
T354	20166	0	0	0
T355	5284	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80837848	1472	0	0
T16	268908	14	0	0
T21	0	35	0	0
T23	0	43	0	0
T133	0	26	0	0
T150	10210	0	0	0
T154	55993	0	0	0
T160	8408	0	0	0
T257	176863	0	0	0
T282	0	14	0	0
T286	51430	0	0	0
T347	0	37	0	0
T348	0	24	0	0
T349	0	3	0	0
T350	0	54	0	0
T351	0	16	0	0
T352	81875	0	0	0
T353	66940	0	0	0
T354	20166	0	0	0
T355	5284	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80837848	2144	0	0
T16	0	19	0	0
T21	0	57	0	0
T23	0	72	0	0
T48	66164	0	0	0
T208	0	20	0	0
T259	273752	18	0	0
T261	155508	0	0	0
T262	72091	0	0	0
T282	0	64	0	0
T311	133493	0	0	0
T312	24610	0	0	0
T316	67722	0	0	0
T317	20295	0	0	0
T347	0	32	0	0
T356	0	13	0	0
T357	0	7	0	0
T358	0	24	0	0
T359	9577	0	0	0
T360	5717	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80837848	1112	0	0
T16	268908	23	0	0
T21	0	28	0	0
T23	0	45	0	0
T133	0	29	0	0
T150	10210	0	0	0
T154	55993	0	0	0
T160	8408	0	0	0
T257	176863	0	0	0
T282	0	21	0	0
T286	51430	0	0	0
T347	0	30	0	0
T348	0	19	0	0
T349	0	3	0	0
T350	0	55	0	0
T351	0	38	0	0
T352	81875	0	0	0
T353	66940	0	0	0
T354	20166	0	0	0
T355	5284	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80837848	1097	0	0
T16	268908	20	0	0
T21	0	39	0	0
T23	0	46	0	0
T133	0	9	0	0
T150	10210	0	0	0
T154	55993	0	0	0
T160	8408	0	0	0
T257	176863	0	0	0
T282	0	22	0	0
T286	51430	0	0	0
T347	0	28	0	0
T348	0	18	0	0
T349	0	9	0	0
T350	0	70	0	0
T351	0	23	0	0
T352	81875	0	0	0
T353	66940	0	0	0
T354	20166	0	0	0
T355	5284	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80837848	1033	0	0
T16	268908	23	0	0
T21	0	18	0	0
T23	0	48	0	0
T133	0	34	0	0
T150	10210	0	0	0
T154	55993	0	0	0
T160	8408	0	0	0
T257	176863	0	0	0
T282	0	25	0	0
T286	51430	0	0	0
T300	0	5	0	0
T347	0	21	0	0
T349	0	12	0	0
T350	0	45	0	0
T351	0	17	0	0
T352	81875	0	0	0
T353	66940	0	0	0
T354	20166	0	0	0
T355	5284	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80837848	1099	0	0
T16	268908	24	0	0
T21	0	13	0	0
T23	0	33	0	0
T133	0	29	0	0
T150	10210	0	0	0
T154	55993	0	0	0
T160	8408	0	0	0
T257	176863	0	0	0
T282	0	15	0	0
T286	51430	0	0	0
T347	0	24	0	0
T348	0	14	0	0
T349	0	11	0	0
T350	0	48	0	0
T351	0	37	0	0
T352	81875	0	0	0
T353	66940	0	0	0
T354	20166	0	0	0
T355	5284	0	0	0