Unified Coverage Report :: Module :: prim_secded_inv_72_64_dec

Module : prim_secded_inv_72_64_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	64.71			64.71
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	66.18			66.18
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	69.85			69.85
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	71.32			71.32
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	72.06			72.06
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	73.53			73.53
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	73.53			73.53
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	75.00			75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	75.00			75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	75.00			75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	75.00			75.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.71			64.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.71			64.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.18			66.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.18			66.18

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.85			69.85

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.85			69.85

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.32			71.32

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.32			71.32

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T5,T11,T86	Yes	T5,T11,T86	INPUT
data_o[63:0]	Yes	Yes	T5,T11,T86	Yes	T5,T11,T86	OUTPUT
syndrome_o[2:0]	Yes	Yes	T102,T149	Yes	T102,T149	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T102,*T149	Yes	T102,T149	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	176	64.71
Total Bits 0->1	136	88	64.71
Total Bits 1->0	136	88	64.71

Ports	2	0	0.00
Port Bits	272	176	64.71
Port Bits 0->1	136	88	64.71
Port Bits 1->0	136	88	64.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[1]	No	No		No		INPUT
data_i[3:2]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[4]	No	No		No		INPUT
data_i[6:5]	Yes	Yes	T86,T87,T88	Yes	T12,T130,T86	INPUT
data_i[7]	No	No		No		INPUT
data_i[8]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[11:9]	No	No		No		INPUT
data_i[15:12]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[16]	No	No		No		INPUT
data_i[17]	Yes	Yes	*T86,*T87,*T88	Yes	T12,T130,T86	INPUT
data_i[18]	No	No		No		INPUT
data_i[19]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[20]	No	No		No		INPUT
data_i[23:21]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[24]	No	No		No		INPUT
data_i[26:25]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[27]	No	No		No		INPUT
data_i[29:28]	Yes	Yes	T86,T87,T88	Yes	T12,T130,T86	INPUT
data_i[31:30]	No	No		No		INPUT
data_i[32]	Yes	Yes	*T86,*T87,*T88	Yes	T12,T130,T86	INPUT
data_i[33]	No	No		No		INPUT
data_i[36:34]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[37]	No	No		No		INPUT
data_i[38]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[40:39]	No	No		No		INPUT
data_i[44:41]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[45]	No	No		No		INPUT
data_i[46]	Yes	Yes	*T86,*T87,*T88	Yes	T12,T130,T86	INPUT
data_i[48:47]	No	No		No		INPUT
data_i[56:49]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[58:57]	No	No		No		INPUT
data_i[61:59]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[63:62]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T13	INPUT
data_o[0]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[3:2]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[6:5]	Yes	Yes	T86,T87,T88	Yes	T12,T130,T86	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[8]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[11:9]	No	No		No		OUTPUT
data_o[15:12]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[17]	Yes	Yes	*T86,*T87,*T88	Yes	T12,T130,T86	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[19]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[23:21]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[26:25]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[27]	No	No		No		OUTPUT
data_o[29:28]	Yes	Yes	T86,T87,T88	Yes	T12,T130,T86	OUTPUT
data_o[31:30]	No	No		No		OUTPUT
data_o[32]	Yes	Yes	*T86,*T87,*T88	Yes	T12,T130,T86	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[36:34]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[38]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[40:39]	No	No		No		OUTPUT
data_o[44:41]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[45]	No	No		No		OUTPUT
data_o[46]	Yes	Yes	*T86,*T87,*T88	Yes	T12,T130,T86	OUTPUT
data_o[48:47]	No	No		No		OUTPUT
data_o[56:49]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[58:57]	No	No		No		OUTPUT
data_o[61:59]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[63:62]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	180	66.18
Total Bits 0->1	136	90	66.18
Total Bits 1->0	136	90	66.18

Ports	2	0	0.00
Port Bits	272	180	66.18
Port Bits 0->1	136	90	66.18
Port Bits 1->0	136	90	66.18

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[3:1]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[4]	No	No		No		INPUT
data_i[6:5]	Yes	Yes	*T106,*T6,*T13	Yes	T106,T5,T6	INPUT
data_i[8:7]	No	No		No		INPUT
data_i[15:9]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[16]	No	No		No		INPUT
data_i[17]	Yes	Yes	*T86,*T87,*T88	Yes	T12,T86,T87	INPUT
data_i[18]	No	No		No		INPUT
data_i[19]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[21:20]	No	No		No		INPUT
data_i[24:22]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[26:25]	No	No		No		INPUT
data_i[28:27]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[29]	No	No		No		INPUT
data_i[30]	Yes	Yes	*T86,*T87,*T88	Yes	T12,T86,T87	INPUT
data_i[34:31]	No	No		No		INPUT
data_i[42:35]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[43]	No	No		No		INPUT
data_i[45:44]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[46]	No	No		No		INPUT
data_i[47]	Yes	Yes	*T86,*T87,*T88	Yes	T12,T86,T87	INPUT
data_i[48]	No	No		No		INPUT
data_i[53:49]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[54]	No	No		No		INPUT
data_i[55]	Yes	Yes	*T86,*T87,*T88	Yes	T12,T86,T87	INPUT
data_i[59:56]	No	No		No		INPUT
data_i[71:60]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[3:1]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[6:5]	Yes	Yes	*T106,*T6,*T13	Yes	T106,T5,T6	OUTPUT
data_o[8:7]	No	No		No		OUTPUT
data_o[15:9]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[17]	Yes	Yes	*T86,*T87,*T88	Yes	T12,T86,T87	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[19]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[21:20]	No	No		No		OUTPUT
data_o[24:22]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[26:25]	No	No		No		OUTPUT
data_o[28:27]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[30]	Yes	Yes	*T86,*T87,*T88	Yes	T12,T86,T87	OUTPUT
data_o[34:31]	No	No		No		OUTPUT
data_o[42:35]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[45:44]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[47]	Yes	Yes	*T86,*T87,*T88	Yes	T12,T86,T87	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[53:49]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[55]	Yes	Yes	*T86,*T87,*T88	Yes	T12,T86,T87	OUTPUT
data_o[59:56]	No	No		No		OUTPUT
data_o[63:60]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	190	69.85
Total Bits 0->1	136	95	69.85
Total Bits 1->0	136	95	69.85

Ports	2	0	0.00
Port Bits	272	190	69.85
Port Bits 0->1	136	95	69.85
Port Bits 1->0	136	95	69.85

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[1:0]	No	No		No		INPUT
data_i[3:2]	Yes	Yes	T86,T87,T88	Yes	T12,T130,T86	INPUT
data_i[5:4]	No	No		No		INPUT
data_i[10:6]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[11]	No	No		No		INPUT
data_i[14:12]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[15]	No	No		No		INPUT
data_i[22:16]	Yes	Yes	T86,T87,T88	Yes	T12,T130,T86	INPUT
data_i[23]	No	No		No		INPUT
data_i[25:24]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[26]	No	No		No		INPUT
data_i[28:27]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[31:29]	No	No		No		INPUT
data_i[34:32]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[35]	No	No		No		INPUT
data_i[36]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[37]	No	No		No		INPUT
data_i[42:38]	Yes	Yes	T86,T87,T88	Yes	T12,T86,T87	INPUT
data_i[43]	No	No		No		INPUT
data_i[46:44]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[48:47]	No	No		No		INPUT
data_i[51:49]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[52]	No	No		No		INPUT
data_i[53]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[54]	No	No		No		INPUT
data_i[56:55]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[58:57]	No	No		No		INPUT
data_i[70:59]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[71]	No	No		No		INPUT
data_o[1:0]	No	No		No		OUTPUT
data_o[3:2]	Yes	Yes	T86,T87,T88	Yes	T12,T130,T86	OUTPUT
data_o[5:4]	No	No		No		OUTPUT
data_o[10:6]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[14:12]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[22:16]	Yes	Yes	T86,T87,T88	Yes	T12,T130,T86	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[25:24]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[28:27]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[31:29]	No	No		No		OUTPUT
data_o[34:32]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[36]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[42:38]	Yes	Yes	T86,T87,T88	Yes	T12,T86,T87	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[46:44]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[48:47]	No	No		No		OUTPUT
data_o[51:49]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[53]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[56:55]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[58:57]	No	No		No		OUTPUT
data_o[63:59]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	194	71.32
Total Bits 0->1	136	97	71.32
Total Bits 1->0	136	97	71.32

Ports	2	0	0.00
Port Bits	272	194	71.32
Port Bits 0->1	136	97	71.32
Port Bits 1->0	136	97	71.32

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[2:1]	No	No		No		INPUT
data_i[3]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[4]	No	No		No		INPUT
data_i[8:5]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[9]	No	No		No		INPUT
data_i[11:10]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[13:12]	No	No		No		INPUT
data_i[16:14]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[17]	No	No		No		INPUT
data_i[22:18]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[24:23]	No	No		No		INPUT
data_i[26:25]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[27]	No	No		No		INPUT
data_i[33:28]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[34]	No	No		No		INPUT
data_i[35]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[36]	No	No		No		INPUT
data_i[42:37]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[43]	No	No		No		INPUT
data_i[46:44]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[48:47]	No	No		No		INPUT
data_i[50:49]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T13	INPUT
data_i[52:51]	No	No		No		INPUT
data_i[57:53]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[58]	No	No		No		INPUT
data_i[60:59]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T13	INPUT
data_i[61]	No	No		No		INPUT
data_i[63:62]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[64]	No	No		No		INPUT
data_i[71:65]	Yes	Yes	T129,T244,T284	Yes	T129,T244,T285	INPUT
data_o[0]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[2:1]	No	No		No		OUTPUT
data_o[3]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[8:5]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[11:10]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[13:12]	No	No		No		OUTPUT
data_o[16:14]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[22:18]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[24:23]	No	No		No		OUTPUT
data_o[26:25]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[27]	No	No		No		OUTPUT
data_o[33:28]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[34]	No	No		No		OUTPUT
data_o[35]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[36]	No	No		No		OUTPUT
data_o[42:37]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[46:44]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[48:47]	No	No		No		OUTPUT
data_o[50:49]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T13	OUTPUT
data_o[52:51]	No	No		No		OUTPUT
data_o[57:53]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[60:59]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T13	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	196	72.06
Total Bits 0->1	136	98	72.06
Total Bits 1->0	136	98	72.06

Ports	2	0	0.00
Port Bits	272	196	72.06
Port Bits 0->1	136	98	72.06
Port Bits 1->0	136	98	72.06

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[3:1]	Yes	Yes	T6,T13,T130	Yes	T6,T12,T13	INPUT
data_i[4]	No	No		No		INPUT
data_i[5]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[7:6]	No	No		No		INPUT
data_i[19:8]	Yes	Yes	T6,*T13,*T130	Yes	T6,T12,T13	INPUT
data_i[20]	No	No		No		INPUT
data_i[23:21]	Yes	Yes	T6,T86,T87	Yes	T6,T12,T130	INPUT
data_i[25:24]	No	No		No		INPUT
data_i[26]	Yes	Yes	*T6,*T86,*T87	Yes	T6,T12,T130	INPUT
data_i[28:27]	No	No		No		INPUT
data_i[33:29]	Yes	Yes	T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[34]	No	No		No		INPUT
data_i[38:35]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[40:39]	No	No		No		INPUT
data_i[44:41]	Yes	Yes	T6,T86,T87	Yes	T6,T12,T130	INPUT
data_i[46:45]	No	No		No		INPUT
data_i[48:47]	Yes	Yes	*T6,T86,T87	Yes	T6,T12,T130	INPUT
data_i[49]	No	No		No		INPUT
data_i[53:50]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[54]	No	No		No		INPUT
data_i[56:55]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[57]	No	No		No		INPUT
data_i[58]	Yes	Yes	*T86,*T87,*T88	Yes	T12,T130,T86	INPUT
data_i[60:59]	No	No		No		INPUT
data_i[71:61]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[3:1]	Yes	Yes	T6,T13,T130	Yes	T6,T12,T13	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[5]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[7:6]	No	No		No		OUTPUT
data_o[19:8]	Yes	Yes	T6,*T13,*T130	Yes	T6,T12,T13	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[23:21]	Yes	Yes	T6,T86,T87	Yes	T6,T12,T130	OUTPUT
data_o[25:24]	No	No		No		OUTPUT
data_o[26]	Yes	Yes	*T6,*T86,*T87	Yes	T6,T12,T130	OUTPUT
data_o[28:27]	No	No		No		OUTPUT
data_o[33:29]	Yes	Yes	T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[34]	No	No		No		OUTPUT
data_o[38:35]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[40:39]	No	No		No		OUTPUT
data_o[44:41]	Yes	Yes	T6,T86,T87	Yes	T6,T12,T130	OUTPUT
data_o[46:45]	No	No		No		OUTPUT
data_o[48:47]	Yes	Yes	*T6,T86,T87	Yes	T6,T12,T130	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[53:50]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[56:55]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[57]	No	No		No		OUTPUT
data_o[58]	Yes	Yes	*T86,*T87,*T88	Yes	T12,T130,T86	OUTPUT
data_o[60:59]	No	No		No		OUTPUT
data_o[63:61]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	200	73.53
Total Bits 0->1	136	100	73.53
Total Bits 1->0	136	100	73.53

Ports	2	0	0.00
Port Bits	272	200	73.53
Port Bits 0->1	136	100	73.53
Port Bits 1->0	136	100	73.53

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[4:1]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[5]	No	No		No		INPUT
data_i[10:6]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[11]	No	No		No		INPUT
data_i[15:12]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[16]	No	No		No		INPUT
data_i[23:17]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[24]	No	No		No		INPUT
data_i[26:25]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[27]	No	No		No		INPUT
data_i[29:28]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[30]	No	No		No		INPUT
data_i[35:31]	Yes	Yes	T6,T13,*T130	Yes	T5,T6,T13	INPUT
data_i[37:36]	No	No		No		INPUT
data_i[38]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[39]	No	No		No		INPUT
data_i[42:40]	Yes	Yes	T6,T13,T86	Yes	T5,T6,T13	INPUT
data_i[44:43]	No	No		No		INPUT
data_i[46:45]	Yes	Yes	T6,T13,T86	Yes	T5,T6,T13	INPUT
data_i[47]	No	No		No		INPUT
data_i[48]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[50:49]	No	No		No		INPUT
data_i[55:51]	Yes	Yes	T6,T13,*T130	Yes	T5,T6,T12	INPUT
data_i[56]	No	No		No		INPUT
data_i[59:57]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[60]	No	No		No		INPUT
data_i[62:61]	Yes	Yes	T6,T13,T86	Yes	T5,T6,T13	INPUT
data_i[63]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T6,T13,T86	Yes	T5,T6,T12	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[4:1]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[10:6]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[15:12]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[23:17]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[26:25]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[27]	No	No		No		OUTPUT
data_o[29:28]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[30]	No	No		No		OUTPUT
data_o[35:31]	Yes	Yes	T6,T13,*T130	Yes	T5,T6,T13	OUTPUT
data_o[37:36]	No	No		No		OUTPUT
data_o[38]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[42:40]	Yes	Yes	T6,T13,T86	Yes	T5,T6,T13	OUTPUT
data_o[44:43]	No	No		No		OUTPUT
data_o[46:45]	Yes	Yes	T6,T13,T86	Yes	T5,T6,T13	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[48]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[50:49]	No	No		No		OUTPUT
data_o[55:51]	Yes	Yes	T6,T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[59:57]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[62:61]	Yes	Yes	T6,T13,T86	Yes	T5,T6,T13	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	200	73.53
Total Bits 0->1	136	100	73.53
Total Bits 1->0	136	100	73.53

Ports	2	0	0.00
Port Bits	272	200	73.53
Port Bits 0->1	136	100	73.53
Port Bits 1->0	136	100	73.53

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	No	No		No		INPUT
data_i[6:3]	Yes	Yes	T6,T13,*T130	Yes	T5,T6,T12	INPUT
data_i[7]	No	No		No		INPUT
data_i[8]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[10:9]	No	No		No		INPUT
data_i[18:11]	Yes	Yes	T6,T13,T86	Yes	T5,T6,T13	INPUT
data_i[19]	No	No		No		INPUT
data_i[23:20]	Yes	Yes	T6,T86,T87	Yes	T5,T6,T130	INPUT
data_i[24]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T6,*T86,*T87	Yes	T5,T6,T130	INPUT
data_i[26]	No	No		No		INPUT
data_i[28:27]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[29]	No	No		No		INPUT
data_i[30]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[31]	No	No		No		INPUT
data_i[40:32]	Yes	Yes	T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[41]	No	No		No		INPUT
data_i[42]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[43]	No	No		No		INPUT
data_i[49:44]	Yes	Yes	T6,T86,T87	Yes	T5,T6,T130	INPUT
data_i[51:50]	No	No		No		INPUT
data_i[52]	Yes	Yes	*T6,*T86,*T87	Yes	T6,T130,T86	INPUT
data_i[53]	No	No		No		INPUT
data_i[54]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[55]	No	No		No		INPUT
data_i[56]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[57]	No	No		No		INPUT
data_i[71:58]	Yes	Yes	T6,T86,T87	Yes	T6,T130,T86	INPUT
data_o[2:0]	No	No		No		OUTPUT
data_o[6:3]	Yes	Yes	T6,T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[8]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[10:9]	No	No		No		OUTPUT
data_o[18:11]	Yes	Yes	T6,T13,T86	Yes	T5,T6,T13	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[23:20]	Yes	Yes	T6,T86,T87	Yes	T5,T6,T130	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T6,*T86,*T87	Yes	T5,T6,T130	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[28:27]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[30]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[40:32]	Yes	Yes	T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[42]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[49:44]	Yes	Yes	T6,T86,T87	Yes	T5,T6,T130	OUTPUT
data_o[51:50]	No	No		No		OUTPUT
data_o[52]	Yes	Yes	*T6,*T86,*T87	Yes	T6,T130,T86	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[54]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[56]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[57]	No	No		No		OUTPUT
data_o[63:58]	Yes	Yes	T6,T86,T87	Yes	T6,T130,T86	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	204	75.00
Total Bits 0->1	136	102	75.00
Total Bits 1->0	136	102	75.00

Ports	2	0	0.00
Port Bits	272	204	75.00
Port Bits 0->1	136	102	75.00
Port Bits 1->0	136	102	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[3]	No	No		No		INPUT
data_i[6:4]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[8:7]	No	No		No		INPUT
data_i[17:9]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[18]	No	No		No		INPUT
data_i[19]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[20]	No	No		No		INPUT
data_i[23:21]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[25:24]	No	No		No		INPUT
data_i[28:26]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[31]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[32]	No	No		No		INPUT
data_i[34:33]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[35]	No	No		No		INPUT
data_i[37:36]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[38]	No	No		No		INPUT
data_i[44:39]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[45]	No	No		No		INPUT
data_i[46]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[48:47]	No	No		No		INPUT
data_i[49]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[50]	No	No		No		INPUT
data_i[55:51]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[56]	No	No		No		INPUT
data_i[71:57]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_o[2:0]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[6:4]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[8:7]	No	No		No		OUTPUT
data_o[17:9]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[19]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[23:21]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[25:24]	No	No		No		OUTPUT
data_o[28:26]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[31]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[34:33]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[37:36]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[44:39]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[45]	No	No		No		OUTPUT
data_o[46]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[48:47]	No	No		No		OUTPUT
data_o[49]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[55:51]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[63:57]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	204	75.00
Total Bits 0->1	136	102	75.00
Total Bits 1->0	136	102	75.00

Ports	2	0	0.00
Port Bits	272	204	75.00
Port Bits 0->1	136	102	75.00
Port Bits 1->0	136	102	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[4:0]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T13	INPUT
data_i[5]	No	No		No		INPUT
data_i[8:6]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T13	INPUT
data_i[9]	No	No		No		INPUT
data_i[12:10]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[13]	No	No		No		INPUT
data_i[14]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[15]	No	No		No		INPUT
data_i[17:16]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[18]	No	No		No		INPUT
data_i[22:19]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T13	INPUT
data_i[23]	No	No		No		INPUT
data_i[24]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T13	INPUT
data_i[27:25]	No	No		No		INPUT
data_i[28]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[29]	No	No		No		INPUT
data_i[32:30]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[34:33]	No	No		No		INPUT
data_i[42:35]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T13	INPUT
data_i[44:43]	No	No		No		INPUT
data_i[50:45]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T13	INPUT
data_i[53:51]	No	No		No		INPUT
data_i[71:54]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T13	INPUT
data_o[4:0]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T13	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[8:6]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T13	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[12:10]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[14]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[17:16]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[22:19]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T13	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[24]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T13	OUTPUT
data_o[27:25]	No	No		No		OUTPUT
data_o[28]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[32:30]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[34:33]	No	No		No		OUTPUT
data_o[42:35]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T13	OUTPUT
data_o[44:43]	No	No		No		OUTPUT
data_o[50:45]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T13	OUTPUT
data_o[53:51]	No	No		No		OUTPUT
data_o[63:54]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T13	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	204	75.00
Total Bits 0->1	136	102	75.00
Total Bits 1->0	136	102	75.00

Ports	2	0	0.00
Port Bits	272	204	75.00
Port Bits 0->1	136	102	75.00
Port Bits 1->0	136	102	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	Yes	Yes	T6,T86,T87	Yes	T6,T130,T86	INPUT
data_i[3]	No	No		No		INPUT
data_i[8:4]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[12:9]	No	No		No		INPUT
data_i[15:13]	Yes	Yes	T6,T86,T87	Yes	T6,T130,T86	INPUT
data_i[17:16]	No	No		No		INPUT
data_i[23:18]	Yes	Yes	T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[25:24]	No	No		No		INPUT
data_i[32:26]	Yes	Yes	T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[33]	No	No		No		INPUT
data_i[36:34]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[37]	No	No		No		INPUT
data_i[38]	Yes	Yes	*T6,*T86,*T87	Yes	T6,T130,T86	INPUT
data_i[39]	No	No		No		INPUT
data_i[43:40]	Yes	Yes	T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[44]	No	No		No		INPUT
data_i[51:45]	Yes	Yes	T6,T86,T87	Yes	T6,T130,T86	INPUT
data_i[52]	No	No		No		INPUT
data_i[57:53]	Yes	Yes	T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[58]	No	No		No		INPUT
data_i[59]	Yes	Yes	*T6,*T86,*T87	Yes	T6,T130,T86	INPUT
data_i[61:60]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T6,T86,T87	Yes	T6,T130,T86	INPUT
data_o[2:0]	Yes	Yes	T6,T86,T87	Yes	T6,T130,T86	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[8:4]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[12:9]	No	No		No		OUTPUT
data_o[15:13]	Yes	Yes	T6,T86,T87	Yes	T6,T130,T86	OUTPUT
data_o[17:16]	No	No		No		OUTPUT
data_o[23:18]	Yes	Yes	T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[25:24]	No	No		No		OUTPUT
data_o[32:26]	Yes	Yes	T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[36:34]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[38]	Yes	Yes	*T6,*T86,*T87	Yes	T6,T130,T86	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[43:40]	Yes	Yes	T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[51:45]	Yes	Yes	T6,T86,T87	Yes	T6,T130,T86	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[57:53]	Yes	Yes	T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[59]	Yes	Yes	*T6,*T86,*T87	Yes	T6,T130,T86	OUTPUT
data_o[61:60]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T6,T86,T87	Yes	T6,T130,T86	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	204	75.00
Total Bits 0->1	136	102	75.00
Total Bits 1->0	136	102	75.00

Ports	2	0	0.00
Port Bits	272	204	75.00
Port Bits 0->1	136	102	75.00
Port Bits 1->0	136	102	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	Yes	Yes	T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[3]	No	No		No		INPUT
data_i[5:4]	Yes	Yes	T6,T86,T87	Yes	T6,T130,T86	INPUT
data_i[6]	No	No		No		INPUT
data_i[7]	Yes	Yes	*T6,*T86,*T87	Yes	T6,T130,T86	INPUT
data_i[8]	No	No		No		INPUT
data_i[11:9]	Yes	Yes	T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[13:12]	No	No		No		INPUT
data_i[25:14]	Yes	Yes	T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[26]	No	No		No		INPUT
data_i[28:27]	Yes	Yes	T6,T86,T87	Yes	T6,T130,T86	INPUT
data_i[29]	No	No		No		INPUT
data_i[33:30]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[34]	No	No		No		INPUT
data_i[38:35]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[39]	No	No		No		INPUT
data_i[41:40]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[42]	No	No		No		INPUT
data_i[43]	Yes	Yes	*T87,*T88,*T19	Yes	T130,T87,T88	INPUT
data_i[44]	No	No		No		INPUT
data_i[45]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	INPUT
data_i[46]	No	No		No		INPUT
data_i[49:47]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	INPUT
data_i[50]	No	No		No		INPUT
data_i[51]	Yes	Yes	*T87,*T88,*T19	Yes	T87,T88,T19	INPUT
data_i[52]	No	No		No		INPUT
data_i[53]	Yes	Yes	*T87,*T88,*T19	Yes	T87,T88,T19	INPUT
data_i[54]	No	No		No		INPUT
data_i[61:55]	Yes	Yes	T87,T88,T19	Yes	T87,T88,T19	INPUT
data_i[63:62]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T13,T130,T86	Yes	T5,T12,T13	INPUT
data_o[2:0]	Yes	Yes	T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[5:4]	Yes	Yes	T6,T86,T87	Yes	T6,T130,T86	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[7]	Yes	Yes	*T6,*T86,*T87	Yes	T6,T130,T86	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[11:9]	Yes	Yes	T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[13:12]	No	No		No		OUTPUT
data_o[25:14]	Yes	Yes	T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[28:27]	Yes	Yes	T6,T86,T87	Yes	T6,T130,T86	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[33:30]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[34]	No	No		No		OUTPUT
data_o[38:35]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[41:40]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[42]	No	No		No		OUTPUT
data_o[43]	Yes	Yes	*T87,*T88,*T19	Yes	T130,T87,T88	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[45]	Yes	Yes	*T6,*T13,*T130	Yes	T5,T6,T12	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[49:47]	Yes	Yes	T6,T13,T130	Yes	T5,T6,T12	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[51]	Yes	Yes	*T87,*T88,*T19	Yes	T87,T88,T19	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[53]	Yes	Yes	*T87,*T88,*T19	Yes	T87,T88,T19	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[61:55]	Yes	Yes	T87,T88,T19	Yes	T87,T88,T19	OUTPUT
data_o[63:62]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T11,T86	Yes	T5,T11,T86	INPUT
data_o[63:0]	Yes	Yes	T5,T11,T86	Yes	T5,T11,T86	OUTPUT
syndrome_o[2:0]	Yes	Yes	T149	Yes	T149	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T149	Yes	T149	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T11,T88,T19	Yes	T11,T88,T19	INPUT
data_o[63:0]	Yes	Yes	T11,T88,T19	Yes	T11,T88,T19	OUTPUT
syndrome_o[2:0]	Yes	Yes	T102,T149	Yes	T102,T149	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T102,*T149	Yes	T102,T149	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T19,T145,T122	Yes	T19,T145,T122	INPUT
data_o[63:0]	Yes	Yes	T19,T145,T122	Yes	T19,T145,T122	OUTPUT
syndrome_o[2:0]	Yes	Yes	T149	Yes	T149	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T149	Yes	T149	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T88,T116	Yes	T5,T88,T116	INPUT
data_o[63:0]	Yes	Yes	T5,T88,T116	Yes	T5,T88,T116	OUTPUT
syndrome_o[2:0]	Yes	Yes	T102,T149	Yes	T102,T149	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T102,*T149	Yes	T102,T149	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T11,T86,T66	Yes	T11,T86,T66	INPUT
data_o[63:0]	Yes	Yes	T11,T86,T66	Yes	T11,T86,T66	OUTPUT
syndrome_o[7:0]	Excluded	Excluded	T102,T149	Excluded	T102,T149	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded	T102,T149	Excluded	T102,T149	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T229,T286,T59	Yes	T229,T286,T59	INPUT
data_o[63:0]	Yes	Yes	T229,T286,T59	Yes	T229,T286,T59	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T287,T47,T280	Yes	T287,T47,T280	INPUT
data_o[63:0]	Yes	Yes	T287,T47,T280	Yes	T287,T47,T280	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T86,T88,T61	Yes	T86,T88,T61	INPUT
data_o[63:0]	Yes	Yes	T86,T88,T61	Yes	T86,T88,T61	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T88,T66,T100	Yes	T88,T66,T288	INPUT
data_o[63:0]	Yes	Yes	T88,T66,T100	Yes	T88,T66,T288	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T262,T280,T286	Yes	T262,T280,T286	INPUT
data_o[63:0]	Yes	Yes	T262,T280,T286	Yes	T262,T280,T286	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T13,T153,T164	Yes	T13,T153,T289	INPUT
data_o[63:0]	Yes	Yes	T13,T153,T164	Yes	T13,T153,T289	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T117,T194,T290	Yes	T117,T194,T290	INPUT
data_o[63:0]	Yes	Yes	T117,T194,T290	Yes	T117,T194,T290	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T118,T204,T291	Yes	T118,T204,T292	INPUT
data_o[63:0]	Yes	Yes	T118,T204,T291	Yes	T118,T204,T292	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T125,T117,T118	Yes	T125,T117,T118	INPUT
data_o[63:0]	Yes	Yes	T125,T117,T118	Yes	T125,T117,T118	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T13,T86,T88	Yes	T13,T86,T88	INPUT
data_o[63:0]	Yes	Yes	T13,T86,T88	Yes	T13,T86,T88	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T6,T13	Yes	T5,T6,T13	INPUT
data_o[63:0]	Yes	Yes	T5,T6,T13	Yes	T5,T6,T13	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T6,T87	Yes	T5,T6,T12	INPUT
data_o[63:0]	Yes	Yes	T5,T6,T87	Yes	T5,T6,T12	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T6,T11,T13	Yes	T6,T11,T13	INPUT
data_o[63:0]	Yes	Yes	T6,T11,T13	Yes	T6,T11,T13	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T7,T122,T128	Yes	T7,T130,T122	INPUT
data_o[63:0]	Yes	Yes	T7,T122,T128	Yes	T7,T130,T122	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T4,T145,T118	Yes	T4,T145,T118	INPUT
data_o[63:0]	Yes	Yes	T4,T145,T118	Yes	T4,T145,T118	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T4,T117,T195	Yes	T4,T117,T195	INPUT
data_o[63:0]	Yes	Yes	T4,T117,T195	Yes	T4,T117,T195	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T18,T116,T118	Yes	T18,T116,T118	INPUT
data_o[63:0]	Yes	Yes	T18,T116,T118	Yes	T18,T116,T118	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T118,T199,T204	Yes	T118,T197,T199	INPUT
data_o[63:0]	Yes	Yes	T118,T199,T204	Yes	T118,T197,T199	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T6,T88,T116	Yes	T6,T88,T116	INPUT
data_o[63:0]	Yes	Yes	T6,T88,T116	Yes	T6,T88,T116	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T204,T135,T205	Yes	T199,T201,T204	INPUT
data_o[63:0]	Yes	Yes	T204,T135,T205	Yes	T199,T201,T204	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T86,T118,T199	Yes	T86,T118,T199	INPUT
data_o[63:0]	Yes	Yes	T86,T118,T199	Yes	T86,T118,T199	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T13,T66,T121	Yes	T13,T66,T121	INPUT
data_o[63:0]	Yes	Yes	T13,T66,T121	Yes	T13,T66,T121	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T6,T116,T92	Yes	T6,T116,T194	INPUT
data_o[63:0]	Yes	Yes	T6,T116,T92	Yes	T6,T116,T194	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T66,T293,T45	Yes	T66,T293,T45	INPUT
data_o[63:0]	Yes	Yes	T66,T293,T45	Yes	T66,T293,T45	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T117,T199	Yes	T2,T117,T194	INPUT
data_o[63:0]	Yes	Yes	T2,T117,T199	Yes	T2,T117,T194	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T4,T119,T127	Yes	T4,T119,T127	INPUT
data_o[63:0]	Yes	Yes	T4,T119,T127	Yes	T4,T119,T127	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T4,T13,T61	Yes	T4,T13,T61	INPUT
data_o[63:0]	Yes	Yes	T4,T13,T61	Yes	T4,T13,T61	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T121,T95,T129	Yes	T121,T95,T129	INPUT
data_o[63:0]	Yes	Yes	T121,T95,T129	Yes	T121,T95,T129	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T7,T86,T66	Yes	T7,T86,T66	INPUT
data_o[63:0]	Yes	Yes	T7,T86,T66	Yes	T7,T86,T66	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T117,T122,T205	Yes	T117,T122,T205	INPUT
data_o[63:0]	Yes	Yes	T117,T122,T205	Yes	T117,T122,T205	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T4,T118,T194	Yes	T4,T118,T194	INPUT
data_o[63:0]	Yes	Yes	T4,T118,T194	Yes	T4,T118,T194	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T13,T117,T100	Yes	T11,T13,T117	INPUT
data_o[63:0]	Yes	Yes	T13,T117,T100	Yes	T11,T13,T117	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T86,T117,T199	Yes	T86,T117,T199	INPUT
data_o[63:0]	Yes	Yes	T86,T117,T199	Yes	T86,T117,T199	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T86,T66,T117	Yes	T86,T66,T117	INPUT
data_o[63:0]	Yes	Yes	T86,T66,T117	Yes	T86,T66,T117	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR