| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 94.95 | 93.71 | 96.70 | 95.53 | 91.81 | 97.51 | 96.34 | 93.07 |
| T1254 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2350030588 | Sep 11 12:57:10 PM UTC 24 | Sep 11 12:57:14 PM UTC 24 | 71628460 ps | ||
| T1255 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.354418986 | Sep 11 12:57:10 PM UTC 24 | Sep 11 12:57:14 PM UTC 24 | 1027212973 ps | ||
| T1256 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.3601171637 | Sep 11 12:57:11 PM UTC 24 | Sep 11 12:57:14 PM UTC 24 | 152654725 ps | ||
| T1257 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.2425967872 | Sep 11 12:57:15 PM UTC 24 | Sep 11 12:57:18 PM UTC 24 | 71792660 ps | ||
| T1258 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.2548201342 | Sep 11 12:57:11 PM UTC 24 | Sep 11 12:57:14 PM UTC 24 | 39791915 ps | ||
| T1259 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1793224585 | Sep 11 12:57:09 PM UTC 24 | Sep 11 12:57:15 PM UTC 24 | 409509155 ps | ||
| T1260 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.3099752051 | Sep 11 12:57:13 PM UTC 24 | Sep 11 12:57:15 PM UTC 24 | 562732856 ps | ||
| T1261 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.310720290 | Sep 11 12:57:12 PM UTC 24 | Sep 11 12:57:15 PM UTC 24 | 572305858 ps | ||
| T1262 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.1552733948 | Sep 11 12:57:13 PM UTC 24 | Sep 11 12:57:16 PM UTC 24 | 40190529 ps | ||
| T1263 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.1503736073 | Sep 11 12:57:13 PM UTC 24 | Sep 11 12:57:16 PM UTC 24 | 85367078 ps | ||
| T1264 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.258082379 | Sep 11 12:57:14 PM UTC 24 | Sep 11 12:57:17 PM UTC 24 | 589403264 ps | ||
| T1265 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1558396760 | Sep 11 12:57:07 PM UTC 24 | Sep 11 12:57:17 PM UTC 24 | 402755064 ps | ||
| T1266 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.1372586380 | Sep 11 12:57:14 PM UTC 24 | Sep 11 12:57:17 PM UTC 24 | 52419194 ps | ||
| T1267 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2930474039 | Sep 11 12:57:09 PM UTC 24 | Sep 11 12:57:17 PM UTC 24 | 1191809904 ps | ||
| T1268 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.3435623930 | Sep 11 12:57:14 PM UTC 24 | Sep 11 12:57:17 PM UTC 24 | 551192318 ps | ||
| T1269 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.438582044 | Sep 11 12:57:14 PM UTC 24 | Sep 11 12:57:17 PM UTC 24 | 40212271 ps | ||
| T1270 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.2466248058 | Sep 11 12:57:14 PM UTC 24 | Sep 11 12:57:17 PM UTC 24 | 39756262 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.1656794499 | Sep 11 12:57:14 PM UTC 24 | Sep 11 12:57:17 PM UTC 24 | 135289558 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.3352872841 | Sep 11 12:57:14 PM UTC 24 | Sep 11 12:57:18 PM UTC 24 | 90553551 ps | ||
| T1273 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.4171839744 | Sep 11 12:57:14 PM UTC 24 | Sep 11 12:57:18 PM UTC 24 | 43437972 ps | ||
| T1274 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.3039067754 | Sep 11 12:57:14 PM UTC 24 | Sep 11 12:57:18 PM UTC 24 | 41570770 ps | ||
| T1275 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2244664651 | Sep 11 12:57:04 PM UTC 24 | Sep 11 12:57:18 PM UTC 24 | 1694819518 ps | ||
| T1276 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.2793910926 | Sep 11 12:57:15 PM UTC 24 | Sep 11 12:57:18 PM UTC 24 | 40672309 ps | ||
| T1277 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.3890459494 | Sep 11 12:57:15 PM UTC 24 | Sep 11 12:57:19 PM UTC 24 | 39607846 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1068819893 | Sep 11 12:56:51 PM UTC 24 | Sep 11 12:57:19 PM UTC 24 | 20316282643 ps | ||
| T1278 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.4094850761 | Sep 11 12:57:17 PM UTC 24 | Sep 11 12:57:19 PM UTC 24 | 144106474 ps | ||
| T1279 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.3270193670 | Sep 11 12:57:17 PM UTC 24 | Sep 11 12:57:20 PM UTC 24 | 37112058 ps | ||
| T1280 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.738627449 | Sep 11 12:57:17 PM UTC 24 | Sep 11 12:57:20 PM UTC 24 | 154730374 ps | ||
| T1281 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.3336008183 | Sep 11 12:57:17 PM UTC 24 | Sep 11 12:57:20 PM UTC 24 | 45537950 ps | ||
| T1282 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.9415274 | Sep 11 12:57:17 PM UTC 24 | Sep 11 12:57:20 PM UTC 24 | 550257936 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.3649996253 | Sep 11 12:56:59 PM UTC 24 | Sep 11 12:57:20 PM UTC 24 | 1177992360 ps | ||
| T1283 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.1877218088 | Sep 11 12:57:18 PM UTC 24 | Sep 11 12:57:21 PM UTC 24 | 75125629 ps | ||
| T1284 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.1715125918 | Sep 11 12:57:19 PM UTC 24 | Sep 11 12:57:21 PM UTC 24 | 74377951 ps | ||
| T1285 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.2223580978 | Sep 11 12:57:18 PM UTC 24 | Sep 11 12:57:21 PM UTC 24 | 39365221 ps | ||
| T1286 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.440306602 | Sep 11 12:57:18 PM UTC 24 | Sep 11 12:57:22 PM UTC 24 | 71251309 ps | ||
| T1287 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.2647648661 | Sep 11 12:57:18 PM UTC 24 | Sep 11 12:57:22 PM UTC 24 | 571845220 ps | ||
| T1288 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.1657375458 | Sep 11 12:57:18 PM UTC 24 | Sep 11 12:57:22 PM UTC 24 | 592413971 ps | ||
| T1289 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.959361345 | Sep 11 12:56:59 PM UTC 24 | Sep 11 12:57:24 PM UTC 24 | 4751827146 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.3301441727 | Sep 11 12:57:06 PM UTC 24 | Sep 11 12:57:28 PM UTC 24 | 5888917410 ps | ||
| T1290 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.4252726402 | Sep 11 12:57:08 PM UTC 24 | Sep 11 12:57:31 PM UTC 24 | 2565699421 ps | ||
| T1291 | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2880027458 | Sep 11 12:57:10 PM UTC 24 | Sep 11 12:57:34 PM UTC 24 | 2974020265 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_regwen.3174227046 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4132053182 ps |
| CPU time | 12.56 seconds |
| Started | Sep 11 12:57:20 PM UTC 24 |
| Finished | Sep 11 12:57:34 PM UTC 24 |
| Peak memory | 253392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174227046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.3174227046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_background_chks.2042474216 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 585007500 ps |
| CPU time | 16.29 seconds |
| Started | Sep 11 12:57:19 PM UTC 24 |
| Finished | Sep 11 12:57:36 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042474216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.2042474216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.1304074231 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 15859129075 ps |
| CPU time | 66.68 seconds |
| Started | Sep 11 12:57:21 PM UTC 24 |
| Finished | Sep 11 12:58:29 PM UTC 24 |
| Peak memory | 257612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1304074231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.otp_ctrl_stress_all_with_rand_reset.1304074231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_test_access.1224788626 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 770048914 ps |
| CPU time | 18.83 seconds |
| Started | Sep 11 12:57:21 PM UTC 24 |
| Finished | Sep 11 12:57:41 PM UTC 24 |
| Peak memory | 250972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224788626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.1224788626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_check_fail.57517732 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2073487650 ps |
| CPU time | 23.49 seconds |
| Started | Sep 11 12:57:36 PM UTC 24 |
| Finished | Sep 11 12:58:01 PM UTC 24 |
| Peak memory | 255736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57517732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.57517732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all.2650103399 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 12355420692 ps |
| CPU time | 103.59 seconds |
| Started | Sep 11 12:57:29 PM UTC 24 |
| Finished | Sep 11 12:59:15 PM UTC 24 |
| Peak memory | 255404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650103399 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.2650103399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all.3310486571 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 6202231789 ps |
| CPU time | 168.07 seconds |
| Started | Sep 11 12:57:49 PM UTC 24 |
| Finished | Sep 11 01:00:40 PM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310486571 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.3310486571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_init_fail.183397252 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 616202588 ps |
| CPU time | 4.4 seconds |
| Started | Sep 11 12:57:23 PM UTC 24 |
| Finished | Sep 11 12:57:28 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183397252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.183397252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.3069705649 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2801239925 ps |
| CPU time | 84.37 seconds |
| Started | Sep 11 12:57:58 PM UTC 24 |
| Finished | Sep 11 12:59:25 PM UTC 24 |
| Peak memory | 267816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3069705649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.otp_ctrl_stress_all_with_rand_reset.3069705649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.1257154360 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 2100381838 ps |
| CPU time | 3.97 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:52 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257154360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.1257154360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/233.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_sec_cm.3987759603 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 21653145560 ps |
| CPU time | 198.53 seconds |
| Started | Sep 11 12:57:39 PM UTC 24 |
| Finished | Sep 11 01:01:01 PM UTC 24 |
| Peak memory | 298164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987759603 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.3987759603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all.4127706510 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 8852042323 ps |
| CPU time | 64.88 seconds |
| Started | Sep 11 12:58:12 PM UTC 24 |
| Finished | Sep 11 12:59:19 PM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127706510 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.4127706510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_lock.3418253165 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1030464862 ps |
| CPU time | 26.32 seconds |
| Started | Sep 11 12:57:19 PM UTC 24 |
| Finished | Sep 11 12:57:47 PM UTC 24 |
| Peak memory | 253460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418253165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.3418253165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_macro_errs.2750530703 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 30090847680 ps |
| CPU time | 49.42 seconds |
| Started | Sep 11 12:57:25 PM UTC 24 |
| Finished | Sep 11 12:58:16 PM UTC 24 |
| Peak memory | 270124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750530703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.2750530703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_key_req.3716170246 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1989879732 ps |
| CPU time | 28.1 seconds |
| Started | Sep 11 12:57:36 PM UTC 24 |
| Finished | Sep 11 12:58:06 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716170246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.3716170246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.2994378788 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 11505102537 ps |
| CPU time | 201.42 seconds |
| Started | Sep 11 12:57:29 PM UTC 24 |
| Finished | Sep 11 01:00:53 PM UTC 24 |
| Peak memory | 284328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2994378788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.otp_ctrl_stress_all_with_rand_reset.2994378788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_init_fail.628452282 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 204245830 ps |
| CPU time | 4.07 seconds |
| Started | Sep 11 12:59:22 PM UTC 24 |
| Finished | Sep 11 12:59:27 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628452282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.628452282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1997158888 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 954409348 ps |
| CPU time | 13.79 seconds |
| Started | Sep 11 12:56:19 PM UTC 24 |
| Finished | Sep 11 12:56:34 PM UTC 24 |
| Peak memory | 256960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997158888 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_intg_err.1997158888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_init_fail.1193816494 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 212565569 ps |
| CPU time | 3.85 seconds |
| Started | Sep 11 01:06:05 PM UTC 24 |
| Finished | Sep 11 01:06:10 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193816494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.1193816494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/149.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_esc.2710759048 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 526359881 ps |
| CPU time | 3.85 seconds |
| Started | Sep 11 12:57:35 PM UTC 24 |
| Finished | Sep 11 12:57:40 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710759048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.2710759048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.367949519 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 13044227171 ps |
| CPU time | 173.48 seconds |
| Started | Sep 11 01:00:07 PM UTC 24 |
| Finished | Sep 11 01:03:04 PM UTC 24 |
| Peak memory | 267880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=367949519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.367949519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all.1424594032 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 11751923523 ps |
| CPU time | 111.09 seconds |
| Started | Sep 11 12:59:15 PM UTC 24 |
| Finished | Sep 11 01:01:08 PM UTC 24 |
| Peak memory | 257876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424594032 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.1424594032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_init_fail.3485365610 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 473089979 ps |
| CPU time | 4.05 seconds |
| Started | Sep 11 12:57:19 PM UTC 24 |
| Finished | Sep 11 12:57:24 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485365610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.3485365610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_req.2971181821 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 1320575077 ps |
| CPU time | 25.35 seconds |
| Started | Sep 11 12:59:00 PM UTC 24 |
| Finished | Sep 11 12:59:27 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971181821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.2971181821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_check_fail.724174553 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1273312388 ps |
| CPU time | 31.68 seconds |
| Started | Sep 11 01:01:14 PM UTC 24 |
| Finished | Sep 11 01:01:47 PM UTC 24 |
| Peak memory | 253348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724174553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.724174553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all.349642280 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 7705358793 ps |
| CPU time | 41.31 seconds |
| Started | Sep 11 01:00:54 PM UTC 24 |
| Finished | Sep 11 01:01:36 PM UTC 24 |
| Peak memory | 257808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349642280 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.349642280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.4059878542 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 4229579090 ps |
| CPU time | 89.06 seconds |
| Started | Sep 11 12:59:06 PM UTC 24 |
| Finished | Sep 11 01:00:37 PM UTC 24 |
| Peak memory | 257960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4059878542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.otp_ctrl_stress_all_with_rand_reset.4059878542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_alert_test.3939768322 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 230638843 ps |
| CPU time | 2.02 seconds |
| Started | Sep 11 12:57:33 PM UTC 24 |
| Finished | Sep 11 12:57:36 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939768322 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.3939768322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_init_fail.2847424982 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 574673111 ps |
| CPU time | 5.26 seconds |
| Started | Sep 11 01:00:11 PM UTC 24 |
| Finished | Sep 11 01:00:17 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847424982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.2847424982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.3193003495 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 72995258 ps |
| CPU time | 2.51 seconds |
| Started | Sep 11 12:56:29 PM UTC 24 |
| Finished | Sep 11 12:56:32 PM UTC 24 |
| Peak memory | 254736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193003495 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.3193003495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_init_fail.4067820301 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 458298544 ps |
| CPU time | 7.03 seconds |
| Started | Sep 11 12:57:33 PM UTC 24 |
| Finished | Sep 11 12:57:41 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067820301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.4067820301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_init_fail.2288270635 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1558989591 ps |
| CPU time | 6.64 seconds |
| Started | Sep 11 12:58:23 PM UTC 24 |
| Finished | Sep 11 12:58:31 PM UTC 24 |
| Peak memory | 253296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288270635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.2288270635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_macro_errs.3455014236 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1251749633 ps |
| CPU time | 20.63 seconds |
| Started | Sep 11 12:58:51 PM UTC 24 |
| Finished | Sep 11 12:59:13 PM UTC 24 |
| Peak memory | 253720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455014236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.3455014236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.3749992732 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 40693638647 ps |
| CPU time | 160.36 seconds |
| Started | Sep 11 12:59:23 PM UTC 24 |
| Finished | Sep 11 01:02:06 PM UTC 24 |
| Peak memory | 257676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3749992732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.otp_ctrl_stress_all_with_rand_reset.3749992732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_macro_errs.3187846624 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 459518248 ps |
| CPU time | 13.03 seconds |
| Started | Sep 11 12:57:43 PM UTC 24 |
| Finished | Sep 11 12:57:57 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187846624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.3187846624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all.1695352849 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 19918383630 ps |
| CPU time | 173.93 seconds |
| Started | Sep 11 12:57:58 PM UTC 24 |
| Finished | Sep 11 01:00:55 PM UTC 24 |
| Peak memory | 257616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695352849 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.1695352849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_init_fail.1265487508 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 541788319 ps |
| CPU time | 3.76 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:04 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265487508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.1265487508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/136.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_init_fail.4147653111 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 141988369 ps |
| CPU time | 3.97 seconds |
| Started | Sep 11 01:05:24 PM UTC 24 |
| Finished | Sep 11 01:05:30 PM UTC 24 |
| Peak memory | 251340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147653111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.4147653111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/104.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1671410851 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 709146434 ps |
| CPU time | 10.44 seconds |
| Started | Sep 11 12:56:56 PM UTC 24 |
| Finished | Sep 11 12:57:07 PM UTC 24 |
| Peak memory | 256848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671410851 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_intg_err.1671410851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_errs.3051475284 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1099763685 ps |
| CPU time | 35.7 seconds |
| Started | Sep 11 12:57:43 PM UTC 24 |
| Finished | Sep 11 12:58:20 PM UTC 24 |
| Peak memory | 251564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051475284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.3051475284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_init_fail.2595063190 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 547774464 ps |
| CPU time | 5.4 seconds |
| Started | Sep 11 12:57:52 PM UTC 24 |
| Finished | Sep 11 12:57:58 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595063190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.2595063190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.2822568867 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12637840329 ps |
| CPU time | 93.87 seconds |
| Started | Sep 11 01:01:32 PM UTC 24 |
| Finished | Sep 11 01:03:09 PM UTC 24 |
| Peak memory | 267856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2822568867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.otp_ctrl_stress_all_with_rand_reset.2822568867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_background_chks.283114770 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 4057236494 ps |
| CPU time | 30.07 seconds |
| Started | Sep 11 12:57:40 PM UTC 24 |
| Finished | Sep 11 12:58:12 PM UTC 24 |
| Peak memory | 257508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283114770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.283114770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_parallel_lc_esc.385043776 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 117734058 ps |
| CPU time | 4.45 seconds |
| Started | Sep 11 01:05:27 PM UTC 24 |
| Finished | Sep 11 01:05:33 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385043776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.385043776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/107.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all.2739330159 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2725844954 ps |
| CPU time | 71.96 seconds |
| Started | Sep 11 12:59:54 PM UTC 24 |
| Finished | Sep 11 01:01:08 PM UTC 24 |
| Peak memory | 255356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739330159 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.2739330159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_check_fail.1016952112 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3017329355 ps |
| CPU time | 37.57 seconds |
| Started | Sep 11 12:58:51 PM UTC 24 |
| Finished | Sep 11 12:59:30 PM UTC 24 |
| Peak memory | 255472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016952112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.1016952112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_init_fail.1965615335 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 2957175894 ps |
| CPU time | 6.18 seconds |
| Started | Sep 11 01:05:27 PM UTC 24 |
| Finished | Sep 11 01:05:34 PM UTC 24 |
| Peak memory | 253268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965615335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.1965615335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/105.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.708942853 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 9418440050 ps |
| CPU time | 162.61 seconds |
| Started | Sep 11 01:04:39 PM UTC 24 |
| Finished | Sep 11 01:07:25 PM UTC 24 |
| Peak memory | 272040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=708942853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.708942853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/72.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_regwen.2560843109 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 479915792 ps |
| CPU time | 8.1 seconds |
| Started | Sep 11 12:59:27 PM UTC 24 |
| Finished | Sep 11 12:59:37 PM UTC 24 |
| Peak memory | 251528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560843109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.2560843109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_esc.2726265810 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1567080059 ps |
| CPU time | 5.13 seconds |
| Started | Sep 11 12:59:12 PM UTC 24 |
| Finished | Sep 11 12:59:18 PM UTC 24 |
| Peak memory | 257580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726265810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.2726265810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.1093713398 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 19645751957 ps |
| CPU time | 132.64 seconds |
| Started | Sep 11 01:04:39 PM UTC 24 |
| Finished | Sep 11 01:06:54 PM UTC 24 |
| Peak memory | 269904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1093713398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 68.otp_ctrl_stress_all_with_rand_reset.1093713398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_macro_errs.1493325926 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1555109871 ps |
| CPU time | 38.26 seconds |
| Started | Sep 11 12:57:56 PM UTC 24 |
| Finished | Sep 11 12:58:36 PM UTC 24 |
| Peak memory | 267692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493325926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.1493325926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2627768472 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 95089109 ps |
| CPU time | 3.62 seconds |
| Started | Sep 11 12:56:33 PM UTC 24 |
| Finished | Sep 11 12:56:37 PM UTC 24 |
| Peak memory | 252764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627768472 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_reset.2627768472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_parallel_lc_esc.2863315724 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 919016873 ps |
| CPU time | 12.79 seconds |
| Started | Sep 11 01:05:37 PM UTC 24 |
| Finished | Sep 11 01:05:51 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863315724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.2863315724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/112.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_init_fail.654828102 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 460350331 ps |
| CPU time | 4.93 seconds |
| Started | Sep 11 01:05:59 PM UTC 24 |
| Finished | Sep 11 01:06:05 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654828102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.654828102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/135.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_parallel_lc_esc.4139465459 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 126045020 ps |
| CPU time | 4.44 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:06 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139465459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.4139465459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/144.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_parallel_lc_esc.3856154044 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1385680117 ps |
| CPU time | 19.32 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:35 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856154044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.3856154044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/157.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.4052833621 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 208808886 ps |
| CPU time | 4.2 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:04 PM UTC 24 |
| Peak memory | 251080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052833621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.4052833621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/279.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_parallel_lc_esc.2511164153 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 2592840711 ps |
| CPU time | 11.21 seconds |
| Started | Sep 11 01:04:46 PM UTC 24 |
| Finished | Sep 11 01:04:59 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511164153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.2511164153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/78.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.3301441727 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 5888917410 ps |
| CPU time | 19.99 seconds |
| Started | Sep 11 12:57:06 PM UTC 24 |
| Finished | Sep 11 12:57:28 PM UTC 24 |
| Peak memory | 257104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301441727 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_intg_err.3301441727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.2045712129 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 4347316089 ps |
| CPU time | 97.69 seconds |
| Started | Sep 11 01:02:12 PM UTC 24 |
| Finished | Sep 11 01:03:52 PM UTC 24 |
| Peak memory | 267852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2045712129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 33.otp_ctrl_stress_all_with_rand_reset.2045712129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_regwen.1149227141 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 325787170 ps |
| CPU time | 9.9 seconds |
| Started | Sep 11 01:01:13 PM UTC 24 |
| Finished | Sep 11 01:01:24 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149227141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.1149227141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/25.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_check_fail.3352709134 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1086746983 ps |
| CPU time | 12.44 seconds |
| Started | Sep 11 12:57:24 PM UTC 24 |
| Finished | Sep 11 12:57:38 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352709134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.3352709134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_regwen.1407105381 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 533324386 ps |
| CPU time | 10 seconds |
| Started | Sep 11 12:57:39 PM UTC 24 |
| Finished | Sep 11 12:57:50 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407105381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.1407105381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_lock.314890854 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 3264991683 ps |
| CPU time | 32.07 seconds |
| Started | Sep 11 12:57:35 PM UTC 24 |
| Finished | Sep 11 12:58:08 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314890854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.314890854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_key_req.2799635830 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1088922201 ps |
| CPU time | 17.96 seconds |
| Started | Sep 11 12:58:23 PM UTC 24 |
| Finished | Sep 11 12:58:42 PM UTC 24 |
| Peak memory | 257428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799635830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.2799635830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_check_fail.471076952 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 2498902939 ps |
| CPU time | 23.12 seconds |
| Started | Sep 11 12:59:25 PM UTC 24 |
| Finished | Sep 11 12:59:49 PM UTC 24 |
| Peak memory | 253400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471076952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.471076952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1276972183 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 19850668542 ps |
| CPU time | 27.35 seconds |
| Started | Sep 11 12:56:44 PM UTC 24 |
| Finished | Sep 11 12:57:13 PM UTC 24 |
| Peak memory | 252824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276972183 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_intg_err.1276972183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_check_fail.3667692271 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 314192677 ps |
| CPU time | 10.73 seconds |
| Started | Sep 11 01:03:10 PM UTC 24 |
| Finished | Sep 11 01:03:22 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667692271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.3667692271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_regwen.2882986419 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 499806876 ps |
| CPU time | 8.52 seconds |
| Started | Sep 11 01:01:38 PM UTC 24 |
| Finished | Sep 11 01:01:48 PM UTC 24 |
| Peak memory | 257420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882986419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.2882986419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/29.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.3432613288 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 147633928100 ps |
| CPU time | 188.86 seconds |
| Started | Sep 11 12:58:36 PM UTC 24 |
| Finished | Sep 11 01:01:49 PM UTC 24 |
| Peak memory | 269744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432613288 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.3432613288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all.833676924 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 33573702143 ps |
| CPU time | 230.89 seconds |
| Started | Sep 11 12:59:29 PM UTC 24 |
| Finished | Sep 11 01:03:24 PM UTC 24 |
| Peak memory | 286416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833676924 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.833676924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_macro_errs.360693832 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 12447280223 ps |
| CPU time | 30.67 seconds |
| Started | Sep 11 12:58:33 PM UTC 24 |
| Finished | Sep 11 12:59:05 PM UTC 24 |
| Peak memory | 255532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360693832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.360693832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_check_fail.3123323959 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 14603633656 ps |
| CPU time | 22.71 seconds |
| Started | Sep 11 01:00:11 PM UTC 24 |
| Finished | Sep 11 01:00:35 PM UTC 24 |
| Peak memory | 257516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123323959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.3123323959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_check_fail.15804102 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 596849990 ps |
| CPU time | 12.25 seconds |
| Started | Sep 11 01:04:02 PM UTC 24 |
| Finished | Sep 11 01:04:16 PM UTC 24 |
| Peak memory | 253384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15804102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.15804102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/48.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_errs.3122883058 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1955906683 ps |
| CPU time | 40.07 seconds |
| Started | Sep 11 12:59:25 PM UTC 24 |
| Finished | Sep 11 01:00:06 PM UTC 24 |
| Peak memory | 257712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122883058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.3122883058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_init_fail.859725602 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 294208754 ps |
| CPU time | 5.37 seconds |
| Started | Sep 11 12:58:58 PM UTC 24 |
| Finished | Sep 11 12:59:04 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859725602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.859725602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_init_fail.699475009 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 117815665 ps |
| CPU time | 4.51 seconds |
| Started | Sep 11 01:05:21 PM UTC 24 |
| Finished | Sep 11 01:05:26 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699475009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.699475009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/102.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_init_fail.2378867685 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 133913472 ps |
| CPU time | 4.63 seconds |
| Started | Sep 11 01:05:29 PM UTC 24 |
| Finished | Sep 11 01:05:34 PM UTC 24 |
| Peak memory | 253580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378867685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.2378867685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/109.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_init_fail.484547131 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 388771756 ps |
| CPU time | 3.39 seconds |
| Started | Sep 11 12:59:12 PM UTC 24 |
| Finished | Sep 11 12:59:17 PM UTC 24 |
| Peak memory | 250896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484547131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.484547131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_errs.2138225774 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 1137009929 ps |
| CPU time | 18.21 seconds |
| Started | Sep 11 01:02:01 PM UTC 24 |
| Finished | Sep 11 01:02:21 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138225774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.2138225774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/33.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_wake_up.3447241724 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 92677275 ps |
| CPU time | 2.72 seconds |
| Started | Sep 11 12:57:19 PM UTC 24 |
| Finished | Sep 11 12:57:22 PM UTC 24 |
| Peak memory | 250592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447241724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes t +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.3447241724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_req.1843468271 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 465632363 ps |
| CPU time | 11.98 seconds |
| Started | Sep 11 12:57:43 PM UTC 24 |
| Finished | Sep 11 12:57:56 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843468271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.1843468271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_lock.2704892049 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 5117387231 ps |
| CPU time | 15.53 seconds |
| Started | Sep 11 12:57:24 PM UTC 24 |
| Finished | Sep 11 12:57:41 PM UTC 24 |
| Peak memory | 253488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704892049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.2704892049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all.1284925875 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 89642265354 ps |
| CPU time | 281.65 seconds |
| Started | Sep 11 01:00:46 PM UTC 24 |
| Finished | Sep 11 01:05:32 PM UTC 24 |
| Peak memory | 267856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284925875 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.1284925875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all.1084175431 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 44528817035 ps |
| CPU time | 69.76 seconds |
| Started | Sep 11 12:57:21 PM UTC 24 |
| Finished | Sep 11 12:58:33 PM UTC 24 |
| Peak memory | 284456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084175431 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.1084175431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.4256142030 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3132883639 ps |
| CPU time | 21.71 seconds |
| Started | Sep 11 12:56:29 PM UTC 24 |
| Finished | Sep 11 12:56:52 PM UTC 24 |
| Peak memory | 256780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256142030 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_intg_err.4256142030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.4084396461 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 666179888 ps |
| CPU time | 12.24 seconds |
| Started | Sep 11 12:56:43 PM UTC 24 |
| Finished | Sep 11 12:56:58 PM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084396461 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg_err.4084396461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_init_fail.3179522783 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 212963627 ps |
| CPU time | 4.1 seconds |
| Started | Sep 11 01:04:56 PM UTC 24 |
| Finished | Sep 11 01:05:01 PM UTC 24 |
| Peak memory | 253520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179522783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.3179522783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/84.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.746708410 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 93288417 ps |
| CPU time | 3.07 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:01 PM UTC 24 |
| Peak memory | 251340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746708410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.746708410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/249.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all.1746454232 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 12520050574 ps |
| CPU time | 63.79 seconds |
| Started | Sep 11 12:58:23 PM UTC 24 |
| Finished | Sep 11 12:59:29 PM UTC 24 |
| Peak memory | 253364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746454232 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.1746454232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all.2992767895 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 3995405390 ps |
| CPU time | 86.38 seconds |
| Started | Sep 11 12:59:36 PM UTC 24 |
| Finished | Sep 11 01:01:04 PM UTC 24 |
| Peak memory | 268136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992767895 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.2992767895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_init_fail.573233718 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 120838494 ps |
| CPU time | 5.98 seconds |
| Started | Sep 11 12:58:37 PM UTC 24 |
| Finished | Sep 11 12:58:44 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573233718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.573233718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_background_chks.2088341158 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 2101848686 ps |
| CPU time | 19.66 seconds |
| Started | Sep 11 12:57:33 PM UTC 24 |
| Finished | Sep 11 12:57:54 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088341158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.2088341158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3610061304 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 99553708 ps |
| CPU time | 5.7 seconds |
| Started | Sep 11 12:56:21 PM UTC 24 |
| Finished | Sep 11 12:56:28 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610061304 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_aliasing.3610061304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.3216108170 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 129506300 ps |
| CPU time | 7.09 seconds |
| Started | Sep 11 12:56:21 PM UTC 24 |
| Finished | Sep 11 12:56:29 PM UTC 24 |
| Peak memory | 252632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216108170 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_bash.3216108170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.479130845 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 1595283101 ps |
| CPU time | 7.77 seconds |
| Started | Sep 11 12:56:19 PM UTC 24 |
| Finished | Sep 11 12:56:28 PM UTC 24 |
| Peak memory | 252832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479130845 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_reset.479130845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.1291001818 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 168449773 ps |
| CPU time | 4.87 seconds |
| Started | Sep 11 12:56:23 PM UTC 24 |
| Finished | Sep 11 12:56:28 PM UTC 24 |
| Peak memory | 259060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1291001818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_cs r_mem_rw_with_rand_reset.1291001818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2947481215 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 134410731 ps |
| CPU time | 2.38 seconds |
| Started | Sep 11 12:56:21 PM UTC 24 |
| Finished | Sep 11 12:56:25 PM UTC 24 |
| Peak memory | 252836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947481215 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.2947481215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.973949420 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 134047265 ps |
| CPU time | 2.28 seconds |
| Started | Sep 11 12:56:19 PM UTC 24 |
| Finished | Sep 11 12:56:22 PM UTC 24 |
| Peak memory | 242456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973949420 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.973949420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1610350180 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 55586206 ps |
| CPU time | 1.66 seconds |
| Started | Sep 11 12:56:19 PM UTC 24 |
| Finished | Sep 11 12:56:22 PM UTC 24 |
| Peak memory | 240672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610350180 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_partial_access.1610350180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.1473587339 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 557131516 ps |
| CPU time | 2.23 seconds |
| Started | Sep 11 12:56:19 PM UTC 24 |
| Finished | Sep 11 12:56:22 PM UTC 24 |
| Peak memory | 242524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473587339 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.1473587339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.3820955093 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 102769136 ps |
| CPU time | 4.54 seconds |
| Started | Sep 11 12:56:21 PM UTC 24 |
| Finished | Sep 11 12:56:27 PM UTC 24 |
| Peak memory | 252632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820955093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_same_csr_outstanding.3820955093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3171311447 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 128872354 ps |
| CPU time | 6.16 seconds |
| Started | Sep 11 12:56:17 PM UTC 24 |
| Finished | Sep 11 12:56:24 PM UTC 24 |
| Peak memory | 252808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171311447 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.3171311447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1066596270 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 843883837 ps |
| CPU time | 3.63 seconds |
| Started | Sep 11 12:56:27 PM UTC 24 |
| Finished | Sep 11 12:56:32 PM UTC 24 |
| Peak memory | 252676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066596270 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_aliasing.1066596270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.570263596 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 838022079 ps |
| CPU time | 8.76 seconds |
| Started | Sep 11 12:56:27 PM UTC 24 |
| Finished | Sep 11 12:56:37 PM UTC 24 |
| Peak memory | 242388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570263596 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_bash.570263596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.38279376 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 196881725 ps |
| CPU time | 3.55 seconds |
| Started | Sep 11 12:56:25 PM UTC 24 |
| Finished | Sep 11 12:56:30 PM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38279376 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_reset.38279376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.2442695508 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 338818928 ps |
| CPU time | 6.75 seconds |
| Started | Sep 11 12:56:29 PM UTC 24 |
| Finished | Sep 11 12:56:37 PM UTC 24 |
| Peak memory | 259088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2442695508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_cs r_mem_rw_with_rand_reset.2442695508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2432181198 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 39119305 ps |
| CPU time | 1.94 seconds |
| Started | Sep 11 12:56:27 PM UTC 24 |
| Finished | Sep 11 12:56:30 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432181198 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.2432181198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.3598737158 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 517523088 ps |
| CPU time | 2.47 seconds |
| Started | Sep 11 12:56:23 PM UTC 24 |
| Finished | Sep 11 12:56:26 PM UTC 24 |
| Peak memory | 241980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598737158 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.3598737158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.4258920086 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 37724588 ps |
| CPU time | 2.07 seconds |
| Started | Sep 11 12:56:25 PM UTC 24 |
| Finished | Sep 11 12:56:28 PM UTC 24 |
| Peak memory | 242124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258920086 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_partial_access.4258920086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.4165896575 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 40854005 ps |
| CPU time | 2.28 seconds |
| Started | Sep 11 12:56:24 PM UTC 24 |
| Finished | Sep 11 12:56:27 PM UTC 24 |
| Peak memory | 242396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165896575 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.4165896575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.206016608 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 75984911 ps |
| CPU time | 3.61 seconds |
| Started | Sep 11 12:56:27 PM UTC 24 |
| Finished | Sep 11 12:56:32 PM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206016608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_same_csr_outstanding.206016608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.764837763 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 82177689 ps |
| CPU time | 4.75 seconds |
| Started | Sep 11 12:56:23 PM UTC 24 |
| Finished | Sep 11 12:56:28 PM UTC 24 |
| Peak memory | 259008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764837763 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.764837763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3200855130 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 1179442468 ps |
| CPU time | 11.6 seconds |
| Started | Sep 11 12:56:23 PM UTC 24 |
| Finished | Sep 11 12:56:35 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200855130 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_intg_err.3200855130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.584369350 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 1054443110 ps |
| CPU time | 2.58 seconds |
| Started | Sep 11 12:56:53 PM UTC 24 |
| Finished | Sep 11 12:56:57 PM UTC 24 |
| Peak memory | 256872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=584369350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_cs r_mem_rw_with_rand_reset.584369350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.4143675159 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 604404919 ps |
| CPU time | 2.8 seconds |
| Started | Sep 11 12:56:51 PM UTC 24 |
| Finished | Sep 11 12:56:55 PM UTC 24 |
| Peak memory | 252676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143675159 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.4143675159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.2946851449 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 562688760 ps |
| CPU time | 2.57 seconds |
| Started | Sep 11 12:56:51 PM UTC 24 |
| Finished | Sep 11 12:56:55 PM UTC 24 |
| Peak memory | 242588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946851449 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.2946851449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.3015891173 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 44757507 ps |
| CPU time | 2.66 seconds |
| Started | Sep 11 12:56:53 PM UTC 24 |
| Finished | Sep 11 12:56:57 PM UTC 24 |
| Peak memory | 252552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015891173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_same_csr_outstanding.3015891173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.59568768 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 76617960 ps |
| CPU time | 4.94 seconds |
| Started | Sep 11 12:56:51 PM UTC 24 |
| Finished | Sep 11 12:56:57 PM UTC 24 |
| Peak memory | 258992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59568768 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.59568768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1817178988 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 2849742431 ps |
| CPU time | 11.23 seconds |
| Started | Sep 11 12:56:51 PM UTC 24 |
| Finished | Sep 11 12:57:03 PM UTC 24 |
| Peak memory | 256896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817178988 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_intg_err.1817178988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3295289813 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 99914043 ps |
| CPU time | 3.22 seconds |
| Started | Sep 11 12:56:55 PM UTC 24 |
| Finished | Sep 11 12:57:00 PM UTC 24 |
| Peak memory | 258956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3295289813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_c sr_mem_rw_with_rand_reset.3295289813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.4018851531 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 545106998 ps |
| CPU time | 1.6 seconds |
| Started | Sep 11 12:56:53 PM UTC 24 |
| Finished | Sep 11 12:56:56 PM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018851531 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.4018851531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.1274970963 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 79218869 ps |
| CPU time | 2.4 seconds |
| Started | Sep 11 12:56:53 PM UTC 24 |
| Finished | Sep 11 12:56:57 PM UTC 24 |
| Peak memory | 241884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274970963 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.1274970963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.4177005912 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 148947566 ps |
| CPU time | 3.38 seconds |
| Started | Sep 11 12:56:53 PM UTC 24 |
| Finished | Sep 11 12:56:58 PM UTC 24 |
| Peak memory | 254748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177005912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_same_csr_outstanding.4177005912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2111114344 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 432868578 ps |
| CPU time | 5.78 seconds |
| Started | Sep 11 12:56:53 PM UTC 24 |
| Finished | Sep 11 12:57:00 PM UTC 24 |
| Peak memory | 258944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111114344 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.2111114344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3468025884 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 2628397941 ps |
| CPU time | 14.77 seconds |
| Started | Sep 11 12:56:53 PM UTC 24 |
| Finished | Sep 11 12:57:09 PM UTC 24 |
| Peak memory | 256852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468025884 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_intg_err.3468025884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1085175845 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 203276003 ps |
| CPU time | 3.04 seconds |
| Started | Sep 11 12:56:58 PM UTC 24 |
| Finished | Sep 11 12:57:02 PM UTC 24 |
| Peak memory | 258956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1085175845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_c sr_mem_rw_with_rand_reset.1085175845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1642661358 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 126330979 ps |
| CPU time | 2.24 seconds |
| Started | Sep 11 12:56:56 PM UTC 24 |
| Finished | Sep 11 12:56:59 PM UTC 24 |
| Peak memory | 254748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642661358 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.1642661358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.204455600 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 66312242 ps |
| CPU time | 2.42 seconds |
| Started | Sep 11 12:56:56 PM UTC 24 |
| Finished | Sep 11 12:56:59 PM UTC 24 |
| Peak memory | 242600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204455600 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.204455600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2650351947 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 70695058 ps |
| CPU time | 3.36 seconds |
| Started | Sep 11 12:56:58 PM UTC 24 |
| Finished | Sep 11 12:57:02 PM UTC 24 |
| Peak memory | 254792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650351947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_same_csr_outstanding.2650351947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2055412785 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 79178588 ps |
| CPU time | 4.82 seconds |
| Started | Sep 11 12:56:55 PM UTC 24 |
| Finished | Sep 11 12:57:02 PM UTC 24 |
| Peak memory | 259020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055412785 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.2055412785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3275253313 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 1801908013 ps |
| CPU time | 3.99 seconds |
| Started | Sep 11 12:56:59 PM UTC 24 |
| Finished | Sep 11 12:57:04 PM UTC 24 |
| Peak memory | 258940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3275253313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_c sr_mem_rw_with_rand_reset.3275253313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.575935179 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 50104384 ps |
| CPU time | 2.11 seconds |
| Started | Sep 11 12:56:59 PM UTC 24 |
| Finished | Sep 11 12:57:02 PM UTC 24 |
| Peak memory | 254644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575935179 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.575935179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.3995300292 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 576409378 ps |
| CPU time | 2.35 seconds |
| Started | Sep 11 12:56:59 PM UTC 24 |
| Finished | Sep 11 12:57:02 PM UTC 24 |
| Peak memory | 241992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995300292 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.3995300292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.2887389359 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 1907877859 ps |
| CPU time | 6.5 seconds |
| Started | Sep 11 12:56:59 PM UTC 24 |
| Finished | Sep 11 12:57:07 PM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887389359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_same_csr_outstanding.2887389359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.374509759 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 179667960 ps |
| CPU time | 9.18 seconds |
| Started | Sep 11 12:56:58 PM UTC 24 |
| Finished | Sep 11 12:57:08 PM UTC 24 |
| Peak memory | 252856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374509759 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.374509759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.3649996253 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 1177992360 ps |
| CPU time | 19.86 seconds |
| Started | Sep 11 12:56:59 PM UTC 24 |
| Finished | Sep 11 12:57:20 PM UTC 24 |
| Peak memory | 256912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649996253 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_intg_err.3649996253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.3167863547 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 1026981206 ps |
| CPU time | 3.83 seconds |
| Started | Sep 11 12:57:01 PM UTC 24 |
| Finished | Sep 11 12:57:06 PM UTC 24 |
| Peak memory | 258876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3167863547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_c sr_mem_rw_with_rand_reset.3167863547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1135739983 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 81763278 ps |
| CPU time | 2.52 seconds |
| Started | Sep 11 12:57:01 PM UTC 24 |
| Finished | Sep 11 12:57:05 PM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135739983 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.1135739983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.3386121610 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 70019690 ps |
| CPU time | 1.83 seconds |
| Started | Sep 11 12:56:59 PM UTC 24 |
| Finished | Sep 11 12:57:03 PM UTC 24 |
| Peak memory | 241680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386121610 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.3386121610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1597118422 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 88614197 ps |
| CPU time | 2.43 seconds |
| Started | Sep 11 12:57:01 PM UTC 24 |
| Finished | Sep 11 12:57:05 PM UTC 24 |
| Peak memory | 254768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597118422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_same_csr_outstanding.1597118422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2871286208 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 119105186 ps |
| CPU time | 5 seconds |
| Started | Sep 11 12:56:59 PM UTC 24 |
| Finished | Sep 11 12:57:06 PM UTC 24 |
| Peak memory | 252820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871286208 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.2871286208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.959361345 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 4751827146 ps |
| CPU time | 23.08 seconds |
| Started | Sep 11 12:56:59 PM UTC 24 |
| Finished | Sep 11 12:57:24 PM UTC 24 |
| Peak memory | 253028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959361345 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_intg_err.959361345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3528866692 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 157468362 ps |
| CPU time | 2.64 seconds |
| Started | Sep 11 12:57:03 PM UTC 24 |
| Finished | Sep 11 12:57:07 PM UTC 24 |
| Peak memory | 259020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3528866692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_c sr_mem_rw_with_rand_reset.3528866692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3086515008 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 37686007 ps |
| CPU time | 1.79 seconds |
| Started | Sep 11 12:57:03 PM UTC 24 |
| Finished | Sep 11 12:57:06 PM UTC 24 |
| Peak memory | 252012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086515008 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.3086515008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.2151584334 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 141119288 ps |
| CPU time | 1.87 seconds |
| Started | Sep 11 12:57:03 PM UTC 24 |
| Finished | Sep 11 12:57:06 PM UTC 24 |
| Peak memory | 241628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151584334 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.2151584334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2889954271 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 98410616 ps |
| CPU time | 4.43 seconds |
| Started | Sep 11 12:57:03 PM UTC 24 |
| Finished | Sep 11 12:57:08 PM UTC 24 |
| Peak memory | 254672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889954271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_same_csr_outstanding.2889954271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.2521503034 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 992047875 ps |
| CPU time | 3.21 seconds |
| Started | Sep 11 12:57:01 PM UTC 24 |
| Finished | Sep 11 12:57:06 PM UTC 24 |
| Peak memory | 258884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521503034 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.2521503034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.4240878752 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 644944202 ps |
| CPU time | 9.87 seconds |
| Started | Sep 11 12:57:02 PM UTC 24 |
| Finished | Sep 11 12:57:13 PM UTC 24 |
| Peak memory | 256720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240878752 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_intg_err.4240878752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.3396720712 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 104158739 ps |
| CPU time | 3.59 seconds |
| Started | Sep 11 12:57:05 PM UTC 24 |
| Finished | Sep 11 12:57:10 PM UTC 24 |
| Peak memory | 258928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3396720712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_c sr_mem_rw_with_rand_reset.3396720712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3640867408 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 46585839 ps |
| CPU time | 2.09 seconds |
| Started | Sep 11 12:57:04 PM UTC 24 |
| Finished | Sep 11 12:57:07 PM UTC 24 |
| Peak memory | 254728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640867408 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.3640867408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.2198851094 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 38626167 ps |
| CPU time | 1.53 seconds |
| Started | Sep 11 12:57:04 PM UTC 24 |
| Finished | Sep 11 12:57:07 PM UTC 24 |
| Peak memory | 241180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198851094 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.2198851094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.2285105158 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 98789673 ps |
| CPU time | 2.99 seconds |
| Started | Sep 11 12:57:04 PM UTC 24 |
| Finished | Sep 11 12:57:08 PM UTC 24 |
| Peak memory | 252672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285105158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_same_csr_outstanding.2285105158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.3619375929 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 109755788 ps |
| CPU time | 3.95 seconds |
| Started | Sep 11 12:57:04 PM UTC 24 |
| Finished | Sep 11 12:57:09 PM UTC 24 |
| Peak memory | 258900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619375929 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.3619375929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2244664651 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 1694819518 ps |
| CPU time | 12.67 seconds |
| Started | Sep 11 12:57:04 PM UTC 24 |
| Finished | Sep 11 12:57:18 PM UTC 24 |
| Peak memory | 256852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244664651 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_intg_err.2244664651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.1127971942 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 215519016 ps |
| CPU time | 3.73 seconds |
| Started | Sep 11 12:57:07 PM UTC 24 |
| Finished | Sep 11 12:57:12 PM UTC 24 |
| Peak memory | 258956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1127971942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_c sr_mem_rw_with_rand_reset.1127971942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2398693102 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 146942735 ps |
| CPU time | 2.11 seconds |
| Started | Sep 11 12:57:06 PM UTC 24 |
| Finished | Sep 11 12:57:10 PM UTC 24 |
| Peak memory | 254732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398693102 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.2398693102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.2556693985 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 47085764 ps |
| CPU time | 1.9 seconds |
| Started | Sep 11 12:57:06 PM UTC 24 |
| Finished | Sep 11 12:57:09 PM UTC 24 |
| Peak memory | 241188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556693985 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.2556693985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1433299381 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 73200587 ps |
| CPU time | 3.49 seconds |
| Started | Sep 11 12:57:06 PM UTC 24 |
| Finished | Sep 11 12:57:11 PM UTC 24 |
| Peak memory | 254896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433299381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_same_csr_outstanding.1433299381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1972834258 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 77985664 ps |
| CPU time | 5.2 seconds |
| Started | Sep 11 12:57:06 PM UTC 24 |
| Finished | Sep 11 12:57:13 PM UTC 24 |
| Peak memory | 258944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972834258 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1972834258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1793224585 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 409509155 ps |
| CPU time | 4.84 seconds |
| Started | Sep 11 12:57:09 PM UTC 24 |
| Finished | Sep 11 12:57:15 PM UTC 24 |
| Peak memory | 258864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1793224585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_c sr_mem_rw_with_rand_reset.1793224585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3320504693 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 40155969 ps |
| CPU time | 2.46 seconds |
| Started | Sep 11 12:57:08 PM UTC 24 |
| Finished | Sep 11 12:57:11 PM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320504693 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.3320504693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.624334836 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 149758912 ps |
| CPU time | 2.28 seconds |
| Started | Sep 11 12:57:08 PM UTC 24 |
| Finished | Sep 11 12:57:11 PM UTC 24 |
| Peak memory | 241996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624334836 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.624334836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3670483892 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 248473627 ps |
| CPU time | 3.51 seconds |
| Started | Sep 11 12:57:09 PM UTC 24 |
| Finished | Sep 11 12:57:13 PM UTC 24 |
| Peak memory | 252752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670483892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_same_csr_outstanding.3670483892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1558396760 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 402755064 ps |
| CPU time | 8.09 seconds |
| Started | Sep 11 12:57:07 PM UTC 24 |
| Finished | Sep 11 12:57:17 PM UTC 24 |
| Peak memory | 259020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558396760 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.1558396760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.4252726402 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 2565699421 ps |
| CPU time | 22.01 seconds |
| Started | Sep 11 12:57:08 PM UTC 24 |
| Finished | Sep 11 12:57:31 PM UTC 24 |
| Peak memory | 256916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252726402 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_intg_err.4252726402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2350030588 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 71628460 ps |
| CPU time | 2.66 seconds |
| Started | Sep 11 12:57:10 PM UTC 24 |
| Finished | Sep 11 12:57:14 PM UTC 24 |
| Peak memory | 256892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2350030588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_c sr_mem_rw_with_rand_reset.2350030588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1305162952 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 59906437 ps |
| CPU time | 2.14 seconds |
| Started | Sep 11 12:57:10 PM UTC 24 |
| Finished | Sep 11 12:57:13 PM UTC 24 |
| Peak memory | 252632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305162952 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.1305162952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.929639955 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 158358101 ps |
| CPU time | 1.96 seconds |
| Started | Sep 11 12:57:10 PM UTC 24 |
| Finished | Sep 11 12:57:13 PM UTC 24 |
| Peak memory | 240916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929639955 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.929639955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.354418986 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 1027212973 ps |
| CPU time | 2.93 seconds |
| Started | Sep 11 12:57:10 PM UTC 24 |
| Finished | Sep 11 12:57:14 PM UTC 24 |
| Peak memory | 252620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354418986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_same_csr_outstanding.354418986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2930474039 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 1191809904 ps |
| CPU time | 7.07 seconds |
| Started | Sep 11 12:57:09 PM UTC 24 |
| Finished | Sep 11 12:57:17 PM UTC 24 |
| Peak memory | 259124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930474039 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.2930474039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2880027458 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 2974020265 ps |
| CPU time | 22.89 seconds |
| Started | Sep 11 12:57:10 PM UTC 24 |
| Finished | Sep 11 12:57:34 PM UTC 24 |
| Peak memory | 252876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880027458 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_intg_err.2880027458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3222538538 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 377924768 ps |
| CPU time | 7.47 seconds |
| Started | Sep 11 12:56:30 PM UTC 24 |
| Finished | Sep 11 12:56:39 PM UTC 24 |
| Peak memory | 252628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222538538 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_aliasing.3222538538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2468457924 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 5615312127 ps |
| CPU time | 14.52 seconds |
| Started | Sep 11 12:56:30 PM UTC 24 |
| Finished | Sep 11 12:56:46 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468457924 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_bash.2468457924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1216928486 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 70378038 ps |
| CPU time | 2.93 seconds |
| Started | Sep 11 12:56:29 PM UTC 24 |
| Finished | Sep 11 12:56:33 PM UTC 24 |
| Peak memory | 252820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216928486 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_reset.1216928486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.1724032489 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 71904126 ps |
| CPU time | 3.44 seconds |
| Started | Sep 11 12:56:31 PM UTC 24 |
| Finished | Sep 11 12:56:36 PM UTC 24 |
| Peak memory | 256912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1724032489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_cs r_mem_rw_with_rand_reset.1724032489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.4076391543 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 39178728 ps |
| CPU time | 1.74 seconds |
| Started | Sep 11 12:56:29 PM UTC 24 |
| Finished | Sep 11 12:56:31 PM UTC 24 |
| Peak memory | 241180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076391543 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.4076391543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.4082565276 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 35971693 ps |
| CPU time | 1.55 seconds |
| Started | Sep 11 12:56:29 PM UTC 24 |
| Finished | Sep 11 12:56:31 PM UTC 24 |
| Peak memory | 241672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082565276 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_partial_access.4082565276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.1281992802 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 134716345 ps |
| CPU time | 1.89 seconds |
| Started | Sep 11 12:56:29 PM UTC 24 |
| Finished | Sep 11 12:56:32 PM UTC 24 |
| Peak memory | 241668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281992802 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.1281992802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.4096905396 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 108133216 ps |
| CPU time | 2.12 seconds |
| Started | Sep 11 12:56:30 PM UTC 24 |
| Finished | Sep 11 12:56:33 PM UTC 24 |
| Peak memory | 252632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096905396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_same_csr_outstanding.4096905396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2290012673 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 95192349 ps |
| CPU time | 6.64 seconds |
| Started | Sep 11 12:56:29 PM UTC 24 |
| Finished | Sep 11 12:56:36 PM UTC 24 |
| Peak memory | 252936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290012673 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.2290012673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.2548201342 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 39791915 ps |
| CPU time | 2.23 seconds |
| Started | Sep 11 12:57:11 PM UTC 24 |
| Finished | Sep 11 12:57:14 PM UTC 24 |
| Peak memory | 241656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548201342 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.2548201342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/20.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.3601171637 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 152654725 ps |
| CPU time | 2.22 seconds |
| Started | Sep 11 12:57:11 PM UTC 24 |
| Finished | Sep 11 12:57:14 PM UTC 24 |
| Peak memory | 241700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601171637 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.3601171637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/21.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.310720290 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 572305858 ps |
| CPU time | 2.01 seconds |
| Started | Sep 11 12:57:12 PM UTC 24 |
| Finished | Sep 11 12:57:15 PM UTC 24 |
| Peak memory | 241192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310720290 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.310720290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/22.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.3099752051 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 562732856 ps |
| CPU time | 1.75 seconds |
| Started | Sep 11 12:57:13 PM UTC 24 |
| Finished | Sep 11 12:57:15 PM UTC 24 |
| Peak memory | 241060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099752051 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.3099752051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/23.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.1503736073 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 85367078 ps |
| CPU time | 2.32 seconds |
| Started | Sep 11 12:57:13 PM UTC 24 |
| Finished | Sep 11 12:57:16 PM UTC 24 |
| Peak memory | 241684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503736073 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.1503736073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/24.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.1552733948 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 40190529 ps |
| CPU time | 2.04 seconds |
| Started | Sep 11 12:57:13 PM UTC 24 |
| Finished | Sep 11 12:57:16 PM UTC 24 |
| Peak memory | 241724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552733948 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.1552733948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/25.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.3435623930 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 551192318 ps |
| CPU time | 2.11 seconds |
| Started | Sep 11 12:57:14 PM UTC 24 |
| Finished | Sep 11 12:57:17 PM UTC 24 |
| Peak memory | 242652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435623930 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.3435623930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/26.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.2466248058 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 39756262 ps |
| CPU time | 2.16 seconds |
| Started | Sep 11 12:57:14 PM UTC 24 |
| Finished | Sep 11 12:57:17 PM UTC 24 |
| Peak memory | 242468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466248058 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.2466248058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/27.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.258082379 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 589403264 ps |
| CPU time | 1.52 seconds |
| Started | Sep 11 12:57:14 PM UTC 24 |
| Finished | Sep 11 12:57:17 PM UTC 24 |
| Peak memory | 241164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258082379 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.258082379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/28.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.1656794499 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 135289558 ps |
| CPU time | 2.16 seconds |
| Started | Sep 11 12:57:14 PM UTC 24 |
| Finished | Sep 11 12:57:17 PM UTC 24 |
| Peak memory | 242588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656794499 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.1656794499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/29.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.4256072387 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 390533609 ps |
| CPU time | 7.22 seconds |
| Started | Sep 11 12:56:34 PM UTC 24 |
| Finished | Sep 11 12:56:42 PM UTC 24 |
| Peak memory | 252868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256072387 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_aliasing.4256072387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2511222803 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 341673036 ps |
| CPU time | 9.3 seconds |
| Started | Sep 11 12:56:34 PM UTC 24 |
| Finished | Sep 11 12:56:44 PM UTC 24 |
| Peak memory | 242388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511222803 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_bash.2511222803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2535734194 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 109387628 ps |
| CPU time | 4.34 seconds |
| Started | Sep 11 12:56:36 PM UTC 24 |
| Finished | Sep 11 12:56:41 PM UTC 24 |
| Peak memory | 259096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2535734194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_cs r_mem_rw_with_rand_reset.2535734194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.13485591 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 40166456 ps |
| CPU time | 2.39 seconds |
| Started | Sep 11 12:56:34 PM UTC 24 |
| Finished | Sep 11 12:56:37 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13485591 -assert nopostproc +UVM_TESTNAME=otp_c trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.13485591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.1394979881 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 51946299 ps |
| CPU time | 2.35 seconds |
| Started | Sep 11 12:56:33 PM UTC 24 |
| Finished | Sep 11 12:56:36 PM UTC 24 |
| Peak memory | 242000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394979881 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.1394979881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2969295168 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 515049546 ps |
| CPU time | 1.77 seconds |
| Started | Sep 11 12:56:33 PM UTC 24 |
| Finished | Sep 11 12:56:35 PM UTC 24 |
| Peak memory | 240528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969295168 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_partial_access.2969295168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3054550248 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 71401601 ps |
| CPU time | 2.32 seconds |
| Started | Sep 11 12:56:33 PM UTC 24 |
| Finished | Sep 11 12:56:36 PM UTC 24 |
| Peak memory | 241460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054550248 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.3054550248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.3291839093 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 166846192 ps |
| CPU time | 1.99 seconds |
| Started | Sep 11 12:56:36 PM UTC 24 |
| Finished | Sep 11 12:56:39 PM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291839093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_same_csr_outstanding.3291839093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1539579698 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 169335327 ps |
| CPU time | 6.35 seconds |
| Started | Sep 11 12:56:33 PM UTC 24 |
| Finished | Sep 11 12:56:40 PM UTC 24 |
| Peak memory | 258896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539579698 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.1539579698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2912384076 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1411704443 ps |
| CPU time | 26.26 seconds |
| Started | Sep 11 12:56:33 PM UTC 24 |
| Finished | Sep 11 12:57:00 PM UTC 24 |
| Peak memory | 256836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912384076 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_intg_err.2912384076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.3039067754 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 41570770 ps |
| CPU time | 2.35 seconds |
| Started | Sep 11 12:57:14 PM UTC 24 |
| Finished | Sep 11 12:57:18 PM UTC 24 |
| Peak memory | 241920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039067754 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.3039067754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/30.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.3352872841 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 90553551 ps |
| CPU time | 2.16 seconds |
| Started | Sep 11 12:57:14 PM UTC 24 |
| Finished | Sep 11 12:57:18 PM UTC 24 |
| Peak memory | 242600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352872841 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.3352872841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/31.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.1372586380 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 52419194 ps |
| CPU time | 1.58 seconds |
| Started | Sep 11 12:57:14 PM UTC 24 |
| Finished | Sep 11 12:57:17 PM UTC 24 |
| Peak memory | 241016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372586380 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.1372586380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/32.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.4171839744 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 43437972 ps |
| CPU time | 2.18 seconds |
| Started | Sep 11 12:57:14 PM UTC 24 |
| Finished | Sep 11 12:57:18 PM UTC 24 |
| Peak memory | 241844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171839744 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.4171839744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/33.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.438582044 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 40212271 ps |
| CPU time | 1.8 seconds |
| Started | Sep 11 12:57:14 PM UTC 24 |
| Finished | Sep 11 12:57:17 PM UTC 24 |
| Peak memory | 241124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438582044 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.438582044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/34.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.3890459494 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 39607846 ps |
| CPU time | 2.29 seconds |
| Started | Sep 11 12:57:15 PM UTC 24 |
| Finished | Sep 11 12:57:19 PM UTC 24 |
| Peak memory | 241756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890459494 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3890459494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/35.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.2793910926 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 40672309 ps |
| CPU time | 1.53 seconds |
| Started | Sep 11 12:57:15 PM UTC 24 |
| Finished | Sep 11 12:57:18 PM UTC 24 |
| Peak memory | 241068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793910926 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.2793910926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/36.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.2425967872 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 71792660 ps |
| CPU time | 1.61 seconds |
| Started | Sep 11 12:57:15 PM UTC 24 |
| Finished | Sep 11 12:57:18 PM UTC 24 |
| Peak memory | 241188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425967872 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.2425967872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/37.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.4119424828 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 146685067 ps |
| CPU time | 1.53 seconds |
| Started | Sep 11 12:57:16 PM UTC 24 |
| Finished | Sep 11 12:57:18 PM UTC 24 |
| Peak memory | 241100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119424828 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.4119424828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/38.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.9415274 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 550257936 ps |
| CPU time | 2.21 seconds |
| Started | Sep 11 12:57:17 PM UTC 24 |
| Finished | Sep 11 12:57:20 PM UTC 24 |
| Peak memory | 241568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9415274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_ base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.9415274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/39.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2479626590 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 94081925 ps |
| CPU time | 3.19 seconds |
| Started | Sep 11 12:56:38 PM UTC 24 |
| Finished | Sep 11 12:56:43 PM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479626590 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_aliasing.2479626590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2931499894 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 1061847344 ps |
| CPU time | 9.55 seconds |
| Started | Sep 11 12:56:38 PM UTC 24 |
| Finished | Sep 11 12:56:49 PM UTC 24 |
| Peak memory | 242580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931499894 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_bash.2931499894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1757540034 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 271569119 ps |
| CPU time | 3.42 seconds |
| Started | Sep 11 12:56:37 PM UTC 24 |
| Finished | Sep 11 12:56:41 PM UTC 24 |
| Peak memory | 252736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757540034 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_reset.1757540034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3184291320 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 144101521 ps |
| CPU time | 2.24 seconds |
| Started | Sep 11 12:56:38 PM UTC 24 |
| Finished | Sep 11 12:56:42 PM UTC 24 |
| Peak memory | 258968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3184291320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_cs r_mem_rw_with_rand_reset.3184291320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.4112643424 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 72717867 ps |
| CPU time | 2.22 seconds |
| Started | Sep 11 12:56:38 PM UTC 24 |
| Finished | Sep 11 12:56:42 PM UTC 24 |
| Peak memory | 254748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112643424 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.4112643424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.466846814 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 127860078 ps |
| CPU time | 2.09 seconds |
| Started | Sep 11 12:56:37 PM UTC 24 |
| Finished | Sep 11 12:56:40 PM UTC 24 |
| Peak memory | 242128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466846814 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.466846814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1275719578 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 71794570 ps |
| CPU time | 2.24 seconds |
| Started | Sep 11 12:56:37 PM UTC 24 |
| Finished | Sep 11 12:56:40 PM UTC 24 |
| Peak memory | 241188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275719578 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_partial_access.1275719578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.835535724 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 68995297 ps |
| CPU time | 1.65 seconds |
| Started | Sep 11 12:56:37 PM UTC 24 |
| Finished | Sep 11 12:56:40 PM UTC 24 |
| Peak memory | 240580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835535724 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.835535724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.466613424 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 147436420 ps |
| CPU time | 4.02 seconds |
| Started | Sep 11 12:56:38 PM UTC 24 |
| Finished | Sep 11 12:56:44 PM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466613424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_same_csr_outstanding.466613424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.541080463 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 172664303 ps |
| CPU time | 9.52 seconds |
| Started | Sep 11 12:56:36 PM UTC 24 |
| Finished | Sep 11 12:56:46 PM UTC 24 |
| Peak memory | 259064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541080463 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.541080463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1575736499 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 1216599749 ps |
| CPU time | 9.78 seconds |
| Started | Sep 11 12:56:37 PM UTC 24 |
| Finished | Sep 11 12:56:48 PM UTC 24 |
| Peak memory | 256784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575736499 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg_err.1575736499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.4094850761 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 144106474 ps |
| CPU time | 1.62 seconds |
| Started | Sep 11 12:57:17 PM UTC 24 |
| Finished | Sep 11 12:57:19 PM UTC 24 |
| Peak memory | 241008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094850761 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.4094850761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/40.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.3336008183 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 45537950 ps |
| CPU time | 1.69 seconds |
| Started | Sep 11 12:57:17 PM UTC 24 |
| Finished | Sep 11 12:57:20 PM UTC 24 |
| Peak memory | 241128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336008183 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.3336008183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/41.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.738627449 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 154730374 ps |
| CPU time | 1.58 seconds |
| Started | Sep 11 12:57:17 PM UTC 24 |
| Finished | Sep 11 12:57:20 PM UTC 24 |
| Peak memory | 241132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738627449 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.738627449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/42.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.3270193670 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 37112058 ps |
| CPU time | 1.48 seconds |
| Started | Sep 11 12:57:17 PM UTC 24 |
| Finished | Sep 11 12:57:20 PM UTC 24 |
| Peak memory | 241444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270193670 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.3270193670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/43.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.2223580978 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 39365221 ps |
| CPU time | 1.87 seconds |
| Started | Sep 11 12:57:18 PM UTC 24 |
| Finished | Sep 11 12:57:21 PM UTC 24 |
| Peak memory | 241100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223580978 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.2223580978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/44.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.2647648661 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 571845220 ps |
| CPU time | 2.66 seconds |
| Started | Sep 11 12:57:18 PM UTC 24 |
| Finished | Sep 11 12:57:22 PM UTC 24 |
| Peak memory | 241992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647648661 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.2647648661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/45.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.1877218088 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 75125629 ps |
| CPU time | 1.5 seconds |
| Started | Sep 11 12:57:18 PM UTC 24 |
| Finished | Sep 11 12:57:21 PM UTC 24 |
| Peak memory | 241180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877218088 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.1877218088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/46.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.440306602 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 71251309 ps |
| CPU time | 2.15 seconds |
| Started | Sep 11 12:57:18 PM UTC 24 |
| Finished | Sep 11 12:57:22 PM UTC 24 |
| Peak memory | 242176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440306602 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.440306602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/47.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.1657375458 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 592413971 ps |
| CPU time | 2.68 seconds |
| Started | Sep 11 12:57:18 PM UTC 24 |
| Finished | Sep 11 12:57:22 PM UTC 24 |
| Peak memory | 242600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657375458 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.1657375458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/48.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.1715125918 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 74377951 ps |
| CPU time | 1.48 seconds |
| Started | Sep 11 12:57:19 PM UTC 24 |
| Finished | Sep 11 12:57:21 PM UTC 24 |
| Peak memory | 241680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715125918 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.1715125918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/49.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.3885915245 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 384965772 ps |
| CPU time | 3.7 seconds |
| Started | Sep 11 12:56:42 PM UTC 24 |
| Finished | Sep 11 12:56:47 PM UTC 24 |
| Peak memory | 259024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3885915245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_cs r_mem_rw_with_rand_reset.3885915245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.2975697064 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 164797148 ps |
| CPU time | 1.9 seconds |
| Started | Sep 11 12:56:42 PM UTC 24 |
| Finished | Sep 11 12:56:45 PM UTC 24 |
| Peak memory | 253996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975697064 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.2975697064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.3519080881 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 78881127 ps |
| CPU time | 1.94 seconds |
| Started | Sep 11 12:56:40 PM UTC 24 |
| Finished | Sep 11 12:56:43 PM UTC 24 |
| Peak memory | 241332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519080881 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.3519080881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3036893643 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 948616831 ps |
| CPU time | 3.62 seconds |
| Started | Sep 11 12:56:42 PM UTC 24 |
| Finished | Sep 11 12:56:47 PM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036893643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_same_csr_outstanding.3036893643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2713057839 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 432701865 ps |
| CPU time | 5.13 seconds |
| Started | Sep 11 12:56:38 PM UTC 24 |
| Finished | Sep 11 12:56:45 PM UTC 24 |
| Peak memory | 258892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713057839 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.2713057839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3840710367 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1233463587 ps |
| CPU time | 12.09 seconds |
| Started | Sep 11 12:56:40 PM UTC 24 |
| Finished | Sep 11 12:56:53 PM UTC 24 |
| Peak memory | 256896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840710367 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_intg_err.3840710367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1436000901 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 279714161 ps |
| CPU time | 2.61 seconds |
| Started | Sep 11 12:56:44 PM UTC 24 |
| Finished | Sep 11 12:56:48 PM UTC 24 |
| Peak memory | 256824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1436000901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_cs r_mem_rw_with_rand_reset.1436000901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.945447158 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 40495563 ps |
| CPU time | 2.25 seconds |
| Started | Sep 11 12:56:44 PM UTC 24 |
| Finished | Sep 11 12:56:48 PM UTC 24 |
| Peak memory | 254796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945447158 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.945447158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.3071194445 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 81050303 ps |
| CPU time | 1.99 seconds |
| Started | Sep 11 12:56:43 PM UTC 24 |
| Finished | Sep 11 12:56:47 PM UTC 24 |
| Peak memory | 241740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071194445 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.3071194445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.459619555 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 150021797 ps |
| CPU time | 2.92 seconds |
| Started | Sep 11 12:56:44 PM UTC 24 |
| Finished | Sep 11 12:56:48 PM UTC 24 |
| Peak memory | 252616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459619555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_same_csr_outstanding.459619555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.2914675360 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 237996649 ps |
| CPU time | 4.63 seconds |
| Started | Sep 11 12:56:42 PM UTC 24 |
| Finished | Sep 11 12:56:48 PM UTC 24 |
| Peak memory | 258992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914675360 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.2914675360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.603879753 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 103257371 ps |
| CPU time | 4.41 seconds |
| Started | Sep 11 12:56:46 PM UTC 24 |
| Finished | Sep 11 12:56:52 PM UTC 24 |
| Peak memory | 258952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=603879753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr _mem_rw_with_rand_reset.603879753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.103395722 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 665876494 ps |
| CPU time | 2.68 seconds |
| Started | Sep 11 12:56:46 PM UTC 24 |
| Finished | Sep 11 12:56:50 PM UTC 24 |
| Peak memory | 254724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103395722 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.103395722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.3181492519 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 46377831 ps |
| CPU time | 2.36 seconds |
| Started | Sep 11 12:56:46 PM UTC 24 |
| Finished | Sep 11 12:56:50 PM UTC 24 |
| Peak memory | 242180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181492519 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.3181492519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3952364935 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 130151211 ps |
| CPU time | 3.21 seconds |
| Started | Sep 11 12:56:46 PM UTC 24 |
| Finished | Sep 11 12:56:51 PM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952364935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_same_csr_outstanding.3952364935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.768344511 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 2193111586 ps |
| CPU time | 4.58 seconds |
| Started | Sep 11 12:56:44 PM UTC 24 |
| Finished | Sep 11 12:56:50 PM UTC 24 |
| Peak memory | 259084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768344511 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.768344511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.961258447 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 138989419 ps |
| CPU time | 2.35 seconds |
| Started | Sep 11 12:56:48 PM UTC 24 |
| Finished | Sep 11 12:56:52 PM UTC 24 |
| Peak memory | 257100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=961258447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr _mem_rw_with_rand_reset.961258447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.974324077 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 85410049 ps |
| CPU time | 2.56 seconds |
| Started | Sep 11 12:56:48 PM UTC 24 |
| Finished | Sep 11 12:56:52 PM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974324077 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.974324077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.3123843013 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 573523353 ps |
| CPU time | 2.06 seconds |
| Started | Sep 11 12:56:48 PM UTC 24 |
| Finished | Sep 11 12:56:51 PM UTC 24 |
| Peak memory | 242468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123843013 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.3123843013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.921907097 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 124007991 ps |
| CPU time | 3.21 seconds |
| Started | Sep 11 12:56:48 PM UTC 24 |
| Finished | Sep 11 12:56:53 PM UTC 24 |
| Peak memory | 252636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921907097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_same_csr_outstanding.921907097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.271485026 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 2767688523 ps |
| CPU time | 6.93 seconds |
| Started | Sep 11 12:56:48 PM UTC 24 |
| Finished | Sep 11 12:56:56 PM UTC 24 |
| Peak memory | 259084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271485026 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.271485026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2445469439 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 2567867473 ps |
| CPU time | 12.06 seconds |
| Started | Sep 11 12:56:48 PM UTC 24 |
| Finished | Sep 11 12:57:01 PM UTC 24 |
| Peak memory | 256844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445469439 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_intg_err.2445469439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.603066595 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 1718775512 ps |
| CPU time | 6.34 seconds |
| Started | Sep 11 12:56:51 PM UTC 24 |
| Finished | Sep 11 12:56:58 PM UTC 24 |
| Peak memory | 258880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=603066595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr _mem_rw_with_rand_reset.603066595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1210098656 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 43215871 ps |
| CPU time | 2.49 seconds |
| Started | Sep 11 12:56:51 PM UTC 24 |
| Finished | Sep 11 12:56:54 PM UTC 24 |
| Peak memory | 252616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210098656 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.1210098656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.3424023464 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 122253976 ps |
| CPU time | 1.79 seconds |
| Started | Sep 11 12:56:51 PM UTC 24 |
| Finished | Sep 11 12:56:54 PM UTC 24 |
| Peak memory | 241688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424023464 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.3424023464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.150739102 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 265087218 ps |
| CPU time | 3.58 seconds |
| Started | Sep 11 12:56:51 PM UTC 24 |
| Finished | Sep 11 12:56:55 PM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150739102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_same_csr_outstanding.150739102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.405433641 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 252779771 ps |
| CPU time | 6.76 seconds |
| Started | Sep 11 12:56:51 PM UTC 24 |
| Finished | Sep 11 12:56:58 PM UTC 24 |
| Peak memory | 252808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405433641 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.405433641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1068819893 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 20316282643 ps |
| CPU time | 27.04 seconds |
| Started | Sep 11 12:56:51 PM UTC 24 |
| Finished | Sep 11 12:57:19 PM UTC 24 |
| Peak memory | 256916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068819893 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_intg_err.1068819893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_alert_test.2047288939 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 81911258 ps |
| CPU time | 2.98 seconds |
| Started | Sep 11 12:57:22 PM UTC 24 |
| Finished | Sep 11 12:57:26 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047288939 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.2047288939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_check_fail.558666502 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 700158617 ps |
| CPU time | 9.47 seconds |
| Started | Sep 11 12:57:20 PM UTC 24 |
| Finished | Sep 11 12:57:31 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558666502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.558666502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_errs.1365521960 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 814905622 ps |
| CPU time | 13.59 seconds |
| Started | Sep 11 12:57:20 PM UTC 24 |
| Finished | Sep 11 12:57:35 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365521960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.1365521960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_low_freq_read.3787391011 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 6882712101 ps |
| CPU time | 16.86 seconds |
| Started | Sep 11 12:57:19 PM UTC 24 |
| Finished | Sep 11 12:57:37 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787391011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.3787391011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_macro_errs.1697455539 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 4173386473 ps |
| CPU time | 13.07 seconds |
| Started | Sep 11 12:57:20 PM UTC 24 |
| Finished | Sep 11 12:57:34 PM UTC 24 |
| Peak memory | 251608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697455539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.1697455539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_key_req.2806317816 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 3691143591 ps |
| CPU time | 26.3 seconds |
| Started | Sep 11 12:57:20 PM UTC 24 |
| Finished | Sep 11 12:57:48 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806317816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.2806317816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_esc.3274968172 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1053491169 ps |
| CPU time | 23.7 seconds |
| Started | Sep 11 12:57:19 PM UTC 24 |
| Finished | Sep 11 12:57:44 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274968172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.3274968172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_req.550797363 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 668963490 ps |
| CPU time | 17.52 seconds |
| Started | Sep 11 12:57:19 PM UTC 24 |
| Finished | Sep 11 12:57:38 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550797363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.550797363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_partition_walk.4006038207 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1575481571 ps |
| CPU time | 20.55 seconds |
| Started | Sep 11 12:57:19 PM UTC 24 |
| Finished | Sep 11 12:57:40 PM UTC 24 |
| Peak memory | 251496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006038207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.4006038207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_sec_cm.3429085046 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 18490264423 ps |
| CPU time | 176.96 seconds |
| Started | Sep 11 12:57:21 PM UTC 24 |
| Finished | Sep 11 01:00:21 PM UTC 24 |
| Peak memory | 298100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429085046 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.3429085046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_smoke.1436768220 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 437515050 ps |
| CPU time | 12.26 seconds |
| Started | Sep 11 12:57:19 PM UTC 24 |
| Finished | Sep 11 12:57:32 PM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436768220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.1436768220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_background_chks.1993180175 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 740958644 ps |
| CPU time | 12.67 seconds |
| Started | Sep 11 12:57:23 PM UTC 24 |
| Finished | Sep 11 12:57:36 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993180175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.1993180175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_errs.3769614701 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 3007997590 ps |
| CPU time | 28.93 seconds |
| Started | Sep 11 12:57:24 PM UTC 24 |
| Finished | Sep 11 12:57:54 PM UTC 24 |
| Peak memory | 253360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769614701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.3769614701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_key_req.872821271 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1083540233 ps |
| CPU time | 33.01 seconds |
| Started | Sep 11 12:57:25 PM UTC 24 |
| Finished | Sep 11 12:58:00 PM UTC 24 |
| Peak memory | 253352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872821271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.872821271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_esc.2754662381 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 283228011 ps |
| CPU time | 8.44 seconds |
| Started | Sep 11 12:57:23 PM UTC 24 |
| Finished | Sep 11 12:57:32 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754662381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.2754662381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_req.3890277245 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 5432962412 ps |
| CPU time | 21.26 seconds |
| Started | Sep 11 12:57:23 PM UTC 24 |
| Finished | Sep 11 12:57:45 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890277245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.3890277245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_regwen.1909054779 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 257561173 ps |
| CPU time | 4.53 seconds |
| Started | Sep 11 12:57:27 PM UTC 24 |
| Finished | Sep 11 12:57:33 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909054779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.1909054779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_sec_cm.2667427417 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 37138399320 ps |
| CPU time | 210.16 seconds |
| Started | Sep 11 12:57:31 PM UTC 24 |
| Finished | Sep 11 01:01:05 PM UTC 24 |
| Peak memory | 296048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667427417 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.2667427417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_smoke.3612847779 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 897737369 ps |
| CPU time | 8.28 seconds |
| Started | Sep 11 12:57:22 PM UTC 24 |
| Finished | Sep 11 12:57:32 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612847779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.3612847779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_test_access.1986700586 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 168661389 ps |
| CPU time | 7.85 seconds |
| Started | Sep 11 12:57:29 PM UTC 24 |
| Finished | Sep 11 12:57:38 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986700586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.1986700586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_alert_test.1527755371 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 224672737 ps |
| CPU time | 2.8 seconds |
| Started | Sep 11 12:59:09 PM UTC 24 |
| Finished | Sep 11 12:59:13 PM UTC 24 |
| Peak memory | 251404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527755371 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.1527755371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_check_fail.3911444175 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 5424202795 ps |
| CPU time | 18.8 seconds |
| Started | Sep 11 12:59:02 PM UTC 24 |
| Finished | Sep 11 12:59:22 PM UTC 24 |
| Peak memory | 253676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911444175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.3911444175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_errs.2555324685 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 2789268404 ps |
| CPU time | 25.11 seconds |
| Started | Sep 11 12:59:01 PM UTC 24 |
| Finished | Sep 11 12:59:28 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555324685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.2555324685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_lock.709916400 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 1177921915 ps |
| CPU time | 19.06 seconds |
| Started | Sep 11 12:59:01 PM UTC 24 |
| Finished | Sep 11 12:59:22 PM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709916400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.709916400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_macro_errs.1820210015 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 231729828 ps |
| CPU time | 7 seconds |
| Started | Sep 11 12:59:04 PM UTC 24 |
| Finished | Sep 11 12:59:12 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820210015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.1820210015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_key_req.1312129191 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 499919507 ps |
| CPU time | 12.63 seconds |
| Started | Sep 11 12:59:06 PM UTC 24 |
| Finished | Sep 11 12:59:20 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312129191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.1312129191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_esc.1907789075 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 3943257534 ps |
| CPU time | 12.38 seconds |
| Started | Sep 11 12:59:00 PM UTC 24 |
| Finished | Sep 11 12:59:13 PM UTC 24 |
| Peak memory | 251240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907789075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.1907789075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_regwen.3260664037 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 212694023 ps |
| CPU time | 7.62 seconds |
| Started | Sep 11 12:59:06 PM UTC 24 |
| Finished | Sep 11 12:59:15 PM UTC 24 |
| Peak memory | 251272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260664037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.3260664037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_smoke.2828158825 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 451399421 ps |
| CPU time | 10.25 seconds |
| Started | Sep 11 12:58:58 PM UTC 24 |
| Finished | Sep 11 12:59:09 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828158825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.2828158825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all.2038475082 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 9752920619 ps |
| CPU time | 84.29 seconds |
| Started | Sep 11 12:59:09 PM UTC 24 |
| Finished | Sep 11 01:00:35 PM UTC 24 |
| Peak memory | 255416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038475082 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.2038475082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_test_access.149781602 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2976325301 ps |
| CPU time | 9.15 seconds |
| Started | Sep 11 12:59:06 PM UTC 24 |
| Finished | Sep 11 12:59:17 PM UTC 24 |
| Peak memory | 251364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149781602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.149781602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/10.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_init_fail.1676330262 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 1963237537 ps |
| CPU time | 5.72 seconds |
| Started | Sep 11 01:05:20 PM UTC 24 |
| Finished | Sep 11 01:05:27 PM UTC 24 |
| Peak memory | 250488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676330262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.1676330262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/100.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_parallel_lc_esc.2131023907 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 1514877127 ps |
| CPU time | 7.67 seconds |
| Started | Sep 11 01:05:21 PM UTC 24 |
| Finished | Sep 11 01:05:29 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131023907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.2131023907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/100.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_init_fail.3458903986 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 171246782 ps |
| CPU time | 5.5 seconds |
| Started | Sep 11 01:05:21 PM UTC 24 |
| Finished | Sep 11 01:05:27 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458903986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.3458903986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/101.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_parallel_lc_esc.591331801 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 181896594 ps |
| CPU time | 3.84 seconds |
| Started | Sep 11 01:05:21 PM UTC 24 |
| Finished | Sep 11 01:05:26 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591331801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.591331801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/101.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_parallel_lc_esc.2451394039 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 1615634599 ps |
| CPU time | 8.46 seconds |
| Started | Sep 11 01:05:24 PM UTC 24 |
| Finished | Sep 11 01:05:34 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451394039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.2451394039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/102.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_init_fail.207321940 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 236625468 ps |
| CPU time | 4.57 seconds |
| Started | Sep 11 01:05:24 PM UTC 24 |
| Finished | Sep 11 01:05:30 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207321940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.207321940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/103.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_parallel_lc_esc.1648734909 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 380639133 ps |
| CPU time | 7.36 seconds |
| Started | Sep 11 01:05:24 PM UTC 24 |
| Finished | Sep 11 01:05:33 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648734909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.1648734909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/103.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_parallel_lc_esc.2534861941 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 223520788 ps |
| CPU time | 4.83 seconds |
| Started | Sep 11 01:05:27 PM UTC 24 |
| Finished | Sep 11 01:05:33 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534861941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.2534861941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/104.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_parallel_lc_esc.2647907768 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 862486904 ps |
| CPU time | 20.72 seconds |
| Started | Sep 11 01:05:27 PM UTC 24 |
| Finished | Sep 11 01:05:49 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647907768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.2647907768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/105.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_init_fail.2809415181 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 212173666 ps |
| CPU time | 4.26 seconds |
| Started | Sep 11 01:05:27 PM UTC 24 |
| Finished | Sep 11 01:05:32 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809415181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.2809415181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/106.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_parallel_lc_esc.2640460559 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 446845908 ps |
| CPU time | 8.29 seconds |
| Started | Sep 11 01:05:27 PM UTC 24 |
| Finished | Sep 11 01:05:36 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640460559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.2640460559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/106.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_init_fail.217062477 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 1643908654 ps |
| CPU time | 4.08 seconds |
| Started | Sep 11 01:05:27 PM UTC 24 |
| Finished | Sep 11 01:05:32 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217062477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.217062477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/107.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_init_fail.3757998606 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 254798772 ps |
| CPU time | 5.17 seconds |
| Started | Sep 11 01:05:29 PM UTC 24 |
| Finished | Sep 11 01:05:35 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757998606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.3757998606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/108.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_parallel_lc_esc.1088189710 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 200074849 ps |
| CPU time | 8.99 seconds |
| Started | Sep 11 01:05:29 PM UTC 24 |
| Finished | Sep 11 01:05:39 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088189710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.1088189710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/108.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_parallel_lc_esc.3331351349 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 835961746 ps |
| CPU time | 8.25 seconds |
| Started | Sep 11 01:05:29 PM UTC 24 |
| Finished | Sep 11 01:05:38 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331351349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.3331351349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/109.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_alert_test.391765195 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 93325417 ps |
| CPU time | 1.71 seconds |
| Started | Sep 11 12:59:15 PM UTC 24 |
| Finished | Sep 11 12:59:18 PM UTC 24 |
| Peak memory | 251140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391765195 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.391765195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_check_fail.726536165 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 912773212 ps |
| CPU time | 7.08 seconds |
| Started | Sep 11 12:59:12 PM UTC 24 |
| Finished | Sep 11 12:59:21 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726536165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.726536165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_errs.4123370138 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 3170108558 ps |
| CPU time | 21.8 seconds |
| Started | Sep 11 12:59:12 PM UTC 24 |
| Finished | Sep 11 12:59:35 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123370138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.4123370138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_lock.1219162307 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 1196108928 ps |
| CPU time | 12.82 seconds |
| Started | Sep 11 12:59:12 PM UTC 24 |
| Finished | Sep 11 12:59:26 PM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219162307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.1219162307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_macro_errs.2199184513 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 583307320 ps |
| CPU time | 12.94 seconds |
| Started | Sep 11 12:59:15 PM UTC 24 |
| Finished | Sep 11 12:59:29 PM UTC 24 |
| Peak memory | 253484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199184513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.2199184513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_key_req.3076982718 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 127031554 ps |
| CPU time | 7.25 seconds |
| Started | Sep 11 12:59:15 PM UTC 24 |
| Finished | Sep 11 12:59:23 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076982718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.3076982718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_req.2507497838 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 913305703 ps |
| CPU time | 6.99 seconds |
| Started | Sep 11 12:59:12 PM UTC 24 |
| Finished | Sep 11 12:59:20 PM UTC 24 |
| Peak memory | 250820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507497838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.2507497838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_regwen.3302321894 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 172860167 ps |
| CPU time | 6.8 seconds |
| Started | Sep 11 12:59:15 PM UTC 24 |
| Finished | Sep 11 12:59:23 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302321894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.3302321894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_smoke.324158169 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 4304803566 ps |
| CPU time | 11.26 seconds |
| Started | Sep 11 12:59:09 PM UTC 24 |
| Finished | Sep 11 12:59:21 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324158169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.324158169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_test_access.2905968258 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1894488648 ps |
| CPU time | 16.11 seconds |
| Started | Sep 11 12:59:15 PM UTC 24 |
| Finished | Sep 11 12:59:32 PM UTC 24 |
| Peak memory | 251624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905968258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.2905968258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/11.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_init_fail.2222017641 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 415651513 ps |
| CPU time | 5.75 seconds |
| Started | Sep 11 01:05:30 PM UTC 24 |
| Finished | Sep 11 01:05:37 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222017641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.2222017641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/110.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_parallel_lc_esc.3355158670 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 921214351 ps |
| CPU time | 11.99 seconds |
| Started | Sep 11 01:05:30 PM UTC 24 |
| Finished | Sep 11 01:05:44 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355158670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.3355158670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/110.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_init_fail.2889488165 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 134741116 ps |
| CPU time | 4.66 seconds |
| Started | Sep 11 01:05:32 PM UTC 24 |
| Finished | Sep 11 01:05:38 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889488165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.2889488165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/111.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_parallel_lc_esc.160492609 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 1888160565 ps |
| CPU time | 6.06 seconds |
| Started | Sep 11 01:05:32 PM UTC 24 |
| Finished | Sep 11 01:05:39 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160492609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.160492609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/111.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_init_fail.3798598738 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 173368155 ps |
| CPU time | 4.17 seconds |
| Started | Sep 11 01:05:37 PM UTC 24 |
| Finished | Sep 11 01:05:42 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798598738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.3798598738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/112.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_init_fail.581373183 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 142259579 ps |
| CPU time | 5.16 seconds |
| Started | Sep 11 01:05:37 PM UTC 24 |
| Finished | Sep 11 01:05:43 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581373183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.581373183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/113.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_parallel_lc_esc.765041313 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 119050244 ps |
| CPU time | 4.57 seconds |
| Started | Sep 11 01:05:37 PM UTC 24 |
| Finished | Sep 11 01:05:42 PM UTC 24 |
| Peak memory | 251368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765041313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.765041313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/113.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_init_fail.4096405621 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 371690175 ps |
| CPU time | 3.59 seconds |
| Started | Sep 11 01:05:37 PM UTC 24 |
| Finished | Sep 11 01:05:41 PM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096405621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.4096405621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/114.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_parallel_lc_esc.3410286483 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 687451612 ps |
| CPU time | 8 seconds |
| Started | Sep 11 01:05:41 PM UTC 24 |
| Finished | Sep 11 01:05:50 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410286483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.3410286483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/114.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_init_fail.1900227294 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 251159313 ps |
| CPU time | 4.7 seconds |
| Started | Sep 11 01:05:41 PM UTC 24 |
| Finished | Sep 11 01:05:46 PM UTC 24 |
| Peak memory | 251532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900227294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.1900227294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/115.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_parallel_lc_esc.3915018399 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 185735696 ps |
| CPU time | 8.95 seconds |
| Started | Sep 11 01:05:41 PM UTC 24 |
| Finished | Sep 11 01:05:51 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915018399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.3915018399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/115.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_init_fail.428189749 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 487126612 ps |
| CPU time | 4.28 seconds |
| Started | Sep 11 01:05:41 PM UTC 24 |
| Finished | Sep 11 01:05:46 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428189749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.428189749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/116.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_parallel_lc_esc.1002745536 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 192745968 ps |
| CPU time | 4.56 seconds |
| Started | Sep 11 01:05:41 PM UTC 24 |
| Finished | Sep 11 01:05:46 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002745536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.1002745536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/116.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_init_fail.4284095282 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 148465504 ps |
| CPU time | 4.93 seconds |
| Started | Sep 11 01:05:41 PM UTC 24 |
| Finished | Sep 11 01:05:47 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284095282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.4284095282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/117.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_parallel_lc_esc.3735720308 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 512177658 ps |
| CPU time | 6.97 seconds |
| Started | Sep 11 01:05:41 PM UTC 24 |
| Finished | Sep 11 01:05:49 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735720308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.3735720308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/117.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_init_fail.2770538466 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 446062495 ps |
| CPU time | 3.98 seconds |
| Started | Sep 11 01:05:41 PM UTC 24 |
| Finished | Sep 11 01:05:46 PM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770538466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.2770538466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/118.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_parallel_lc_esc.3384192883 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 1154957556 ps |
| CPU time | 14.74 seconds |
| Started | Sep 11 01:05:41 PM UTC 24 |
| Finished | Sep 11 01:05:57 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384192883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.3384192883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/118.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_init_fail.867716786 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 581647685 ps |
| CPU time | 4.42 seconds |
| Started | Sep 11 01:05:41 PM UTC 24 |
| Finished | Sep 11 01:05:46 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867716786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.867716786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/119.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_parallel_lc_esc.3088707270 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 152746821 ps |
| CPU time | 2.81 seconds |
| Started | Sep 11 01:05:41 PM UTC 24 |
| Finished | Sep 11 01:05:45 PM UTC 24 |
| Peak memory | 251328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088707270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.3088707270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/119.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_alert_test.1533997852 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 881021158 ps |
| CPU time | 4.93 seconds |
| Started | Sep 11 12:59:23 PM UTC 24 |
| Finished | Sep 11 12:59:29 PM UTC 24 |
| Peak memory | 251404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533997852 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.1533997852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_check_fail.3440936367 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1079904060 ps |
| CPU time | 11.27 seconds |
| Started | Sep 11 12:59:22 PM UTC 24 |
| Finished | Sep 11 12:59:35 PM UTC 24 |
| Peak memory | 253352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440936367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.3440936367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_errs.2527066100 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 527823264 ps |
| CPU time | 18.91 seconds |
| Started | Sep 11 12:59:22 PM UTC 24 |
| Finished | Sep 11 12:59:42 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527066100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.2527066100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_lock.1384157798 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 3466272036 ps |
| CPU time | 39.29 seconds |
| Started | Sep 11 12:59:22 PM UTC 24 |
| Finished | Sep 11 01:00:03 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384157798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.1384157798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_macro_errs.1472555221 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 708158950 ps |
| CPU time | 22.14 seconds |
| Started | Sep 11 12:59:22 PM UTC 24 |
| Finished | Sep 11 12:59:46 PM UTC 24 |
| Peak memory | 253612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472555221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.1472555221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_key_req.3257921382 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 18232902418 ps |
| CPU time | 25.59 seconds |
| Started | Sep 11 12:59:22 PM UTC 24 |
| Finished | Sep 11 12:59:49 PM UTC 24 |
| Peak memory | 253680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257921382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.3257921382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_esc.2239490802 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 2206266377 ps |
| CPU time | 7.63 seconds |
| Started | Sep 11 12:59:22 PM UTC 24 |
| Finished | Sep 11 12:59:31 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239490802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.2239490802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_req.422428805 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2353699986 ps |
| CPU time | 22.29 seconds |
| Started | Sep 11 12:59:22 PM UTC 24 |
| Finished | Sep 11 12:59:46 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422428805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.422428805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_regwen.4144645442 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 1897248779 ps |
| CPU time | 8.54 seconds |
| Started | Sep 11 12:59:22 PM UTC 24 |
| Finished | Sep 11 12:59:32 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144645442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.4144645442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_smoke.1190628164 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 411573698 ps |
| CPU time | 4.97 seconds |
| Started | Sep 11 12:59:22 PM UTC 24 |
| Finished | Sep 11 12:59:28 PM UTC 24 |
| Peak memory | 251368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190628164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.1190628164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all.3528837127 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 66257219402 ps |
| CPU time | 320.23 seconds |
| Started | Sep 11 12:59:23 PM UTC 24 |
| Finished | Sep 11 01:04:47 PM UTC 24 |
| Peak memory | 290388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528837127 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.3528837127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_test_access.3065919959 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1625660135 ps |
| CPU time | 22.79 seconds |
| Started | Sep 11 12:59:22 PM UTC 24 |
| Finished | Sep 11 12:59:47 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065919959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.3065919959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/12.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_init_fail.862672793 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 141667113 ps |
| CPU time | 5.26 seconds |
| Started | Sep 11 01:05:41 PM UTC 24 |
| Finished | Sep 11 01:05:47 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862672793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.862672793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/120.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_parallel_lc_esc.4268819171 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 208408248 ps |
| CPU time | 5.2 seconds |
| Started | Sep 11 01:05:41 PM UTC 24 |
| Finished | Sep 11 01:05:47 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268819171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.4268819171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/120.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_init_fail.971803495 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 298826209 ps |
| CPU time | 4.54 seconds |
| Started | Sep 11 01:05:41 PM UTC 24 |
| Finished | Sep 11 01:05:47 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971803495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.971803495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/121.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_parallel_lc_esc.24654854 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 363739695 ps |
| CPU time | 10.38 seconds |
| Started | Sep 11 01:05:41 PM UTC 24 |
| Finished | Sep 11 01:05:53 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24654854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.24654854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/121.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_init_fail.2311286795 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 192831770 ps |
| CPU time | 4.22 seconds |
| Started | Sep 11 01:05:44 PM UTC 24 |
| Finished | Sep 11 01:05:49 PM UTC 24 |
| Peak memory | 250756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311286795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.2311286795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/122.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_parallel_lc_esc.2443280108 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 325057280 ps |
| CPU time | 3.19 seconds |
| Started | Sep 11 01:05:44 PM UTC 24 |
| Finished | Sep 11 01:05:48 PM UTC 24 |
| Peak memory | 250776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443280108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.2443280108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/122.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_init_fail.3320723761 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 2525716993 ps |
| CPU time | 6.4 seconds |
| Started | Sep 11 01:05:44 PM UTC 24 |
| Finished | Sep 11 01:05:51 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320723761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.3320723761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/123.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_parallel_lc_esc.332851491 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 585807374 ps |
| CPU time | 7.44 seconds |
| Started | Sep 11 01:05:44 PM UTC 24 |
| Finished | Sep 11 01:05:52 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332851491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.332851491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/123.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_init_fail.3610487014 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 144617400 ps |
| CPU time | 3.87 seconds |
| Started | Sep 11 01:05:44 PM UTC 24 |
| Finished | Sep 11 01:05:49 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610487014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.3610487014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/124.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_parallel_lc_esc.3009592728 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 2730910049 ps |
| CPU time | 9.52 seconds |
| Started | Sep 11 01:05:47 PM UTC 24 |
| Finished | Sep 11 01:05:58 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009592728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.3009592728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/124.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_init_fail.3168257350 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 246168631 ps |
| CPU time | 3.77 seconds |
| Started | Sep 11 01:05:47 PM UTC 24 |
| Finished | Sep 11 01:05:52 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168257350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.3168257350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/125.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_parallel_lc_esc.3234710055 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 448915830 ps |
| CPU time | 11.76 seconds |
| Started | Sep 11 01:05:47 PM UTC 24 |
| Finished | Sep 11 01:06:00 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234710055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.3234710055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/125.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_init_fail.3710918925 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 2109169151 ps |
| CPU time | 5.1 seconds |
| Started | Sep 11 01:05:48 PM UTC 24 |
| Finished | Sep 11 01:05:54 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710918925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.3710918925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/126.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_parallel_lc_esc.321535387 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 530314072 ps |
| CPU time | 7.01 seconds |
| Started | Sep 11 01:05:48 PM UTC 24 |
| Finished | Sep 11 01:05:56 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321535387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.321535387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/126.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_init_fail.3469516473 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 157113411 ps |
| CPU time | 3.46 seconds |
| Started | Sep 11 01:05:48 PM UTC 24 |
| Finished | Sep 11 01:05:52 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469516473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.3469516473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/127.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_parallel_lc_esc.2101519163 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 209756435 ps |
| CPU time | 4.32 seconds |
| Started | Sep 11 01:05:48 PM UTC 24 |
| Finished | Sep 11 01:05:53 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101519163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.2101519163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/127.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_init_fail.164703275 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 136453322 ps |
| CPU time | 3.94 seconds |
| Started | Sep 11 01:05:48 PM UTC 24 |
| Finished | Sep 11 01:05:53 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164703275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.164703275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/128.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_parallel_lc_esc.1838759290 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 1848716577 ps |
| CPU time | 5.03 seconds |
| Started | Sep 11 01:05:48 PM UTC 24 |
| Finished | Sep 11 01:05:54 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838759290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.1838759290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/128.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_init_fail.3616976243 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 97888647 ps |
| CPU time | 3.86 seconds |
| Started | Sep 11 01:05:48 PM UTC 24 |
| Finished | Sep 11 01:05:53 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616976243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.3616976243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/129.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_parallel_lc_esc.506454720 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 2599225701 ps |
| CPU time | 9.04 seconds |
| Started | Sep 11 01:05:50 PM UTC 24 |
| Finished | Sep 11 01:06:00 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506454720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.506454720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/129.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_alert_test.1595953563 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 58755248 ps |
| CPU time | 2.45 seconds |
| Started | Sep 11 12:59:29 PM UTC 24 |
| Finished | Sep 11 12:59:33 PM UTC 24 |
| Peak memory | 251240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595953563 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.1595953563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_lock.4226092172 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 14740232301 ps |
| CPU time | 42.49 seconds |
| Started | Sep 11 12:59:24 PM UTC 24 |
| Finished | Sep 11 01:00:08 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226092172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.4226092172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_init_fail.2801681952 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 254808458 ps |
| CPU time | 4.03 seconds |
| Started | Sep 11 12:59:23 PM UTC 24 |
| Finished | Sep 11 12:59:28 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801681952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.2801681952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_macro_errs.3970114428 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 394233316 ps |
| CPU time | 8.28 seconds |
| Started | Sep 11 12:59:25 PM UTC 24 |
| Finished | Sep 11 12:59:34 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970114428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.3970114428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_key_req.769127131 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 938963862 ps |
| CPU time | 8.21 seconds |
| Started | Sep 11 12:59:27 PM UTC 24 |
| Finished | Sep 11 12:59:37 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769127131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.769127131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_esc.671930888 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 2087206591 ps |
| CPU time | 6.81 seconds |
| Started | Sep 11 12:59:24 PM UTC 24 |
| Finished | Sep 11 12:59:32 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671930888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.671930888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_req.617048459 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 224627035 ps |
| CPU time | 5.03 seconds |
| Started | Sep 11 12:59:24 PM UTC 24 |
| Finished | Sep 11 12:59:30 PM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617048459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.617048459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_smoke.773356373 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 3412542567 ps |
| CPU time | 18.97 seconds |
| Started | Sep 11 12:59:23 PM UTC 24 |
| Finished | Sep 11 12:59:43 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773356373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.773356373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.4094726256 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 43330547074 ps |
| CPU time | 129.36 seconds |
| Started | Sep 11 12:59:27 PM UTC 24 |
| Finished | Sep 11 01:01:39 PM UTC 24 |
| Peak memory | 267940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4094726256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.otp_ctrl_stress_all_with_rand_reset.4094726256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_test_access.1412493561 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 2319692441 ps |
| CPU time | 21.84 seconds |
| Started | Sep 11 12:59:27 PM UTC 24 |
| Finished | Sep 11 12:59:51 PM UTC 24 |
| Peak memory | 251432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412493561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.1412493561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/13.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_init_fail.2130615537 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 501146217 ps |
| CPU time | 4.7 seconds |
| Started | Sep 11 01:05:50 PM UTC 24 |
| Finished | Sep 11 01:05:56 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130615537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.2130615537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/130.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_parallel_lc_esc.3326559529 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 204278529 ps |
| CPU time | 3.11 seconds |
| Started | Sep 11 01:05:50 PM UTC 24 |
| Finished | Sep 11 01:05:54 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326559529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.3326559529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/130.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_init_fail.3823505624 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 130026089 ps |
| CPU time | 4.57 seconds |
| Started | Sep 11 01:05:50 PM UTC 24 |
| Finished | Sep 11 01:05:56 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823505624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.3823505624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/131.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_parallel_lc_esc.538243405 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 688032153 ps |
| CPU time | 6.03 seconds |
| Started | Sep 11 01:05:50 PM UTC 24 |
| Finished | Sep 11 01:05:57 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538243405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.538243405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/131.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_init_fail.1461038232 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 1849898530 ps |
| CPU time | 5.11 seconds |
| Started | Sep 11 01:05:50 PM UTC 24 |
| Finished | Sep 11 01:05:56 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461038232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.1461038232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/132.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_parallel_lc_esc.1430398688 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 283889785 ps |
| CPU time | 3.95 seconds |
| Started | Sep 11 01:05:50 PM UTC 24 |
| Finished | Sep 11 01:05:55 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430398688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.1430398688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/132.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_init_fail.1727468379 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 387700513 ps |
| CPU time | 3.16 seconds |
| Started | Sep 11 01:05:50 PM UTC 24 |
| Finished | Sep 11 01:05:54 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727468379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.1727468379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/133.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_parallel_lc_esc.1041399117 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 893835840 ps |
| CPU time | 15.09 seconds |
| Started | Sep 11 01:05:50 PM UTC 24 |
| Finished | Sep 11 01:06:07 PM UTC 24 |
| Peak memory | 250996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041399117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.1041399117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/133.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_init_fail.1137356310 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1703924834 ps |
| CPU time | 5.14 seconds |
| Started | Sep 11 01:05:50 PM UTC 24 |
| Finished | Sep 11 01:05:57 PM UTC 24 |
| Peak memory | 253324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137356310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.1137356310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/134.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_parallel_lc_esc.1198541860 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 11826934301 ps |
| CPU time | 34.8 seconds |
| Started | Sep 11 01:05:59 PM UTC 24 |
| Finished | Sep 11 01:06:36 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198541860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.1198541860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/134.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_parallel_lc_esc.122673933 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 1267551488 ps |
| CPU time | 6.91 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:08 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122673933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.122673933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/135.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_parallel_lc_esc.281780170 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 131082021 ps |
| CPU time | 2.73 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:03 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281780170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.281780170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/136.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_init_fail.3835696343 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 247691456 ps |
| CPU time | 3.31 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:04 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835696343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.3835696343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/137.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_parallel_lc_esc.113838688 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 4189573838 ps |
| CPU time | 11.34 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:12 PM UTC 24 |
| Peak memory | 251240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113838688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.113838688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/137.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_init_fail.660071312 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 95533494 ps |
| CPU time | 3.1 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:04 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660071312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.660071312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/138.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_parallel_lc_esc.2193075922 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 222458157 ps |
| CPU time | 3.8 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:05 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193075922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.2193075922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/138.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_init_fail.3050179836 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 115185447 ps |
| CPU time | 3.92 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:05 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050179836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.3050179836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/139.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_parallel_lc_esc.1585116182 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 7164433197 ps |
| CPU time | 12.4 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:13 PM UTC 24 |
| Peak memory | 253488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585116182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.1585116182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/139.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_alert_test.2693611659 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 53054075 ps |
| CPU time | 2.5 seconds |
| Started | Sep 11 12:59:36 PM UTC 24 |
| Finished | Sep 11 12:59:39 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693611659 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.2693611659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_check_fail.507577263 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 10383333411 ps |
| CPU time | 24.19 seconds |
| Started | Sep 11 12:59:32 PM UTC 24 |
| Finished | Sep 11 12:59:58 PM UTC 24 |
| Peak memory | 253552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507577263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.507577263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_errs.876857753 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 682892773 ps |
| CPU time | 23.56 seconds |
| Started | Sep 11 12:59:32 PM UTC 24 |
| Finished | Sep 11 12:59:57 PM UTC 24 |
| Peak memory | 251580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876857753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.876857753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_lock.2217742238 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 466482092 ps |
| CPU time | 5.38 seconds |
| Started | Sep 11 12:59:32 PM UTC 24 |
| Finished | Sep 11 12:59:39 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217742238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.2217742238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_init_fail.2539975334 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2589157225 ps |
| CPU time | 9.56 seconds |
| Started | Sep 11 12:59:29 PM UTC 24 |
| Finished | Sep 11 12:59:40 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539975334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.2539975334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_macro_errs.1916811296 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 22994318095 ps |
| CPU time | 42.47 seconds |
| Started | Sep 11 12:59:32 PM UTC 24 |
| Finished | Sep 11 01:00:16 PM UTC 24 |
| Peak memory | 267820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916811296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.1916811296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_key_req.424916664 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 15051879943 ps |
| CPU time | 47.75 seconds |
| Started | Sep 11 12:59:34 PM UTC 24 |
| Finished | Sep 11 01:00:23 PM UTC 24 |
| Peak memory | 253676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424916664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.424916664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_esc.3263760332 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 591923053 ps |
| CPU time | 6.39 seconds |
| Started | Sep 11 12:59:32 PM UTC 24 |
| Finished | Sep 11 12:59:40 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263760332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.3263760332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_req.1979482115 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 612504929 ps |
| CPU time | 12.5 seconds |
| Started | Sep 11 12:59:29 PM UTC 24 |
| Finished | Sep 11 12:59:43 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979482115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.1979482115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_regwen.1579008709 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 463297982 ps |
| CPU time | 7.83 seconds |
| Started | Sep 11 12:59:34 PM UTC 24 |
| Finished | Sep 11 12:59:43 PM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579008709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.1579008709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_smoke.530645355 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 678715343 ps |
| CPU time | 10.77 seconds |
| Started | Sep 11 12:59:29 PM UTC 24 |
| Finished | Sep 11 12:59:41 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530645355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.530645355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_test_access.782830202 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2944924290 ps |
| CPU time | 26.39 seconds |
| Started | Sep 11 12:59:34 PM UTC 24 |
| Finished | Sep 11 01:00:02 PM UTC 24 |
| Peak memory | 257548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782830202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.782830202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/14.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_init_fail.4048222929 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 166097802 ps |
| CPU time | 4.69 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:06 PM UTC 24 |
| Peak memory | 253580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048222929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.4048222929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/140.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_parallel_lc_esc.3876854397 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 502391397 ps |
| CPU time | 5.63 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:07 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876854397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.3876854397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/140.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_init_fail.1170368396 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 129818956 ps |
| CPU time | 5.03 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:06 PM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170368396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.1170368396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/141.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_parallel_lc_esc.887335328 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 316260997 ps |
| CPU time | 3.83 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:05 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887335328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.887335328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/141.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_init_fail.1108203049 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 170703382 ps |
| CPU time | 4.65 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:06 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108203049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.1108203049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/142.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_parallel_lc_esc.3012829855 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 13349358000 ps |
| CPU time | 25.29 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:26 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012829855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.3012829855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/142.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_init_fail.3268567505 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 404493724 ps |
| CPU time | 3.45 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:05 PM UTC 24 |
| Peak memory | 251240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268567505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.3268567505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/143.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_parallel_lc_esc.947139368 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 3213972159 ps |
| CPU time | 7.6 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:09 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947139368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.947139368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/143.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_init_fail.2878144884 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 2234591029 ps |
| CPU time | 6.55 seconds |
| Started | Sep 11 01:06:00 PM UTC 24 |
| Finished | Sep 11 01:06:08 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878144884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.2878144884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/144.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_init_fail.2877980273 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 191168813 ps |
| CPU time | 4.47 seconds |
| Started | Sep 11 01:06:04 PM UTC 24 |
| Finished | Sep 11 01:06:10 PM UTC 24 |
| Peak memory | 251532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877980273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.2877980273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/145.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_parallel_lc_esc.358698382 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 642411116 ps |
| CPU time | 12.94 seconds |
| Started | Sep 11 01:06:05 PM UTC 24 |
| Finished | Sep 11 01:06:19 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358698382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.358698382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/145.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_init_fail.2398392776 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 271380888 ps |
| CPU time | 4.11 seconds |
| Started | Sep 11 01:06:05 PM UTC 24 |
| Finished | Sep 11 01:06:10 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398392776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.2398392776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/146.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_parallel_lc_esc.2596888460 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 3950081714 ps |
| CPU time | 5.75 seconds |
| Started | Sep 11 01:06:05 PM UTC 24 |
| Finished | Sep 11 01:06:11 PM UTC 24 |
| Peak memory | 251568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596888460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.2596888460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/146.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_init_fail.1167433316 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 2632770439 ps |
| CPU time | 7.25 seconds |
| Started | Sep 11 01:06:05 PM UTC 24 |
| Finished | Sep 11 01:06:13 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167433316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.1167433316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/147.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_parallel_lc_esc.1092331093 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 335910480 ps |
| CPU time | 4.37 seconds |
| Started | Sep 11 01:06:05 PM UTC 24 |
| Finished | Sep 11 01:06:10 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092331093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.1092331093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/147.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_init_fail.616888204 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 141373289 ps |
| CPU time | 4.44 seconds |
| Started | Sep 11 01:06:05 PM UTC 24 |
| Finished | Sep 11 01:06:10 PM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616888204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.616888204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/148.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_parallel_lc_esc.3751923678 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 599076965 ps |
| CPU time | 7.12 seconds |
| Started | Sep 11 01:06:05 PM UTC 24 |
| Finished | Sep 11 01:06:13 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751923678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.3751923678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/148.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_parallel_lc_esc.2589098967 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 289239258 ps |
| CPU time | 8.18 seconds |
| Started | Sep 11 01:06:05 PM UTC 24 |
| Finished | Sep 11 01:06:14 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589098967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.2589098967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/149.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_alert_test.74240865 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 67906124 ps |
| CPU time | 2.4 seconds |
| Started | Sep 11 12:59:46 PM UTC 24 |
| Finished | Sep 11 12:59:50 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74240865 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.74240865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_check_fail.2305403885 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 2622856749 ps |
| CPU time | 26.59 seconds |
| Started | Sep 11 12:59:41 PM UTC 24 |
| Finished | Sep 11 01:00:09 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305403885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.2305403885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_errs.1609560374 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 6585253986 ps |
| CPU time | 41.05 seconds |
| Started | Sep 11 12:59:40 PM UTC 24 |
| Finished | Sep 11 01:00:22 PM UTC 24 |
| Peak memory | 257392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609560374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.1609560374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_lock.2766382592 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 3569485651 ps |
| CPU time | 41.37 seconds |
| Started | Sep 11 12:59:40 PM UTC 24 |
| Finished | Sep 11 01:00:23 PM UTC 24 |
| Peak memory | 257780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766382592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.2766382592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_init_fail.3280158334 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2445437098 ps |
| CPU time | 6.02 seconds |
| Started | Sep 11 12:59:37 PM UTC 24 |
| Finished | Sep 11 12:59:45 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280158334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.3280158334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_macro_errs.3389370396 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 13904521779 ps |
| CPU time | 50.49 seconds |
| Started | Sep 11 12:59:41 PM UTC 24 |
| Finished | Sep 11 01:00:33 PM UTC 24 |
| Peak memory | 257684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389370396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.3389370396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_key_req.3175890955 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 768816780 ps |
| CPU time | 28.98 seconds |
| Started | Sep 11 12:59:43 PM UTC 24 |
| Finished | Sep 11 01:00:13 PM UTC 24 |
| Peak memory | 253588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175890955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.3175890955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_esc.2202471304 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 4600226209 ps |
| CPU time | 13.5 seconds |
| Started | Sep 11 12:59:39 PM UTC 24 |
| Finished | Sep 11 12:59:53 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202471304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.2202471304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_req.3362002975 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 313428671 ps |
| CPU time | 10.21 seconds |
| Started | Sep 11 12:59:38 PM UTC 24 |
| Finished | Sep 11 12:59:49 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362002975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.3362002975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_regwen.3383140849 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 606656694 ps |
| CPU time | 10.45 seconds |
| Started | Sep 11 12:59:43 PM UTC 24 |
| Finished | Sep 11 12:59:54 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383140849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.3383140849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_smoke.2511138186 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 351543034 ps |
| CPU time | 6.89 seconds |
| Started | Sep 11 12:59:37 PM UTC 24 |
| Finished | Sep 11 12:59:45 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511138186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.2511138186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all.2031582778 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 7157195053 ps |
| CPU time | 54.34 seconds |
| Started | Sep 11 12:59:46 PM UTC 24 |
| Finished | Sep 11 01:00:42 PM UTC 24 |
| Peak memory | 253712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031582778 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.2031582778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_test_access.3151010982 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 287470194 ps |
| CPU time | 4.97 seconds |
| Started | Sep 11 12:59:46 PM UTC 24 |
| Finished | Sep 11 12:59:52 PM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151010982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.3151010982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/15.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_init_fail.1165956335 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 2589788358 ps |
| CPU time | 4.7 seconds |
| Started | Sep 11 01:06:05 PM UTC 24 |
| Finished | Sep 11 01:06:11 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165956335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.1165956335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/150.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_parallel_lc_esc.983179389 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 124219586 ps |
| CPU time | 6.1 seconds |
| Started | Sep 11 01:06:05 PM UTC 24 |
| Finished | Sep 11 01:06:12 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983179389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.983179389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/150.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_init_fail.1664082234 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 205513382 ps |
| CPU time | 3.61 seconds |
| Started | Sep 11 01:06:05 PM UTC 24 |
| Finished | Sep 11 01:06:10 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664082234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.1664082234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/151.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_parallel_lc_esc.1731703493 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 859861680 ps |
| CPU time | 6.73 seconds |
| Started | Sep 11 01:06:05 PM UTC 24 |
| Finished | Sep 11 01:06:13 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731703493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.1731703493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/151.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_init_fail.2001445932 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 86218263 ps |
| CPU time | 2.55 seconds |
| Started | Sep 11 01:06:05 PM UTC 24 |
| Finished | Sep 11 01:06:09 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001445932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.2001445932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/152.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_parallel_lc_esc.2172736458 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 192262488 ps |
| CPU time | 4.29 seconds |
| Started | Sep 11 01:06:05 PM UTC 24 |
| Finished | Sep 11 01:06:10 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172736458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.2172736458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/152.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_init_fail.259017648 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 347847209 ps |
| CPU time | 4.16 seconds |
| Started | Sep 11 01:06:05 PM UTC 24 |
| Finished | Sep 11 01:06:10 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259017648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.259017648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/153.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_parallel_lc_esc.3283165126 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 1639847126 ps |
| CPU time | 10.69 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:27 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283165126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.3283165126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/153.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_init_fail.326717596 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 2402589624 ps |
| CPU time | 5.15 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:21 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326717596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.326717596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/154.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_parallel_lc_esc.3755885692 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 99632177 ps |
| CPU time | 2.14 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:18 PM UTC 24 |
| Peak memory | 251096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755885692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.3755885692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/154.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_init_fail.1447877192 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 155520771 ps |
| CPU time | 3.38 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:19 PM UTC 24 |
| Peak memory | 251464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447877192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.1447877192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/155.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_parallel_lc_esc.1567660629 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 176512457 ps |
| CPU time | 4.37 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:20 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567660629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.1567660629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/155.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_init_fail.676201611 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 156170643 ps |
| CPU time | 3.32 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:19 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676201611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.676201611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/156.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_parallel_lc_esc.3522778000 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 2397999234 ps |
| CPU time | 5.19 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:21 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522778000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.3522778000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/156.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_init_fail.381838562 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 386716900 ps |
| CPU time | 3.45 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:19 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381838562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.381838562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/157.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_init_fail.111094712 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 124777690 ps |
| CPU time | 3.28 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:19 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111094712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.111094712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/158.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_parallel_lc_esc.3255628307 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 539036274 ps |
| CPU time | 6.08 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:22 PM UTC 24 |
| Peak memory | 250968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255628307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.3255628307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/158.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_init_fail.1921240352 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 126374950 ps |
| CPU time | 3.92 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:20 PM UTC 24 |
| Peak memory | 251012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921240352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.1921240352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/159.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_parallel_lc_esc.1275153885 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 525282526 ps |
| CPU time | 11.73 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:28 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275153885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.1275153885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/159.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_alert_test.1148080878 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 96489532 ps |
| CPU time | 1.75 seconds |
| Started | Sep 11 12:59:54 PM UTC 24 |
| Finished | Sep 11 12:59:57 PM UTC 24 |
| Peak memory | 251060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148080878 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.1148080878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_check_fail.3300150753 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 677833233 ps |
| CPU time | 17.92 seconds |
| Started | Sep 11 12:59:49 PM UTC 24 |
| Finished | Sep 11 01:00:08 PM UTC 24 |
| Peak memory | 253420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300150753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.3300150753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_errs.2311296579 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1402571233 ps |
| CPU time | 24.15 seconds |
| Started | Sep 11 12:59:48 PM UTC 24 |
| Finished | Sep 11 01:00:14 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311296579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.2311296579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_lock.3369606051 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 674501864 ps |
| CPU time | 21.9 seconds |
| Started | Sep 11 12:59:48 PM UTC 24 |
| Finished | Sep 11 01:00:11 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369606051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.3369606051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_init_fail.539715361 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 503123280 ps |
| CPU time | 6.33 seconds |
| Started | Sep 11 12:59:46 PM UTC 24 |
| Finished | Sep 11 12:59:54 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539715361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.539715361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_macro_errs.3737256264 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 3046932685 ps |
| CPU time | 39 seconds |
| Started | Sep 11 12:59:52 PM UTC 24 |
| Finished | Sep 11 01:00:32 PM UTC 24 |
| Peak memory | 257644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737256264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.3737256264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_key_req.2249418459 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2271355583 ps |
| CPU time | 17.24 seconds |
| Started | Sep 11 12:59:52 PM UTC 24 |
| Finished | Sep 11 01:00:10 PM UTC 24 |
| Peak memory | 253420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249418459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.2249418459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_esc.2141551896 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 1496610923 ps |
| CPU time | 11.49 seconds |
| Started | Sep 11 12:59:48 PM UTC 24 |
| Finished | Sep 11 01:00:01 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141551896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.2141551896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_req.2442010422 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1478738748 ps |
| CPU time | 30.46 seconds |
| Started | Sep 11 12:59:46 PM UTC 24 |
| Finished | Sep 11 01:00:18 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442010422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.2442010422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_regwen.2157189758 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 698198081 ps |
| CPU time | 8.51 seconds |
| Started | Sep 11 12:59:52 PM UTC 24 |
| Finished | Sep 11 01:00:02 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157189758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.2157189758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_smoke.4016053739 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2455956657 ps |
| CPU time | 22.13 seconds |
| Started | Sep 11 12:59:46 PM UTC 24 |
| Finished | Sep 11 01:00:10 PM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016053739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.4016053739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_test_access.2081772752 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 747684930 ps |
| CPU time | 13.37 seconds |
| Started | Sep 11 12:59:52 PM UTC 24 |
| Finished | Sep 11 01:00:07 PM UTC 24 |
| Peak memory | 251560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081772752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.2081772752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/16.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_init_fail.75842224 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 103273368 ps |
| CPU time | 3.24 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:19 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75842224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.75842224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/160.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_parallel_lc_esc.1529226936 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 264554580 ps |
| CPU time | 4.39 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:21 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529226936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.1529226936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/160.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_init_fail.2346108773 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 1511541469 ps |
| CPU time | 3.39 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:20 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346108773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.2346108773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/161.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_parallel_lc_esc.4152358324 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 1113210661 ps |
| CPU time | 14.74 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:31 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152358324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.4152358324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/161.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_init_fail.3328072576 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 294935723 ps |
| CPU time | 3.46 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:20 PM UTC 24 |
| Peak memory | 251404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328072576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.3328072576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/162.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_parallel_lc_esc.3410426529 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 597534666 ps |
| CPU time | 6.21 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:22 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410426529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.3410426529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/162.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_init_fail.3531532472 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 122484941 ps |
| CPU time | 3.71 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:20 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531532472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.3531532472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/163.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_parallel_lc_esc.4010308103 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 219687577 ps |
| CPU time | 4.8 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:21 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010308103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.4010308103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/163.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_init_fail.2845059234 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1946018117 ps |
| CPU time | 5.48 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:22 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845059234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.2845059234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/164.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_parallel_lc_esc.4173520786 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 590504460 ps |
| CPU time | 7.46 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:24 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173520786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.4173520786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/164.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_init_fail.940312675 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 123657042 ps |
| CPU time | 2.9 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:19 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940312675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.940312675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/165.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_parallel_lc_esc.3255479083 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 3544142140 ps |
| CPU time | 9.59 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:26 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255479083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.3255479083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/165.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_init_fail.456912789 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 119041556 ps |
| CPU time | 4.14 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:21 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456912789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.456912789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/166.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_parallel_lc_esc.3051885149 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 345320889 ps |
| CPU time | 4.28 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:21 PM UTC 24 |
| Peak memory | 251096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051885149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.3051885149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/166.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_init_fail.4206609720 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 297308348 ps |
| CPU time | 4.85 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:21 PM UTC 24 |
| Peak memory | 251532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206609720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.4206609720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/167.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_parallel_lc_esc.1930263471 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 245975563 ps |
| CPU time | 5.02 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:22 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930263471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.1930263471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/167.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_init_fail.2752543413 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 2311741252 ps |
| CPU time | 5.63 seconds |
| Started | Sep 11 01:06:15 PM UTC 24 |
| Finished | Sep 11 01:06:22 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752543413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.2752543413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/168.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_parallel_lc_esc.117225389 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 254920506 ps |
| CPU time | 11.92 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:39 PM UTC 24 |
| Peak memory | 251116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117225389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.117225389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/168.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_init_fail.3006595548 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 181683777 ps |
| CPU time | 3.95 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:31 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006595548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.3006595548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/169.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_parallel_lc_esc.157076998 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 823041910 ps |
| CPU time | 7.71 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:35 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157076998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.157076998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/169.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_alert_test.558515382 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 815925089 ps |
| CPU time | 4.04 seconds |
| Started | Sep 11 01:00:11 PM UTC 24 |
| Finished | Sep 11 01:00:16 PM UTC 24 |
| Peak memory | 251240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558515382 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.558515382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_check_fail.1993242412 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 643876646 ps |
| CPU time | 5.84 seconds |
| Started | Sep 11 12:59:59 PM UTC 24 |
| Finished | Sep 11 01:00:07 PM UTC 24 |
| Peak memory | 253356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993242412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.1993242412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_errs.2762115410 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 520482817 ps |
| CPU time | 12.58 seconds |
| Started | Sep 11 12:59:57 PM UTC 24 |
| Finished | Sep 11 01:00:11 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762115410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.2762115410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_lock.2753892778 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1541493810 ps |
| CPU time | 13.84 seconds |
| Started | Sep 11 12:59:57 PM UTC 24 |
| Finished | Sep 11 01:00:12 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753892778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.2753892778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_init_fail.485695634 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 297454798 ps |
| CPU time | 4.06 seconds |
| Started | Sep 11 12:59:55 PM UTC 24 |
| Finished | Sep 11 01:00:01 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485695634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.485695634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_macro_errs.245821178 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2443695144 ps |
| CPU time | 29.9 seconds |
| Started | Sep 11 12:59:59 PM UTC 24 |
| Finished | Sep 11 01:00:31 PM UTC 24 |
| Peak memory | 267756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245821178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.245821178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_key_req.3739345543 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 9665732585 ps |
| CPU time | 15.78 seconds |
| Started | Sep 11 01:00:02 PM UTC 24 |
| Finished | Sep 11 01:00:24 PM UTC 24 |
| Peak memory | 253744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739345543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.3739345543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_esc.1906596552 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 487189611 ps |
| CPU time | 15.96 seconds |
| Started | Sep 11 12:59:57 PM UTC 24 |
| Finished | Sep 11 01:00:14 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906596552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.1906596552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_req.3488006846 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1445535117 ps |
| CPU time | 17.63 seconds |
| Started | Sep 11 12:59:55 PM UTC 24 |
| Finished | Sep 11 01:00:15 PM UTC 24 |
| Peak memory | 251532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488006846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.3488006846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_regwen.1156870352 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 232779926 ps |
| CPU time | 4.11 seconds |
| Started | Sep 11 01:00:02 PM UTC 24 |
| Finished | Sep 11 01:00:12 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156870352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.1156870352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_smoke.1390243222 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1259318184 ps |
| CPU time | 11.35 seconds |
| Started | Sep 11 12:59:55 PM UTC 24 |
| Finished | Sep 11 01:00:08 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390243222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.1390243222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all.186993327 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 211920443828 ps |
| CPU time | 338.15 seconds |
| Started | Sep 11 01:00:07 PM UTC 24 |
| Finished | Sep 11 01:05:51 PM UTC 24 |
| Peak memory | 351720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186993327 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.186993327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_test_access.1034194931 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1065992492 ps |
| CPU time | 28 seconds |
| Started | Sep 11 01:00:02 PM UTC 24 |
| Finished | Sep 11 01:00:37 PM UTC 24 |
| Peak memory | 253544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034194931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.1034194931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/17.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_init_fail.3236396361 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 2080487529 ps |
| CPU time | 4.99 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:32 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236396361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.3236396361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/170.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_parallel_lc_esc.3767258998 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 9531835903 ps |
| CPU time | 20.29 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:48 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767258998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.3767258998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/170.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_init_fail.388847732 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 574723601 ps |
| CPU time | 3.75 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:31 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388847732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.388847732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/171.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_parallel_lc_esc.2376875264 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 330901616 ps |
| CPU time | 7.04 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:34 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376875264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.2376875264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/171.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_init_fail.99513993 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 127266722 ps |
| CPU time | 3.43 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:31 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99513993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.99513993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/172.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_parallel_lc_esc.765650979 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 616526542 ps |
| CPU time | 8.35 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:36 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765650979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.765650979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/172.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_init_fail.3005587391 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 509155899 ps |
| CPU time | 4.12 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:32 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005587391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.3005587391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/173.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_parallel_lc_esc.2962643415 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 431414481 ps |
| CPU time | 6 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:34 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962643415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.2962643415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/173.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_init_fail.3526071821 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 164978453 ps |
| CPU time | 3.93 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:32 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526071821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.3526071821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/174.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_parallel_lc_esc.3758576309 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 2125830666 ps |
| CPU time | 28.31 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:56 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758576309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.3758576309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/174.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_init_fail.1215150618 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 185082740 ps |
| CPU time | 3.79 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:31 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215150618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.1215150618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/175.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_parallel_lc_esc.250722350 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 904842254 ps |
| CPU time | 6.06 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:34 PM UTC 24 |
| Peak memory | 251240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250722350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.250722350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/175.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_init_fail.1548089353 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 418681214 ps |
| CPU time | 3.24 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:31 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548089353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.1548089353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/176.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_parallel_lc_esc.2478987489 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 195739776 ps |
| CPU time | 5.87 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:34 PM UTC 24 |
| Peak memory | 250980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478987489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.2478987489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/176.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_init_fail.985744862 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 217921157 ps |
| CPU time | 4.14 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:32 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985744862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.985744862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/177.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_parallel_lc_esc.2225368826 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 527155106 ps |
| CPU time | 3.73 seconds |
| Started | Sep 11 01:06:26 PM UTC 24 |
| Finished | Sep 11 01:06:31 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225368826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.2225368826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/177.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_init_fail.1649765882 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 154178953 ps |
| CPU time | 2.96 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:31 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649765882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.1649765882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/178.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_parallel_lc_esc.2648055340 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 116721367 ps |
| CPU time | 5.86 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:34 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648055340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.2648055340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/178.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_init_fail.586659297 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 2397165164 ps |
| CPU time | 5.8 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:34 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586659297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.586659297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/179.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_parallel_lc_esc.929784980 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 469922140 ps |
| CPU time | 9.85 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:38 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929784980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.929784980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/179.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_alert_test.1263209275 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 146049620 ps |
| CPU time | 2.36 seconds |
| Started | Sep 11 01:00:13 PM UTC 24 |
| Finished | Sep 11 01:00:16 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263209275 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.1263209275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_errs.3461362070 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1020478992 ps |
| CPU time | 15.28 seconds |
| Started | Sep 11 01:00:11 PM UTC 24 |
| Finished | Sep 11 01:00:27 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461362070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.3461362070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_lock.1700333847 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 362814209 ps |
| CPU time | 10.07 seconds |
| Started | Sep 11 01:00:11 PM UTC 24 |
| Finished | Sep 11 01:00:22 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700333847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.1700333847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_macro_errs.3659944277 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1124087316 ps |
| CPU time | 18.85 seconds |
| Started | Sep 11 01:00:11 PM UTC 24 |
| Finished | Sep 11 01:00:31 PM UTC 24 |
| Peak memory | 257556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659944277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.3659944277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_key_req.3180103397 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 1902709803 ps |
| CPU time | 41.43 seconds |
| Started | Sep 11 01:00:11 PM UTC 24 |
| Finished | Sep 11 01:00:54 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180103397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.3180103397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_esc.2500673668 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 442054432 ps |
| CPU time | 9.19 seconds |
| Started | Sep 11 01:00:11 PM UTC 24 |
| Finished | Sep 11 01:00:21 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500673668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.2500673668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_req.3478657883 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 12099195922 ps |
| CPU time | 43.47 seconds |
| Started | Sep 11 01:00:11 PM UTC 24 |
| Finished | Sep 11 01:00:56 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478657883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.3478657883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_regwen.2569760204 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 563127204 ps |
| CPU time | 10.52 seconds |
| Started | Sep 11 01:00:11 PM UTC 24 |
| Finished | Sep 11 01:00:23 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569760204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.2569760204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_smoke.3116968272 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 533932391 ps |
| CPU time | 7.59 seconds |
| Started | Sep 11 01:00:11 PM UTC 24 |
| Finished | Sep 11 01:00:19 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116968272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.3116968272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all.4248943130 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 28283730775 ps |
| CPU time | 186.57 seconds |
| Started | Sep 11 01:00:13 PM UTC 24 |
| Finished | Sep 11 01:03:23 PM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248943130 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.4248943130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.2474147208 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 4147039558 ps |
| CPU time | 79.14 seconds |
| Started | Sep 11 01:00:13 PM UTC 24 |
| Finished | Sep 11 01:01:34 PM UTC 24 |
| Peak memory | 268148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2474147208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.otp_ctrl_stress_all_with_rand_reset.2474147208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_test_access.356752454 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1031535603 ps |
| CPU time | 12.29 seconds |
| Started | Sep 11 01:00:11 PM UTC 24 |
| Finished | Sep 11 01:00:25 PM UTC 24 |
| Peak memory | 251596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356752454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.356752454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/18.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_init_fail.711722584 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 124886702 ps |
| CPU time | 4.6 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:33 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711722584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.711722584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/180.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_parallel_lc_esc.4290332404 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 213052934 ps |
| CPU time | 5.3 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:33 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290332404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.4290332404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_init_fail.2693006408 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 228967084 ps |
| CPU time | 4.91 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:33 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693006408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.2693006408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/181.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_parallel_lc_esc.992430602 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 305657317 ps |
| CPU time | 4.17 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:32 PM UTC 24 |
| Peak memory | 251144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992430602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.992430602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/181.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_init_fail.3370556527 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 1465947802 ps |
| CPU time | 4.88 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:33 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370556527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.3370556527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/182.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_parallel_lc_esc.921523309 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 198640956 ps |
| CPU time | 3.75 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:32 PM UTC 24 |
| Peak memory | 253160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921523309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.921523309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/182.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_init_fail.2495927781 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 537818581 ps |
| CPU time | 4.82 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:33 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495927781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.2495927781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/183.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_parallel_lc_esc.1415637330 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 343211310 ps |
| CPU time | 3.29 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:31 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415637330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.1415637330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/183.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_init_fail.1506553730 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 101969859 ps |
| CPU time | 3.82 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:32 PM UTC 24 |
| Peak memory | 251340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506553730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.1506553730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/184.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_parallel_lc_esc.1158444576 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 219849012 ps |
| CPU time | 2.85 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:31 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158444576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.1158444576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/184.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_init_fail.343631019 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 2277591827 ps |
| CPU time | 4.54 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:33 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343631019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.343631019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/185.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.3597394192 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 528159446 ps |
| CPU time | 6.35 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:35 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597394192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.3597394192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/185.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_init_fail.2537609881 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 188311958 ps |
| CPU time | 3.62 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:32 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537609881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.2537609881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/186.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.1495489288 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 302680816 ps |
| CPU time | 6.73 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:35 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495489288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.1495489288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/186.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_init_fail.1090250536 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 117901317 ps |
| CPU time | 4.66 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:33 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090250536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.1090250536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/187.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.927849426 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 399098021 ps |
| CPU time | 6.47 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:35 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927849426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.927849426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/187.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_init_fail.574215530 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 251933156 ps |
| CPU time | 4.04 seconds |
| Started | Sep 11 01:06:27 PM UTC 24 |
| Finished | Sep 11 01:06:32 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574215530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.574215530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/188.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.1549977960 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 2854994123 ps |
| CPU time | 6.26 seconds |
| Started | Sep 11 01:06:30 PM UTC 24 |
| Finished | Sep 11 01:06:37 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549977960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.1549977960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/188.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_init_fail.2372126810 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 747756673 ps |
| CPU time | 4.29 seconds |
| Started | Sep 11 01:06:30 PM UTC 24 |
| Finished | Sep 11 01:06:35 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372126810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.2372126810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/189.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.946950974 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 1321374654 ps |
| CPU time | 15.18 seconds |
| Started | Sep 11 01:06:30 PM UTC 24 |
| Finished | Sep 11 01:06:46 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946950974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.946950974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/189.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_alert_test.2350296652 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 130223200 ps |
| CPU time | 2.57 seconds |
| Started | Sep 11 01:00:22 PM UTC 24 |
| Finished | Sep 11 01:00:26 PM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350296652 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.2350296652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_check_fail.774605381 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1585882915 ps |
| CPU time | 10.84 seconds |
| Started | Sep 11 01:00:17 PM UTC 24 |
| Finished | Sep 11 01:00:29 PM UTC 24 |
| Peak memory | 253592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774605381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.774605381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_errs.843864216 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 932502455 ps |
| CPU time | 22.66 seconds |
| Started | Sep 11 01:00:16 PM UTC 24 |
| Finished | Sep 11 01:00:40 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843864216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.843864216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_lock.3274920534 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 5156677892 ps |
| CPU time | 27.07 seconds |
| Started | Sep 11 01:00:16 PM UTC 24 |
| Finished | Sep 11 01:00:44 PM UTC 24 |
| Peak memory | 257500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274920534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.3274920534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_init_fail.3700973372 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1477402756 ps |
| CPU time | 5.03 seconds |
| Started | Sep 11 01:00:13 PM UTC 24 |
| Finished | Sep 11 01:00:19 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700973372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.3700973372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_macro_errs.820738793 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2312813533 ps |
| CPU time | 18.26 seconds |
| Started | Sep 11 01:00:17 PM UTC 24 |
| Finished | Sep 11 01:00:37 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820738793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.820738793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_key_req.2488593988 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 302483915 ps |
| CPU time | 13.89 seconds |
| Started | Sep 11 01:00:17 PM UTC 24 |
| Finished | Sep 11 01:00:32 PM UTC 24 |
| Peak memory | 257404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488593988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.2488593988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_esc.897561775 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 840191082 ps |
| CPU time | 9.68 seconds |
| Started | Sep 11 01:00:16 PM UTC 24 |
| Finished | Sep 11 01:00:27 PM UTC 24 |
| Peak memory | 251496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897561775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.897561775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_req.1133190872 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 5998129526 ps |
| CPU time | 15.98 seconds |
| Started | Sep 11 01:00:16 PM UTC 24 |
| Finished | Sep 11 01:00:33 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133190872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.1133190872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_regwen.187358516 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 427003474 ps |
| CPU time | 9.49 seconds |
| Started | Sep 11 01:00:18 PM UTC 24 |
| Finished | Sep 11 01:00:29 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187358516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.187358516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_smoke.2988319247 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 243121593 ps |
| CPU time | 8.63 seconds |
| Started | Sep 11 01:00:13 PM UTC 24 |
| Finished | Sep 11 01:00:23 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988319247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.2988319247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all.4017567429 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 31704671868 ps |
| CPU time | 134.35 seconds |
| Started | Sep 11 01:00:21 PM UTC 24 |
| Finished | Sep 11 01:02:37 PM UTC 24 |
| Peak memory | 290348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017567429 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.4017567429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_test_access.731477297 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 1811818911 ps |
| CPU time | 37 seconds |
| Started | Sep 11 01:00:20 PM UTC 24 |
| Finished | Sep 11 01:00:59 PM UTC 24 |
| Peak memory | 253452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731477297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.731477297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/19.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.1117784359 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 183948630 ps |
| CPU time | 3.6 seconds |
| Started | Sep 11 01:06:30 PM UTC 24 |
| Finished | Sep 11 01:06:34 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117784359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.1117784359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/190.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.1067065317 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 718666020 ps |
| CPU time | 8.08 seconds |
| Started | Sep 11 01:06:30 PM UTC 24 |
| Finished | Sep 11 01:06:39 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067065317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.1067065317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/190.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_init_fail.2897133143 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 140551280 ps |
| CPU time | 3.66 seconds |
| Started | Sep 11 01:06:37 PM UTC 24 |
| Finished | Sep 11 01:06:42 PM UTC 24 |
| Peak memory | 251464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897133143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.2897133143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/191.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.3452906058 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 352149512 ps |
| CPU time | 8.23 seconds |
| Started | Sep 11 01:06:37 PM UTC 24 |
| Finished | Sep 11 01:06:47 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452906058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.3452906058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/191.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_init_fail.2565055398 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 221936739 ps |
| CPU time | 3.69 seconds |
| Started | Sep 11 01:06:37 PM UTC 24 |
| Finished | Sep 11 01:06:42 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565055398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.2565055398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/192.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.2870299375 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 220160487 ps |
| CPU time | 5.24 seconds |
| Started | Sep 11 01:06:37 PM UTC 24 |
| Finished | Sep 11 01:06:44 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870299375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.2870299375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/192.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.142857742 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 2242585498 ps |
| CPU time | 6.31 seconds |
| Started | Sep 11 01:06:37 PM UTC 24 |
| Finished | Sep 11 01:06:45 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142857742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.142857742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/193.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.1041496666 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 277423599 ps |
| CPU time | 6.87 seconds |
| Started | Sep 11 01:06:37 PM UTC 24 |
| Finished | Sep 11 01:06:46 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041496666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.1041496666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/193.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_init_fail.1311212247 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 627378740 ps |
| CPU time | 4.86 seconds |
| Started | Sep 11 01:06:37 PM UTC 24 |
| Finished | Sep 11 01:06:44 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311212247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.1311212247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/194.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.4171177958 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 710937909 ps |
| CPU time | 4.42 seconds |
| Started | Sep 11 01:06:37 PM UTC 24 |
| Finished | Sep 11 01:06:44 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171177958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.4171177958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/194.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.3072574300 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 261899993 ps |
| CPU time | 3.52 seconds |
| Started | Sep 11 01:06:37 PM UTC 24 |
| Finished | Sep 11 01:06:43 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072574300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.3072574300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/195.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.354761155 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 213145521 ps |
| CPU time | 3.35 seconds |
| Started | Sep 11 01:06:37 PM UTC 24 |
| Finished | Sep 11 01:06:42 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354761155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.354761155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/195.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.3284202306 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 2692752973 ps |
| CPU time | 5.21 seconds |
| Started | Sep 11 01:06:37 PM UTC 24 |
| Finished | Sep 11 01:06:44 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284202306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.3284202306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/196.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.2914463724 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 386550331 ps |
| CPU time | 3.85 seconds |
| Started | Sep 11 01:06:37 PM UTC 24 |
| Finished | Sep 11 01:06:43 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914463724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.2914463724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/196.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.2929764154 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 112444803 ps |
| CPU time | 3.32 seconds |
| Started | Sep 11 01:06:37 PM UTC 24 |
| Finished | Sep 11 01:06:43 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929764154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.2929764154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/197.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.716368865 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 361105473 ps |
| CPU time | 6.28 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:46 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716368865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.716368865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/197.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.191381888 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 179919107 ps |
| CPU time | 3.83 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:43 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191381888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.191381888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/198.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.4015649834 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 553266415 ps |
| CPU time | 8.45 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:48 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015649834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.4015649834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/198.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.3999151613 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 368647601 ps |
| CPU time | 5.2 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:45 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999151613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.3999151613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/199.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.2537372124 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 471397599 ps |
| CPU time | 5.13 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:45 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537372124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.2537372124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/199.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_alert_test.2276255502 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 169109086 ps |
| CPU time | 1.74 seconds |
| Started | Sep 11 12:57:39 PM UTC 24 |
| Finished | Sep 11 12:57:42 PM UTC 24 |
| Peak memory | 251084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276255502 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.2276255502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_errs.3494913149 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1284739243 ps |
| CPU time | 34.01 seconds |
| Started | Sep 11 12:57:35 PM UTC 24 |
| Finished | Sep 11 12:58:10 PM UTC 24 |
| Peak memory | 253592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494913149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.3494913149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_macro_errs.817749947 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1369902738 ps |
| CPU time | 42.14 seconds |
| Started | Sep 11 12:57:36 PM UTC 24 |
| Finished | Sep 11 12:58:20 PM UTC 24 |
| Peak memory | 253416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817749947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.817749947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_req.4233425016 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 282592968 ps |
| CPU time | 9.25 seconds |
| Started | Sep 11 12:57:33 PM UTC 24 |
| Finished | Sep 11 12:57:43 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233425016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.4233425016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_smoke.3951836962 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 369315283 ps |
| CPU time | 5.99 seconds |
| Started | Sep 11 12:57:33 PM UTC 24 |
| Finished | Sep 11 12:57:40 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951836962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.3951836962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all.4178920124 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 5080407186 ps |
| CPU time | 39.66 seconds |
| Started | Sep 11 12:57:39 PM UTC 24 |
| Finished | Sep 11 12:58:20 PM UTC 24 |
| Peak memory | 255412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178920124 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.4178920124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.4175773301 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7818413932 ps |
| CPU time | 133.15 seconds |
| Started | Sep 11 12:57:39 PM UTC 24 |
| Finished | Sep 11 12:59:55 PM UTC 24 |
| Peak memory | 268136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4175773301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.otp_ctrl_stress_all_with_rand_reset.4175773301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_test_access.1097578573 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2714130850 ps |
| CPU time | 32.79 seconds |
| Started | Sep 11 12:57:39 PM UTC 24 |
| Finished | Sep 11 12:58:13 PM UTC 24 |
| Peak memory | 251368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097578573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.1097578573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/2.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_alert_test.1862721260 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 127042364 ps |
| CPU time | 3.7 seconds |
| Started | Sep 11 01:00:31 PM UTC 24 |
| Finished | Sep 11 01:00:37 PM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862721260 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.1862721260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/20.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_check_fail.1262499866 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 526234296 ps |
| CPU time | 14.14 seconds |
| Started | Sep 11 01:00:27 PM UTC 24 |
| Finished | Sep 11 01:00:44 PM UTC 24 |
| Peak memory | 251048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262499866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.1262499866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_errs.3818766040 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 5146835706 ps |
| CPU time | 22.31 seconds |
| Started | Sep 11 01:00:27 PM UTC 24 |
| Finished | Sep 11 01:00:52 PM UTC 24 |
| Peak memory | 251020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818766040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.3818766040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/20.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_lock.3240339028 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 2547635456 ps |
| CPU time | 25.34 seconds |
| Started | Sep 11 01:00:24 PM UTC 24 |
| Finished | Sep 11 01:00:52 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240339028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.3240339028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/20.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_init_fail.2053495698 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 209057606 ps |
| CPU time | 4.81 seconds |
| Started | Sep 11 01:00:24 PM UTC 24 |
| Finished | Sep 11 01:00:31 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053495698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.2053495698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/20.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_macro_errs.2195879478 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1157537722 ps |
| CPU time | 11.58 seconds |
| Started | Sep 11 01:00:27 PM UTC 24 |
| Finished | Sep 11 01:00:41 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195879478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.2195879478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/20.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_key_req.426124975 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 1048609110 ps |
| CPU time | 12.51 seconds |
| Started | Sep 11 01:00:27 PM UTC 24 |
| Finished | Sep 11 01:00:42 PM UTC 24 |
| Peak memory | 253348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426124975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.426124975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_esc.2022557352 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 380371199 ps |
| CPU time | 6.91 seconds |
| Started | Sep 11 01:00:24 PM UTC 24 |
| Finished | Sep 11 01:00:34 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022557352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.2022557352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_req.2465222994 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 316266012 ps |
| CPU time | 6.05 seconds |
| Started | Sep 11 01:00:24 PM UTC 24 |
| Finished | Sep 11 01:00:33 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465222994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.2465222994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_regwen.1468149589 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 262047949 ps |
| CPU time | 6.62 seconds |
| Started | Sep 11 01:00:27 PM UTC 24 |
| Finished | Sep 11 01:00:36 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468149589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.1468149589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/20.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_smoke.3169231383 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 87467500 ps |
| CPU time | 3.63 seconds |
| Started | Sep 11 01:00:22 PM UTC 24 |
| Finished | Sep 11 01:00:27 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169231383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.3169231383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/20.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all.1593456628 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 32319304381 ps |
| CPU time | 263.29 seconds |
| Started | Sep 11 01:00:30 PM UTC 24 |
| Finished | Sep 11 01:04:59 PM UTC 24 |
| Peak memory | 284180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593456628 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.1593456628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_test_access.2811660011 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 12356603089 ps |
| CPU time | 31.76 seconds |
| Started | Sep 11 01:00:28 PM UTC 24 |
| Finished | Sep 11 01:01:03 PM UTC 24 |
| Peak memory | 253480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811660011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.2811660011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/20.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.110846968 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 156667070 ps |
| CPU time | 3.44 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:43 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110846968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.110846968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/200.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.1623225652 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 1505702362 ps |
| CPU time | 4.6 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:44 PM UTC 24 |
| Peak memory | 253256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623225652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.1623225652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/201.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.3528702777 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 143789817 ps |
| CPU time | 3.62 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:43 PM UTC 24 |
| Peak memory | 251116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528702777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.3528702777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/202.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.1130133471 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 1949195947 ps |
| CPU time | 3.89 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:43 PM UTC 24 |
| Peak memory | 251108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130133471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.1130133471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/203.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.3545078510 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 205000336 ps |
| CPU time | 3.46 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:43 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545078510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.3545078510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/204.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.2745644111 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 2014995286 ps |
| CPU time | 4.43 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:44 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745644111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.2745644111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/205.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.3448463311 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 409658222 ps |
| CPU time | 3.8 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:43 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448463311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.3448463311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/206.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.3423966658 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 141899627 ps |
| CPU time | 3.99 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:44 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423966658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.3423966658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/207.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.3479879787 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 2566768866 ps |
| CPU time | 5.01 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:45 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479879787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.3479879787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/208.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.1209700820 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 305616426 ps |
| CPU time | 3.86 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:43 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209700820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.1209700820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/209.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_alert_test.1297005437 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 47845421 ps |
| CPU time | 2.35 seconds |
| Started | Sep 11 01:00:38 PM UTC 24 |
| Finished | Sep 11 01:00:42 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297005437 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.1297005437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/21.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_check_fail.2754871712 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 11448957867 ps |
| CPU time | 25.96 seconds |
| Started | Sep 11 01:00:35 PM UTC 24 |
| Finished | Sep 11 01:01:03 PM UTC 24 |
| Peak memory | 253420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754871712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.2754871712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/21.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_errs.3969852087 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 4694562180 ps |
| CPU time | 40.06 seconds |
| Started | Sep 11 01:00:35 PM UTC 24 |
| Finished | Sep 11 01:01:18 PM UTC 24 |
| Peak memory | 259508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969852087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.3969852087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/21.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_lock.2758932232 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 2790134604 ps |
| CPU time | 19.64 seconds |
| Started | Sep 11 01:00:35 PM UTC 24 |
| Finished | Sep 11 01:00:57 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758932232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.2758932232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/21.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_init_fail.844231798 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 209184797 ps |
| CPU time | 3.67 seconds |
| Started | Sep 11 01:00:33 PM UTC 24 |
| Finished | Sep 11 01:00:39 PM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844231798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.844231798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/21.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_macro_errs.1160518504 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 8854814735 ps |
| CPU time | 58.56 seconds |
| Started | Sep 11 01:00:36 PM UTC 24 |
| Finished | Sep 11 01:01:36 PM UTC 24 |
| Peak memory | 269804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160518504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.1160518504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/21.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_key_req.2637262459 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 273531634 ps |
| CPU time | 7.36 seconds |
| Started | Sep 11 01:00:36 PM UTC 24 |
| Finished | Sep 11 01:00:45 PM UTC 24 |
| Peak memory | 253360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637262459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.2637262459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_esc.647710092 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 96679146 ps |
| CPU time | 3.83 seconds |
| Started | Sep 11 01:00:33 PM UTC 24 |
| Finished | Sep 11 01:00:39 PM UTC 24 |
| Peak memory | 251144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647710092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.647710092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_req.724638555 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1011337644 ps |
| CPU time | 13.79 seconds |
| Started | Sep 11 01:00:33 PM UTC 24 |
| Finished | Sep 11 01:00:49 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724638555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.724638555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_regwen.1425715098 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 168849107 ps |
| CPU time | 5.32 seconds |
| Started | Sep 11 01:00:36 PM UTC 24 |
| Finished | Sep 11 01:00:42 PM UTC 24 |
| Peak memory | 257612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425715098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.1425715098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/21.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_smoke.1796819839 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 1123634715 ps |
| CPU time | 6.62 seconds |
| Started | Sep 11 01:00:31 PM UTC 24 |
| Finished | Sep 11 01:00:40 PM UTC 24 |
| Peak memory | 257488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796819839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.1796819839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/21.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all.3002219305 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2478176210 ps |
| CPU time | 42.14 seconds |
| Started | Sep 11 01:00:38 PM UTC 24 |
| Finished | Sep 11 01:01:22 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002219305 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.3002219305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_test_access.247156402 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 4720694462 ps |
| CPU time | 30.88 seconds |
| Started | Sep 11 01:00:38 PM UTC 24 |
| Finished | Sep 11 01:01:11 PM UTC 24 |
| Peak memory | 253416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247156402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.247156402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/21.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.3130228821 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 334179298 ps |
| CPU time | 4.12 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:44 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130228821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.3130228821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/210.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.504837096 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 1795235343 ps |
| CPU time | 5.25 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:45 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504837096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.504837096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/211.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.1281839993 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 286906897 ps |
| CPU time | 4.76 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:44 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281839993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.1281839993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/212.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.978829501 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 188629951 ps |
| CPU time | 3.94 seconds |
| Started | Sep 11 01:06:38 PM UTC 24 |
| Finished | Sep 11 01:06:44 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978829501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.978829501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/213.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.633069044 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 2239867087 ps |
| CPU time | 5.61 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:53 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633069044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.633069044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/214.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.2196358044 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2006979127 ps |
| CPU time | 4.71 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:52 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196358044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.2196358044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/215.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.1953305564 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 162879241 ps |
| CPU time | 3.32 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:51 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953305564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.1953305564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/216.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.3509389843 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 172300624 ps |
| CPU time | 3.8 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:51 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509389843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.3509389843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/217.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.2345436775 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 152491555 ps |
| CPU time | 3.15 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:51 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345436775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.2345436775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/218.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.2145378217 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 2264648590 ps |
| CPU time | 3.56 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:51 PM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145378217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.2145378217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/219.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_alert_test.3288360085 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 251718181 ps |
| CPU time | 2.29 seconds |
| Started | Sep 11 01:00:46 PM UTC 24 |
| Finished | Sep 11 01:00:50 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288360085 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.3288360085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/22.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_check_fail.1200272285 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1617889511 ps |
| CPU time | 31.89 seconds |
| Started | Sep 11 01:00:41 PM UTC 24 |
| Finished | Sep 11 01:01:14 PM UTC 24 |
| Peak memory | 253356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200272285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.1200272285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/22.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_errs.1286779599 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 1837040304 ps |
| CPU time | 45.18 seconds |
| Started | Sep 11 01:00:41 PM UTC 24 |
| Finished | Sep 11 01:01:28 PM UTC 24 |
| Peak memory | 259548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286779599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.1286779599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/22.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_lock.2736269589 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 991056190 ps |
| CPU time | 19.57 seconds |
| Started | Sep 11 01:00:41 PM UTC 24 |
| Finished | Sep 11 01:01:02 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736269589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.2736269589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/22.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_init_fail.1344387850 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2622929626 ps |
| CPU time | 8.7 seconds |
| Started | Sep 11 01:00:38 PM UTC 24 |
| Finished | Sep 11 01:00:48 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344387850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.1344387850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/22.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_macro_errs.2497084023 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 797323219 ps |
| CPU time | 11.08 seconds |
| Started | Sep 11 01:00:41 PM UTC 24 |
| Finished | Sep 11 01:00:53 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497084023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.2497084023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/22.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_key_req.2991321335 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 6415698652 ps |
| CPU time | 23.09 seconds |
| Started | Sep 11 01:00:41 PM UTC 24 |
| Finished | Sep 11 01:01:05 PM UTC 24 |
| Peak memory | 257520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991321335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.2991321335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_esc.3053974863 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 312236336 ps |
| CPU time | 6.28 seconds |
| Started | Sep 11 01:00:41 PM UTC 24 |
| Finished | Sep 11 01:00:48 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053974863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.3053974863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_req.585752595 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 593085176 ps |
| CPU time | 20.24 seconds |
| Started | Sep 11 01:00:41 PM UTC 24 |
| Finished | Sep 11 01:01:02 PM UTC 24 |
| Peak memory | 257224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585752595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.585752595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_regwen.3433992111 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 388472376 ps |
| CPU time | 12.67 seconds |
| Started | Sep 11 01:00:46 PM UTC 24 |
| Finished | Sep 11 01:01:00 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433992111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.3433992111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/22.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_smoke.1706681171 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 468870557 ps |
| CPU time | 5.79 seconds |
| Started | Sep 11 01:00:38 PM UTC 24 |
| Finished | Sep 11 01:00:45 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706681171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.1706681171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/22.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_test_access.1280381774 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 888715273 ps |
| CPU time | 19.53 seconds |
| Started | Sep 11 01:00:46 PM UTC 24 |
| Finished | Sep 11 01:01:07 PM UTC 24 |
| Peak memory | 251368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280381774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.1280381774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/22.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.898868638 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 184548853 ps |
| CPU time | 3.25 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:51 PM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898868638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.898868638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/220.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.388960015 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 1841661759 ps |
| CPU time | 5.42 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:53 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388960015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.388960015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/221.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.3797483595 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 172165310 ps |
| CPU time | 4.18 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:52 PM UTC 24 |
| Peak memory | 251272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797483595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.3797483595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/222.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.3267977191 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 2244751813 ps |
| CPU time | 5.11 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:53 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267977191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.3267977191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/223.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.969516314 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 289304234 ps |
| CPU time | 4.2 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:52 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969516314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.969516314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/224.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.2674186500 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 533917124 ps |
| CPU time | 3.06 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:51 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674186500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.2674186500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/225.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.132828752 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 168752865 ps |
| CPU time | 3.68 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:52 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132828752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.132828752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/226.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.2575254292 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 302302489 ps |
| CPU time | 2.98 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:51 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575254292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.2575254292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/227.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.37574670 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 132964341 ps |
| CPU time | 3.03 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:51 PM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37574670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.37574670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/228.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.950265368 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 508253221 ps |
| CPU time | 3.51 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:51 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950265368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.950265368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/229.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_alert_test.2342580294 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 180553099 ps |
| CPU time | 2.65 seconds |
| Started | Sep 11 01:00:54 PM UTC 24 |
| Finished | Sep 11 01:00:57 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342580294 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.2342580294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/23.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_check_fail.1346615203 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 728704911 ps |
| CPU time | 12.95 seconds |
| Started | Sep 11 01:00:50 PM UTC 24 |
| Finished | Sep 11 01:01:04 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346615203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.1346615203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/23.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_errs.3546193334 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 9067996544 ps |
| CPU time | 17.81 seconds |
| Started | Sep 11 01:00:48 PM UTC 24 |
| Finished | Sep 11 01:01:07 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546193334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.3546193334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/23.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_lock.2743601008 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 197683906 ps |
| CPU time | 5.83 seconds |
| Started | Sep 11 01:00:47 PM UTC 24 |
| Finished | Sep 11 01:00:54 PM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743601008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.2743601008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/23.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_init_fail.2012285275 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 377503574 ps |
| CPU time | 4.96 seconds |
| Started | Sep 11 01:00:47 PM UTC 24 |
| Finished | Sep 11 01:00:53 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012285275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.2012285275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/23.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_macro_errs.2938143372 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 5092524269 ps |
| CPU time | 15.34 seconds |
| Started | Sep 11 01:00:50 PM UTC 24 |
| Finished | Sep 11 01:01:06 PM UTC 24 |
| Peak memory | 255452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938143372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.2938143372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/23.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_key_req.1224687217 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1303011432 ps |
| CPU time | 20.84 seconds |
| Started | Sep 11 01:00:50 PM UTC 24 |
| Finished | Sep 11 01:01:12 PM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224687217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.1224687217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_esc.2325904391 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2135394420 ps |
| CPU time | 10.46 seconds |
| Started | Sep 11 01:00:47 PM UTC 24 |
| Finished | Sep 11 01:00:58 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325904391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.2325904391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_req.2344069168 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 185597715 ps |
| CPU time | 4.86 seconds |
| Started | Sep 11 01:00:47 PM UTC 24 |
| Finished | Sep 11 01:00:53 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344069168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.2344069168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_regwen.2258999138 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 586724099 ps |
| CPU time | 9.26 seconds |
| Started | Sep 11 01:00:51 PM UTC 24 |
| Finished | Sep 11 01:01:01 PM UTC 24 |
| Peak memory | 251272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258999138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.2258999138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/23.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_smoke.3854785217 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 240960516 ps |
| CPU time | 6.18 seconds |
| Started | Sep 11 01:00:47 PM UTC 24 |
| Finished | Sep 11 01:00:54 PM UTC 24 |
| Peak memory | 251396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854785217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.3854785217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/23.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.1750748709 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 9002155273 ps |
| CPU time | 78.34 seconds |
| Started | Sep 11 01:00:54 PM UTC 24 |
| Finished | Sep 11 01:02:14 PM UTC 24 |
| Peak memory | 257676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1750748709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 23.otp_ctrl_stress_all_with_rand_reset.1750748709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_test_access.159238229 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 616943148 ps |
| CPU time | 7.92 seconds |
| Started | Sep 11 01:00:54 PM UTC 24 |
| Finished | Sep 11 01:01:03 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159238229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.159238229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/23.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.1530617632 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 1885353656 ps |
| CPU time | 4.74 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:53 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530617632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.1530617632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/230.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.202702567 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 121568625 ps |
| CPU time | 3.41 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:51 PM UTC 24 |
| Peak memory | 251532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202702567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.202702567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/231.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.752841353 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 97731269 ps |
| CPU time | 3.2 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:51 PM UTC 24 |
| Peak memory | 251576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752841353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.752841353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/232.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.3682753035 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 216691164 ps |
| CPU time | 2.96 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:51 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682753035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.3682753035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/234.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.3026014983 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 341334615 ps |
| CPU time | 3.4 seconds |
| Started | Sep 11 01:06:46 PM UTC 24 |
| Finished | Sep 11 01:06:51 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026014983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.3026014983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/235.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.3918950581 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 144010098 ps |
| CPU time | 3.46 seconds |
| Started | Sep 11 01:06:47 PM UTC 24 |
| Finished | Sep 11 01:06:51 PM UTC 24 |
| Peak memory | 250224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918950581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.3918950581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/236.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.3751699619 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 293890408 ps |
| CPU time | 3.53 seconds |
| Started | Sep 11 01:06:47 PM UTC 24 |
| Finished | Sep 11 01:06:51 PM UTC 24 |
| Peak memory | 250384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751699619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.3751699619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/237.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.3397874142 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 124071978 ps |
| CPU time | 3.22 seconds |
| Started | Sep 11 01:06:47 PM UTC 24 |
| Finished | Sep 11 01:06:51 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397874142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.3397874142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/238.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.3983354409 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1987842189 ps |
| CPU time | 3.97 seconds |
| Started | Sep 11 01:06:47 PM UTC 24 |
| Finished | Sep 11 01:06:52 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983354409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.3983354409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/239.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_alert_test.30022267 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 153851088 ps |
| CPU time | 2.5 seconds |
| Started | Sep 11 01:01:03 PM UTC 24 |
| Finished | Sep 11 01:01:06 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30022267 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.30022267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/24.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_check_fail.3878437797 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 504377403 ps |
| CPU time | 16.95 seconds |
| Started | Sep 11 01:01:01 PM UTC 24 |
| Finished | Sep 11 01:01:19 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878437797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.3878437797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/24.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_errs.3333354037 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1008947607 ps |
| CPU time | 28.46 seconds |
| Started | Sep 11 01:01:00 PM UTC 24 |
| Finished | Sep 11 01:01:30 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333354037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.3333354037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/24.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_lock.3070229407 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1871341977 ps |
| CPU time | 21 seconds |
| Started | Sep 11 01:01:00 PM UTC 24 |
| Finished | Sep 11 01:01:23 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070229407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.3070229407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/24.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_init_fail.1887366795 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 450117157 ps |
| CPU time | 6.29 seconds |
| Started | Sep 11 01:01:00 PM UTC 24 |
| Finished | Sep 11 01:01:08 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887366795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.1887366795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/24.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_macro_errs.1780925745 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 345419133 ps |
| CPU time | 12.41 seconds |
| Started | Sep 11 01:01:01 PM UTC 24 |
| Finished | Sep 11 01:01:14 PM UTC 24 |
| Peak memory | 253584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780925745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.1780925745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/24.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_key_req.4037703220 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 712395376 ps |
| CPU time | 15.05 seconds |
| Started | Sep 11 01:01:01 PM UTC 24 |
| Finished | Sep 11 01:01:17 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037703220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.4037703220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_esc.3978773884 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2772012247 ps |
| CPU time | 7.71 seconds |
| Started | Sep 11 01:01:00 PM UTC 24 |
| Finished | Sep 11 01:01:09 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978773884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.3978773884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_req.2485965787 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 185376130 ps |
| CPU time | 4.99 seconds |
| Started | Sep 11 01:01:00 PM UTC 24 |
| Finished | Sep 11 01:01:06 PM UTC 24 |
| Peak memory | 251132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485965787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.2485965787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_regwen.2161249947 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 116687225 ps |
| CPU time | 6.19 seconds |
| Started | Sep 11 01:01:01 PM UTC 24 |
| Finished | Sep 11 01:01:08 PM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161249947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.2161249947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/24.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_smoke.1926600047 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 201171285 ps |
| CPU time | 6.4 seconds |
| Started | Sep 11 01:01:00 PM UTC 24 |
| Finished | Sep 11 01:01:08 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926600047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.1926600047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/24.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all.3143705588 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 145987413 ps |
| CPU time | 5.36 seconds |
| Started | Sep 11 01:01:03 PM UTC 24 |
| Finished | Sep 11 01:01:09 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143705588 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all.3143705588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_test_access.40178376 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 1866396429 ps |
| CPU time | 31.98 seconds |
| Started | Sep 11 01:01:01 PM UTC 24 |
| Finished | Sep 11 01:01:34 PM UTC 24 |
| Peak memory | 253352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40178376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.40178376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/24.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.3176161040 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 192375076 ps |
| CPU time | 3.77 seconds |
| Started | Sep 11 01:06:47 PM UTC 24 |
| Finished | Sep 11 01:06:52 PM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176161040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.3176161040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/240.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.2237984857 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 2218576394 ps |
| CPU time | 5.88 seconds |
| Started | Sep 11 01:06:47 PM UTC 24 |
| Finished | Sep 11 01:06:54 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237984857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.2237984857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/241.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.3677290351 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 645141275 ps |
| CPU time | 4.16 seconds |
| Started | Sep 11 01:06:47 PM UTC 24 |
| Finished | Sep 11 01:06:52 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677290351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.3677290351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/242.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.512894155 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 192151830 ps |
| CPU time | 4.03 seconds |
| Started | Sep 11 01:06:47 PM UTC 24 |
| Finished | Sep 11 01:06:52 PM UTC 24 |
| Peak memory | 250172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512894155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.512894155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/243.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.292914142 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 194795838 ps |
| CPU time | 3.59 seconds |
| Started | Sep 11 01:06:47 PM UTC 24 |
| Finished | Sep 11 01:06:52 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292914142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.292914142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/244.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.2715311092 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1552038663 ps |
| CPU time | 3.65 seconds |
| Started | Sep 11 01:06:47 PM UTC 24 |
| Finished | Sep 11 01:06:52 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715311092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.2715311092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/245.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.3624072534 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 159121005 ps |
| CPU time | 3.79 seconds |
| Started | Sep 11 01:06:47 PM UTC 24 |
| Finished | Sep 11 01:06:52 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624072534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.3624072534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/246.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.4237174550 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 184386964 ps |
| CPU time | 2.99 seconds |
| Started | Sep 11 01:06:47 PM UTC 24 |
| Finished | Sep 11 01:06:51 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237174550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.4237174550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/247.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.3722039794 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 133721654 ps |
| CPU time | 5.01 seconds |
| Started | Sep 11 01:06:47 PM UTC 24 |
| Finished | Sep 11 01:06:53 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722039794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.3722039794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/248.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_alert_test.3473996827 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 108292782 ps |
| CPU time | 2.71 seconds |
| Started | Sep 11 01:01:14 PM UTC 24 |
| Finished | Sep 11 01:01:17 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473996827 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.3473996827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/25.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_check_fail.4107261721 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 13391941512 ps |
| CPU time | 25.84 seconds |
| Started | Sep 11 01:01:06 PM UTC 24 |
| Finished | Sep 11 01:01:33 PM UTC 24 |
| Peak memory | 257536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107261721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.4107261721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/25.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_errs.1391998961 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 343093491 ps |
| CPU time | 12.32 seconds |
| Started | Sep 11 01:01:06 PM UTC 24 |
| Finished | Sep 11 01:01:20 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391998961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.1391998961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/25.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_lock.1950316341 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 582367928 ps |
| CPU time | 12.52 seconds |
| Started | Sep 11 01:01:06 PM UTC 24 |
| Finished | Sep 11 01:01:20 PM UTC 24 |
| Peak memory | 257044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950316341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.1950316341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/25.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_init_fail.3240580539 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 2135388290 ps |
| CPU time | 5.34 seconds |
| Started | Sep 11 01:01:06 PM UTC 24 |
| Finished | Sep 11 01:01:12 PM UTC 24 |
| Peak memory | 251112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240580539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.3240580539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/25.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_macro_errs.885423522 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 4376892308 ps |
| CPU time | 7.59 seconds |
| Started | Sep 11 01:01:06 PM UTC 24 |
| Finished | Sep 11 01:01:15 PM UTC 24 |
| Peak memory | 253528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885423522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.885423522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/25.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_key_req.1995673161 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 456133303 ps |
| CPU time | 10.45 seconds |
| Started | Sep 11 01:01:13 PM UTC 24 |
| Finished | Sep 11 01:01:25 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995673161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.1995673161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_esc.2986038591 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2257859417 ps |
| CPU time | 8.43 seconds |
| Started | Sep 11 01:01:06 PM UTC 24 |
| Finished | Sep 11 01:01:16 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986038591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.2986038591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_req.1366885634 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1045633578 ps |
| CPU time | 13.08 seconds |
| Started | Sep 11 01:01:06 PM UTC 24 |
| Finished | Sep 11 01:01:20 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366885634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.1366885634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_smoke.2177871377 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1216872942 ps |
| CPU time | 8 seconds |
| Started | Sep 11 01:01:03 PM UTC 24 |
| Finished | Sep 11 01:01:12 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177871377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.2177871377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/25.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all.1632387766 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 6428960369 ps |
| CPU time | 169.32 seconds |
| Started | Sep 11 01:01:14 PM UTC 24 |
| Finished | Sep 11 01:04:06 PM UTC 24 |
| Peak memory | 267756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632387766 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.1632387766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.3576773766 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 3316307338 ps |
| CPU time | 90.75 seconds |
| Started | Sep 11 01:01:14 PM UTC 24 |
| Finished | Sep 11 01:02:46 PM UTC 24 |
| Peak memory | 257640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3576773766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 25.otp_ctrl_stress_all_with_rand_reset.3576773766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_test_access.2263439852 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 794632195 ps |
| CPU time | 15.38 seconds |
| Started | Sep 11 01:01:14 PM UTC 24 |
| Finished | Sep 11 01:01:30 PM UTC 24 |
| Peak memory | 251496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263439852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.2263439852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/25.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.2178233724 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 154145509 ps |
| CPU time | 3.7 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:02 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178233724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.2178233724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/250.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.4135589944 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 285459711 ps |
| CPU time | 3.63 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:02 PM UTC 24 |
| Peak memory | 251068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135589944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.4135589944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/251.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.32608826 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 359653057 ps |
| CPU time | 3.13 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:02 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32608826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.32608826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/252.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.3682333635 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 293735148 ps |
| CPU time | 3.98 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:02 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682333635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.3682333635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/253.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.2695408329 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 393453703 ps |
| CPU time | 3.29 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:01 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695408329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.2695408329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/254.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.3894727891 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 229328207 ps |
| CPU time | 2.94 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:01 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894727891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.3894727891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/255.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.4095916442 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 155879538 ps |
| CPU time | 4.2 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095916442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.4095916442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/256.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.2598876419 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 184668545 ps |
| CPU time | 3.22 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:02 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598876419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.2598876419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/257.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.1131462639 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 220819012 ps |
| CPU time | 3 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:01 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131462639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.1131462639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/258.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.1427861441 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 168356542 ps |
| CPU time | 3.92 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427861441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.1427861441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/259.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_alert_test.2048078983 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 218000506 ps |
| CPU time | 2.71 seconds |
| Started | Sep 11 01:01:17 PM UTC 24 |
| Finished | Sep 11 01:01:21 PM UTC 24 |
| Peak memory | 251240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048078983 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.2048078983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/26.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_errs.2060219553 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 930053936 ps |
| CPU time | 32.25 seconds |
| Started | Sep 11 01:01:14 PM UTC 24 |
| Finished | Sep 11 01:01:48 PM UTC 24 |
| Peak memory | 255348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060219553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.2060219553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/26.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_lock.614138871 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 3666360483 ps |
| CPU time | 37.33 seconds |
| Started | Sep 11 01:01:14 PM UTC 24 |
| Finished | Sep 11 01:01:53 PM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614138871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.614138871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/26.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_init_fail.100066145 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 475534398 ps |
| CPU time | 3.43 seconds |
| Started | Sep 11 01:01:14 PM UTC 24 |
| Finished | Sep 11 01:01:18 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100066145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.100066145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_macro_errs.156547551 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 866414610 ps |
| CPU time | 14.91 seconds |
| Started | Sep 11 01:01:14 PM UTC 24 |
| Finished | Sep 11 01:01:30 PM UTC 24 |
| Peak memory | 257456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156547551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.156547551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/26.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_key_req.2479140131 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 3756967552 ps |
| CPU time | 24.21 seconds |
| Started | Sep 11 01:01:14 PM UTC 24 |
| Finished | Sep 11 01:01:40 PM UTC 24 |
| Peak memory | 257516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479140131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.2479140131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_esc.926595431 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 886175130 ps |
| CPU time | 15.23 seconds |
| Started | Sep 11 01:01:14 PM UTC 24 |
| Finished | Sep 11 01:01:30 PM UTC 24 |
| Peak memory | 250792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926595431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.926595431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_req.3700669777 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 196980185 ps |
| CPU time | 6.62 seconds |
| Started | Sep 11 01:01:14 PM UTC 24 |
| Finished | Sep 11 01:01:22 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700669777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.3700669777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_regwen.3584150855 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 340109004 ps |
| CPU time | 6.43 seconds |
| Started | Sep 11 01:01:14 PM UTC 24 |
| Finished | Sep 11 01:01:22 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584150855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.3584150855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/26.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_smoke.338939868 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 840159108 ps |
| CPU time | 8.58 seconds |
| Started | Sep 11 01:01:14 PM UTC 24 |
| Finished | Sep 11 01:01:23 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338939868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.338939868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/26.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all.436684886 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 7111972047 ps |
| CPU time | 60.76 seconds |
| Started | Sep 11 01:01:17 PM UTC 24 |
| Finished | Sep 11 01:02:19 PM UTC 24 |
| Peak memory | 255408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436684886 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.436684886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_test_access.3079794436 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 946202801 ps |
| CPU time | 28.07 seconds |
| Started | Sep 11 01:01:14 PM UTC 24 |
| Finished | Sep 11 01:01:44 PM UTC 24 |
| Peak memory | 251624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079794436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.3079794436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/26.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.1516331964 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 590240161 ps |
| CPU time | 4.09 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516331964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.1516331964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/260.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.3884499645 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 119291439 ps |
| CPU time | 2.94 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:02 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884499645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.3884499645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/261.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.678092046 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 528482014 ps |
| CPU time | 4.09 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678092046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.678092046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/262.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.3076873390 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 181927330 ps |
| CPU time | 3.36 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:02 PM UTC 24 |
| Peak memory | 251272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076873390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.3076873390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/263.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.2597134333 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 132239672 ps |
| CPU time | 3.58 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:02 PM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597134333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.2597134333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/264.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.2733638500 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 209325734 ps |
| CPU time | 4.14 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733638500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.2733638500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/265.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.753101022 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 676038356 ps |
| CPU time | 5.06 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:04 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753101022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.753101022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/266.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.1945462423 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 117514664 ps |
| CPU time | 3.48 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:02 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945462423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.1945462423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/267.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.2759673101 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 147413846 ps |
| CPU time | 3.69 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759673101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.2759673101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/268.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.623330812 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 382874877 ps |
| CPU time | 3.69 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 253256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623330812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.623330812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/269.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_alert_test.2369391799 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 54418765 ps |
| CPU time | 2.07 seconds |
| Started | Sep 11 01:01:25 PM UTC 24 |
| Finished | Sep 11 01:01:28 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369391799 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.2369391799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/27.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_check_fail.4242955178 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 409153650 ps |
| CPU time | 9.68 seconds |
| Started | Sep 11 01:01:22 PM UTC 24 |
| Finished | Sep 11 01:01:33 PM UTC 24 |
| Peak memory | 257452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242955178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.4242955178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/27.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_errs.1245931186 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 9915252749 ps |
| CPU time | 34.94 seconds |
| Started | Sep 11 01:01:19 PM UTC 24 |
| Finished | Sep 11 01:01:56 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245931186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.1245931186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/27.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_lock.3625385518 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 13575609221 ps |
| CPU time | 26.75 seconds |
| Started | Sep 11 01:01:19 PM UTC 24 |
| Finished | Sep 11 01:01:47 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625385518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.3625385518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/27.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_init_fail.2814342650 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 123845587 ps |
| CPU time | 3.89 seconds |
| Started | Sep 11 01:01:17 PM UTC 24 |
| Finished | Sep 11 01:01:22 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814342650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.2814342650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/27.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_macro_errs.2682109597 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 2383346778 ps |
| CPU time | 21.92 seconds |
| Started | Sep 11 01:01:22 PM UTC 24 |
| Finished | Sep 11 01:01:45 PM UTC 24 |
| Peak memory | 257516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682109597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.2682109597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/27.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_key_req.540851085 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 535616059 ps |
| CPU time | 4.9 seconds |
| Started | Sep 11 01:01:22 PM UTC 24 |
| Finished | Sep 11 01:01:28 PM UTC 24 |
| Peak memory | 251304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540851085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.540851085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_esc.3764470897 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 216372086 ps |
| CPU time | 4.05 seconds |
| Started | Sep 11 01:01:19 PM UTC 24 |
| Finished | Sep 11 01:01:24 PM UTC 24 |
| Peak memory | 251084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764470897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.3764470897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_req.387097652 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 1598490902 ps |
| CPU time | 15.19 seconds |
| Started | Sep 11 01:01:19 PM UTC 24 |
| Finished | Sep 11 01:01:36 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387097652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.387097652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_regwen.4110116354 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 304021412 ps |
| CPU time | 11.22 seconds |
| Started | Sep 11 01:01:22 PM UTC 24 |
| Finished | Sep 11 01:01:35 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110116354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.4110116354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/27.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_smoke.3022482073 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 506995375 ps |
| CPU time | 4.84 seconds |
| Started | Sep 11 01:01:17 PM UTC 24 |
| Finished | Sep 11 01:01:23 PM UTC 24 |
| Peak memory | 251668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022482073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.3022482073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/27.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all.3174224358 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 42057518190 ps |
| CPU time | 117.33 seconds |
| Started | Sep 11 01:01:23 PM UTC 24 |
| Finished | Sep 11 01:03:22 PM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174224358 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.3174224358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_test_access.1961227512 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 461971252 ps |
| CPU time | 16.92 seconds |
| Started | Sep 11 01:01:22 PM UTC 24 |
| Finished | Sep 11 01:01:40 PM UTC 24 |
| Peak memory | 251624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961227512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.1961227512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/27.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.4022961810 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 144453718 ps |
| CPU time | 3.36 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022961810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.4022961810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/270.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.3341833156 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 233632808 ps |
| CPU time | 3.62 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341833156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.3341833156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/271.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.3805048870 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 1797122216 ps |
| CPU time | 3.62 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805048870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.3805048870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/272.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.2411074412 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 2174353170 ps |
| CPU time | 4.91 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:04 PM UTC 24 |
| Peak memory | 251096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411074412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.2411074412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/273.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.1289703695 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 1751684871 ps |
| CPU time | 4.08 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289703695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.1289703695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/274.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.967014562 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 475618458 ps |
| CPU time | 3.28 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967014562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.967014562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/275.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.2348107265 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 239200923 ps |
| CPU time | 3.64 seconds |
| Started | Sep 11 01:06:57 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348107265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.2348107265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/276.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.2698439906 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 155503434 ps |
| CPU time | 3.37 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698439906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.2698439906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/277.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.56352755 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 2241604900 ps |
| CPU time | 5.34 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:05 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56352755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.56352755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/278.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_alert_test.1810235478 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 187654388 ps |
| CPU time | 2.81 seconds |
| Started | Sep 11 01:01:33 PM UTC 24 |
| Finished | Sep 11 01:01:37 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810235478 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.1810235478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/28.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_check_fail.2665207272 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 3644819552 ps |
| CPU time | 13.36 seconds |
| Started | Sep 11 01:01:27 PM UTC 24 |
| Finished | Sep 11 01:01:42 PM UTC 24 |
| Peak memory | 253420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665207272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.2665207272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/28.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_errs.2781007537 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 3795055085 ps |
| CPU time | 15.94 seconds |
| Started | Sep 11 01:01:27 PM UTC 24 |
| Finished | Sep 11 01:01:44 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781007537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.2781007537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/28.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_lock.495128114 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 628200561 ps |
| CPU time | 17.22 seconds |
| Started | Sep 11 01:01:25 PM UTC 24 |
| Finished | Sep 11 01:01:44 PM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495128114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.495128114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/28.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_init_fail.3100133691 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 515806561 ps |
| CPU time | 6.08 seconds |
| Started | Sep 11 01:01:25 PM UTC 24 |
| Finished | Sep 11 01:01:32 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100133691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.3100133691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/28.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_macro_errs.328854713 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 3405387263 ps |
| CPU time | 36.18 seconds |
| Started | Sep 11 01:01:29 PM UTC 24 |
| Finished | Sep 11 01:02:07 PM UTC 24 |
| Peak memory | 268080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328854713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.328854713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/28.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_key_req.2161181130 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 145183396 ps |
| CPU time | 3.51 seconds |
| Started | Sep 11 01:01:30 PM UTC 24 |
| Finished | Sep 11 01:01:34 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161181130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.2161181130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_esc.3131532636 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 2788262538 ps |
| CPU time | 12.38 seconds |
| Started | Sep 11 01:01:25 PM UTC 24 |
| Finished | Sep 11 01:01:39 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131532636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.3131532636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_req.2365691227 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 12398124881 ps |
| CPU time | 26.44 seconds |
| Started | Sep 11 01:01:25 PM UTC 24 |
| Finished | Sep 11 01:01:53 PM UTC 24 |
| Peak memory | 257420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365691227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.2365691227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_regwen.4120497918 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 1059759798 ps |
| CPU time | 9.76 seconds |
| Started | Sep 11 01:01:30 PM UTC 24 |
| Finished | Sep 11 01:01:41 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120497918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.4120497918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/28.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_smoke.1269672194 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 365004521 ps |
| CPU time | 6.35 seconds |
| Started | Sep 11 01:01:25 PM UTC 24 |
| Finished | Sep 11 01:01:33 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269672194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.1269672194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/28.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all.1001830369 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 22571387669 ps |
| CPU time | 202.33 seconds |
| Started | Sep 11 01:01:32 PM UTC 24 |
| Finished | Sep 11 01:04:58 PM UTC 24 |
| Peak memory | 267724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001830369 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.1001830369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_test_access.2350912770 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 2406978119 ps |
| CPU time | 13.78 seconds |
| Started | Sep 11 01:01:30 PM UTC 24 |
| Finished | Sep 11 01:01:45 PM UTC 24 |
| Peak memory | 251368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350912770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.2350912770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/28.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.2509966371 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 282036974 ps |
| CPU time | 3.77 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509966371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.2509966371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/280.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.2635014170 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 124758147 ps |
| CPU time | 3.69 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635014170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.2635014170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/281.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.4202531536 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 1858445877 ps |
| CPU time | 3.61 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202531536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.4202531536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/282.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.3989806622 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 95267460 ps |
| CPU time | 3.92 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989806622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.3989806622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/283.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.1810813145 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 233830155 ps |
| CPU time | 3 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810813145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.1810813145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/284.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.3093041750 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 112505591 ps |
| CPU time | 4.46 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:04 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093041750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.3093041750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/285.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.4193589331 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 401051644 ps |
| CPU time | 3.36 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193589331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.4193589331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/286.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.2696048752 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 427540309 ps |
| CPU time | 3.03 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:02 PM UTC 24 |
| Peak memory | 251400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696048752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.2696048752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/287.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.185554392 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 2155228209 ps |
| CPU time | 4.95 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:04 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185554392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.185554392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/288.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.3448930069 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 203306856 ps |
| CPU time | 3.88 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:03 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448930069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.3448930069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/289.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_alert_test.4098566489 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 584791114 ps |
| CPU time | 3.04 seconds |
| Started | Sep 11 01:01:40 PM UTC 24 |
| Finished | Sep 11 01:01:44 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098566489 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.4098566489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/29.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_check_fail.653968486 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1540299739 ps |
| CPU time | 19.47 seconds |
| Started | Sep 11 01:01:37 PM UTC 24 |
| Finished | Sep 11 01:01:59 PM UTC 24 |
| Peak memory | 253484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653968486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.653968486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_errs.3523895031 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 681222740 ps |
| CPU time | 16 seconds |
| Started | Sep 11 01:01:37 PM UTC 24 |
| Finished | Sep 11 01:01:55 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523895031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.3523895031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/29.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_lock.399418591 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 10101080358 ps |
| CPU time | 19.56 seconds |
| Started | Sep 11 01:01:34 PM UTC 24 |
| Finished | Sep 11 01:01:55 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399418591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.399418591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/29.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_init_fail.2103178946 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 142692141 ps |
| CPU time | 5.25 seconds |
| Started | Sep 11 01:01:34 PM UTC 24 |
| Finished | Sep 11 01:01:41 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103178946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.2103178946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/29.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_macro_errs.3826253012 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 3899538082 ps |
| CPU time | 27.35 seconds |
| Started | Sep 11 01:01:37 PM UTC 24 |
| Finished | Sep 11 01:02:07 PM UTC 24 |
| Peak memory | 255444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826253012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.3826253012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/29.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_key_req.3183351697 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1639303203 ps |
| CPU time | 31.77 seconds |
| Started | Sep 11 01:01:38 PM UTC 24 |
| Finished | Sep 11 01:02:11 PM UTC 24 |
| Peak memory | 257520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183351697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.3183351697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_esc.2009632676 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 613124985 ps |
| CPU time | 17.77 seconds |
| Started | Sep 11 01:01:34 PM UTC 24 |
| Finished | Sep 11 01:01:53 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009632676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.2009632676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_req.588462663 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 415817340 ps |
| CPU time | 14.02 seconds |
| Started | Sep 11 01:01:34 PM UTC 24 |
| Finished | Sep 11 01:01:50 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588462663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.588462663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_smoke.3006084164 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 147976544 ps |
| CPU time | 5.33 seconds |
| Started | Sep 11 01:01:33 PM UTC 24 |
| Finished | Sep 11 01:01:39 PM UTC 24 |
| Peak memory | 251668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006084164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.3006084164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/29.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all.18724264 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 468997429 ps |
| CPU time | 10.97 seconds |
| Started | Sep 11 01:01:40 PM UTC 24 |
| Finished | Sep 11 01:01:52 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18724264 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.18724264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_test_access.2042621932 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1446643121 ps |
| CPU time | 13.76 seconds |
| Started | Sep 11 01:01:38 PM UTC 24 |
| Finished | Sep 11 01:01:53 PM UTC 24 |
| Peak memory | 251496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042621932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.2042621932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/29.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.1347022847 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 215201340 ps |
| CPU time | 4.37 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:04 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347022847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.1347022847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/290.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.2219109171 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 264675531 ps |
| CPU time | 2.76 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:02 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219109171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.2219109171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/291.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.745132362 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 588431136 ps |
| CPU time | 4.52 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:04 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745132362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.745132362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/292.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.4272418094 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 367234400 ps |
| CPU time | 4.54 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:04 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272418094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.4272418094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/293.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.333052313 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 1852731416 ps |
| CPU time | 4.31 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:04 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333052313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.333052313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/294.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.116919226 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 243705364 ps |
| CPU time | 3.9 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:04 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116919226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.116919226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/295.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.3536402878 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 302559167 ps |
| CPU time | 5.28 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:05 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536402878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.3536402878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/296.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.1214790513 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 147629493 ps |
| CPU time | 4.02 seconds |
| Started | Sep 11 01:06:58 PM UTC 24 |
| Finished | Sep 11 01:07:04 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214790513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.1214790513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/297.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.3402621825 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 216741840 ps |
| CPU time | 3.6 seconds |
| Started | Sep 11 01:07:09 PM UTC 24 |
| Finished | Sep 11 01:07:14 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402621825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.3402621825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/298.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.2419669301 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 179442829 ps |
| CPU time | 3.72 seconds |
| Started | Sep 11 01:07:09 PM UTC 24 |
| Finished | Sep 11 01:07:14 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419669301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.2419669301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/299.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_alert_test.2944862504 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 49358911 ps |
| CPU time | 2.7 seconds |
| Started | Sep 11 12:57:50 PM UTC 24 |
| Finished | Sep 11 12:57:54 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944862504 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.2944862504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_check_fail.3627302258 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 304206032 ps |
| CPU time | 6.58 seconds |
| Started | Sep 11 12:57:43 PM UTC 24 |
| Finished | Sep 11 12:57:51 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627302258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.3627302258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_lock.3501631843 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 524992206 ps |
| CPU time | 11.74 seconds |
| Started | Sep 11 12:57:43 PM UTC 24 |
| Finished | Sep 11 12:57:56 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501631843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.3501631843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_init_fail.1652651076 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1619703550 ps |
| CPU time | 8.99 seconds |
| Started | Sep 11 12:57:39 PM UTC 24 |
| Finished | Sep 11 12:57:49 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652651076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.1652651076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_key_req.2764559705 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 589633487 ps |
| CPU time | 13.18 seconds |
| Started | Sep 11 12:57:44 PM UTC 24 |
| Finished | Sep 11 12:57:59 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764559705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.2764559705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_esc.1898787539 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 1101792629 ps |
| CPU time | 19.6 seconds |
| Started | Sep 11 12:57:43 PM UTC 24 |
| Finished | Sep 11 12:58:04 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898787539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.1898787539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_regwen.2182908383 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 349315749 ps |
| CPU time | 6.51 seconds |
| Started | Sep 11 12:57:46 PM UTC 24 |
| Finished | Sep 11 12:57:54 PM UTC 24 |
| Peak memory | 251532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182908383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.2182908383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_sec_cm.3338401878 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 154676177970 ps |
| CPU time | 263.5 seconds |
| Started | Sep 11 12:57:49 PM UTC 24 |
| Finished | Sep 11 01:02:16 PM UTC 24 |
| Peak memory | 290036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338401878 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.3338401878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_smoke.2151699730 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 4556590991 ps |
| CPU time | 14.07 seconds |
| Started | Sep 11 12:57:39 PM UTC 24 |
| Finished | Sep 11 12:57:55 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151699730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.2151699730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.4169397578 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10393703543 ps |
| CPU time | 89.35 seconds |
| Started | Sep 11 12:57:46 PM UTC 24 |
| Finished | Sep 11 12:59:18 PM UTC 24 |
| Peak memory | 274088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4169397578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.otp_ctrl_stress_all_with_rand_reset.4169397578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_test_access.2501701780 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1134353088 ps |
| CPU time | 6.87 seconds |
| Started | Sep 11 12:57:46 PM UTC 24 |
| Finished | Sep 11 12:57:54 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501701780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.2501701780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_alert_test.3092199151 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 147690894 ps |
| CPU time | 3.13 seconds |
| Started | Sep 11 01:01:48 PM UTC 24 |
| Finished | Sep 11 01:01:52 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092199151 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.3092199151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/30.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_check_fail.3387026887 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 1023407460 ps |
| CPU time | 20.62 seconds |
| Started | Sep 11 01:01:44 PM UTC 24 |
| Finished | Sep 11 01:02:06 PM UTC 24 |
| Peak memory | 257452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387026887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.3387026887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/30.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_errs.3920226976 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 228342711 ps |
| CPU time | 10.48 seconds |
| Started | Sep 11 01:01:44 PM UTC 24 |
| Finished | Sep 11 01:01:56 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920226976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.3920226976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/30.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_lock.2915994579 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 286022414 ps |
| CPU time | 7 seconds |
| Started | Sep 11 01:01:44 PM UTC 24 |
| Finished | Sep 11 01:01:53 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915994579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.2915994579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/30.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_init_fail.3527779718 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 225215711 ps |
| CPU time | 4.88 seconds |
| Started | Sep 11 01:01:44 PM UTC 24 |
| Finished | Sep 11 01:01:50 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527779718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.3527779718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/30.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_macro_errs.2432050598 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 222430066 ps |
| CPU time | 5.08 seconds |
| Started | Sep 11 01:01:45 PM UTC 24 |
| Finished | Sep 11 01:01:51 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432050598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.2432050598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/30.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_key_req.407925919 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1151959505 ps |
| CPU time | 11.05 seconds |
| Started | Sep 11 01:01:45 PM UTC 24 |
| Finished | Sep 11 01:01:57 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407925919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.407925919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_esc.3651363351 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 459694505 ps |
| CPU time | 11.57 seconds |
| Started | Sep 11 01:01:44 PM UTC 24 |
| Finished | Sep 11 01:01:57 PM UTC 24 |
| Peak memory | 257324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651363351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.3651363351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_req.213172152 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 268103026 ps |
| CPU time | 4.7 seconds |
| Started | Sep 11 01:01:44 PM UTC 24 |
| Finished | Sep 11 01:01:50 PM UTC 24 |
| Peak memory | 251052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213172152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.213172152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_regwen.1448949111 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 183250400 ps |
| CPU time | 6.03 seconds |
| Started | Sep 11 01:01:45 PM UTC 24 |
| Finished | Sep 11 01:01:52 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448949111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.1448949111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/30.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_smoke.3428080256 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 415056692 ps |
| CPU time | 7.76 seconds |
| Started | Sep 11 01:01:40 PM UTC 24 |
| Finished | Sep 11 01:01:49 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428080256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.3428080256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/30.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all.2673279995 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 66159803954 ps |
| CPU time | 244.7 seconds |
| Started | Sep 11 01:01:48 PM UTC 24 |
| Finished | Sep 11 01:05:56 PM UTC 24 |
| Peak memory | 274028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673279995 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.2673279995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_test_access.808722345 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 906481945 ps |
| CPU time | 7.88 seconds |
| Started | Sep 11 01:01:48 PM UTC 24 |
| Finished | Sep 11 01:01:57 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808722345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.808722345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/30.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_alert_test.1420784238 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 83241862 ps |
| CPU time | 2.13 seconds |
| Started | Sep 11 01:01:55 PM UTC 24 |
| Finished | Sep 11 01:01:59 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420784238 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.1420784238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/31.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_check_fail.3694572416 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 607861320 ps |
| CPU time | 11.33 seconds |
| Started | Sep 11 01:01:50 PM UTC 24 |
| Finished | Sep 11 01:02:03 PM UTC 24 |
| Peak memory | 257516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694572416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.3694572416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/31.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_errs.4226909996 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 1255884035 ps |
| CPU time | 22.22 seconds |
| Started | Sep 11 01:01:50 PM UTC 24 |
| Finished | Sep 11 01:02:14 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226909996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.4226909996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/31.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_lock.2327350125 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1140994564 ps |
| CPU time | 19.76 seconds |
| Started | Sep 11 01:01:50 PM UTC 24 |
| Finished | Sep 11 01:02:11 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327350125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.2327350125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/31.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_init_fail.4162550910 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 323010279 ps |
| CPU time | 5.18 seconds |
| Started | Sep 11 01:01:48 PM UTC 24 |
| Finished | Sep 11 01:01:54 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162550910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.4162550910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/31.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_macro_errs.3016909516 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 3703593779 ps |
| CPU time | 47.34 seconds |
| Started | Sep 11 01:01:51 PM UTC 24 |
| Finished | Sep 11 01:02:39 PM UTC 24 |
| Peak memory | 257580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016909516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.3016909516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/31.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_key_req.2947587431 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 732851291 ps |
| CPU time | 16.97 seconds |
| Started | Sep 11 01:01:51 PM UTC 24 |
| Finished | Sep 11 01:02:09 PM UTC 24 |
| Peak memory | 257432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947587431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.2947587431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_esc.580058532 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 1359864004 ps |
| CPU time | 8.11 seconds |
| Started | Sep 11 01:01:50 PM UTC 24 |
| Finished | Sep 11 01:02:00 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580058532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.580058532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_req.1339446767 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 844030599 ps |
| CPU time | 17.69 seconds |
| Started | Sep 11 01:01:50 PM UTC 24 |
| Finished | Sep 11 01:02:09 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339446767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.1339446767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_regwen.1570410612 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 1060676985 ps |
| CPU time | 11.74 seconds |
| Started | Sep 11 01:01:55 PM UTC 24 |
| Finished | Sep 11 01:02:08 PM UTC 24 |
| Peak memory | 251272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570410612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.1570410612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/31.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_smoke.75934380 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 357539453 ps |
| CPU time | 4.46 seconds |
| Started | Sep 11 01:01:48 PM UTC 24 |
| Finished | Sep 11 01:01:53 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75934380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.75934380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/31.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all.3548276115 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 44937377576 ps |
| CPU time | 251.48 seconds |
| Started | Sep 11 01:01:55 PM UTC 24 |
| Finished | Sep 11 01:06:11 PM UTC 24 |
| Peak memory | 267700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548276115 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.3548276115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_test_access.3485812936 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 869334576 ps |
| CPU time | 10.02 seconds |
| Started | Sep 11 01:01:55 PM UTC 24 |
| Finished | Sep 11 01:02:07 PM UTC 24 |
| Peak memory | 251624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485812936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.3485812936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/31.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_alert_test.68254710 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 57066819 ps |
| CPU time | 2.8 seconds |
| Started | Sep 11 01:01:58 PM UTC 24 |
| Finished | Sep 11 01:02:02 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68254710 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.68254710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/32.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_check_fail.1149174803 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 3429649313 ps |
| CPU time | 33.07 seconds |
| Started | Sep 11 01:01:56 PM UTC 24 |
| Finished | Sep 11 01:02:30 PM UTC 24 |
| Peak memory | 251628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149174803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.1149174803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/32.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_errs.1675863319 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 505497548 ps |
| CPU time | 11.98 seconds |
| Started | Sep 11 01:01:56 PM UTC 24 |
| Finished | Sep 11 01:02:09 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675863319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.1675863319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/32.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_lock.3187396576 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1431970481 ps |
| CPU time | 25.89 seconds |
| Started | Sep 11 01:01:56 PM UTC 24 |
| Finished | Sep 11 01:02:23 PM UTC 24 |
| Peak memory | 253684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187396576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.3187396576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/32.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_init_fail.1921948682 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 151742084 ps |
| CPU time | 4 seconds |
| Started | Sep 11 01:01:56 PM UTC 24 |
| Finished | Sep 11 01:02:01 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921948682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.1921948682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/32.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_macro_errs.3882784321 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 2926266000 ps |
| CPU time | 23.33 seconds |
| Started | Sep 11 01:01:56 PM UTC 24 |
| Finished | Sep 11 01:02:20 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882784321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.3882784321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/32.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_key_req.2529253768 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 1369973009 ps |
| CPU time | 17.4 seconds |
| Started | Sep 11 01:01:56 PM UTC 24 |
| Finished | Sep 11 01:02:15 PM UTC 24 |
| Peak memory | 253336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529253768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.2529253768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_esc.2792110018 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 198051387 ps |
| CPU time | 9.82 seconds |
| Started | Sep 11 01:01:56 PM UTC 24 |
| Finished | Sep 11 01:02:07 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792110018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.2792110018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_req.3672866139 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 1652546304 ps |
| CPU time | 22.6 seconds |
| Started | Sep 11 01:01:56 PM UTC 24 |
| Finished | Sep 11 01:02:20 PM UTC 24 |
| Peak memory | 250900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672866139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.3672866139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_regwen.1481515260 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 350358251 ps |
| CPU time | 10.1 seconds |
| Started | Sep 11 01:01:56 PM UTC 24 |
| Finished | Sep 11 01:02:07 PM UTC 24 |
| Peak memory | 251272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481515260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.1481515260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/32.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_smoke.244405153 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 622821299 ps |
| CPU time | 4.35 seconds |
| Started | Sep 11 01:01:55 PM UTC 24 |
| Finished | Sep 11 01:02:01 PM UTC 24 |
| Peak memory | 251672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244405153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.244405153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/32.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all.3898478285 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 6054704887 ps |
| CPU time | 78.5 seconds |
| Started | Sep 11 01:01:58 PM UTC 24 |
| Finished | Sep 11 01:03:19 PM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898478285 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.3898478285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.101814352 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 72114452028 ps |
| CPU time | 213.25 seconds |
| Started | Sep 11 01:01:58 PM UTC 24 |
| Finished | Sep 11 01:05:35 PM UTC 24 |
| Peak memory | 267916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=101814352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.101814352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_test_access.1397148521 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 2499116962 ps |
| CPU time | 16.54 seconds |
| Started | Sep 11 01:01:58 PM UTC 24 |
| Finished | Sep 11 01:02:16 PM UTC 24 |
| Peak memory | 251600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397148521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.1397148521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/32.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_alert_test.1391153873 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 116454502 ps |
| CPU time | 2.64 seconds |
| Started | Sep 11 01:02:12 PM UTC 24 |
| Finished | Sep 11 01:02:16 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391153873 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.1391153873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/33.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_check_fail.1403270616 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 6679444636 ps |
| CPU time | 15.09 seconds |
| Started | Sep 11 01:02:01 PM UTC 24 |
| Finished | Sep 11 01:02:18 PM UTC 24 |
| Peak memory | 257424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403270616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.1403270616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/33.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_lock.1309678401 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 8311751412 ps |
| CPU time | 16.84 seconds |
| Started | Sep 11 01:02:00 PM UTC 24 |
| Finished | Sep 11 01:02:18 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309678401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.1309678401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/33.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_init_fail.2457355087 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 461811931 ps |
| CPU time | 7.42 seconds |
| Started | Sep 11 01:01:58 PM UTC 24 |
| Finished | Sep 11 01:02:07 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457355087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.2457355087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/33.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_macro_errs.575725725 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1442091211 ps |
| CPU time | 15.15 seconds |
| Started | Sep 11 01:02:02 PM UTC 24 |
| Finished | Sep 11 01:02:19 PM UTC 24 |
| Peak memory | 253360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575725725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.575725725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/33.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_key_req.139558992 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 3690455509 ps |
| CPU time | 11.3 seconds |
| Started | Sep 11 01:02:03 PM UTC 24 |
| Finished | Sep 11 01:02:15 PM UTC 24 |
| Peak memory | 257680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139558992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.139558992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_esc.238230033 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1156035201 ps |
| CPU time | 12.26 seconds |
| Started | Sep 11 01:02:00 PM UTC 24 |
| Finished | Sep 11 01:02:13 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238230033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.238230033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_req.3645393668 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 335525740 ps |
| CPU time | 10.85 seconds |
| Started | Sep 11 01:01:58 PM UTC 24 |
| Finished | Sep 11 01:02:10 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645393668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.3645393668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_regwen.3270791929 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 208622000 ps |
| CPU time | 7.61 seconds |
| Started | Sep 11 01:02:04 PM UTC 24 |
| Finished | Sep 11 01:02:12 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270791929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.3270791929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/33.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_smoke.3487661633 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 561148866 ps |
| CPU time | 7.52 seconds |
| Started | Sep 11 01:01:58 PM UTC 24 |
| Finished | Sep 11 01:02:07 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487661633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.3487661633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/33.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all.931247554 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 12067960604 ps |
| CPU time | 136.12 seconds |
| Started | Sep 11 01:02:12 PM UTC 24 |
| Finished | Sep 11 01:04:31 PM UTC 24 |
| Peak memory | 267784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931247554 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all.931247554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_test_access.3985586518 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 457467639 ps |
| CPU time | 8.66 seconds |
| Started | Sep 11 01:02:12 PM UTC 24 |
| Finished | Sep 11 01:02:22 PM UTC 24 |
| Peak memory | 257448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985586518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.3985586518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/33.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_alert_test.1123006731 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 41407672 ps |
| CPU time | 2.2 seconds |
| Started | Sep 11 01:02:15 PM UTC 24 |
| Finished | Sep 11 01:02:18 PM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123006731 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.1123006731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/34.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_check_fail.1182573641 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 418132257 ps |
| CPU time | 10.45 seconds |
| Started | Sep 11 01:02:12 PM UTC 24 |
| Finished | Sep 11 01:02:24 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182573641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.1182573641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/34.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_errs.479934503 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 220361495 ps |
| CPU time | 12.96 seconds |
| Started | Sep 11 01:02:12 PM UTC 24 |
| Finished | Sep 11 01:02:27 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479934503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.479934503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/34.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_lock.4060177546 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 324942150 ps |
| CPU time | 8.22 seconds |
| Started | Sep 11 01:02:12 PM UTC 24 |
| Finished | Sep 11 01:02:22 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060177546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.4060177546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/34.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_init_fail.4104755522 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1653003010 ps |
| CPU time | 6.25 seconds |
| Started | Sep 11 01:02:12 PM UTC 24 |
| Finished | Sep 11 01:02:20 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104755522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.4104755522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/34.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_macro_errs.1299287870 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 8826299377 ps |
| CPU time | 15.69 seconds |
| Started | Sep 11 01:02:12 PM UTC 24 |
| Finished | Sep 11 01:02:29 PM UTC 24 |
| Peak memory | 257516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299287870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.1299287870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/34.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_key_req.3711583742 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 359223364 ps |
| CPU time | 11.49 seconds |
| Started | Sep 11 01:02:12 PM UTC 24 |
| Finished | Sep 11 01:02:25 PM UTC 24 |
| Peak memory | 253336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711583742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.3711583742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_esc.1397254608 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 392483474 ps |
| CPU time | 12.31 seconds |
| Started | Sep 11 01:02:12 PM UTC 24 |
| Finished | Sep 11 01:02:26 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397254608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.1397254608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_req.3066638482 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 2837618669 ps |
| CPU time | 23.96 seconds |
| Started | Sep 11 01:02:12 PM UTC 24 |
| Finished | Sep 11 01:02:37 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066638482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.3066638482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_regwen.4030240846 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 4180126472 ps |
| CPU time | 11.03 seconds |
| Started | Sep 11 01:02:12 PM UTC 24 |
| Finished | Sep 11 01:02:25 PM UTC 24 |
| Peak memory | 251340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030240846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.4030240846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/34.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_smoke.1516621781 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 283251678 ps |
| CPU time | 6.32 seconds |
| Started | Sep 11 01:02:12 PM UTC 24 |
| Finished | Sep 11 01:02:20 PM UTC 24 |
| Peak memory | 251304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516621781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.1516621781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/34.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all.1354414419 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 10384966578 ps |
| CPU time | 125.02 seconds |
| Started | Sep 11 01:02:15 PM UTC 24 |
| Finished | Sep 11 01:04:23 PM UTC 24 |
| Peak memory | 267852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354414419 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.1354414419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.1333959872 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 4850530816 ps |
| CPU time | 130.29 seconds |
| Started | Sep 11 01:02:15 PM UTC 24 |
| Finished | Sep 11 01:04:28 PM UTC 24 |
| Peak memory | 267500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1333959872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 34.otp_ctrl_stress_all_with_rand_reset.1333959872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_test_access.1988150710 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 13820542222 ps |
| CPU time | 45.03 seconds |
| Started | Sep 11 01:02:15 PM UTC 24 |
| Finished | Sep 11 01:03:01 PM UTC 24 |
| Peak memory | 257176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988150710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.1988150710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/34.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_alert_test.1394828298 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 90531016 ps |
| CPU time | 3.01 seconds |
| Started | Sep 11 01:02:25 PM UTC 24 |
| Finished | Sep 11 01:02:29 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394828298 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.1394828298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/35.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_check_fail.1380460076 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 3063784904 ps |
| CPU time | 32.09 seconds |
| Started | Sep 11 01:02:18 PM UTC 24 |
| Finished | Sep 11 01:02:51 PM UTC 24 |
| Peak memory | 257516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380460076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.1380460076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/35.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_errs.4054338564 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 2932933281 ps |
| CPU time | 10.25 seconds |
| Started | Sep 11 01:02:18 PM UTC 24 |
| Finished | Sep 11 01:02:29 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054338564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.4054338564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/35.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_lock.3954865991 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 2285282313 ps |
| CPU time | 6.87 seconds |
| Started | Sep 11 01:02:17 PM UTC 24 |
| Finished | Sep 11 01:02:25 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954865991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.3954865991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/35.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_init_fail.867485953 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 358294443 ps |
| CPU time | 4.1 seconds |
| Started | Sep 11 01:02:15 PM UTC 24 |
| Finished | Sep 11 01:02:20 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867485953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.867485953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/35.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_macro_errs.3313102205 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 701371273 ps |
| CPU time | 11.33 seconds |
| Started | Sep 11 01:02:20 PM UTC 24 |
| Finished | Sep 11 01:02:32 PM UTC 24 |
| Peak memory | 253352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313102205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.3313102205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/35.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_key_req.260487912 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 270327567 ps |
| CPU time | 9.91 seconds |
| Started | Sep 11 01:02:20 PM UTC 24 |
| Finished | Sep 11 01:02:31 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260487912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.260487912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_esc.1788500513 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 342109497 ps |
| CPU time | 4.85 seconds |
| Started | Sep 11 01:02:17 PM UTC 24 |
| Finished | Sep 11 01:02:23 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788500513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.1788500513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_req.1683056364 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 1567886784 ps |
| CPU time | 20.75 seconds |
| Started | Sep 11 01:02:17 PM UTC 24 |
| Finished | Sep 11 01:02:39 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683056364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.1683056364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_regwen.3794736018 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 401446035 ps |
| CPU time | 5.62 seconds |
| Started | Sep 11 01:02:20 PM UTC 24 |
| Finished | Sep 11 01:02:26 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794736018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.3794736018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/35.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_smoke.1309745349 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 6301211585 ps |
| CPU time | 11.74 seconds |
| Started | Sep 11 01:02:15 PM UTC 24 |
| Finished | Sep 11 01:02:28 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309745349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.1309745349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/35.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all.2171971111 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 32563602862 ps |
| CPU time | 102.58 seconds |
| Started | Sep 11 01:02:25 PM UTC 24 |
| Finished | Sep 11 01:04:09 PM UTC 24 |
| Peak memory | 267756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171971111 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.2171971111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.1995698992 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 11008823233 ps |
| CPU time | 95.21 seconds |
| Started | Sep 11 01:02:20 PM UTC 24 |
| Finished | Sep 11 01:03:57 PM UTC 24 |
| Peak memory | 272040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1995698992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.otp_ctrl_stress_all_with_rand_reset.1995698992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_test_access.1560967484 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 619729565 ps |
| CPU time | 16.46 seconds |
| Started | Sep 11 01:02:20 PM UTC 24 |
| Finished | Sep 11 01:02:37 PM UTC 24 |
| Peak memory | 251620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560967484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.1560967484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/35.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_alert_test.3850354660 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 87009569 ps |
| CPU time | 2.01 seconds |
| Started | Sep 11 01:02:28 PM UTC 24 |
| Finished | Sep 11 01:02:31 PM UTC 24 |
| Peak memory | 250944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850354660 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.3850354660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/36.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_check_fail.278626438 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 416820908 ps |
| CPU time | 11.25 seconds |
| Started | Sep 11 01:02:25 PM UTC 24 |
| Finished | Sep 11 01:02:37 PM UTC 24 |
| Peak memory | 257520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278626438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.278626438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/36.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_errs.3992518356 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 1386002562 ps |
| CPU time | 19.04 seconds |
| Started | Sep 11 01:02:25 PM UTC 24 |
| Finished | Sep 11 01:02:45 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992518356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.3992518356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/36.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_lock.2069115904 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 305134443 ps |
| CPU time | 7.69 seconds |
| Started | Sep 11 01:02:25 PM UTC 24 |
| Finished | Sep 11 01:02:34 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069115904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.2069115904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/36.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_init_fail.2993456148 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 155036395 ps |
| CPU time | 5.82 seconds |
| Started | Sep 11 01:02:25 PM UTC 24 |
| Finished | Sep 11 01:02:32 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993456148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.2993456148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/36.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_macro_errs.3261454274 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 2641281465 ps |
| CPU time | 29.58 seconds |
| Started | Sep 11 01:02:25 PM UTC 24 |
| Finished | Sep 11 01:02:56 PM UTC 24 |
| Peak memory | 267680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261454274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.3261454274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/36.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_key_req.3503543385 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 732151310 ps |
| CPU time | 7.61 seconds |
| Started | Sep 11 01:02:27 PM UTC 24 |
| Finished | Sep 11 01:02:36 PM UTC 24 |
| Peak memory | 257776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503543385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.3503543385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_esc.3155790095 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 2138493558 ps |
| CPU time | 23.29 seconds |
| Started | Sep 11 01:02:25 PM UTC 24 |
| Finished | Sep 11 01:02:49 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155790095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.3155790095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_req.934250361 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 570511258 ps |
| CPU time | 19.16 seconds |
| Started | Sep 11 01:02:25 PM UTC 24 |
| Finished | Sep 11 01:02:45 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934250361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.934250361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_regwen.356947157 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 379339199 ps |
| CPU time | 10.01 seconds |
| Started | Sep 11 01:02:27 PM UTC 24 |
| Finished | Sep 11 01:02:39 PM UTC 24 |
| Peak memory | 251144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356947157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.356947157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/36.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_smoke.1906658950 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 552563154 ps |
| CPU time | 5.13 seconds |
| Started | Sep 11 01:02:25 PM UTC 24 |
| Finished | Sep 11 01:02:31 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906658950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.1906658950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/36.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all.1705974738 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 12995778632 ps |
| CPU time | 109.07 seconds |
| Started | Sep 11 01:02:28 PM UTC 24 |
| Finished | Sep 11 01:04:19 PM UTC 24 |
| Peak memory | 257716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705974738 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.1705974738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.1279856267 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 7902369498 ps |
| CPU time | 81.7 seconds |
| Started | Sep 11 01:02:28 PM UTC 24 |
| Finished | Sep 11 01:03:51 PM UTC 24 |
| Peak memory | 257808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1279856267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.otp_ctrl_stress_all_with_rand_reset.1279856267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_test_access.3086433842 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 4545135273 ps |
| CPU time | 24.94 seconds |
| Started | Sep 11 01:02:28 PM UTC 24 |
| Finished | Sep 11 01:02:54 PM UTC 24 |
| Peak memory | 257508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086433842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.3086433842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/36.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_alert_test.1435863097 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 715614128 ps |
| CPU time | 3.23 seconds |
| Started | Sep 11 01:02:34 PM UTC 24 |
| Finished | Sep 11 01:02:38 PM UTC 24 |
| Peak memory | 251240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435863097 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.1435863097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/37.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_check_fail.2309181902 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 339946360 ps |
| CPU time | 6.88 seconds |
| Started | Sep 11 01:02:34 PM UTC 24 |
| Finished | Sep 11 01:02:42 PM UTC 24 |
| Peak memory | 257300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309181902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.2309181902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/37.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_errs.3273188524 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 608335305 ps |
| CPU time | 16.68 seconds |
| Started | Sep 11 01:02:31 PM UTC 24 |
| Finished | Sep 11 01:02:48 PM UTC 24 |
| Peak memory | 253340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273188524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.3273188524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/37.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_lock.428409311 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 10693892989 ps |
| CPU time | 24.16 seconds |
| Started | Sep 11 01:02:30 PM UTC 24 |
| Finished | Sep 11 01:02:56 PM UTC 24 |
| Peak memory | 257532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428409311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.428409311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/37.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_init_fail.252624174 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 195835332 ps |
| CPU time | 6.83 seconds |
| Started | Sep 11 01:02:30 PM UTC 24 |
| Finished | Sep 11 01:02:38 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252624174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.252624174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/37.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_macro_errs.1521984662 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 1250572424 ps |
| CPU time | 14.62 seconds |
| Started | Sep 11 01:02:34 PM UTC 24 |
| Finished | Sep 11 01:02:49 PM UTC 24 |
| Peak memory | 253616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521984662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.1521984662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/37.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_key_req.516588503 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 2960668826 ps |
| CPU time | 7.99 seconds |
| Started | Sep 11 01:02:34 PM UTC 24 |
| Finished | Sep 11 01:02:43 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516588503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.516588503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_esc.3932354506 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 768488847 ps |
| CPU time | 11.56 seconds |
| Started | Sep 11 01:02:30 PM UTC 24 |
| Finished | Sep 11 01:02:43 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932354506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.3932354506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_req.2277274659 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 4238765412 ps |
| CPU time | 11.87 seconds |
| Started | Sep 11 01:02:30 PM UTC 24 |
| Finished | Sep 11 01:02:43 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277274659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.2277274659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_regwen.643482975 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 751276123 ps |
| CPU time | 7.72 seconds |
| Started | Sep 11 01:02:34 PM UTC 24 |
| Finished | Sep 11 01:02:43 PM UTC 24 |
| Peak memory | 251272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643482975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.643482975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/37.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_smoke.3535565331 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 319904079 ps |
| CPU time | 7.71 seconds |
| Started | Sep 11 01:02:28 PM UTC 24 |
| Finished | Sep 11 01:02:37 PM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535565331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.3535565331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/37.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.1026608676 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 37231172073 ps |
| CPU time | 353.08 seconds |
| Started | Sep 11 01:02:34 PM UTC 24 |
| Finished | Sep 11 01:08:32 PM UTC 24 |
| Peak memory | 317032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026608676 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.1026608676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.1279400084 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 8922805796 ps |
| CPU time | 106.92 seconds |
| Started | Sep 11 01:02:34 PM UTC 24 |
| Finished | Sep 11 01:04:23 PM UTC 24 |
| Peak memory | 274052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1279400084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 37.otp_ctrl_stress_all_with_rand_reset.1279400084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_test_access.838763879 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 15755773554 ps |
| CPU time | 36.11 seconds |
| Started | Sep 11 01:02:34 PM UTC 24 |
| Finished | Sep 11 01:03:11 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838763879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.838763879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/37.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_alert_test.2716998735 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 199415385 ps |
| CPU time | 2.69 seconds |
| Started | Sep 11 01:02:43 PM UTC 24 |
| Finished | Sep 11 01:02:47 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716998735 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.2716998735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/38.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_check_fail.2664417064 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 1452041121 ps |
| CPU time | 32.68 seconds |
| Started | Sep 11 01:02:40 PM UTC 24 |
| Finished | Sep 11 01:03:14 PM UTC 24 |
| Peak memory | 253612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664417064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.2664417064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/38.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_errs.1268623518 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 4358837896 ps |
| CPU time | 38.37 seconds |
| Started | Sep 11 01:02:40 PM UTC 24 |
| Finished | Sep 11 01:03:20 PM UTC 24 |
| Peak memory | 257260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268623518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.1268623518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/38.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_lock.2738629659 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 1420119281 ps |
| CPU time | 15.48 seconds |
| Started | Sep 11 01:02:40 PM UTC 24 |
| Finished | Sep 11 01:02:57 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738629659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.2738629659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/38.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_init_fail.3668399046 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 118561727 ps |
| CPU time | 4.51 seconds |
| Started | Sep 11 01:02:37 PM UTC 24 |
| Finished | Sep 11 01:02:42 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668399046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.3668399046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/38.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_macro_errs.1437945217 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 1102319321 ps |
| CPU time | 9.63 seconds |
| Started | Sep 11 01:02:40 PM UTC 24 |
| Finished | Sep 11 01:02:51 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437945217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.1437945217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/38.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_key_req.1526903796 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 482854703 ps |
| CPU time | 7.06 seconds |
| Started | Sep 11 01:02:40 PM UTC 24 |
| Finished | Sep 11 01:02:48 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526903796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.1526903796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_esc.2577928996 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 192936491 ps |
| CPU time | 9.38 seconds |
| Started | Sep 11 01:02:40 PM UTC 24 |
| Finished | Sep 11 01:02:50 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577928996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.2577928996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_req.2579367167 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 1081797678 ps |
| CPU time | 21.6 seconds |
| Started | Sep 11 01:02:37 PM UTC 24 |
| Finished | Sep 11 01:03:00 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579367167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.2579367167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_regwen.1378069103 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 370588796 ps |
| CPU time | 3.74 seconds |
| Started | Sep 11 01:02:40 PM UTC 24 |
| Finished | Sep 11 01:02:45 PM UTC 24 |
| Peak memory | 257504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378069103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.1378069103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/38.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_smoke.3908465186 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 371414890 ps |
| CPU time | 8.66 seconds |
| Started | Sep 11 01:02:35 PM UTC 24 |
| Finished | Sep 11 01:02:45 PM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908465186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.3908465186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/38.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all.1670545707 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 77403157741 ps |
| CPU time | 205.81 seconds |
| Started | Sep 11 01:02:43 PM UTC 24 |
| Finished | Sep 11 01:06:12 PM UTC 24 |
| Peak memory | 267676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670545707 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.1670545707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.3085988045 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 38385450338 ps |
| CPU time | 89.41 seconds |
| Started | Sep 11 01:02:43 PM UTC 24 |
| Finished | Sep 11 01:04:15 PM UTC 24 |
| Peak memory | 267796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3085988045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 38.otp_ctrl_stress_all_with_rand_reset.3085988045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_test_access.3343426827 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 1042540134 ps |
| CPU time | 19.17 seconds |
| Started | Sep 11 01:02:40 PM UTC 24 |
| Finished | Sep 11 01:03:01 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343426827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.3343426827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/38.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_alert_test.2848600292 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 125272908 ps |
| CPU time | 2.66 seconds |
| Started | Sep 11 01:02:53 PM UTC 24 |
| Finished | Sep 11 01:02:57 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848600292 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.2848600292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/39.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_check_fail.1610449857 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1025867063 ps |
| CPU time | 13.22 seconds |
| Started | Sep 11 01:02:48 PM UTC 24 |
| Finished | Sep 11 01:03:02 PM UTC 24 |
| Peak memory | 257684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610449857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.1610449857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_errs.1340270239 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 1015368175 ps |
| CPU time | 33.89 seconds |
| Started | Sep 11 01:02:48 PM UTC 24 |
| Finished | Sep 11 01:03:23 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340270239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.1340270239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/39.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_lock.1685076495 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 835267146 ps |
| CPU time | 15.88 seconds |
| Started | Sep 11 01:02:45 PM UTC 24 |
| Finished | Sep 11 01:03:03 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685076495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.1685076495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/39.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_init_fail.3583216378 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2168357317 ps |
| CPU time | 7.45 seconds |
| Started | Sep 11 01:02:44 PM UTC 24 |
| Finished | Sep 11 01:02:52 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583216378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.3583216378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/39.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_macro_errs.3919782161 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 648843874 ps |
| CPU time | 15.15 seconds |
| Started | Sep 11 01:02:48 PM UTC 24 |
| Finished | Sep 11 01:03:04 PM UTC 24 |
| Peak memory | 255356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919782161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.3919782161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/39.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_key_req.835432826 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 570279266 ps |
| CPU time | 14.29 seconds |
| Started | Sep 11 01:02:48 PM UTC 24 |
| Finished | Sep 11 01:03:03 PM UTC 24 |
| Peak memory | 257424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835432826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.835432826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_esc.2301729491 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 347493245 ps |
| CPU time | 6.7 seconds |
| Started | Sep 11 01:02:45 PM UTC 24 |
| Finished | Sep 11 01:02:53 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301729491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.2301729491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_req.2206350706 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 489194452 ps |
| CPU time | 13.87 seconds |
| Started | Sep 11 01:02:45 PM UTC 24 |
| Finished | Sep 11 01:03:00 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206350706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.2206350706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_regwen.4013743725 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 230834545 ps |
| CPU time | 4.63 seconds |
| Started | Sep 11 01:02:48 PM UTC 24 |
| Finished | Sep 11 01:02:54 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013743725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.4013743725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/39.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_smoke.1835290933 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 284274329 ps |
| CPU time | 7.46 seconds |
| Started | Sep 11 01:02:44 PM UTC 24 |
| Finished | Sep 11 01:02:52 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835290933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.1835290933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/39.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all.3270210348 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 1077461004 ps |
| CPU time | 25.21 seconds |
| Started | Sep 11 01:02:53 PM UTC 24 |
| Finished | Sep 11 01:03:19 PM UTC 24 |
| Peak memory | 257484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270210348 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.3270210348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_test_access.782319739 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 2308500490 ps |
| CPU time | 25.57 seconds |
| Started | Sep 11 01:02:53 PM UTC 24 |
| Finished | Sep 11 01:03:20 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782319739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.782319739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/39.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_alert_test.3127867537 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 792217653 ps |
| CPU time | 3.16 seconds |
| Started | Sep 11 12:58:00 PM UTC 24 |
| Finished | Sep 11 12:58:04 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127867537 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.3127867537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_background_chks.397554483 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 200622244 ps |
| CPU time | 7.24 seconds |
| Started | Sep 11 12:57:52 PM UTC 24 |
| Finished | Sep 11 12:58:00 PM UTC 24 |
| Peak memory | 251560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397554483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.397554483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_check_fail.1120322166 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 567065063 ps |
| CPU time | 15.18 seconds |
| Started | Sep 11 12:57:56 PM UTC 24 |
| Finished | Sep 11 12:58:13 PM UTC 24 |
| Peak memory | 257520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120322166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.1120322166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_errs.2789491869 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 1042908963 ps |
| CPU time | 22.32 seconds |
| Started | Sep 11 12:57:56 PM UTC 24 |
| Finished | Sep 11 12:58:20 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789491869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.2789491869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_lock.2816520636 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 5586552511 ps |
| CPU time | 43.78 seconds |
| Started | Sep 11 12:57:56 PM UTC 24 |
| Finished | Sep 11 12:58:41 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816520636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.2816520636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_key_req.104407961 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1542607654 ps |
| CPU time | 18.74 seconds |
| Started | Sep 11 12:57:58 PM UTC 24 |
| Finished | Sep 11 12:58:18 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104407961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.104407961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_esc.2160895097 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 176370792 ps |
| CPU time | 4.27 seconds |
| Started | Sep 11 12:57:56 PM UTC 24 |
| Finished | Sep 11 12:58:01 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160895097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.2160895097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_req.2268035509 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 356581886 ps |
| CPU time | 7.62 seconds |
| Started | Sep 11 12:57:56 PM UTC 24 |
| Finished | Sep 11 12:58:05 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268035509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.2268035509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_regwen.4031185524 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 567132976 ps |
| CPU time | 6.11 seconds |
| Started | Sep 11 12:57:58 PM UTC 24 |
| Finished | Sep 11 12:58:05 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031185524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.4031185524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_sec_cm.1699662899 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 19012536125 ps |
| CPU time | 215.15 seconds |
| Started | Sep 11 12:58:00 PM UTC 24 |
| Finished | Sep 11 01:01:39 PM UTC 24 |
| Peak memory | 287860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699662899 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.1699662899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_smoke.172963754 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 112364572 ps |
| CPU time | 4.89 seconds |
| Started | Sep 11 12:57:50 PM UTC 24 |
| Finished | Sep 11 12:57:56 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172963754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.172963754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_test_access.2767351973 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1441851304 ps |
| CPU time | 36.25 seconds |
| Started | Sep 11 12:57:58 PM UTC 24 |
| Finished | Sep 11 12:58:36 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767351973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.2767351973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/4.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_alert_test.2649143523 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 52889979 ps |
| CPU time | 2.21 seconds |
| Started | Sep 11 01:03:00 PM UTC 24 |
| Finished | Sep 11 01:03:03 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649143523 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.2649143523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/40.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_check_fail.3033436221 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 610382317 ps |
| CPU time | 7.68 seconds |
| Started | Sep 11 01:02:55 PM UTC 24 |
| Finished | Sep 11 01:03:04 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033436221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.3033436221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/40.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_errs.730019182 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 2056319977 ps |
| CPU time | 29.57 seconds |
| Started | Sep 11 01:02:55 PM UTC 24 |
| Finished | Sep 11 01:03:26 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730019182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.730019182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/40.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_lock.3866329597 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 2000783973 ps |
| CPU time | 17.03 seconds |
| Started | Sep 11 01:02:53 PM UTC 24 |
| Finished | Sep 11 01:03:12 PM UTC 24 |
| Peak memory | 253340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866329597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.3866329597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/40.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_init_fail.3602198345 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 1704581188 ps |
| CPU time | 7.06 seconds |
| Started | Sep 11 01:02:53 PM UTC 24 |
| Finished | Sep 11 01:03:01 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602198345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.3602198345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/40.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_macro_errs.2311571317 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 3232354186 ps |
| CPU time | 28.57 seconds |
| Started | Sep 11 01:02:55 PM UTC 24 |
| Finished | Sep 11 01:03:25 PM UTC 24 |
| Peak memory | 253396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311571317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.2311571317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/40.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_key_req.172933018 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 10028079019 ps |
| CPU time | 21.9 seconds |
| Started | Sep 11 01:02:56 PM UTC 24 |
| Finished | Sep 11 01:03:19 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172933018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.172933018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_esc.1329304123 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 125679189 ps |
| CPU time | 5.15 seconds |
| Started | Sep 11 01:02:53 PM UTC 24 |
| Finished | Sep 11 01:02:59 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329304123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.1329304123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_req.3953077018 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 293605797 ps |
| CPU time | 4.06 seconds |
| Started | Sep 11 01:02:53 PM UTC 24 |
| Finished | Sep 11 01:02:58 PM UTC 24 |
| Peak memory | 257500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953077018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.3953077018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_regwen.3631469320 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 290953281 ps |
| CPU time | 8.35 seconds |
| Started | Sep 11 01:02:58 PM UTC 24 |
| Finished | Sep 11 01:03:07 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631469320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.3631469320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/40.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_smoke.3876878172 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 377282689 ps |
| CPU time | 10.12 seconds |
| Started | Sep 11 01:02:53 PM UTC 24 |
| Finished | Sep 11 01:03:04 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876878172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.3876878172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/40.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all.2362282050 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 5124770071 ps |
| CPU time | 41.31 seconds |
| Started | Sep 11 01:02:58 PM UTC 24 |
| Finished | Sep 11 01:03:41 PM UTC 24 |
| Peak memory | 255568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362282050 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.2362282050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.484743403 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 4719877731 ps |
| CPU time | 42.31 seconds |
| Started | Sep 11 01:02:58 PM UTC 24 |
| Finished | Sep 11 01:03:42 PM UTC 24 |
| Peak memory | 257740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=484743403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.484743403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_test_access.2744243890 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 556017345 ps |
| CPU time | 6.17 seconds |
| Started | Sep 11 01:02:58 PM UTC 24 |
| Finished | Sep 11 01:03:05 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744243890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.2744243890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/40.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_alert_test.1869757704 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 151127281 ps |
| CPU time | 2.53 seconds |
| Started | Sep 11 01:03:08 PM UTC 24 |
| Finished | Sep 11 01:03:12 PM UTC 24 |
| Peak memory | 251404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869757704 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.1869757704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/41.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_check_fail.2797280591 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 693359311 ps |
| CPU time | 7.4 seconds |
| Started | Sep 11 01:03:04 PM UTC 24 |
| Finished | Sep 11 01:03:13 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797280591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.2797280591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_errs.1140897761 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 389012635 ps |
| CPU time | 12.13 seconds |
| Started | Sep 11 01:03:02 PM UTC 24 |
| Finished | Sep 11 01:03:16 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140897761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.1140897761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/41.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_lock.939410639 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 881123351 ps |
| CPU time | 31.96 seconds |
| Started | Sep 11 01:03:02 PM UTC 24 |
| Finished | Sep 11 01:03:36 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939410639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.939410639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/41.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_init_fail.949949143 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 249785769 ps |
| CPU time | 3.43 seconds |
| Started | Sep 11 01:03:02 PM UTC 24 |
| Finished | Sep 11 01:03:07 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949949143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.949949143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/41.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_macro_errs.820802356 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 514553481 ps |
| CPU time | 10.35 seconds |
| Started | Sep 11 01:03:04 PM UTC 24 |
| Finished | Sep 11 01:03:16 PM UTC 24 |
| Peak memory | 257776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820802356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.820802356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/41.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_key_req.566570046 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 679633303 ps |
| CPU time | 8.28 seconds |
| Started | Sep 11 01:03:04 PM UTC 24 |
| Finished | Sep 11 01:03:14 PM UTC 24 |
| Peak memory | 253460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566570046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.566570046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_esc.42756791 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 2716682691 ps |
| CPU time | 20.43 seconds |
| Started | Sep 11 01:03:02 PM UTC 24 |
| Finished | Sep 11 01:03:24 PM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42756791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.42756791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_req.4116443021 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 894076605 ps |
| CPU time | 7.5 seconds |
| Started | Sep 11 01:03:02 PM UTC 24 |
| Finished | Sep 11 01:03:11 PM UTC 24 |
| Peak memory | 251080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116443021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.4116443021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_regwen.3950031001 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 1071360942 ps |
| CPU time | 12.19 seconds |
| Started | Sep 11 01:03:05 PM UTC 24 |
| Finished | Sep 11 01:03:18 PM UTC 24 |
| Peak memory | 251600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950031001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.3950031001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/41.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_smoke.3041288327 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 617433504 ps |
| CPU time | 5.95 seconds |
| Started | Sep 11 01:03:00 PM UTC 24 |
| Finished | Sep 11 01:03:07 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041288327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.3041288327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/41.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all.86638476 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 23755693126 ps |
| CPU time | 272.62 seconds |
| Started | Sep 11 01:03:08 PM UTC 24 |
| Finished | Sep 11 01:07:45 PM UTC 24 |
| Peak memory | 306588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86638476 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.86638476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_test_access.3431722112 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 695476010 ps |
| CPU time | 21.52 seconds |
| Started | Sep 11 01:03:05 PM UTC 24 |
| Finished | Sep 11 01:03:27 PM UTC 24 |
| Peak memory | 257512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431722112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.3431722112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/41.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_alert_test.1641418748 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 62607522 ps |
| CPU time | 2.66 seconds |
| Started | Sep 11 01:03:16 PM UTC 24 |
| Finished | Sep 11 01:03:20 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641418748 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.1641418748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/42.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_errs.400117564 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 1437564978 ps |
| CPU time | 9.99 seconds |
| Started | Sep 11 01:03:09 PM UTC 24 |
| Finished | Sep 11 01:03:20 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400117564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.400117564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/42.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_lock.2446137138 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 14878257020 ps |
| CPU time | 30.19 seconds |
| Started | Sep 11 01:03:09 PM UTC 24 |
| Finished | Sep 11 01:03:40 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446137138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.2446137138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/42.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_init_fail.1249925889 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 79668665 ps |
| CPU time | 3.55 seconds |
| Started | Sep 11 01:03:08 PM UTC 24 |
| Finished | Sep 11 01:03:13 PM UTC 24 |
| Peak memory | 253244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249925889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.1249925889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/42.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_macro_errs.3729335395 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 1902520781 ps |
| CPU time | 16.45 seconds |
| Started | Sep 11 01:03:12 PM UTC 24 |
| Finished | Sep 11 01:03:29 PM UTC 24 |
| Peak memory | 253460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729335395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.3729335395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/42.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_key_req.1878981071 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 1653843524 ps |
| CPU time | 10.68 seconds |
| Started | Sep 11 01:03:14 PM UTC 24 |
| Finished | Sep 11 01:03:26 PM UTC 24 |
| Peak memory | 251568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878981071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.1878981071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_esc.2995909654 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 270203607 ps |
| CPU time | 5.74 seconds |
| Started | Sep 11 01:03:09 PM UTC 24 |
| Finished | Sep 11 01:03:15 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995909654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.2995909654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_req.1925974475 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 1050043049 ps |
| CPU time | 16.75 seconds |
| Started | Sep 11 01:03:08 PM UTC 24 |
| Finished | Sep 11 01:03:26 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925974475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.1925974475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_regwen.10698471 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 254780352 ps |
| CPU time | 6.28 seconds |
| Started | Sep 11 01:03:14 PM UTC 24 |
| Finished | Sep 11 01:03:21 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10698471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ot p_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.10698471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/42.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_smoke.63940797 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 189559090 ps |
| CPU time | 4.28 seconds |
| Started | Sep 11 01:03:08 PM UTC 24 |
| Finished | Sep 11 01:03:14 PM UTC 24 |
| Peak memory | 251524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63940797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.63940797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/42.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all.3139959715 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 5029030608 ps |
| CPU time | 43.94 seconds |
| Started | Sep 11 01:03:14 PM UTC 24 |
| Finished | Sep 11 01:03:59 PM UTC 24 |
| Peak memory | 253712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139959715 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.3139959715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_test_access.2761439704 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 1644426169 ps |
| CPU time | 32.88 seconds |
| Started | Sep 11 01:03:14 PM UTC 24 |
| Finished | Sep 11 01:03:48 PM UTC 24 |
| Peak memory | 257448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761439704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.2761439704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/42.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_alert_test.3666139654 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 62682969 ps |
| CPU time | 1.78 seconds |
| Started | Sep 11 01:03:24 PM UTC 24 |
| Finished | Sep 11 01:03:27 PM UTC 24 |
| Peak memory | 251140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666139654 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.3666139654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/43.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_check_fail.4291196278 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 790548594 ps |
| CPU time | 24.1 seconds |
| Started | Sep 11 01:03:23 PM UTC 24 |
| Finished | Sep 11 01:03:49 PM UTC 24 |
| Peak memory | 257516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291196278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.4291196278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/43.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_errs.2190835968 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 505635419 ps |
| CPU time | 9.5 seconds |
| Started | Sep 11 01:03:23 PM UTC 24 |
| Finished | Sep 11 01:03:34 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190835968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.2190835968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/43.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_lock.3451567365 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 532277539 ps |
| CPU time | 12.22 seconds |
| Started | Sep 11 01:03:18 PM UTC 24 |
| Finished | Sep 11 01:03:32 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451567365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.3451567365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/43.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_init_fail.4007540808 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 322923633 ps |
| CPU time | 4.27 seconds |
| Started | Sep 11 01:03:16 PM UTC 24 |
| Finished | Sep 11 01:03:22 PM UTC 24 |
| Peak memory | 251264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007540808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.4007540808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/43.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_macro_errs.2133069892 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 2011128140 ps |
| CPU time | 30.09 seconds |
| Started | Sep 11 01:03:23 PM UTC 24 |
| Finished | Sep 11 01:03:55 PM UTC 24 |
| Peak memory | 255416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133069892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.2133069892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/43.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_key_req.1240395069 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 22760478787 ps |
| CPU time | 27.35 seconds |
| Started | Sep 11 01:03:23 PM UTC 24 |
| Finished | Sep 11 01:03:52 PM UTC 24 |
| Peak memory | 253404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240395069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.1240395069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_esc.3732445730 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 513825573 ps |
| CPU time | 8.62 seconds |
| Started | Sep 11 01:03:18 PM UTC 24 |
| Finished | Sep 11 01:03:28 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732445730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.3732445730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_req.2822325925 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 1201566544 ps |
| CPU time | 22.76 seconds |
| Started | Sep 11 01:03:16 PM UTC 24 |
| Finished | Sep 11 01:03:41 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822325925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.2822325925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_regwen.1931608322 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 268960166 ps |
| CPU time | 9.19 seconds |
| Started | Sep 11 01:03:23 PM UTC 24 |
| Finished | Sep 11 01:03:34 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931608322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.1931608322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/43.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_smoke.3823221866 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 743340320 ps |
| CPU time | 6.25 seconds |
| Started | Sep 11 01:03:16 PM UTC 24 |
| Finished | Sep 11 01:03:24 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823221866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.3823221866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/43.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.938558567 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 17060274837 ps |
| CPU time | 34.51 seconds |
| Started | Sep 11 01:03:24 PM UTC 24 |
| Finished | Sep 11 01:04:00 PM UTC 24 |
| Peak memory | 255504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938558567 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.938558567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_test_access.1634077743 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 6697861833 ps |
| CPU time | 37.76 seconds |
| Started | Sep 11 01:03:24 PM UTC 24 |
| Finished | Sep 11 01:04:03 PM UTC 24 |
| Peak memory | 251368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634077743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.1634077743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/43.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_alert_test.349627317 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 548082432 ps |
| CPU time | 5.49 seconds |
| Started | Sep 11 01:03:34 PM UTC 24 |
| Finished | Sep 11 01:03:40 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349627317 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.349627317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/44.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_check_fail.787029835 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 1535321458 ps |
| CPU time | 18.61 seconds |
| Started | Sep 11 01:03:33 PM UTC 24 |
| Finished | Sep 11 01:03:54 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787029835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.787029835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/44.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_errs.1046373955 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 748591129 ps |
| CPU time | 23.3 seconds |
| Started | Sep 11 01:03:33 PM UTC 24 |
| Finished | Sep 11 01:03:58 PM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046373955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.1046373955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/44.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_lock.246621593 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 1128398278 ps |
| CPU time | 10.94 seconds |
| Started | Sep 11 01:03:33 PM UTC 24 |
| Finished | Sep 11 01:03:46 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246621593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.246621593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/44.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_init_fail.1075938467 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 184094987 ps |
| CPU time | 5.03 seconds |
| Started | Sep 11 01:03:24 PM UTC 24 |
| Finished | Sep 11 01:03:30 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075938467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.1075938467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/44.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_macro_errs.632685904 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 142357214 ps |
| CPU time | 5.03 seconds |
| Started | Sep 11 01:03:33 PM UTC 24 |
| Finished | Sep 11 01:03:40 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632685904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.632685904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/44.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_key_req.333870026 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 1759791606 ps |
| CPU time | 22.62 seconds |
| Started | Sep 11 01:03:34 PM UTC 24 |
| Finished | Sep 11 01:03:58 PM UTC 24 |
| Peak memory | 253356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333870026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.333870026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_esc.2792297065 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 785804962 ps |
| CPU time | 7.49 seconds |
| Started | Sep 11 01:03:33 PM UTC 24 |
| Finished | Sep 11 01:03:42 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792297065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.2792297065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_req.2339491916 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 1021134469 ps |
| CPU time | 7.15 seconds |
| Started | Sep 11 01:03:33 PM UTC 24 |
| Finished | Sep 11 01:03:42 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339491916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.2339491916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_regwen.3010841563 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 97438686 ps |
| CPU time | 3.59 seconds |
| Started | Sep 11 01:03:34 PM UTC 24 |
| Finished | Sep 11 01:03:39 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010841563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.3010841563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/44.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_smoke.3229350796 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 535824805 ps |
| CPU time | 5.91 seconds |
| Started | Sep 11 01:03:24 PM UTC 24 |
| Finished | Sep 11 01:03:31 PM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229350796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.3229350796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/44.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.2564986366 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 3136640646 ps |
| CPU time | 20.87 seconds |
| Started | Sep 11 01:03:34 PM UTC 24 |
| Finished | Sep 11 01:03:56 PM UTC 24 |
| Peak memory | 251576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564986366 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.2564986366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_test_access.1851450367 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 296350643 ps |
| CPU time | 4.04 seconds |
| Started | Sep 11 01:03:34 PM UTC 24 |
| Finished | Sep 11 01:03:39 PM UTC 24 |
| Peak memory | 251304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851450367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.1851450367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/44.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_alert_test.3668778428 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 91110906 ps |
| CPU time | 2.26 seconds |
| Started | Sep 11 01:03:40 PM UTC 24 |
| Finished | Sep 11 01:03:43 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668778428 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.3668778428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/45.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_check_fail.4224225072 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 5876032305 ps |
| CPU time | 35.21 seconds |
| Started | Sep 11 01:03:34 PM UTC 24 |
| Finished | Sep 11 01:04:11 PM UTC 24 |
| Peak memory | 257516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224225072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.4224225072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_errs.4175337894 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 8541416010 ps |
| CPU time | 15.74 seconds |
| Started | Sep 11 01:03:34 PM UTC 24 |
| Finished | Sep 11 01:03:51 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175337894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.4175337894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/45.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_lock.3910319241 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 195867919 ps |
| CPU time | 5.2 seconds |
| Started | Sep 11 01:03:34 PM UTC 24 |
| Finished | Sep 11 01:03:41 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910319241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.3910319241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/45.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_init_fail.1893990658 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 290385452 ps |
| CPU time | 6.13 seconds |
| Started | Sep 11 01:03:34 PM UTC 24 |
| Finished | Sep 11 01:03:41 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893990658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.1893990658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/45.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_macro_errs.1999578974 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 1825976071 ps |
| CPU time | 25.45 seconds |
| Started | Sep 11 01:03:36 PM UTC 24 |
| Finished | Sep 11 01:04:03 PM UTC 24 |
| Peak memory | 257512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999578974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.1999578974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/45.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_key_req.1256490046 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 366829339 ps |
| CPU time | 6.78 seconds |
| Started | Sep 11 01:03:36 PM UTC 24 |
| Finished | Sep 11 01:03:44 PM UTC 24 |
| Peak memory | 251264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256490046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.1256490046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_esc.3736280544 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 1118081908 ps |
| CPU time | 16.41 seconds |
| Started | Sep 11 01:03:34 PM UTC 24 |
| Finished | Sep 11 01:03:52 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736280544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.3736280544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_req.738322070 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 5192824996 ps |
| CPU time | 21.35 seconds |
| Started | Sep 11 01:03:34 PM UTC 24 |
| Finished | Sep 11 01:03:57 PM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738322070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.738322070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_regwen.2833663527 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 2106498420 ps |
| CPU time | 6.24 seconds |
| Started | Sep 11 01:03:36 PM UTC 24 |
| Finished | Sep 11 01:03:43 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833663527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.2833663527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/45.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_smoke.3618140934 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 2185685487 ps |
| CPU time | 5.69 seconds |
| Started | Sep 11 01:03:34 PM UTC 24 |
| Finished | Sep 11 01:03:41 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618140934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.3618140934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/45.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.1477550493 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 17409124921 ps |
| CPU time | 142.75 seconds |
| Started | Sep 11 01:03:40 PM UTC 24 |
| Finished | Sep 11 01:06:05 PM UTC 24 |
| Peak memory | 257580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477550493 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.1477550493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.2347609836 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 10973184187 ps |
| CPU time | 128.04 seconds |
| Started | Sep 11 01:03:40 PM UTC 24 |
| Finished | Sep 11 01:05:50 PM UTC 24 |
| Peak memory | 272008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2347609836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.otp_ctrl_stress_all_with_rand_reset.2347609836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_test_access.2436793844 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 1702220586 ps |
| CPU time | 21.99 seconds |
| Started | Sep 11 01:03:38 PM UTC 24 |
| Finished | Sep 11 01:04:01 PM UTC 24 |
| Peak memory | 257512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436793844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.2436793844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/45.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_alert_test.1943151768 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 46428295 ps |
| CPU time | 2.55 seconds |
| Started | Sep 11 01:03:45 PM UTC 24 |
| Finished | Sep 11 01:03:49 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943151768 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.1943151768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/46.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_check_fail.1100408494 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 4154521346 ps |
| CPU time | 14.34 seconds |
| Started | Sep 11 01:03:45 PM UTC 24 |
| Finished | Sep 11 01:04:00 PM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100408494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.1100408494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_errs.1991703998 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 593458008 ps |
| CPU time | 16.55 seconds |
| Started | Sep 11 01:03:45 PM UTC 24 |
| Finished | Sep 11 01:04:03 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991703998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.1991703998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/46.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_lock.583027834 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 12137168087 ps |
| CPU time | 28.71 seconds |
| Started | Sep 11 01:03:45 PM UTC 24 |
| Finished | Sep 11 01:04:15 PM UTC 24 |
| Peak memory | 257552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583027834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.583027834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/46.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_init_fail.666894738 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 661985276 ps |
| CPU time | 5.37 seconds |
| Started | Sep 11 01:03:41 PM UTC 24 |
| Finished | Sep 11 01:03:48 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666894738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.666894738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/46.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_macro_errs.845806819 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 4105409913 ps |
| CPU time | 27.66 seconds |
| Started | Sep 11 01:03:45 PM UTC 24 |
| Finished | Sep 11 01:04:14 PM UTC 24 |
| Peak memory | 253348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845806819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.845806819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/46.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_key_req.1599883807 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 1314117564 ps |
| CPU time | 10.1 seconds |
| Started | Sep 11 01:03:45 PM UTC 24 |
| Finished | Sep 11 01:03:56 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599883807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.1599883807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_esc.2757482968 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 137178947 ps |
| CPU time | 6.77 seconds |
| Started | Sep 11 01:03:45 PM UTC 24 |
| Finished | Sep 11 01:03:53 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757482968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.2757482968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_req.1914870640 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 671701990 ps |
| CPU time | 13.68 seconds |
| Started | Sep 11 01:03:41 PM UTC 24 |
| Finished | Sep 11 01:03:56 PM UTC 24 |
| Peak memory | 257364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914870640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.1914870640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_regwen.25106019 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 263284974 ps |
| CPU time | 9.84 seconds |
| Started | Sep 11 01:03:45 PM UTC 24 |
| Finished | Sep 11 01:03:56 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25106019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ot p_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.25106019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/46.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_smoke.3835482832 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 663146091 ps |
| CPU time | 11.27 seconds |
| Started | Sep 11 01:03:41 PM UTC 24 |
| Finished | Sep 11 01:03:54 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835482832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.3835482832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/46.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all.268368124 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 38584460854 ps |
| CPU time | 87.54 seconds |
| Started | Sep 11 01:03:45 PM UTC 24 |
| Finished | Sep 11 01:05:15 PM UTC 24 |
| Peak memory | 257508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268368124 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.268368124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_test_access.2865257391 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 480273385 ps |
| CPU time | 8.72 seconds |
| Started | Sep 11 01:03:45 PM UTC 24 |
| Finished | Sep 11 01:03:55 PM UTC 24 |
| Peak memory | 251304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865257391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.2865257391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/46.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_alert_test.1101767760 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 161948031 ps |
| CPU time | 2.02 seconds |
| Started | Sep 11 01:04:02 PM UTC 24 |
| Finished | Sep 11 01:04:05 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101767760 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.1101767760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/47.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_check_fail.4110380136 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 444952399 ps |
| CPU time | 4.37 seconds |
| Started | Sep 11 01:03:55 PM UTC 24 |
| Finished | Sep 11 01:04:00 PM UTC 24 |
| Peak memory | 251012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110380136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.4110380136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/47.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_errs.40708282 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 1158614744 ps |
| CPU time | 14.51 seconds |
| Started | Sep 11 01:03:51 PM UTC 24 |
| Finished | Sep 11 01:04:07 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40708282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.40708282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/47.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_lock.220720061 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 806301533 ps |
| CPU time | 6.7 seconds |
| Started | Sep 11 01:03:51 PM UTC 24 |
| Finished | Sep 11 01:03:59 PM UTC 24 |
| Peak memory | 257556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220720061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.220720061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/47.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_init_fail.1707349769 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 464209403 ps |
| CPU time | 5.85 seconds |
| Started | Sep 11 01:03:47 PM UTC 24 |
| Finished | Sep 11 01:03:54 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707349769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.1707349769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/47.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_macro_errs.2534285717 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 1887715690 ps |
| CPU time | 21.76 seconds |
| Started | Sep 11 01:03:55 PM UTC 24 |
| Finished | Sep 11 01:04:18 PM UTC 24 |
| Peak memory | 252896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534285717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.2534285717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/47.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_key_req.3675906094 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 1144464668 ps |
| CPU time | 29.33 seconds |
| Started | Sep 11 01:03:55 PM UTC 24 |
| Finished | Sep 11 01:04:26 PM UTC 24 |
| Peak memory | 257712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675906094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.3675906094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_esc.3767750748 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 334797859 ps |
| CPU time | 5.82 seconds |
| Started | Sep 11 01:03:49 PM UTC 24 |
| Finished | Sep 11 01:03:56 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767750748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.3767750748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_req.920465635 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 174678225 ps |
| CPU time | 5.71 seconds |
| Started | Sep 11 01:03:49 PM UTC 24 |
| Finished | Sep 11 01:03:56 PM UTC 24 |
| Peak memory | 257352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920465635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.920465635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_regwen.4210308257 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 709041019 ps |
| CPU time | 8.86 seconds |
| Started | Sep 11 01:03:55 PM UTC 24 |
| Finished | Sep 11 01:04:05 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210308257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.4210308257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/47.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_smoke.1757542563 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 4896969212 ps |
| CPU time | 23.35 seconds |
| Started | Sep 11 01:03:45 PM UTC 24 |
| Finished | Sep 11 01:04:10 PM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757542563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.1757542563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/47.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all.1850505846 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 76523282 ps |
| CPU time | 2.33 seconds |
| Started | Sep 11 01:03:55 PM UTC 24 |
| Finished | Sep 11 01:03:59 PM UTC 24 |
| Peak memory | 251112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850505846 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.1850505846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_test_access.115266712 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 1021636196 ps |
| CPU time | 19.26 seconds |
| Started | Sep 11 01:03:55 PM UTC 24 |
| Finished | Sep 11 01:04:16 PM UTC 24 |
| Peak memory | 253352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115266712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.115266712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/47.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_alert_test.601274593 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 105463546 ps |
| CPU time | 1.94 seconds |
| Started | Sep 11 01:04:02 PM UTC 24 |
| Finished | Sep 11 01:04:06 PM UTC 24 |
| Peak memory | 251080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601274593 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.601274593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/48.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_errs.3006547790 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 1128644751 ps |
| CPU time | 16.04 seconds |
| Started | Sep 11 01:04:02 PM UTC 24 |
| Finished | Sep 11 01:04:19 PM UTC 24 |
| Peak memory | 251096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006547790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.3006547790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/48.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_lock.2706904765 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 780400905 ps |
| CPU time | 8.46 seconds |
| Started | Sep 11 01:04:02 PM UTC 24 |
| Finished | Sep 11 01:04:12 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706904765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.2706904765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/48.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_init_fail.393149379 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 136908639 ps |
| CPU time | 4.76 seconds |
| Started | Sep 11 01:04:02 PM UTC 24 |
| Finished | Sep 11 01:04:08 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393149379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.393149379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/48.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_macro_errs.4256966173 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 9713041053 ps |
| CPU time | 23.44 seconds |
| Started | Sep 11 01:04:02 PM UTC 24 |
| Finished | Sep 11 01:04:27 PM UTC 24 |
| Peak memory | 255788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256966173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.4256966173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/48.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_key_req.2265334385 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 3097744435 ps |
| CPU time | 30.02 seconds |
| Started | Sep 11 01:04:02 PM UTC 24 |
| Finished | Sep 11 01:04:34 PM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265334385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.2265334385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_esc.2587577561 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 335542500 ps |
| CPU time | 12.16 seconds |
| Started | Sep 11 01:04:02 PM UTC 24 |
| Finished | Sep 11 01:04:15 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587577561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.2587577561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_req.2838630843 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 558814340 ps |
| CPU time | 7.3 seconds |
| Started | Sep 11 01:04:02 PM UTC 24 |
| Finished | Sep 11 01:04:10 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838630843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.2838630843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_regwen.1854720528 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 1591314539 ps |
| CPU time | 2.93 seconds |
| Started | Sep 11 01:04:02 PM UTC 24 |
| Finished | Sep 11 01:04:06 PM UTC 24 |
| Peak memory | 257360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854720528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.1854720528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/48.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_smoke.2846654245 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 734282739 ps |
| CPU time | 5.56 seconds |
| Started | Sep 11 01:04:02 PM UTC 24 |
| Finished | Sep 11 01:04:09 PM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846654245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.2846654245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/48.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.2522282415 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 1885950187 ps |
| CPU time | 30.96 seconds |
| Started | Sep 11 01:04:02 PM UTC 24 |
| Finished | Sep 11 01:04:35 PM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522282415 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.2522282415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.4014043335 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 5581726946 ps |
| CPU time | 65.67 seconds |
| Started | Sep 11 01:04:02 PM UTC 24 |
| Finished | Sep 11 01:05:10 PM UTC 24 |
| Peak memory | 267944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4014043335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.otp_ctrl_stress_all_with_rand_reset.4014043335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_test_access.3629861925 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 4351513202 ps |
| CPU time | 25.84 seconds |
| Started | Sep 11 01:04:02 PM UTC 24 |
| Finished | Sep 11 01:04:29 PM UTC 24 |
| Peak memory | 257512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629861925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.3629861925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/48.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_alert_test.1799388027 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 48735238 ps |
| CPU time | 2.16 seconds |
| Started | Sep 11 01:04:13 PM UTC 24 |
| Finished | Sep 11 01:04:16 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799388027 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.1799388027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/49.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_check_fail.2704008271 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 1091093491 ps |
| CPU time | 11.49 seconds |
| Started | Sep 11 01:04:06 PM UTC 24 |
| Finished | Sep 11 01:04:19 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704008271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.2704008271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/49.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_errs.4289600923 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 862135969 ps |
| CPU time | 10.74 seconds |
| Started | Sep 11 01:04:06 PM UTC 24 |
| Finished | Sep 11 01:04:18 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289600923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.4289600923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/49.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_lock.3167786990 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 3094584989 ps |
| CPU time | 29.72 seconds |
| Started | Sep 11 01:04:06 PM UTC 24 |
| Finished | Sep 11 01:04:37 PM UTC 24 |
| Peak memory | 253492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167786990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.3167786990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/49.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_init_fail.3071597130 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 120773720 ps |
| CPU time | 4.85 seconds |
| Started | Sep 11 01:04:03 PM UTC 24 |
| Finished | Sep 11 01:04:09 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071597130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.3071597130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/49.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_macro_errs.3547311567 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 1679408095 ps |
| CPU time | 12.36 seconds |
| Started | Sep 11 01:04:06 PM UTC 24 |
| Finished | Sep 11 01:04:19 PM UTC 24 |
| Peak memory | 251628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547311567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.3547311567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/49.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_key_req.2560039148 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 13175661825 ps |
| CPU time | 27.49 seconds |
| Started | Sep 11 01:04:06 PM UTC 24 |
| Finished | Sep 11 01:04:35 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560039148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.2560039148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_esc.614057616 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 376199610 ps |
| CPU time | 8.5 seconds |
| Started | Sep 11 01:04:06 PM UTC 24 |
| Finished | Sep 11 01:04:15 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614057616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.614057616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_req.3066074906 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 144942522 ps |
| CPU time | 5.58 seconds |
| Started | Sep 11 01:04:03 PM UTC 24 |
| Finished | Sep 11 01:04:09 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066074906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.3066074906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_regwen.3756446667 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 1988867832 ps |
| CPU time | 6.81 seconds |
| Started | Sep 11 01:04:06 PM UTC 24 |
| Finished | Sep 11 01:04:14 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756446667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.3756446667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/49.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_smoke.3044789081 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 721044438 ps |
| CPU time | 11.4 seconds |
| Started | Sep 11 01:04:02 PM UTC 24 |
| Finished | Sep 11 01:04:15 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044789081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.3044789081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/49.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all.1966393895 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 157690703 ps |
| CPU time | 6.06 seconds |
| Started | Sep 11 01:04:13 PM UTC 24 |
| Finished | Sep 11 01:04:20 PM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966393895 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.1966393895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_test_access.3325908989 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 7767422091 ps |
| CPU time | 17.2 seconds |
| Started | Sep 11 01:04:06 PM UTC 24 |
| Finished | Sep 11 01:04:25 PM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325908989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.3325908989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/49.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_alert_test.458959070 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 107525375 ps |
| CPU time | 2.52 seconds |
| Started | Sep 11 12:58:12 PM UTC 24 |
| Finished | Sep 11 12:58:16 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458959070 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.458959070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_background_chks.640595536 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 5361549467 ps |
| CPU time | 18.15 seconds |
| Started | Sep 11 12:58:02 PM UTC 24 |
| Finished | Sep 11 12:58:22 PM UTC 24 |
| Peak memory | 257572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640595536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.640595536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_check_fail.2682496414 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11027757443 ps |
| CPU time | 32.27 seconds |
| Started | Sep 11 12:58:06 PM UTC 24 |
| Finished | Sep 11 12:58:40 PM UTC 24 |
| Peak memory | 257840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682496414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.2682496414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_errs.1077277754 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 327788211 ps |
| CPU time | 22.58 seconds |
| Started | Sep 11 12:58:05 PM UTC 24 |
| Finished | Sep 11 12:58:29 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077277754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.1077277754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_lock.4027425502 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 11287362788 ps |
| CPU time | 27.99 seconds |
| Started | Sep 11 12:58:05 PM UTC 24 |
| Finished | Sep 11 12:58:34 PM UTC 24 |
| Peak memory | 253488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027425502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.4027425502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_init_fail.4255339188 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 95787542 ps |
| CPU time | 4.77 seconds |
| Started | Sep 11 12:58:02 PM UTC 24 |
| Finished | Sep 11 12:58:08 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255339188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.4255339188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_macro_errs.384544612 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 15120497262 ps |
| CPU time | 37.19 seconds |
| Started | Sep 11 12:58:06 PM UTC 24 |
| Finished | Sep 11 12:58:45 PM UTC 24 |
| Peak memory | 257512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384544612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.384544612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_key_req.3496207279 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 506034604 ps |
| CPU time | 23.03 seconds |
| Started | Sep 11 12:58:06 PM UTC 24 |
| Finished | Sep 11 12:58:31 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496207279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.3496207279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_esc.1501246016 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 512290550 ps |
| CPU time | 8.89 seconds |
| Started | Sep 11 12:58:02 PM UTC 24 |
| Finished | Sep 11 12:58:12 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501246016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.1501246016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_req.529651916 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 9224597702 ps |
| CPU time | 22.97 seconds |
| Started | Sep 11 12:58:02 PM UTC 24 |
| Finished | Sep 11 12:58:27 PM UTC 24 |
| Peak memory | 257420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529651916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.529651916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_regwen.2122183444 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 115362891 ps |
| CPU time | 4.62 seconds |
| Started | Sep 11 12:58:08 PM UTC 24 |
| Finished | Sep 11 12:58:14 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122183444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.2122183444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_smoke.447062011 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 101043659 ps |
| CPU time | 4.28 seconds |
| Started | Sep 11 12:58:00 PM UTC 24 |
| Finished | Sep 11 12:58:05 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447062011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.447062011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.1422904818 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 23096000894 ps |
| CPU time | 90.54 seconds |
| Started | Sep 11 12:58:10 PM UTC 24 |
| Finished | Sep 11 12:59:42 PM UTC 24 |
| Peak memory | 257588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1422904818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.otp_ctrl_stress_all_with_rand_reset.1422904818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_test_access.1110661875 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 5339837954 ps |
| CPU time | 22 seconds |
| Started | Sep 11 12:58:10 PM UTC 24 |
| Finished | Sep 11 12:58:33 PM UTC 24 |
| Peak memory | 253420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110661875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.1110661875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/5.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_init_fail.1225740165 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 1535211847 ps |
| CPU time | 3.95 seconds |
| Started | Sep 11 01:04:13 PM UTC 24 |
| Finished | Sep 11 01:04:18 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225740165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.1225740165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/50.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_parallel_lc_esc.2933442299 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 1145192236 ps |
| CPU time | 8.29 seconds |
| Started | Sep 11 01:04:13 PM UTC 24 |
| Finished | Sep 11 01:04:22 PM UTC 24 |
| Peak memory | 251124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933442299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.2933442299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/50.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.2087927154 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 5753710097 ps |
| CPU time | 60.52 seconds |
| Started | Sep 11 01:04:13 PM UTC 24 |
| Finished | Sep 11 01:05:15 PM UTC 24 |
| Peak memory | 267880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2087927154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 50.otp_ctrl_stress_all_with_rand_reset.2087927154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_init_fail.348167724 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1688128880 ps |
| CPU time | 3.45 seconds |
| Started | Sep 11 01:04:13 PM UTC 24 |
| Finished | Sep 11 01:04:17 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348167724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.348167724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/51.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_parallel_lc_esc.3611432633 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 682626346 ps |
| CPU time | 4.51 seconds |
| Started | Sep 11 01:04:13 PM UTC 24 |
| Finished | Sep 11 01:04:19 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611432633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.3611432633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/51.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.691319947 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 11144080535 ps |
| CPU time | 115.29 seconds |
| Started | Sep 11 01:04:13 PM UTC 24 |
| Finished | Sep 11 01:06:10 PM UTC 24 |
| Peak memory | 267828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=691319947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.691319947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_init_fail.2119982206 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 207712794 ps |
| CPU time | 3.73 seconds |
| Started | Sep 11 01:04:13 PM UTC 24 |
| Finished | Sep 11 01:04:18 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119982206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.2119982206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/52.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_parallel_lc_esc.1086676207 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 625161450 ps |
| CPU time | 9.86 seconds |
| Started | Sep 11 01:04:13 PM UTC 24 |
| Finished | Sep 11 01:04:24 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086676207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.1086676207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/52.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.2986113218 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 54732594711 ps |
| CPU time | 170.23 seconds |
| Started | Sep 11 01:04:13 PM UTC 24 |
| Finished | Sep 11 01:07:06 PM UTC 24 |
| Peak memory | 268172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2986113218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 52.otp_ctrl_stress_all_with_rand_reset.2986113218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_init_fail.1123832666 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 285218764 ps |
| CPU time | 3.56 seconds |
| Started | Sep 11 01:04:13 PM UTC 24 |
| Finished | Sep 11 01:04:18 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123832666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.1123832666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/53.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_parallel_lc_esc.1053425939 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 3939563665 ps |
| CPU time | 14.56 seconds |
| Started | Sep 11 01:04:15 PM UTC 24 |
| Finished | Sep 11 01:04:31 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053425939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.1053425939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/53.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_init_fail.1548669507 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 233729188 ps |
| CPU time | 6.02 seconds |
| Started | Sep 11 01:04:15 PM UTC 24 |
| Finished | Sep 11 01:04:22 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548669507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.1548669507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/54.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_parallel_lc_esc.2694429708 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 342832632 ps |
| CPU time | 4.4 seconds |
| Started | Sep 11 01:04:15 PM UTC 24 |
| Finished | Sep 11 01:04:21 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694429708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.2694429708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/54.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.2736390837 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 42656458688 ps |
| CPU time | 99.99 seconds |
| Started | Sep 11 01:04:15 PM UTC 24 |
| Finished | Sep 11 01:05:57 PM UTC 24 |
| Peak memory | 267852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2736390837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 54.otp_ctrl_stress_all_with_rand_reset.2736390837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/54.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_init_fail.2818281360 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 627469592 ps |
| CPU time | 4.55 seconds |
| Started | Sep 11 01:04:19 PM UTC 24 |
| Finished | Sep 11 01:04:25 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818281360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.2818281360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/55.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_parallel_lc_esc.1360152220 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 131409224 ps |
| CPU time | 5.4 seconds |
| Started | Sep 11 01:04:19 PM UTC 24 |
| Finished | Sep 11 01:04:26 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360152220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.1360152220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/55.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_init_fail.2694187975 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2734778013 ps |
| CPU time | 6.32 seconds |
| Started | Sep 11 01:04:19 PM UTC 24 |
| Finished | Sep 11 01:04:27 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694187975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.2694187975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/56.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_parallel_lc_esc.1167388145 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 604581477 ps |
| CPU time | 4.81 seconds |
| Started | Sep 11 01:04:19 PM UTC 24 |
| Finished | Sep 11 01:04:25 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167388145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.1167388145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/56.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.3432957199 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 14670523043 ps |
| CPU time | 77.8 seconds |
| Started | Sep 11 01:04:19 PM UTC 24 |
| Finished | Sep 11 01:05:39 PM UTC 24 |
| Peak memory | 257716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3432957199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 56.otp_ctrl_stress_all_with_rand_reset.3432957199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_init_fail.1560919779 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 125387560 ps |
| CPU time | 5.03 seconds |
| Started | Sep 11 01:04:19 PM UTC 24 |
| Finished | Sep 11 01:04:25 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560919779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.1560919779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/57.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_parallel_lc_esc.2606839494 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 367279780 ps |
| CPU time | 7.39 seconds |
| Started | Sep 11 01:04:19 PM UTC 24 |
| Finished | Sep 11 01:04:28 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606839494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.2606839494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/57.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.1005672218 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 20267260081 ps |
| CPU time | 121.55 seconds |
| Started | Sep 11 01:04:19 PM UTC 24 |
| Finished | Sep 11 01:06:24 PM UTC 24 |
| Peak memory | 274060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1005672218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 57.otp_ctrl_stress_all_with_rand_reset.1005672218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/57.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_init_fail.3056395786 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 309898356 ps |
| CPU time | 6.21 seconds |
| Started | Sep 11 01:04:20 PM UTC 24 |
| Finished | Sep 11 01:04:27 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056395786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.3056395786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/58.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_parallel_lc_esc.4076747780 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 5350591879 ps |
| CPU time | 26 seconds |
| Started | Sep 11 01:04:20 PM UTC 24 |
| Finished | Sep 11 01:04:47 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076747780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.4076747780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/58.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_init_fail.1058086624 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 105521830 ps |
| CPU time | 3.71 seconds |
| Started | Sep 11 01:04:20 PM UTC 24 |
| Finished | Sep 11 01:04:24 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058086624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.1058086624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/59.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_parallel_lc_esc.1339947878 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 8127111358 ps |
| CPU time | 14.47 seconds |
| Started | Sep 11 01:04:20 PM UTC 24 |
| Finished | Sep 11 01:04:35 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339947878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.1339947878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_alert_test.1138604260 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 137985600 ps |
| CPU time | 3.43 seconds |
| Started | Sep 11 12:58:23 PM UTC 24 |
| Finished | Sep 11 12:58:28 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138604260 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.1138604260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_background_chks.820236177 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 757589630 ps |
| CPU time | 6.96 seconds |
| Started | Sep 11 12:58:14 PM UTC 24 |
| Finished | Sep 11 12:58:22 PM UTC 24 |
| Peak memory | 257420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820236177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.820236177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_check_fail.13710977 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 780556279 ps |
| CPU time | 9.63 seconds |
| Started | Sep 11 12:58:19 PM UTC 24 |
| Finished | Sep 11 12:58:31 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13710977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.13710977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_errs.2832449347 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 845716006 ps |
| CPU time | 15.72 seconds |
| Started | Sep 11 12:58:17 PM UTC 24 |
| Finished | Sep 11 12:58:34 PM UTC 24 |
| Peak memory | 251092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832449347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.2832449347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_lock.197221497 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 523887269 ps |
| CPU time | 8.86 seconds |
| Started | Sep 11 12:58:17 PM UTC 24 |
| Finished | Sep 11 12:58:27 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197221497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.197221497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_init_fail.788032175 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 133575930 ps |
| CPU time | 5.3 seconds |
| Started | Sep 11 12:58:14 PM UTC 24 |
| Finished | Sep 11 12:58:20 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788032175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.788032175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_macro_errs.3414472366 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1603604850 ps |
| CPU time | 35.34 seconds |
| Started | Sep 11 12:58:19 PM UTC 24 |
| Finished | Sep 11 12:58:57 PM UTC 24 |
| Peak memory | 255728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414472366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.3414472366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_esc.4077064476 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 241797630 ps |
| CPU time | 6.29 seconds |
| Started | Sep 11 12:58:16 PM UTC 24 |
| Finished | Sep 11 12:58:23 PM UTC 24 |
| Peak memory | 257328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077064476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.4077064476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_req.1281055416 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 1810393064 ps |
| CPU time | 23.19 seconds |
| Started | Sep 11 12:58:16 PM UTC 24 |
| Finished | Sep 11 12:58:40 PM UTC 24 |
| Peak memory | 257620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281055416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.1281055416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_regwen.2051627821 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 158864096 ps |
| CPU time | 6.85 seconds |
| Started | Sep 11 12:58:23 PM UTC 24 |
| Finished | Sep 11 12:58:31 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051627821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.2051627821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_smoke.3270707745 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 422064555 ps |
| CPU time | 7.16 seconds |
| Started | Sep 11 12:58:14 PM UTC 24 |
| Finished | Sep 11 12:58:22 PM UTC 24 |
| Peak memory | 257388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270707745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.3270707745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.586689807 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 14255419502 ps |
| CPU time | 71.66 seconds |
| Started | Sep 11 12:58:23 PM UTC 24 |
| Finished | Sep 11 12:59:37 PM UTC 24 |
| Peak memory | 257552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=586689807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.586689807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_test_access.1305336703 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 246127693 ps |
| CPU time | 12.42 seconds |
| Started | Sep 11 12:58:23 PM UTC 24 |
| Finished | Sep 11 12:58:37 PM UTC 24 |
| Peak memory | 251624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305336703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.1305336703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/6.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_init_fail.4130953802 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 120283043 ps |
| CPU time | 5.39 seconds |
| Started | Sep 11 01:04:23 PM UTC 24 |
| Finished | Sep 11 01:04:30 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130953802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.4130953802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/60.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_parallel_lc_esc.4159765428 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 181854503 ps |
| CPU time | 5.89 seconds |
| Started | Sep 11 01:04:23 PM UTC 24 |
| Finished | Sep 11 01:04:30 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159765428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.4159765428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/60.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.3986448940 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 8792285104 ps |
| CPU time | 76.44 seconds |
| Started | Sep 11 01:04:23 PM UTC 24 |
| Finished | Sep 11 01:05:42 PM UTC 24 |
| Peak memory | 257676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3986448940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 60.otp_ctrl_stress_all_with_rand_reset.3986448940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/60.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_init_fail.1513902019 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 179752466 ps |
| CPU time | 5.18 seconds |
| Started | Sep 11 01:04:24 PM UTC 24 |
| Finished | Sep 11 01:04:30 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513902019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.1513902019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/61.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_parallel_lc_esc.1075864471 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 171883911 ps |
| CPU time | 3.32 seconds |
| Started | Sep 11 01:04:24 PM UTC 24 |
| Finished | Sep 11 01:04:28 PM UTC 24 |
| Peak memory | 251116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075864471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.1075864471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/61.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_init_fail.4224715602 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 594735329 ps |
| CPU time | 5.22 seconds |
| Started | Sep 11 01:04:24 PM UTC 24 |
| Finished | Sep 11 01:04:30 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224715602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.4224715602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/62.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_parallel_lc_esc.1576868712 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 286058432 ps |
| CPU time | 4.44 seconds |
| Started | Sep 11 01:04:24 PM UTC 24 |
| Finished | Sep 11 01:04:29 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576868712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.1576868712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/62.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.645109914 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 4340499780 ps |
| CPU time | 93.15 seconds |
| Started | Sep 11 01:04:29 PM UTC 24 |
| Finished | Sep 11 01:06:04 PM UTC 24 |
| Peak memory | 268200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=645109914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.645109914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_init_fail.1245271000 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 2178143418 ps |
| CPU time | 4 seconds |
| Started | Sep 11 01:04:29 PM UTC 24 |
| Finished | Sep 11 01:04:34 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245271000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.1245271000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/63.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_parallel_lc_esc.3780593276 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 3981366369 ps |
| CPU time | 9.06 seconds |
| Started | Sep 11 01:04:29 PM UTC 24 |
| Finished | Sep 11 01:04:39 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780593276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.3780593276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/63.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_init_fail.4047511160 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 137195541 ps |
| CPU time | 3.45 seconds |
| Started | Sep 11 01:04:29 PM UTC 24 |
| Finished | Sep 11 01:04:34 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047511160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.4047511160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/64.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_parallel_lc_esc.4287075923 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 3226556217 ps |
| CPU time | 9.51 seconds |
| Started | Sep 11 01:04:29 PM UTC 24 |
| Finished | Sep 11 01:04:40 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287075923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.4287075923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/64.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_init_fail.3400396306 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 181431791 ps |
| CPU time | 3.95 seconds |
| Started | Sep 11 01:04:29 PM UTC 24 |
| Finished | Sep 11 01:04:35 PM UTC 24 |
| Peak memory | 250736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400396306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.3400396306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/65.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_parallel_lc_esc.279941928 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 446976061 ps |
| CPU time | 5.82 seconds |
| Started | Sep 11 01:04:30 PM UTC 24 |
| Finished | Sep 11 01:04:37 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279941928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.279941928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/65.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.1171917943 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 8091908628 ps |
| CPU time | 62 seconds |
| Started | Sep 11 01:04:30 PM UTC 24 |
| Finished | Sep 11 01:05:33 PM UTC 24 |
| Peak memory | 257440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1171917943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 65.otp_ctrl_stress_all_with_rand_reset.1171917943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_init_fail.3883336516 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 497245217 ps |
| CPU time | 4.86 seconds |
| Started | Sep 11 01:04:30 PM UTC 24 |
| Finished | Sep 11 01:04:36 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883336516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.3883336516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/66.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_parallel_lc_esc.3195277069 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 624061585 ps |
| CPU time | 8.63 seconds |
| Started | Sep 11 01:04:30 PM UTC 24 |
| Finished | Sep 11 01:04:40 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195277069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.3195277069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/66.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.1364321577 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 46845339673 ps |
| CPU time | 86.51 seconds |
| Started | Sep 11 01:04:30 PM UTC 24 |
| Finished | Sep 11 01:05:58 PM UTC 24 |
| Peak memory | 267852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1364321577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 66.otp_ctrl_stress_all_with_rand_reset.1364321577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_init_fail.3477822409 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 577304752 ps |
| CPU time | 4.2 seconds |
| Started | Sep 11 01:04:30 PM UTC 24 |
| Finished | Sep 11 01:04:35 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477822409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.3477822409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/67.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_parallel_lc_esc.1553186596 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1424952409 ps |
| CPU time | 21.3 seconds |
| Started | Sep 11 01:04:30 PM UTC 24 |
| Finished | Sep 11 01:04:52 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553186596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.1553186596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/67.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_init_fail.2275211953 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 119270228 ps |
| CPU time | 3.44 seconds |
| Started | Sep 11 01:04:38 PM UTC 24 |
| Finished | Sep 11 01:04:42 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275211953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.2275211953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/68.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_parallel_lc_esc.478260387 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 206332533 ps |
| CPU time | 4 seconds |
| Started | Sep 11 01:04:38 PM UTC 24 |
| Finished | Sep 11 01:04:43 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478260387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.478260387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/68.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_init_fail.349040862 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 483729284 ps |
| CPU time | 5.46 seconds |
| Started | Sep 11 01:04:39 PM UTC 24 |
| Finished | Sep 11 01:04:45 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349040862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.349040862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/69.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_parallel_lc_esc.2921906564 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 509587498 ps |
| CPU time | 16.17 seconds |
| Started | Sep 11 01:04:39 PM UTC 24 |
| Finished | Sep 11 01:04:56 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921906564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.2921906564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/69.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.4018151803 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 5218857997 ps |
| CPU time | 96.06 seconds |
| Started | Sep 11 01:04:39 PM UTC 24 |
| Finished | Sep 11 01:06:17 PM UTC 24 |
| Peak memory | 267876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4018151803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 69.otp_ctrl_stress_all_with_rand_reset.4018151803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/69.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_alert_test.1413926024 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 953262763 ps |
| CPU time | 2.6 seconds |
| Started | Sep 11 12:58:37 PM UTC 24 |
| Finished | Sep 11 12:58:40 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413926024 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.1413926024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_background_chks.2434490586 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 4778450733 ps |
| CPU time | 25.87 seconds |
| Started | Sep 11 12:58:24 PM UTC 24 |
| Finished | Sep 11 12:58:52 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434490586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.2434490586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_check_fail.1317838265 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 3246415174 ps |
| CPU time | 25.75 seconds |
| Started | Sep 11 12:58:31 PM UTC 24 |
| Finished | Sep 11 12:58:58 PM UTC 24 |
| Peak memory | 257516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317838265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.1317838265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_errs.2659705391 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 763129821 ps |
| CPU time | 23.78 seconds |
| Started | Sep 11 12:58:31 PM UTC 24 |
| Finished | Sep 11 12:58:56 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659705391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.2659705391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_lock.1734998565 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 1312096159 ps |
| CPU time | 23.94 seconds |
| Started | Sep 11 12:58:29 PM UTC 24 |
| Finished | Sep 11 12:58:54 PM UTC 24 |
| Peak memory | 251568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734998565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.1734998565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_key_req.1308439380 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 319467910 ps |
| CPU time | 9.67 seconds |
| Started | Sep 11 12:58:33 PM UTC 24 |
| Finished | Sep 11 12:58:44 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308439380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.1308439380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_esc.1506565220 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1596498518 ps |
| CPU time | 5.97 seconds |
| Started | Sep 11 12:58:28 PM UTC 24 |
| Finished | Sep 11 12:58:35 PM UTC 24 |
| Peak memory | 250864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506565220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.1506565220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_req.1373257030 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 353664199 ps |
| CPU time | 12.92 seconds |
| Started | Sep 11 12:58:28 PM UTC 24 |
| Finished | Sep 11 12:58:42 PM UTC 24 |
| Peak memory | 256676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373257030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.1373257030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_regwen.1616710564 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 3227320554 ps |
| CPU time | 8.25 seconds |
| Started | Sep 11 12:58:33 PM UTC 24 |
| Finished | Sep 11 12:58:42 PM UTC 24 |
| Peak memory | 251336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616710564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.1616710564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_smoke.510013016 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 196005612 ps |
| CPU time | 6.31 seconds |
| Started | Sep 11 12:58:23 PM UTC 24 |
| Finished | Sep 11 12:58:31 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510013016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.510013016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.1958116346 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 51068014015 ps |
| CPU time | 86.32 seconds |
| Started | Sep 11 12:58:33 PM UTC 24 |
| Finished | Sep 11 01:00:02 PM UTC 24 |
| Peak memory | 270224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1958116346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.otp_ctrl_stress_all_with_rand_reset.1958116346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_test_access.1379155175 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 3002163160 ps |
| CPU time | 29.56 seconds |
| Started | Sep 11 12:58:33 PM UTC 24 |
| Finished | Sep 11 12:59:04 PM UTC 24 |
| Peak memory | 251368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379155175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.1379155175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/7.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_init_fail.411184561 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2245136485 ps |
| CPU time | 5.7 seconds |
| Started | Sep 11 01:04:39 PM UTC 24 |
| Finished | Sep 11 01:04:46 PM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411184561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.411184561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/70.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_parallel_lc_esc.2724626231 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 148581625 ps |
| CPU time | 4.49 seconds |
| Started | Sep 11 01:04:39 PM UTC 24 |
| Finished | Sep 11 01:04:45 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724626231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.2724626231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/70.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_init_fail.1831599291 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 156077764 ps |
| CPU time | 4.75 seconds |
| Started | Sep 11 01:04:39 PM UTC 24 |
| Finished | Sep 11 01:04:45 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831599291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.1831599291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/71.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_parallel_lc_esc.1068004740 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 144267271 ps |
| CPU time | 3.35 seconds |
| Started | Sep 11 01:04:39 PM UTC 24 |
| Finished | Sep 11 01:04:43 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068004740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.1068004740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/71.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_init_fail.3469505682 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 1746440278 ps |
| CPU time | 6.14 seconds |
| Started | Sep 11 01:04:39 PM UTC 24 |
| Finished | Sep 11 01:04:46 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469505682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.3469505682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/72.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_parallel_lc_esc.1625000220 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 476039399 ps |
| CPU time | 4.47 seconds |
| Started | Sep 11 01:04:39 PM UTC 24 |
| Finished | Sep 11 01:04:45 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625000220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.1625000220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/72.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_init_fail.1175732519 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 278465880 ps |
| CPU time | 5.15 seconds |
| Started | Sep 11 01:04:39 PM UTC 24 |
| Finished | Sep 11 01:04:45 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175732519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.1175732519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/73.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_parallel_lc_esc.803546195 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 467237163 ps |
| CPU time | 12.1 seconds |
| Started | Sep 11 01:04:39 PM UTC 24 |
| Finished | Sep 11 01:04:53 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803546195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.803546195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/73.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.1708707155 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 18756879185 ps |
| CPU time | 70.89 seconds |
| Started | Sep 11 01:04:39 PM UTC 24 |
| Finished | Sep 11 01:05:52 PM UTC 24 |
| Peak memory | 267828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1708707155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 73.otp_ctrl_stress_all_with_rand_reset.1708707155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_init_fail.1331919449 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 195271352 ps |
| CPU time | 4.75 seconds |
| Started | Sep 11 01:04:39 PM UTC 24 |
| Finished | Sep 11 01:04:45 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331919449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.1331919449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/74.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_parallel_lc_esc.1298233541 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 124611985 ps |
| CPU time | 2.4 seconds |
| Started | Sep 11 01:04:39 PM UTC 24 |
| Finished | Sep 11 01:04:43 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298233541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.1298233541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/74.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_init_fail.3250071344 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 284319472 ps |
| CPU time | 4.51 seconds |
| Started | Sep 11 01:04:42 PM UTC 24 |
| Finished | Sep 11 01:04:48 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250071344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.3250071344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/75.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_parallel_lc_esc.579515157 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 562127608 ps |
| CPU time | 7.67 seconds |
| Started | Sep 11 01:04:42 PM UTC 24 |
| Finished | Sep 11 01:04:51 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579515157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.579515157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/75.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_init_fail.1747157612 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 113131056 ps |
| CPU time | 4.68 seconds |
| Started | Sep 11 01:04:43 PM UTC 24 |
| Finished | Sep 11 01:04:48 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747157612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.1747157612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/76.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_parallel_lc_esc.1470256553 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 385402818 ps |
| CPU time | 21.24 seconds |
| Started | Sep 11 01:04:43 PM UTC 24 |
| Finished | Sep 11 01:05:05 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470256553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.1470256553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/76.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_init_fail.2189706828 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 1787074828 ps |
| CPU time | 4.65 seconds |
| Started | Sep 11 01:04:46 PM UTC 24 |
| Finished | Sep 11 01:04:52 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189706828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.2189706828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/77.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_parallel_lc_esc.3589140543 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 500814232 ps |
| CPU time | 4.75 seconds |
| Started | Sep 11 01:04:46 PM UTC 24 |
| Finished | Sep 11 01:04:52 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589140543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.3589140543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/77.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_init_fail.37780276 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 342561410 ps |
| CPU time | 4.47 seconds |
| Started | Sep 11 01:04:46 PM UTC 24 |
| Finished | Sep 11 01:04:52 PM UTC 24 |
| Peak memory | 253268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37780276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.37780276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/78.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.4024931584 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 50535268463 ps |
| CPU time | 124.04 seconds |
| Started | Sep 11 01:04:46 PM UTC 24 |
| Finished | Sep 11 01:06:53 PM UTC 24 |
| Peak memory | 273932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4024931584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 78.otp_ctrl_stress_all_with_rand_reset.4024931584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/78.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_init_fail.2754024315 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 159388633 ps |
| CPU time | 3.87 seconds |
| Started | Sep 11 01:04:46 PM UTC 24 |
| Finished | Sep 11 01:04:51 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754024315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.2754024315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/79.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_parallel_lc_esc.1980345424 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 6535920191 ps |
| CPU time | 11.94 seconds |
| Started | Sep 11 01:04:46 PM UTC 24 |
| Finished | Sep 11 01:05:00 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980345424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.1980345424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/79.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_alert_test.1836511747 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 316630822 ps |
| CPU time | 2.96 seconds |
| Started | Sep 11 12:58:45 PM UTC 24 |
| Finished | Sep 11 12:58:50 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836511747 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.1836511747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_background_chks.604018729 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 3013315669 ps |
| CPU time | 27.26 seconds |
| Started | Sep 11 12:58:37 PM UTC 24 |
| Finished | Sep 11 12:59:05 PM UTC 24 |
| Peak memory | 253472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604018729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.604018729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_check_fail.644356197 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 382939855 ps |
| CPU time | 10.04 seconds |
| Started | Sep 11 12:58:40 PM UTC 24 |
| Finished | Sep 11 12:58:52 PM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644356197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.644356197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_errs.517575900 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 13650367322 ps |
| CPU time | 42.7 seconds |
| Started | Sep 11 12:58:40 PM UTC 24 |
| Finished | Sep 11 12:59:25 PM UTC 24 |
| Peak memory | 255476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517575900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.517575900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_lock.3413980667 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 527612732 ps |
| CPU time | 8.54 seconds |
| Started | Sep 11 12:58:40 PM UTC 24 |
| Finished | Sep 11 12:58:50 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413980667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.3413980667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_macro_errs.3028277907 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 2954251046 ps |
| CPU time | 28.66 seconds |
| Started | Sep 11 12:58:42 PM UTC 24 |
| Finished | Sep 11 12:59:12 PM UTC 24 |
| Peak memory | 251628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028277907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.3028277907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_key_req.2314735239 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1447519690 ps |
| CPU time | 26.82 seconds |
| Started | Sep 11 12:58:42 PM UTC 24 |
| Finished | Sep 11 12:59:11 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314735239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.2314735239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_esc.2175184263 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1174475919 ps |
| CPU time | 20.95 seconds |
| Started | Sep 11 12:58:40 PM UTC 24 |
| Finished | Sep 11 12:59:02 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175184263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.2175184263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_req.355581099 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 13008608677 ps |
| CPU time | 36.7 seconds |
| Started | Sep 11 12:58:40 PM UTC 24 |
| Finished | Sep 11 12:59:18 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355581099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.355581099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_regwen.87532980 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1938260360 ps |
| CPU time | 9.61 seconds |
| Started | Sep 11 12:58:42 PM UTC 24 |
| Finished | Sep 11 12:58:53 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87532980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ot p_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.87532980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_smoke.242029475 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 3442188183 ps |
| CPU time | 8.95 seconds |
| Started | Sep 11 12:58:37 PM UTC 24 |
| Finished | Sep 11 12:58:47 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242029475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.242029475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all.52770548 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 8928485435 ps |
| CPU time | 74.84 seconds |
| Started | Sep 11 12:58:45 PM UTC 24 |
| Finished | Sep 11 01:00:02 PM UTC 24 |
| Peak memory | 259620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52770548 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.52770548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_test_access.2795139102 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2275710708 ps |
| CPU time | 29.93 seconds |
| Started | Sep 11 12:58:45 PM UTC 24 |
| Finished | Sep 11 12:59:17 PM UTC 24 |
| Peak memory | 257516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795139102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.2795139102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/8.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_init_fail.1029859653 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 165073314 ps |
| CPU time | 3.88 seconds |
| Started | Sep 11 01:04:51 PM UTC 24 |
| Finished | Sep 11 01:04:56 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029859653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.1029859653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/80.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_parallel_lc_esc.2175667784 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 139294242 ps |
| CPU time | 4.96 seconds |
| Started | Sep 11 01:04:51 PM UTC 24 |
| Finished | Sep 11 01:04:57 PM UTC 24 |
| Peak memory | 253460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175667784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.2175667784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/80.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_init_fail.185640954 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 2435115729 ps |
| CPU time | 7.12 seconds |
| Started | Sep 11 01:04:51 PM UTC 24 |
| Finished | Sep 11 01:05:00 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185640954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.185640954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/81.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_parallel_lc_esc.837569676 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 276457742 ps |
| CPU time | 7.75 seconds |
| Started | Sep 11 01:04:51 PM UTC 24 |
| Finished | Sep 11 01:05:00 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837569676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.837569676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/81.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.1985998222 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 7483505667 ps |
| CPU time | 113.92 seconds |
| Started | Sep 11 01:04:52 PM UTC 24 |
| Finished | Sep 11 01:06:48 PM UTC 24 |
| Peak memory | 267880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1985998222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 81.otp_ctrl_stress_all_with_rand_reset.1985998222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_init_fail.737206401 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 295542519 ps |
| CPU time | 3.22 seconds |
| Started | Sep 11 01:04:52 PM UTC 24 |
| Finished | Sep 11 01:04:56 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737206401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.737206401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/82.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_parallel_lc_esc.286644877 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 172417985 ps |
| CPU time | 8.26 seconds |
| Started | Sep 11 01:04:56 PM UTC 24 |
| Finished | Sep 11 01:05:05 PM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286644877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.286644877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/82.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_init_fail.3424541518 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 2584727578 ps |
| CPU time | 7.44 seconds |
| Started | Sep 11 01:04:56 PM UTC 24 |
| Finished | Sep 11 01:05:04 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424541518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.3424541518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/83.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_parallel_lc_esc.1907608010 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 160696181 ps |
| CPU time | 9.23 seconds |
| Started | Sep 11 01:04:56 PM UTC 24 |
| Finished | Sep 11 01:05:06 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907608010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.1907608010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/83.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_parallel_lc_esc.2372851969 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 1865277174 ps |
| CPU time | 17.7 seconds |
| Started | Sep 11 01:04:56 PM UTC 24 |
| Finished | Sep 11 01:05:15 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372851969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.2372851969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/84.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_init_fail.2850150120 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 256939378 ps |
| CPU time | 4.56 seconds |
| Started | Sep 11 01:04:56 PM UTC 24 |
| Finished | Sep 11 01:05:02 PM UTC 24 |
| Peak memory | 253268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850150120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.2850150120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/85.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_parallel_lc_esc.707354086 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1404905784 ps |
| CPU time | 11.14 seconds |
| Started | Sep 11 01:05:03 PM UTC 24 |
| Finished | Sep 11 01:05:16 PM UTC 24 |
| Peak memory | 251432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707354086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.707354086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_init_fail.3341274572 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 346530467 ps |
| CPU time | 5.26 seconds |
| Started | Sep 11 01:05:04 PM UTC 24 |
| Finished | Sep 11 01:05:10 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341274572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.3341274572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/86.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_parallel_lc_esc.3492777372 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 730175525 ps |
| CPU time | 10.71 seconds |
| Started | Sep 11 01:05:04 PM UTC 24 |
| Finished | Sep 11 01:05:16 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492777372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.3492777372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/86.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_init_fail.1293875570 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 256850977 ps |
| CPU time | 3.56 seconds |
| Started | Sep 11 01:05:04 PM UTC 24 |
| Finished | Sep 11 01:05:09 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293875570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.1293875570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/87.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_parallel_lc_esc.770363442 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 415945977 ps |
| CPU time | 9.37 seconds |
| Started | Sep 11 01:05:04 PM UTC 24 |
| Finished | Sep 11 01:05:15 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770363442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.770363442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/87.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.29835083 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 4205497284 ps |
| CPU time | 69.25 seconds |
| Started | Sep 11 01:05:04 PM UTC 24 |
| Finished | Sep 11 01:06:15 PM UTC 24 |
| Peak memory | 257908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=29835083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.29835083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/87.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_init_fail.3846616953 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 666043551 ps |
| CPU time | 4.34 seconds |
| Started | Sep 11 01:05:04 PM UTC 24 |
| Finished | Sep 11 01:05:10 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846616953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.3846616953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/88.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_parallel_lc_esc.1077937463 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 2158199202 ps |
| CPU time | 8.04 seconds |
| Started | Sep 11 01:05:09 PM UTC 24 |
| Finished | Sep 11 01:05:19 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077937463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.1077937463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/88.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.2637498075 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 7711580689 ps |
| CPU time | 87.16 seconds |
| Started | Sep 11 01:05:10 PM UTC 24 |
| Finished | Sep 11 01:06:39 PM UTC 24 |
| Peak memory | 274000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2637498075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 88.otp_ctrl_stress_all_with_rand_reset.2637498075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/88.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_init_fail.1875383254 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 118755963 ps |
| CPU time | 3.77 seconds |
| Started | Sep 11 01:05:10 PM UTC 24 |
| Finished | Sep 11 01:05:14 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875383254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.1875383254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/89.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_parallel_lc_esc.1982292102 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 361684703 ps |
| CPU time | 4.23 seconds |
| Started | Sep 11 01:05:10 PM UTC 24 |
| Finished | Sep 11 01:05:15 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982292102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.1982292102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/89.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_alert_test.4272435078 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 87466356 ps |
| CPU time | 3.28 seconds |
| Started | Sep 11 12:58:56 PM UTC 24 |
| Finished | Sep 11 12:59:00 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272435078 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.4272435078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_background_chks.590551658 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 5069286323 ps |
| CPU time | 34.76 seconds |
| Started | Sep 11 12:58:47 PM UTC 24 |
| Finished | Sep 11 12:59:23 PM UTC 24 |
| Peak memory | 253112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590551658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.590551658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_errs.1045286702 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 384756609 ps |
| CPU time | 14.28 seconds |
| Started | Sep 11 12:58:50 PM UTC 24 |
| Finished | Sep 11 12:59:05 PM UTC 24 |
| Peak memory | 251104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045286702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.1045286702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_lock.1417601266 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 950487114 ps |
| CPU time | 22.65 seconds |
| Started | Sep 11 12:58:50 PM UTC 24 |
| Finished | Sep 11 12:59:14 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417601266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.1417601266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_init_fail.2168409830 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 406486688 ps |
| CPU time | 4.63 seconds |
| Started | Sep 11 12:58:45 PM UTC 24 |
| Finished | Sep 11 12:58:51 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168409830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.2168409830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_key_req.3486936328 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 792023542 ps |
| CPU time | 20.02 seconds |
| Started | Sep 11 12:58:52 PM UTC 24 |
| Finished | Sep 11 12:59:13 PM UTC 24 |
| Peak memory | 253360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486936328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.3486936328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_esc.3190517750 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 287127124 ps |
| CPU time | 8.44 seconds |
| Started | Sep 11 12:58:47 PM UTC 24 |
| Finished | Sep 11 12:58:57 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190517750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.3190517750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_req.285270207 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 1806387455 ps |
| CPU time | 15.77 seconds |
| Started | Sep 11 12:58:47 PM UTC 24 |
| Finished | Sep 11 12:59:04 PM UTC 24 |
| Peak memory | 257424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285270207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.285270207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_regwen.2410163871 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 334074917 ps |
| CPU time | 6.66 seconds |
| Started | Sep 11 12:58:53 PM UTC 24 |
| Finished | Sep 11 12:59:01 PM UTC 24 |
| Peak memory | 257208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410163871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.2410163871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_smoke.3818125989 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 258347027 ps |
| CPU time | 3.51 seconds |
| Started | Sep 11 12:58:45 PM UTC 24 |
| Finished | Sep 11 12:58:50 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818125989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.3818125989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all.3249619079 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 67705094308 ps |
| CPU time | 163.35 seconds |
| Started | Sep 11 12:58:54 PM UTC 24 |
| Finished | Sep 11 01:01:40 PM UTC 24 |
| Peak memory | 255460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249619079 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.3249619079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_test_access.3201679308 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 762859722 ps |
| CPU time | 15.68 seconds |
| Started | Sep 11 12:58:53 PM UTC 24 |
| Finished | Sep 11 12:59:10 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201679308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.3201679308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/9.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_init_fail.3556090920 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 559179771 ps |
| CPU time | 4.52 seconds |
| Started | Sep 11 01:05:10 PM UTC 24 |
| Finished | Sep 11 01:05:15 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556090920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.3556090920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/90.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_parallel_lc_esc.2522438344 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 404114206 ps |
| CPU time | 6.17 seconds |
| Started | Sep 11 01:05:10 PM UTC 24 |
| Finished | Sep 11 01:05:17 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522438344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.2522438344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/90.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.2532234490 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 11452602348 ps |
| CPU time | 189.53 seconds |
| Started | Sep 11 01:05:10 PM UTC 24 |
| Finished | Sep 11 01:08:22 PM UTC 24 |
| Peak memory | 273772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2532234490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 90.otp_ctrl_stress_all_with_rand_reset.2532234490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/90.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_init_fail.2979042851 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 317679749 ps |
| CPU time | 5.92 seconds |
| Started | Sep 11 01:05:10 PM UTC 24 |
| Finished | Sep 11 01:05:17 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979042851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.2979042851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/91.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_parallel_lc_esc.1827578245 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 151054031 ps |
| CPU time | 5.97 seconds |
| Started | Sep 11 01:05:10 PM UTC 24 |
| Finished | Sep 11 01:05:17 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827578245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.1827578245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/91.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_init_fail.2749387826 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2229624026 ps |
| CPU time | 5.48 seconds |
| Started | Sep 11 01:05:10 PM UTC 24 |
| Finished | Sep 11 01:05:17 PM UTC 24 |
| Peak memory | 250660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749387826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.2749387826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/92.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_parallel_lc_esc.63457878 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 871650107 ps |
| CPU time | 6.41 seconds |
| Started | Sep 11 01:05:10 PM UTC 24 |
| Finished | Sep 11 01:05:18 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63457878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.63457878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/92.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_init_fail.3270849833 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 139809381 ps |
| CPU time | 5.31 seconds |
| Started | Sep 11 01:05:10 PM UTC 24 |
| Finished | Sep 11 01:05:17 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270849833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.3270849833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/93.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_parallel_lc_esc.1890529505 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 3079645001 ps |
| CPU time | 10.74 seconds |
| Started | Sep 11 01:05:13 PM UTC 24 |
| Finished | Sep 11 01:05:25 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890529505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.1890529505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/93.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_init_fail.1136668931 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 149024657 ps |
| CPU time | 4.94 seconds |
| Started | Sep 11 01:05:13 PM UTC 24 |
| Finished | Sep 11 01:05:19 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136668931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.1136668931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/94.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_parallel_lc_esc.2769044762 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 315921978 ps |
| CPU time | 4.05 seconds |
| Started | Sep 11 01:05:13 PM UTC 24 |
| Finished | Sep 11 01:05:18 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769044762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.2769044762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/94.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.1976080017 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 1743286198 ps |
| CPU time | 44.92 seconds |
| Started | Sep 11 01:05:18 PM UTC 24 |
| Finished | Sep 11 01:06:05 PM UTC 24 |
| Peak memory | 257548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1976080017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 94.otp_ctrl_stress_all_with_rand_reset.1976080017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_init_fail.1493969202 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 401249384 ps |
| CPU time | 4.36 seconds |
| Started | Sep 11 01:05:18 PM UTC 24 |
| Finished | Sep 11 01:05:24 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493969202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.1493969202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/95.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_parallel_lc_esc.2610688313 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 788092588 ps |
| CPU time | 11.02 seconds |
| Started | Sep 11 01:05:18 PM UTC 24 |
| Finished | Sep 11 01:05:31 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610688313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.2610688313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_init_fail.1823080631 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 159639105 ps |
| CPU time | 3.35 seconds |
| Started | Sep 11 01:05:19 PM UTC 24 |
| Finished | Sep 11 01:05:23 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823080631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.1823080631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/96.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_parallel_lc_esc.1500846978 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 113885313 ps |
| CPU time | 4.49 seconds |
| Started | Sep 11 01:05:19 PM UTC 24 |
| Finished | Sep 11 01:05:24 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500846978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.1500846978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/96.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.3503330233 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 2257035568 ps |
| CPU time | 78.24 seconds |
| Started | Sep 11 01:05:19 PM UTC 24 |
| Finished | Sep 11 01:06:39 PM UTC 24 |
| Peak memory | 267944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3503330233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 96.otp_ctrl_stress_all_with_rand_reset.3503330233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/96.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_init_fail.1123059298 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 173760247 ps |
| CPU time | 4.26 seconds |
| Started | Sep 11 01:05:19 PM UTC 24 |
| Finished | Sep 11 01:05:24 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123059298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.1123059298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/97.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_parallel_lc_esc.3423494759 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 608657923 ps |
| CPU time | 7.64 seconds |
| Started | Sep 11 01:05:19 PM UTC 24 |
| Finished | Sep 11 01:05:28 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423494759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.3423494759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/97.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.4203055345 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 4639223589 ps |
| CPU time | 55.47 seconds |
| Started | Sep 11 01:05:19 PM UTC 24 |
| Finished | Sep 11 01:06:16 PM UTC 24 |
| Peak memory | 257932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4203055345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 97.otp_ctrl_stress_all_with_rand_reset.4203055345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/97.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_init_fail.169086154 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 2050575058 ps |
| CPU time | 6.47 seconds |
| Started | Sep 11 01:05:19 PM UTC 24 |
| Finished | Sep 11 01:05:27 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169086154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.169086154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/98.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_parallel_lc_esc.3898443218 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 286809257 ps |
| CPU time | 3.16 seconds |
| Started | Sep 11 01:05:19 PM UTC 24 |
| Finished | Sep 11 01:05:23 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898443218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.3898443218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/98.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_init_fail.1670769644 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 174081999 ps |
| CPU time | 5.64 seconds |
| Started | Sep 11 01:05:19 PM UTC 24 |
| Finished | Sep 11 01:05:26 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670769644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.1670769644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/99.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_parallel_lc_esc.1628841034 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 3822400913 ps |
| CPU time | 22.43 seconds |
| Started | Sep 11 01:05:19 PM UTC 24 |
| Finished | Sep 11 01:05:43 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628841034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.1628841034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/99.otp_ctrl_parallel_lc_esc/latest |
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