SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 41406 | 1 | T4 | 136 | T92 | 58 | T164 | 141 | ||||
access_err | 51035 | 1 | T5 | 26 | T6 | 5 | T8 | 56 | ||||
write_blank_err | 359 | 1 | T8 | 4 | T9 | 6 | T219 | 1 | ||||
ecc_uncorr_err | 52882 | 1 | T8 | 379 | T117 | 6 | T9 | 384 | ||||
ecc_corr_err | 1539 | 1 | T117 | 2 | T9 | 1 | T164 | 7 | ||||
no_err | 70333 | 1 | T3 | 56 | T4 | 1 | T5 | 43 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 549 | 1 | T8 | 13 | T9 | 6 | T10 | 3 | ||||
secret2 | 19373 | 1 | T3 | 1 | T5 | 10 | T6 | 1 | ||||
secret1 | 21996 | 1 | T3 | 5 | T4 | 137 | T5 | 8 | ||||
secret0 | 27589 | 1 | T3 | 8 | T5 | 3 | T6 | 2 | ||||
hw_cfg1 | 29775 | 1 | T3 | 16 | T5 | 4 | T6 | 1 | ||||
hw_cfg0 | 20030 | 1 | T5 | 9 | T90 | 5 | T89 | 7 | ||||
rot_creator_auth_state | 18230 | 1 | T3 | 4 | T5 | 3 | T8 | 33 | ||||
rot_creator_auth_codesign | 16969 | 1 | T3 | 9 | T5 | 11 | T12 | 3 | ||||
owner_sw_cfg | 16489 | 1 | T3 | 2 | T5 | 2 | T8 | 17 | ||||
creator_sw_cfg | 15997 | 1 | T3 | 5 | T5 | 11 | T8 | 6 | ||||
vendor_test | 30557 | 1 | T3 | 6 | T5 | 8 | T6 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 2869 | 1 | T304 | 267 | T317 | 103 | T364 | 464 | ||||
fsm_err | secret1 | 2675 | 1 | T4 | 136 | T280 | 439 | T224 | 264 | ||||
fsm_err | secret0 | 2730 | 1 | T275 | 177 | T276 | 19 | T212 | 19 | ||||
fsm_err | hw_cfg1 | 1682 | 1 | T172 | 542 | T150 | 54 | T373 | 166 | ||||
fsm_err | hw_cfg0 | 2604 | 1 | T251 | 194 | T274 | 132 | T157 | 22 | ||||
fsm_err | rot_creator_auth_state | 3814 | 1 | T164 | 68 | T157 | 27 | T281 | 275 | ||||
fsm_err | rot_creator_auth_codesign | 3103 | 1 | T167 | 33 | T173 | 426 | T199 | 22 | ||||
fsm_err | owner_sw_cfg | 2662 | 1 | T158 | 128 | T151 | 71 | T374 | 309 | ||||
fsm_err | creator_sw_cfg | 3060 | 1 | T13 | 334 | T149 | 7 | T159 | 72 | ||||
fsm_err | vendor_test | 16207 | 1 | T92 | 58 | T164 | 73 | T148 | 23 | ||||
access_err | life_cycle | 549 | 1 | T8 | 13 | T9 | 6 | T10 | 3 | ||||
access_err | secret2 | 8608 | 1 | T5 | 10 | T6 | 1 | T90 | 1 | ||||
access_err | secret1 | 6014 | 1 | T6 | 1 | T8 | 1 | T31 | 12 | ||||
access_err | secret0 | 4555 | 1 | T6 | 2 | T31 | 3 | T16 | 4 | ||||
access_err | hw_cfg1 | 1133 | 1 | T6 | 1 | T31 | 4 | T16 | 3 | ||||
access_err | hw_cfg0 | 2107 | 1 | T18 | 2 | T105 | 2 | T118 | 2 | ||||
access_err | rot_creator_auth_state | 4353 | 1 | T5 | 2 | T8 | 23 | T31 | 1 | ||||
access_err | rot_creator_auth_codesign | 6260 | 1 | T5 | 5 | T16 | 23 | T18 | 4 | ||||
access_err | owner_sw_cfg | 5653 | 1 | T8 | 12 | T31 | 11 | T16 | 23 | ||||
access_err | creator_sw_cfg | 5900 | 1 | T5 | 6 | T8 | 5 | T31 | 2 | ||||
access_err | vendor_test | 5903 | 1 | T5 | 3 | T8 | 2 | T31 | 2 | ||||
write_blank_err | secret2 | 8 | 1 | T10 | 1 | T375 | 1 | T376 | 1 | ||||
write_blank_err | secret1 | 15 | 1 | T246 | 1 | T248 | 1 | T247 | 1 | ||||
write_blank_err | secret0 | 35 | 1 | T8 | 1 | T9 | 1 | T219 | 1 | ||||
write_blank_err | hw_cfg1 | 58 | 1 | T9 | 1 | T112 | 1 | T249 | 1 | ||||
write_blank_err | hw_cfg0 | 14 | 1 | T260 | 1 | T377 | 1 | T378 | 1 | ||||
write_blank_err | rot_creator_auth_state | 138 | 1 | T8 | 3 | T9 | 3 | T10 | 1 | ||||
write_blank_err | rot_creator_auth_codesign | 39 | 1 | T9 | 1 | T10 | 1 | T249 | 2 | ||||
write_blank_err | owner_sw_cfg | 9 | 1 | T247 | 1 | T172 | 1 | T243 | 2 | ||||
write_blank_err | creator_sw_cfg | 16 | 1 | T10 | 1 | T20 | 1 | T243 | 1 | ||||
write_blank_err | vendor_test | 27 | 1 | T248 | 1 | T247 | 1 | T260 | 1 | ||||
ecc_uncorr_err | secret2 | 3404 | 1 | T164 | 125 | T10 | 192 | T167 | 35 | ||||
ecc_uncorr_err | secret1 | 6854 | 1 | T164 | 76 | T148 | 39 | T167 | 34 | ||||
ecc_uncorr_err | secret0 | 14164 | 1 | T8 | 379 | T9 | 384 | T219 | 486 | ||||
ecc_uncorr_err | hw_cfg1 | 18226 | 1 | T117 | 2 | T164 | 139 | T112 | 478 | ||||
ecc_uncorr_err | hw_cfg0 | 5449 | 1 | T164 | 74 | T260 | 289 | T165 | 49 | ||||
ecc_uncorr_err | rot_creator_auth_state | 2832 | 1 | T117 | 2 | T165 | 57 | T158 | 60 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 596 | 1 | T370 | 119 | T158 | 59 | T150 | 57 | ||||
ecc_uncorr_err | owner_sw_cfg | 701 | 1 | T167 | 36 | T204 | 129 | T159 | 75 | ||||
ecc_uncorr_err | creator_sw_cfg | 656 | 1 | T117 | 2 | T157 | 25 | T204 | 42 | ||||
ecc_corr_err | secret2 | 63 | 1 | T164 | 1 | T99 | 3 | T33 | 2 | ||||
ecc_corr_err | secret1 | 139 | 1 | T117 | 1 | T99 | 2 | T33 | 1 | ||||
ecc_corr_err | secret0 | 138 | 1 | T164 | 1 | T99 | 2 | T33 | 3 | ||||
ecc_corr_err | hw_cfg1 | 281 | 1 | T9 | 1 | T45 | 1 | T99 | 12 | ||||
ecc_corr_err | hw_cfg0 | 344 | 1 | T164 | 2 | T148 | 1 | T45 | 1 | ||||
ecc_corr_err | rot_creator_auth_state | 136 | 1 | T117 | 1 | T148 | 1 | T45 | 3 | ||||
ecc_corr_err | rot_creator_auth_codesign | 166 | 1 | T164 | 2 | T45 | 2 | T99 | 5 | ||||
ecc_corr_err | owner_sw_cfg | 151 | 1 | T45 | 1 | T99 | 3 | T33 | 3 | ||||
ecc_corr_err | creator_sw_cfg | 121 | 1 | T164 | 1 | T45 | 1 | T99 | 3 | ||||
no_err | secret2 | 4421 | 1 | T3 | 1 | T12 | 2 | T8 | 6 | ||||
no_err | secret1 | 6299 | 1 | T3 | 5 | T4 | 1 | T5 | 8 | ||||
no_err | secret0 | 5967 | 1 | T3 | 8 | T5 | 3 | T8 | 6 | ||||
no_err | hw_cfg1 | 8395 | 1 | T3 | 16 | T5 | 4 | T8 | 6 | ||||
no_err | hw_cfg0 | 9512 | 1 | T5 | 9 | T90 | 5 | T89 | 7 | ||||
no_err | rot_creator_auth_state | 6957 | 1 | T3 | 4 | T5 | 1 | T8 | 7 | ||||
no_err | rot_creator_auth_codesign | 6805 | 1 | T3 | 9 | T5 | 6 | T12 | 3 | ||||
no_err | owner_sw_cfg | 7313 | 1 | T3 | 2 | T5 | 2 | T8 | 5 | ||||
no_err | creator_sw_cfg | 6244 | 1 | T3 | 5 | T5 | 5 | T8 | 1 | ||||
no_err | vendor_test | 8420 | 1 | T3 | 6 | T5 | 5 | T6 | 1 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |