Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5039310

1

T1

13

T2

1257

T3

698

full_word

2419999

1

T1

6

T2

638

T3

161

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7459009	1			T1	19		T2	1895		T3	859
auto[TlIntgErrCmd]	99	1			T285	1		T286	6		T287	2
auto[TlIntgErrData]	95	1			T285	3		T286	1		T287	4
auto[TlIntgErrBoth]	106	1			T285	6		T286	3		T287	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5688993

1

T1

4

T2

1724

T3

680

auto[1]

1770316

1

T1

15

T2

171

T3

179

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3800664	1			T1	3		T2	1177		T3	608
auto[TlIntgErrNone]	partial	auto[1]	1238374	1			T1	10		T2	80		T3	90
auto[TlIntgErrNone]	full_word	auto[0]	1888196	1			T1	1		T2	547		T3	72
auto[TlIntgErrNone]	full_word	auto[1]	531775	1			T1	5		T2	91		T3	89
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T285	1		T286	1		T287	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T286	4		T287	1		T298	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T286	1		T398	1		T399	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T299	1		T395	1		T397	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T286	1		T287	3		T298	4
auto[TlIntgErrData]	partial	auto[1]	39	1			T285	2		T287	1		T298	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T298	1		T394	2		T400	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T285	1		T298	1		T401	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T285	3		T286	2		T287	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T285	3		T286	1		T287	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T287	1		T394	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T397	1		T402	1		T403	2