| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| mubi4_cov_of_tb.dut.u_lc_check_byp_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
| mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
| mubi4_cov_of_tb.dut.u_lc_dft_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
| mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
| mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 6 | 0 | 6 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 6 | 0 | 6 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 6 | 0 | 6 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 6 | 0 | 6 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 6 | 0 | 6 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 6 | 0 | 6 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 583 | 1 | T4 | 1 | T68 | 1 | T35 | 1 | ||||
| others[1] | 561 | 1 | T97 | 1 | T68 | 1 | T55 | 1 | ||||
| others[2] | 570 | 1 | T1 | 1 | T44 | 1 | T51 | 1 | ||||
| others[3] | 947 | 1 | T2 | 1 | T3 | 1 | T12 | 1 | ||||
| false | 5423 | 1 | T2 | 1 | T3 | 1 | T4 | 8 | ||||
| true | 7382 | 1 | T2 | 1 | T3 | 2 | T4 | 15 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 6 | 0 | 6 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 210 | 1 | T98 | 1 | T106 | 1 | T159 | 1 | ||||
| others[1] | 177 | 1 | T95 | 1 | T6 | 1 | T180 | 1 | ||||
| others[2] | 202 | 1 | T4 | 2 | T9 | 1 | T124 | 1 | ||||
| others[3] | 335 | 1 | T4 | 1 | T35 | 1 | T51 | 1 | ||||
| false | 1804 | 1 | T4 | 2 | T35 | 2 | T51 | 2 | ||||
| true | 15442 | 1 | T1 | 1 | T2 | 2 | T3 | 4 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 6 | 0 | 6 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 1439 | 1 | T3 | 3 | T5 | 1 | T17 | 1 | ||||
| others[1] | 1411 | 1 | T35 | 3 | T130 | 3 | T98 | 3 | ||||
| others[2] | 1567 | 1 | T4 | 3 | T9 | 3 | T10 | 1 | ||||
| others[3] | 2502 | 1 | T2 | 2 | T3 | 2 | T4 | 3 | ||||
| false | 12322 | 1 | T1 | 1 | T2 | 1 | T4 | 13 | ||||
| true | 4209 | 1 | T11 | 1 | T17 | 1 | T18 | 1 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 6 | 0 | 6 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 29 | 1 | T413 | 1 | T179 | 1 | T174 | 1 | ||||
| others[1] | 24 | 1 | T165 | 1 | T15 | 2 | T271 | 1 | ||||
| others[2] | 19 | 1 | T148 | 1 | T260 | 1 | T174 | 1 | ||||
| others[3] | 42 | 1 | T96 | 1 | T105 | 1 | T202 | 1 | ||||
| false | 13813 | 1 | T1 | 1 | T2 | 2 | T3 | 4 | ||||
| true | 188 | 1 | T9 | 1 | T94 | 1 | T100 | 1 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 6 | 0 | 6 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 877 | 1 | T3 | 3 | T4 | 3 | T51 | 3 | ||||
| others[1] | 859 | 1 | T4 | 5 | T68 | 3 | T51 | 3 | ||||
| others[2] | 816 | 1 | T9 | 2 | T5 | 3 | T35 | 3 | ||||
| others[3] | 1469 | 1 | T2 | 1 | T4 | 3 | T12 | 3 | ||||
| false | 7280 | 1 | T1 | 1 | T2 | 2 | T4 | 10 | ||||
| true | 7213 | 1 | T3 | 2 | T9 | 3 | T10 | 1 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |