Unified Coverage Report :: Module

Line Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=32,EnDataPort=0,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Line Coverage for Module self-instances :

SCORE	LINE
87.74	92.31

tb.dut.u_edn_arb

	Line No.	Total	Covered	Percent
TOTAL		26	24	92.31
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00



61                        logic unused_req_chk;
62         1/1            assign unused_req_chk = req_chk_i;
           Tests:       T1 T2 T3 
63                      
64                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
65                      
66                        // this case is basically just a bypass
67                        if (N == 1) begin : gen_degenerate_case
68                      
69                          assign valid_o  = req_i[0];
70                          assign data_o   = data_i[0];
71                          assign gnt_o[0] = valid_o & ready_i;
72                          assign idx_o    = '0;
73                      
74                        end else begin : gen_normal_case
75                      
76                          // align to powers of 2 for simplicity
77                          // a full binary tree with N levels has 2**N + 2**N-1 nodes
78                          logic [2**(IdxW+1)-2:0]           req_tree;
79                          logic [2**(IdxW+1)-2:0]           prio_tree;
80                          logic [2**(IdxW+1)-2:0]           sel_tree;
81                          logic [2**(IdxW+1)-2:0]           mask_tree;
82                          logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree;
83                          logic [2**(IdxW+1)-2:0][DW-1:0]   data_tree;
84                          logic [N-1:0]                     prio_mask_d, prio_mask_q;
85                      
86                          for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree
87                            //
88                            // level+1   C0   C1   <- "Base1" points to the first node on "level+1",
89                            //            \  /         these nodes are the children of the nodes one level below
90                            // level       Pa      <- "Base0", points to the first node on "level",
91                            //                         these nodes are the parents of the nodes one level above
92                            //
93                            // hence we have the following indices for the Pa, C0, C1 nodes:
94                            // Pa = 2**level     - 1 + offset       = Base0 + offset
95                            // C0 = 2**(level+1) - 1 + 2*offset     = Base1 + 2*offset
96                            // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1
97                            //
98                            localparam int Base0 = (2**level)-1;
99                            localparam int Base1 = (2**(level+1))-1;
100                     
101                           for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level
102                             localparam int Pa = Base0 + offset;
103                             localparam int C0 = Base1 + 2*offset;
104                             localparam int C1 = Base1 + 2*offset + 1;
105                     
106                             // this assigns the gated interrupt source signals, their
107                             // corresponding IDs and priorities to the tree leafs
108                             if (level == IdxW) begin : gen_leafs
109                               if (offset < N) begin : gen_assign
110                                 // forward path (requests and data)
111                                 // all requests inputs are assigned to the request tree
112        2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
113                                 // we basically split the incoming request vector into two halves with the following
114                                 // priority assignment. the prio_mask_q register contains a prefix sum that has been
115                                 // computed using the last winning index, and hence masks out all requests at offsets
116                                 // lower or equal the previously granted index. hence, all higher indices are considered
117                                 // first in the arbitration tree nodes below, before considering the lower indices.
118        2/2                      assign prio_tree[Pa]     = req_i[offset] & prio_mask_q[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
119                                 // input for the index muxes (used to compute the winner index)
120                                 assign idx_tree[Pa]      = offset;
121                                 // input for the data muxes
122        0/2     ==>              assign data_tree[Pa]     = data_i[offset];
123                     
124                                 // backward path (grants and prefix sum)
125                                 // grant if selected, ready and request asserted
126        2/2                      assign gnt_o[offset]       = req_i[offset] & sel_tree[Pa] & ready_i;
           Tests:       T1 T2 T3  | T1 T2 T3 
127                                 // only update mask if there is a valid request
128        2/2                      assign prio_mask_d[offset] = (|req_i) ?
           Tests:       T1 T2 T3  | T1 T2 T3 
129                                                              mask_tree[Pa] | sel_tree[Pa] & ~ready_i :
130                                                              prio_mask_q[offset];
131                               end else begin : gen_tie_off
132                                 // forward path
133                                 assign req_tree[Pa]  = '0;
134                                 assign prio_tree[Pa] = '0;
135                                 assign idx_tree[Pa]  = '0;
136                                 assign data_tree[Pa] = '0;
137                                 logic unused_sigs;
138                                 assign unused_sigs = ^{mask_tree[Pa],
139                                                        sel_tree[Pa]};
140                               end
141                             // this creates the node assignments
142                             end else begin : gen_nodes
143                               // local helper variable
144                               logic sel;
145                     
146                               // forward path (requests and data)
147                               // each node looks at its two children, and selects the one with higher priority
148        1/1                    assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1];
           Tests:       T1 T2 T3 
149                               // propagate requests
150        1/1                    assign req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
151        1/1                    assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0];
           Tests:       T1 T2 T3 
152                               // data and index muxes
153                               // Note: these ternaries have triggered a synthesis bug in Vivado versions older
154                               // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
155        1/1                    assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
156        1/1                    assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
157                     
158                               // backward path (grants and prefix sum)
159                               // this propagates the selction index back and computes a hot one mask
160        1/1                    assign sel_tree[C0] = sel_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
161        1/1                    assign sel_tree[C1] = sel_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
162                               // this performs a prefix sum for masking the input requests in the next cycle
163        unreachable            assign mask_tree[C0] = mask_tree[Pa];
164        1/1                    assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0];
           Tests:       T1 T2 T3 
165                             end
166                           end : gen_level
167                         end : gen_tree
168                     
169                         // the results can be found at the tree root
170                         if (EnDataPort) begin : gen_data_port
171                           assign data_o      = data_tree[0];
172                         end else begin : gen_no_dataport
173                           logic [DW-1:0] unused_data;
174        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
175                           assign data_o = '1;
176                         end
177                     
178                         // This index is unused.
179                         logic unused_prio_tree;
180        1/1              assign unused_prio_tree = prio_tree[0];
           Tests:       T1 T2 T3 
181                     
182        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
183        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
184                     
185                         // the select tree computes a hot one signal that indicates which request is currently selected
186                         assign sel_tree[0] = 1'b1;
187                         // the mask tree is basically a prefix sum of the hot one select signal computed above
188                         assign mask_tree[0] = 1'b0;
189                     
190                         always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg
191        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
192        1/1                  prio_mask_q <= '0;
           Tests:       T1 T2 T3 
193                           end else begin
194        1/1                  prio_mask_q <= prio_mask_d;
           Tests:       T1 T2 T3

SCORE	LINE
97.25	98.07

tb.dut.u_otp_arb

SCORE	LINE
79.55	75.00

tb.dut.u_scrmbl_mtx

	Line No.	Total	Covered	Percent
TOTAL		207	205	99.03
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	0	0
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	0	0
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	0	0
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00



61                        logic unused_req_chk;
62         1/1            assign unused_req_chk = req_chk_i;
           Tests:       T1 T2 T3 
63                      
64                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
65                      
66                        // this case is basically just a bypass
67                        if (N == 1) begin : gen_degenerate_case
68                      
69                          assign valid_o  = req_i[0];
70                          assign data_o   = data_i[0];
71                          assign gnt_o[0] = valid_o & ready_i;
72                          assign idx_o    = '0;
73                      
74                        end else begin : gen_normal_case
75                      
76                          // align to powers of 2 for simplicity
77                          // a full binary tree with N levels has 2**N + 2**N-1 nodes
78                          logic [2**(IdxW+1)-2:0]           req_tree;
79                          logic [2**(IdxW+1)-2:0]           prio_tree;
80                          logic [2**(IdxW+1)-2:0]           sel_tree;
81                          logic [2**(IdxW+1)-2:0]           mask_tree;
82                          logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree;
83                          logic [2**(IdxW+1)-2:0][DW-1:0]   data_tree;
84                          logic [N-1:0]                     prio_mask_d, prio_mask_q;
85                      
86                          for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree
87                            //
88                            // level+1   C0   C1   <- "Base1" points to the first node on "level+1",
89                            //            \  /         these nodes are the children of the nodes one level below
90                            // level       Pa      <- "Base0", points to the first node on "level",
91                            //                         these nodes are the parents of the nodes one level above
92                            //
93                            // hence we have the following indices for the Pa, C0, C1 nodes:
94                            // Pa = 2**level     - 1 + offset       = Base0 + offset
95                            // C0 = 2**(level+1) - 1 + 2*offset     = Base1 + 2*offset
96                            // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1
97                            //
98                            localparam int Base0 = (2**level)-1;
99                            localparam int Base1 = (2**(level+1))-1;
100                     
101                           for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level
102                             localparam int Pa = Base0 + offset;
103                             localparam int C0 = Base1 + 2*offset;
104                             localparam int C1 = Base1 + 2*offset + 1;
105                     
106                             // this assigns the gated interrupt source signals, their
107                             // corresponding IDs and priorities to the tree leafs
108                             if (level == IdxW) begin : gen_leafs
109                               if (offset < N) begin : gen_assign
110                                 // forward path (requests and data)
111                                 // all requests inputs are assigned to the request tree
112        14/14                    assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
113                                 // we basically split the incoming request vector into two halves with the following
114                                 // priority assignment. the prio_mask_q register contains a prefix sum that has been
115                                 // computed using the last winning index, and hence masks out all requests at offsets
116                                 // lower or equal the previously granted index. hence, all higher indices are considered
117                                 // first in the arbitration tree nodes below, before considering the lower indices.
118        14/14                    assign prio_tree[Pa]     = req_i[offset] & prio_mask_q[offset];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
119                                 // input for the index muxes (used to compute the winner index)
120                                 assign idx_tree[Pa]      = offset;
121                                 // input for the data muxes
122        14/14                    assign data_tree[Pa]     = data_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
123                     
124                                 // backward path (grants and prefix sum)
125                                 // grant if selected, ready and request asserted
126        14/14                    assign gnt_o[offset]       = req_i[offset] & sel_tree[Pa] & ready_i;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
127                                 // only update mask if there is a valid request
128        14/14                    assign prio_mask_d[offset] = (|req_i) ?
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
129                                                              mask_tree[Pa] | sel_tree[Pa] & ~ready_i :
130                                                              prio_mask_q[offset];
131                               end else begin : gen_tie_off
132                                 // forward path
133                                 assign req_tree[Pa]  = '0;
134                                 assign prio_tree[Pa] = '0;
135                                 assign idx_tree[Pa]  = '0;
136                                 assign data_tree[Pa] = '0;
137                                 logic unused_sigs;
138        2/2                      assign unused_sigs = ^{mask_tree[Pa],
           Tests:       T1 T2 T3  | T1 T2 T3 
139                                                        sel_tree[Pa]};
140                               end
141                             // this creates the node assignments
142                             end else begin : gen_nodes
143                               // local helper variable
144                               logic sel;
145                     
146                               // forward path (requests and data)
147                               // each node looks at its two children, and selects the one with higher priority
148        14/14(1 unreachable)            assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
149                               // propagate requests
150        14/14(1 unreachable)            assign req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
151        14/14(1 unreachable)            assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
152                               // data and index muxes
153                               // Note: these ternaries have triggered a synthesis bug in Vivado versions older
154                               // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
155        14/15   ==>            assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
156        14/15   ==>            assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
157                     
158                               // backward path (grants and prefix sum)
159                               // this propagates the selction index back and computes a hot one mask
160        14/14(1 unreachable)            assign sel_tree[C0] = sel_tree[Pa] & ~sel;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
161        15/15                  assign sel_tree[C1] = sel_tree[Pa] &  sel;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
162                               // this performs a prefix sum for masking the input requests in the next cycle
163        11/11(4 unreachable)            assign mask_tree[C0] = mask_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164        15/15                  assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
165                             end
166                           end : gen_level
167                         end : gen_tree
168                     
169                         // the results can be found at the tree root
170                         if (EnDataPort) begin : gen_data_port
171        1/1                assign data_o      = data_tree[0];
           Tests:       T1 T2 T3 
172                         end else begin : gen_no_dataport
173                           logic [DW-1:0] unused_data;
174                           assign unused_data = data_tree[0];
175                           assign data_o = '1;
176                         end
177                     
178                         // This index is unused.
179                         logic unused_prio_tree;
180        1/1              assign unused_prio_tree = prio_tree[0];
           Tests:       T1 T2 T3 
181                     
182        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
183        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
184                     
185                         // the select tree computes a hot one signal that indicates which request is currently selected
186                         assign sel_tree[0] = 1'b1;
187                         // the mask tree is basically a prefix sum of the hot one select signal computed above
188                         assign mask_tree[0] = 1'b0;
189                     
190                         always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg
191        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
192        1/1                  prio_mask_q <= '0;
           Tests:       T1 T2 T3 
193                           end else begin
194        1/1                  prio_mask_q <= prio_mask_d;
           Tests:       T1 T2 T3

SCORE	LINE
98.34	100.00

tb.dut.u_otp_ctrl_kdi.u_req_arb

	Line No.	Total	Covered	Percent
TOTAL		103	103	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00



61                        logic unused_req_chk;
62         unreachable    assign unused_req_chk = req_chk_i;
63                      
64                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
65                      
66                        // this case is basically just a bypass
67                        if (N == 1) begin : gen_degenerate_case
68                      
69                          assign valid_o  = req_i[0];
70                          assign data_o   = data_i[0];
71                          assign gnt_o[0] = valid_o & ready_i;
72                          assign idx_o    = '0;
73                      
74                        end else begin : gen_normal_case
75                      
76                          // align to powers of 2 for simplicity
77                          // a full binary tree with N levels has 2**N + 2**N-1 nodes
78                          logic [2**(IdxW+1)-2:0]           req_tree;
79                          logic [2**(IdxW+1)-2:0]           prio_tree;
80                          logic [2**(IdxW+1)-2:0]           sel_tree;
81                          logic [2**(IdxW+1)-2:0]           mask_tree;
82                          logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree;
83                          logic [2**(IdxW+1)-2:0][DW-1:0]   data_tree;
84                          logic [N-1:0]                     prio_mask_d, prio_mask_q;
85                      
86                          for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree
87                            //
88                            // level+1   C0   C1   <- "Base1" points to the first node on "level+1",
89                            //            \  /         these nodes are the children of the nodes one level below
90                            // level       Pa      <- "Base0", points to the first node on "level",
91                            //                         these nodes are the parents of the nodes one level above
92                            //
93                            // hence we have the following indices for the Pa, C0, C1 nodes:
94                            // Pa = 2**level     - 1 + offset       = Base0 + offset
95                            // C0 = 2**(level+1) - 1 + 2*offset     = Base1 + 2*offset
96                            // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1
97                            //
98                            localparam int Base0 = (2**level)-1;
99                            localparam int Base1 = (2**(level+1))-1;
100                     
101                           for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level
102                             localparam int Pa = Base0 + offset;
103                             localparam int C0 = Base1 + 2*offset;
104                             localparam int C1 = Base1 + 2*offset + 1;
105                     
106                             // this assigns the gated interrupt source signals, their
107                             // corresponding IDs and priorities to the tree leafs
108                             if (level == IdxW) begin : gen_leafs
109                               if (offset < N) begin : gen_assign
110                                 // forward path (requests and data)
111                                 // all requests inputs are assigned to the request tree
112        7/7                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5 
113                                 // we basically split the incoming request vector into two halves with the following
114                                 // priority assignment. the prio_mask_q register contains a prefix sum that has been
115                                 // computed using the last winning index, and hence masks out all requests at offsets
116                                 // lower or equal the previously granted index. hence, all higher indices are considered
117                                 // first in the arbitration tree nodes below, before considering the lower indices.
118        7/7                      assign prio_tree[Pa]     = req_i[offset] & prio_mask_q[offset];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
119                                 // input for the index muxes (used to compute the winner index)
120                                 assign idx_tree[Pa]      = offset;
121                                 // input for the data muxes
122        7/7                      assign data_tree[Pa]     = data_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
123                     
124                                 // backward path (grants and prefix sum)
125                                 // grant if selected, ready and request asserted
126        7/7                      assign gnt_o[offset]       = req_i[offset] & sel_tree[Pa] & ready_i;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
127                                 // only update mask if there is a valid request
128        7/7                      assign prio_mask_d[offset] = (|req_i) ?
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
129                                                              mask_tree[Pa] | sel_tree[Pa] & ~ready_i :
130                                                              prio_mask_q[offset];
131                               end else begin : gen_tie_off
132                                 // forward path
133                                 assign req_tree[Pa]  = '0;
134                                 assign prio_tree[Pa] = '0;
135                                 assign idx_tree[Pa]  = '0;
136                                 assign data_tree[Pa] = '0;
137                                 logic unused_sigs;
138        1/1                      assign unused_sigs = ^{mask_tree[Pa],
           Tests:       T2 T4 T5 
139                                                        sel_tree[Pa]};
140                               end
141                             // this creates the node assignments
142                             end else begin : gen_nodes
143                               // local helper variable
144                               logic sel;
145                     
146                               // forward path (requests and data)
147                               // each node looks at its two children, and selects the one with higher priority
148        7/7                    assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1];
           Tests:       T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5 
149                               // propagate requests
150        7/7                    assign req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5 
151        7/7                    assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0];
           Tests:       T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5 
152                               // data and index muxes
153                               // Note: these ternaries have triggered a synthesis bug in Vivado versions older
154                               // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
155        7/7                    assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5 
156        7/7                    assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
157                     
158                               // backward path (grants and prefix sum)
159                               // this propagates the selction index back and computes a hot one mask
160        7/7                    assign sel_tree[C0] = sel_tree[Pa] & ~sel;
           Tests:       T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5 
161        7/7                    assign sel_tree[C1] = sel_tree[Pa] &  sel;
           Tests:       T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5 
162                               // this performs a prefix sum for masking the input requests in the next cycle
163        4/4(3 unreachable)            assign mask_tree[C0] = mask_tree[Pa];
           Tests:       T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5 
164        7/7                    assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0];
           Tests:       T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5  | T2 T4 T5 
165                             end
166                           end : gen_level
167                         end : gen_tree
168                     
169                         // the results can be found at the tree root
170                         if (EnDataPort) begin : gen_data_port
171        1/1                assign data_o      = data_tree[0];
           Tests:       T2 T4 T5 
172                         end else begin : gen_no_dataport
173                           logic [DW-1:0] unused_data;
174                           assign unused_data = data_tree[0];
175                           assign data_o = '1;
176                         end
177                     
178                         // This index is unused.
179                         logic unused_prio_tree;
180        1/1              assign unused_prio_tree = prio_tree[0];
           Tests:       T2 T4 T5 
181                     
182        1/1              assign idx_o       = idx_tree[0];
           Tests:       T2 T4 T5 
183        1/1              assign valid_o     = req_tree[0];
           Tests:       T2 T4 T5 
184                     
185                         // the select tree computes a hot one signal that indicates which request is currently selected
186                         assign sel_tree[0] = 1'b1;
187                         // the mask tree is basically a prefix sum of the hot one select signal computed above
188                         assign mask_tree[0] = 1'b0;
189                     
190                         always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg
191        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
192        1/1                  prio_mask_q <= '0;
           Tests:       T1 T2 T3 
193                           end else begin
194        1/1                  prio_mask_q <= prio_mask_d;
           Tests:       T1 T2 T3

Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=32,EnDataPort=0,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :

SCORE	COND
87.74	65.31

tb.dut.u_edn_arb

	Total	Covered	Percent
Conditions	51	32	62.75
Logical	51	32	62.75
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Not Covered
1	1	Not Covered

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T2,T4,T5

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Covered	T2,T4,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Not Covered
1	1	Not Covered

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T4,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Unreachable

SCORE	COND
97.25	97.16

tb.dut.u_otp_arb

	Total	Covered	Percent
Conditions	559	514	91.95
Logical	559	514	91.95
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
118-150	88.38
150-164	96.98

SCORE	COND
79.55	99.45

tb.dut.u_scrmbl_mtx

	Total	Covered	Percent
Conditions	503	360	71.57
Logical	503	360	71.57
Non-Logical	0	0
Event	0	0

Line numbers	Percent
118-155	71.60
155-164	71.52

SCORE	COND
98.34	99.62

tb.dut.u_otp_ctrl_kdi.u_req_arb

	Total	Covered	Percent
Conditions	269	261	97.03
Logical	269	261	97.03
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       118
 EXPRESSION (req_i[4] & gen_normal_case.prio_mask_q[4])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       118
 EXPRESSION (req_i[5] & gen_normal_case.prio_mask_q[5])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       118
 EXPRESSION (req_i[6] & gen_normal_case.prio_mask_q[6])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T123,T150,T145
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T2,T4,T5

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T123,T150,T145
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T2,T4,T5

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T150,T145,T183
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T2,T4,T5

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T123,T150,T145
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T2,T4,T5

 LINE       126
 EXPRESSION (req_i[4] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T129,T121,T240
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T2,T4,T5

 LINE       126
 EXPRESSION (req_i[5] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T145,T183,T138
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T2,T4,T5

 LINE       126
 EXPRESSION (req_i[6] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T254,T255,T256
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T2,T4,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[4])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[5])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[6])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T100,T145,T183
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T145,T183,T129
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T123,T150,T145
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T123,T150,T145
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T257,T26,T258
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T100,T259,T260
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T150,T145,T183
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T123,T150,T145
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T123,T150,T145
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T150,T145,T183
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T259,T27,T261
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C1])

-1-	-2-	Status	Tests
0	1	Covered	T100,T260,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C1])

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Unreachable

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T2,T4,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Unreachable

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T145,T183,T129
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T145,T183,T129
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T123,T150,T145
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T123,T150,T145
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T145,T183,T129
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T100,T262,T263
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

SCORE	BRANCH
97.25	100.00

tb.dut.u_otp_arb

SCORE	BRANCH
79.55	100.00

tb.dut.u_scrmbl_mtx

	Line No.	Total	Covered	Percent
Branches		88	88	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	1	1	100.00
TERNARY	156	1	1	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==> (Unreachable)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==> (Unreachable)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



191              if (!rst_ni) begin
                 -1-  
192                prio_mask_q <= '0;
                   ==>
193              end else begin
194                prio_mask_q <= prio_mask_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

SCORE	BRANCH
87.74	100.00

tb.dut.u_edn_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



191              if (!rst_ni) begin
                 -1-  
192                prio_mask_q <= '0;
                   ==>
193              end else begin
194                prio_mask_q <= prio_mask_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

SCORE	BRANCH
98.34	100.00

tb.dut.u_otp_ctrl_kdi.u_req_arb

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



155                  assign idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



156                  assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



128                    assign prio_mask_d[offset] = (|req_i) ?
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



191              if (!rst_ni) begin
                 -1-  
192                prio_mask_q <= '0;
                   ==>
193              end else begin
194                prio_mask_q <= prio_mask_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Module : prim_arbiter_tree

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	337774396	334454920	0	0
CheckNGreaterZero_A	4456	4456	0	0
GntImpliesReady_A	337774396	1371159	0	0
GntImpliesValid_A	337774396	1371159	0	0
GrantKnown_A	337774396	334454920	0	0
IdxKnown_A	337774396	334454920	0	0
IndexIsCorrect_A	337774396	1371159	0	0
LockArbDecision_A	337774396	47934794	0	0
NoReadyValidNoGrant_A	337774396	178565394	0	0
ReadyAndValidImplyGrant_A	337774396	1371159	0	0
ReqAndReadyImplyGrant_A	337774396	1371159	0	0
ReqImpliesValid_A	337774396	86245345	0	0
ReqStaysHighUntilGranted0_M	337774396	47934794	0	0
RoundRobin_A	337774396	0	0	4412
ValidKnown_A	337774396	334454920	0	0
gen_data_port_assertion.DataFlow_A	253330797	1192267	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	337774396	334454920
T1	20480	20168
T2	51192	50440
T3	40508	39288
T4	220856	216588
T5	72192	71340
T9	90488	89348
T10	239004	238776
T11	18056	17832
T12	48156	47120
T13	191560	191316

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	4456	4456
T1	4	4
T2	4	4
T3	4	4
T4	4	4
T5	4	4
T9	4	4
T10	4	4
T11	4	4
T12	4	4
T13	4	4

GntImpliesReady_A

Name	Attempts	Real Successes
Total	337774396	1371159
T1	5120	111
T2	38394	289
T3	30381	171
T4	165642	2545
T5	54144	316
T9	67866	153
T10	179253	1356
T11	13542	55
T12	36117	300
T13	143670	949
T17	9082	0
T24	0	55
T35	0	124
T51	0	55
T55	0	161
T95	0	126
T97	0	156
T130	0	107

GntImpliesValid_A

Name	Attempts	Real Successes
Total	337774396	1371159
T1	5120	111
T2	38394	289
T3	30381	171
T4	165642	2545
T5	54144	316
T9	67866	153
T10	179253	1356
T11	13542	55
T12	36117	300
T13	143670	949
T17	9082	0
T24	0	55
T35	0	124
T51	0	55
T55	0	161
T95	0	126
T97	0	156
T130	0	107

GrantKnown_A

Name	Attempts	Real Successes
Total	337774396	334454920
T1	20480	20168
T2	51192	50440
T3	40508	39288
T4	220856	216588
T5	72192	71340
T9	90488	89348
T10	239004	238776
T11	18056	17832
T12	48156	47120
T13	191560	191316

IdxKnown_A

Name	Attempts	Real Successes
Total	337774396	334454920
T1	20480	20168
T2	51192	50440
T3	40508	39288
T4	220856	216588
T5	72192	71340
T9	90488	89348
T10	239004	238776
T11	18056	17832
T12	48156	47120
T13	191560	191316

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	337774396	1371159
T1	5120	111
T2	38394	289
T3	30381	171
T4	165642	2545
T5	54144	316
T9	67866	153
T10	179253	1356
T11	13542	55
T12	36117	300
T13	143670	949
T17	9082	0
T24	0	55
T35	0	124
T51	0	55
T55	0	161
T95	0	126
T97	0	156
T130	0	107

LockArbDecision_A

Name	Attempts	Real Successes
Total	337774396	47934794
T1	5120	624
T2	38394	4061
T3	30381	1284
T4	165642	31504
T5	54144	7792
T9	67866	1312
T10	179253	624
T11	13542	624
T12	36117	1872
T13	143670	624
T17	9082	0
T24	0	2298
T35	0	57261
T51	0	2352
T55	0	6012
T94	0	11817
T95	0	13334
T96	0	5701
T97	0	8506
T130	0	3955

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	337774396	178565394
T1	20480	12298
T2	51192	29509
T3	40508	26323
T4	220856	116379
T5	72192	38093
T9	90488	61535
T10	239004	187214
T11	18056	11301
T12	48156	30349
T13	191560	147526

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	337774396	1371159
T1	5120	111
T2	38394	289
T3	30381	171
T4	165642	2545
T5	54144	316
T9	67866	153
T10	179253	1356
T11	13542	55
T12	36117	300
T13	143670	949
T17	9082	0
T24	0	55
T35	0	124
T51	0	55
T55	0	161
T95	0	126
T97	0	156
T130	0	107

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	337774396	1371159
T1	5120	111
T2	38394	289
T3	30381	171
T4	165642	2545
T5	54144	316
T9	67866	153
T10	179253	1356
T11	13542	55
T12	36117	300
T13	143670	949
T17	9082	0
T24	0	55
T35	0	124
T51	0	55
T55	0	161
T95	0	126
T97	0	156
T130	0	107

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	337774396	86245345
T1	10240	4331
T2	51192	11490
T3	40508	5783
T4	220856	67564
T5	72192	19258
T9	90488	7850
T10	239004	5882
T11	18056	2994
T12	48156	8915
T13	191560	5472
T17	9082	0
T24	0	2353
T35	0	57693
T51	0	2407
T55	0	6173
T94	0	11818
T95	0	13439
T96	0	5702
T97	0	8663
T130	0	4048

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes
Total	337774396	47934794
T1	5120	624
T2	38394	4061
T3	30381	1284
T4	165642	31504
T5	54144	7792
T9	67866	1312
T10	179253	624
T11	13542	624
T12	36117	1872
T13	143670	624
T17	9082	0
T24	0	2298
T35	0	57261
T51	0	2352
T55	0	6012
T94	0	11817
T95	0	13334
T96	0	5701
T97	0	8506
T130	0	3955

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337774396	0	0	4412

ValidKnown_A

Name	Attempts	Real Successes
Total	337774396	334454920
T1	20480	20168
T2	51192	50440
T3	40508	39288
T4	220856	216588
T5	72192	71340
T9	90488	89348
T10	239004	238776
T11	18056	17832
T12	48156	47120
T13	191560	191316

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	253330797	1192267
T1	5120	111
T2	25596	242
T3	20254	171
T4	110428	2389
T5	36096	273
T9	45244	153
T10	119502	1356
T11	9028	55
T12	24078	300
T13	95780	949
T17	4541	0
T24	0	7
T35	0	21
T51	0	7
T55	0	21
T95	0	21
T97	0	21
T130	0	14

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.92	97.11	80.82			100.00	93.75