Module Definition
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Module : prim_secded_inv_72_64_dec
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 68.75 68.75
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 71.32 71.32
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 72.06 72.06
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 72.79 72.79
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 75.00 75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 75.74 75.74
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 75.74 75.74
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 76.47 76.47
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 79.41 79.41
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 82.35 82.35
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 85.29 85.29
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 100.00 100.00


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.75 68.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.75 68.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.32 71.32


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.32 71.32


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.06 72.06


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.06 72.06


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.79 72.79


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.79 72.79


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.74 75.74


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.74 75.74


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.74 75.74


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.74 75.74


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.47 76.47


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.41 79.41


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.41 79.41


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.35 82.35


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.35 82.35


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.29 85.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.29 85.29


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 80.00 100.00 gen_ecc_reg.u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_otp_ctrl_ecc_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T4,T35,T95 Yes T4,T9,T35 INPUT
data_o[63:0] Yes Yes T4,T35,T95 Yes T4,T9,T35 OUTPUT
syndrome_o[2:0] Yes Yes T177,T187,T188 Yes T177,T187,T188 OUTPUT
syndrome_o[7:3] No No No OUTPUT
err_o[0] Yes Yes *T177,*T187,*T188 Yes T177,T187,T188 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 187 68.75
Total Bits 0->1 136 94 69.12
Total Bits 1->0 136 93 68.38

Ports 2 0 0.00
Port Bits 272 187 68.75
Port Bits 0->1 136 94 69.12
Port Bits 1->0 136 93 68.38

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[1:0] No No No INPUT
data_i[4:2] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[5] No No No INPUT
data_i[9:6] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[11:10] No No No INPUT
data_i[12] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[13] No No No INPUT
data_i[16:14] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[18:17] No No No INPUT
data_i[21:19] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[23:22] No No No INPUT
data_i[30:24] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[31] No No No INPUT
data_i[35:32] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[36] No No No INPUT
data_i[37] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[38] No No No INPUT
data_i[41:39] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[42] No No No INPUT
data_i[44:43] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[45] No No No INPUT
data_i[46] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[47] No No No INPUT
data_i[48] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[49] No No No INPUT
data_i[51:50] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[52] No No No INPUT
data_i[53] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[54] No No No INPUT
data_i[55] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[56] No No No INPUT
data_i[57] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[58] No No No INPUT
data_i[65:59] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[66] No No Yes T277 INPUT
data_i[71:67] Yes Yes T4,T5,T12 Yes T4,T5,T97 INPUT
data_o[1:0] No No No OUTPUT
data_o[4:2] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[5] No No No OUTPUT
data_o[9:6] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[11:10] No No No OUTPUT
data_o[12] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[13] No No No OUTPUT
data_o[16:14] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[18:17] No No No OUTPUT
data_o[21:19] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[23:22] No No No OUTPUT
data_o[30:24] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[31] No No No OUTPUT
data_o[35:32] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[36] No No No OUTPUT
data_o[37] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[38] No No No OUTPUT
data_o[41:39] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[42] No No No OUTPUT
data_o[44:43] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[45] No No No OUTPUT
data_o[46] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[47] No No No OUTPUT
data_o[48] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[49] No No No OUTPUT
data_o[51:50] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[52] No No No OUTPUT
data_o[53] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[54] No No No OUTPUT
data_o[55] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[56] No No No OUTPUT
data_o[57] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[58] No No No OUTPUT
data_o[63:59] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 194 71.32
Total Bits 0->1 136 97 71.32
Total Bits 1->0 136 97 71.32

Ports 2 0 0.00
Port Bits 272 194 71.32
Port Bits 0->1 136 97 71.32
Port Bits 1->0 136 97 71.32

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[7:0] Yes Yes T4,T130,T98 Yes T4,T35,T130 INPUT
data_i[8] No No No INPUT
data_i[9] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[10] No No No INPUT
data_i[13:11] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[17:14] No No No INPUT
data_i[18] Yes Yes *T4,*T130,*T98 Yes T4,T35,T130 INPUT
data_i[19] No No No INPUT
data_i[22:20] Yes Yes T4,T130,T98 Yes T4,T35,T130 INPUT
data_i[23] No No No INPUT
data_i[24] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[25] No No No INPUT
data_i[27:26] Yes Yes T4,T130,T98 Yes T4,T35,T130 INPUT
data_i[28] No No No INPUT
data_i[30:29] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[32:31] No No No INPUT
data_i[36:33] Yes Yes T4,T98,*T133 Yes T4,T35,T98 INPUT
data_i[37] No No No INPUT
data_i[43:38] Yes Yes T4,T98,*T133 Yes T4,T35,T98 INPUT
data_i[44] No No No INPUT
data_i[50:45] Yes Yes T4,*T98,*T133 Yes T4,T35,T98 INPUT
data_i[52:51] No No No INPUT
data_i[53] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[54] No No No INPUT
data_i[59:55] Yes Yes T4,*T133,*T19 Yes T4,T133,T19 INPUT
data_i[60] No No No INPUT
data_i[61] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[62] No No No INPUT
data_i[63] Yes Yes *T4,*T133,*T19 Yes T4,T133,T19 INPUT
data_i[64] No No No INPUT
data_i[71:65] Yes Yes T4,T5,T12 Yes T4,T5,T97 INPUT
data_o[7:0] Yes Yes T4,T130,T98 Yes T4,T35,T130 OUTPUT
data_o[8] No No No OUTPUT
data_o[9] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[10] No No No OUTPUT
data_o[13:11] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[17:14] No No No OUTPUT
data_o[18] Yes Yes *T4,*T130,*T98 Yes T4,T35,T130 OUTPUT
data_o[19] No No No OUTPUT
data_o[22:20] Yes Yes T4,T130,T98 Yes T4,T35,T130 OUTPUT
data_o[23] No No No OUTPUT
data_o[24] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[25] No No No OUTPUT
data_o[27:26] Yes Yes T4,T130,T98 Yes T4,T35,T130 OUTPUT
data_o[28] No No No OUTPUT
data_o[30:29] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[32:31] No No No OUTPUT
data_o[36:33] Yes Yes T4,T98,*T133 Yes T4,T35,T98 OUTPUT
data_o[37] No No No OUTPUT
data_o[43:38] Yes Yes T4,T98,*T133 Yes T4,T35,T98 OUTPUT
data_o[44] No No No OUTPUT
data_o[50:45] Yes Yes T4,*T98,*T133 Yes T4,T35,T98 OUTPUT
data_o[52:51] No No No OUTPUT
data_o[53] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[54] No No No OUTPUT
data_o[59:55] Yes Yes T4,*T133,*T19 Yes T4,T133,T19 OUTPUT
data_o[60] No No No OUTPUT
data_o[61] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[62] No No No OUTPUT
data_o[63] Yes Yes T4,T133,T19 Yes T4,T133,T19 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 196 72.06
Total Bits 0->1 136 98 72.06
Total Bits 1->0 136 98 72.06

Ports 2 0 0.00
Port Bits 272 196 72.06
Port Bits 0->1 136 98 72.06
Port Bits 1->0 136 98 72.06

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[6:1] Yes Yes T4,T5,T51 Yes T4,T5,T12 INPUT
data_i[7] No No No INPUT
data_i[9:8] Yes Yes T4,T5,*T97 Yes T4,T5,T12 INPUT
data_i[11:10] No No No INPUT
data_i[15:12] Yes Yes T4,T5,T51 Yes T4,T5,T12 INPUT
data_i[16] No No No INPUT
data_i[21:17] Yes Yes T4,T5,T51 Yes T4,T5,T12 INPUT
data_i[22] No No No INPUT
data_i[24:23] Yes Yes T4,T5,T51 Yes T4,T5,T12 INPUT
data_i[25] No No No INPUT
data_i[27:26] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[28] No No No INPUT
data_i[29] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[30] No No No INPUT
data_i[33:31] Yes Yes T4,T5,T51 Yes T4,T5,T12 INPUT
data_i[35:34] No No No INPUT
data_i[36] Yes Yes *T4,*T5,*T51 Yes T4,T5,T12 INPUT
data_i[38:37] No No No INPUT
data_i[42:39] Yes Yes T4,T5,T51 Yes T4,T5,T12 INPUT
data_i[43] No No No INPUT
data_i[48:44] Yes Yes T4,T5,*T97 Yes T4,T5,T12 INPUT
data_i[49] No No No INPUT
data_i[50] Yes Yes *T4,*T5,*T51 Yes T4,T5,T12 INPUT
data_i[51] No No No INPUT
data_i[55:52] Yes Yes T4,T5,*T97 Yes T4,T5,T12 INPUT
data_i[56] No No No INPUT
data_i[60:57] Yes Yes T4,T5,T51 Yes T4,T5,T12 INPUT
data_i[61] No No No INPUT
data_i[62] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[63] No No No INPUT
data_i[71:64] Yes Yes T134,T135,T278 Yes T134,T135,T199 INPUT
data_o[0] No No No OUTPUT
data_o[6:1] Yes Yes T4,T5,T51 Yes T4,T5,T12 OUTPUT
data_o[7] No No No OUTPUT
data_o[9:8] Yes Yes T4,T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[11:10] No No No OUTPUT
data_o[15:12] Yes Yes T4,T5,T51 Yes T4,T5,T12 OUTPUT
data_o[16] No No No OUTPUT
data_o[21:17] Yes Yes T4,T5,T51 Yes T4,T5,T12 OUTPUT
data_o[22] No No No OUTPUT
data_o[24:23] Yes Yes T4,T5,T51 Yes T4,T5,T12 OUTPUT
data_o[25] No No No OUTPUT
data_o[27:26] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[28] No No No OUTPUT
data_o[29] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[30] No No No OUTPUT
data_o[33:31] Yes Yes T4,T5,T51 Yes T4,T5,T12 OUTPUT
data_o[35:34] No No No OUTPUT
data_o[36] Yes Yes *T4,*T5,*T51 Yes T4,T5,T12 OUTPUT
data_o[38:37] No No No OUTPUT
data_o[42:39] Yes Yes T4,T5,T51 Yes T4,T5,T12 OUTPUT
data_o[43] No No No OUTPUT
data_o[48:44] Yes Yes T4,T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[49] No No No OUTPUT
data_o[50] Yes Yes *T4,*T5,*T51 Yes T4,T5,T12 OUTPUT
data_o[51] No No No OUTPUT
data_o[55:52] Yes Yes T4,T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[56] No No No OUTPUT
data_o[60:57] Yes Yes T4,T5,T51 Yes T4,T5,T12 OUTPUT
data_o[61] No No No OUTPUT
data_o[62] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 198 72.79
Total Bits 0->1 136 99 72.79
Total Bits 1->0 136 99 72.79

Ports 2 0 0.00
Port Bits 272 198 72.79
Port Bits 0->1 136 99 72.79
Port Bits 1->0 136 99 72.79

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[6:1] Yes Yes T4,T5,T51 Yes T4,T5,T12 INPUT
data_i[7] No No No INPUT
data_i[11:8] Yes Yes T4,T5,T51 Yes T4,T5,T12 INPUT
data_i[12] No No No INPUT
data_i[14:13] Yes Yes T4,T5,*T97 Yes T4,T5,T12 INPUT
data_i[16:15] No No No INPUT
data_i[17] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[18] No No No INPUT
data_i[20:19] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[21] No No No INPUT
data_i[23:22] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[24] No No No INPUT
data_i[26:25] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[28:27] No No No INPUT
data_i[35:29] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[36] No No No INPUT
data_i[42:37] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[44:43] No No No INPUT
data_i[47:45] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[48] No No No INPUT
data_i[54:49] Yes Yes T4,T130,T98 Yes T4,T35,T51 INPUT
data_i[55] No No No INPUT
data_i[56] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[57] No No No INPUT
data_i[58] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[59] No No No INPUT
data_i[60] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[61] No No No INPUT
data_i[70:62] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[71] No No No INPUT
data_o[0] No No No OUTPUT
data_o[6:1] Yes Yes T4,T5,T51 Yes T4,T5,T12 OUTPUT
data_o[7] No No No OUTPUT
data_o[11:8] Yes Yes T4,T5,T51 Yes T4,T5,T12 OUTPUT
data_o[12] No No No OUTPUT
data_o[14:13] Yes Yes T4,T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[16:15] No No No OUTPUT
data_o[17] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[18] No No No OUTPUT
data_o[20:19] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[21] No No No OUTPUT
data_o[23:22] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[24] No No No OUTPUT
data_o[26:25] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[28:27] No No No OUTPUT
data_o[35:29] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[36] No No No OUTPUT
data_o[42:37] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[44:43] No No No OUTPUT
data_o[47:45] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[48] No No No OUTPUT
data_o[54:49] Yes Yes T4,T130,T98 Yes T4,T35,T51 OUTPUT
data_o[55] No No No OUTPUT
data_o[56] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[57] No No No OUTPUT
data_o[58] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[59] No No No OUTPUT
data_o[60] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[61] No No No OUTPUT
data_o[63:62] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 204 75.00
Total Bits 0->1 136 102 75.00
Total Bits 1->0 136 102 75.00

Ports 2 0 0.00
Port Bits 272 204 75.00
Port Bits 0->1 136 102 75.00
Port Bits 1->0 136 102 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] No No No INPUT
data_i[5:1] Yes Yes T4,T97,T51 Yes T4,T97,T35 INPUT
data_i[7:6] No No No INPUT
data_i[9:8] Yes Yes T4,T97,T51 Yes T4,T97,T35 INPUT
data_i[10] No No No INPUT
data_i[16:11] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[17] No No No INPUT
data_i[21:18] Yes Yes T4,T51,T55 Yes T4,T35,T51 INPUT
data_i[23:22] No No No INPUT
data_i[31:24] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[32] No No No INPUT
data_i[33] Yes Yes *T4,*T51,*T55 Yes T4,T35,T51 INPUT
data_i[35:34] No No No INPUT
data_i[39:36] Yes Yes T4,T51,T55 Yes T4,T35,T51 INPUT
data_i[40] No No No INPUT
data_i[41] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[42] No No No INPUT
data_i[54:43] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[56:55] No No No INPUT
data_i[60:57] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[61] No No No INPUT
data_i[62] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[64:63] No No No INPUT
data_i[67:65] Yes Yes *T150,*T159,*T279 Yes T150,T159,T279 INPUT
data_i[68] No No No INPUT
data_i[71:69] Yes Yes T4,T97,T35 Yes T4,T97,T51 INPUT
data_o[0] No No No OUTPUT
data_o[5:1] Yes Yes T4,T97,T51 Yes T4,T97,T35 OUTPUT
data_o[7:6] No No No OUTPUT
data_o[9:8] Yes Yes T4,T97,T51 Yes T4,T97,T35 OUTPUT
data_o[10] No No No OUTPUT
data_o[16:11] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[17] No No No OUTPUT
data_o[21:18] Yes Yes T4,T51,T55 Yes T4,T35,T51 OUTPUT
data_o[23:22] No No No OUTPUT
data_o[31:24] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[32] No No No OUTPUT
data_o[33] Yes Yes *T4,*T51,*T55 Yes T4,T35,T51 OUTPUT
data_o[35:34] No No No OUTPUT
data_o[39:36] Yes Yes T4,T51,T55 Yes T4,T35,T51 OUTPUT
data_o[40] No No No OUTPUT
data_o[41] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[42] No No No OUTPUT
data_o[54:43] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[56:55] No No No OUTPUT
data_o[60:57] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[61] No No No OUTPUT
data_o[62] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[63] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 206 75.74
Total Bits 0->1 136 103 75.74
Total Bits 1->0 136 103 75.74

Ports 2 0 0.00
Port Bits 272 206 75.74
Port Bits 0->1 136 103 75.74
Port Bits 1->0 136 103 75.74

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[1:0] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[2] No No No INPUT
data_i[8:3] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[9] No No No INPUT
data_i[10] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[11] No No No INPUT
data_i[15:12] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[18:16] No No No INPUT
data_i[24:19] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[26:25] No No No INPUT
data_i[31:27] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[33:32] No No No INPUT
data_i[39:34] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[41:40] No No No INPUT
data_i[45:42] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[46] No No No INPUT
data_i[54:47] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[55] No No No INPUT
data_i[61:56] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[64:62] No No No INPUT
data_i[71:65] Yes Yes T81,T280,T167 Yes T81,T280,T167 INPUT
data_o[1:0] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[2] No No No OUTPUT
data_o[8:3] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[9] No No No OUTPUT
data_o[10] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[11] No No No OUTPUT
data_o[15:12] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[18:16] No No No OUTPUT
data_o[24:19] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[26:25] No No No OUTPUT
data_o[31:27] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[33:32] No No No OUTPUT
data_o[39:34] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[41:40] No No No OUTPUT
data_o[45:42] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[46] No No No OUTPUT
data_o[54:47] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[55] No No No OUTPUT
data_o[61:56] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[63:62] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 206 75.74
Total Bits 0->1 136 103 75.74
Total Bits 1->0 136 103 75.74

Ports 2 0 0.00
Port Bits 272 206 75.74
Port Bits 0->1 136 103 75.74
Port Bits 1->0 136 103 75.74

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[7:0] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[8] No No No INPUT
data_i[14:9] Yes Yes T4,T55,T95 Yes T4,T35,T51 INPUT
data_i[15] No No No INPUT
data_i[19:16] Yes Yes T4,T55,T95 Yes T4,T51,T55 INPUT
data_i[20] No No No INPUT
data_i[22:21] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[26:23] No No No INPUT
data_i[34:27] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[35] No No No INPUT
data_i[43:36] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[45:44] No No No INPUT
data_i[47:46] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[48] No No No INPUT
data_i[50:49] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[51] No No No INPUT
data_i[52] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[53] No No No INPUT
data_i[56:54] Yes Yes T4,T55,T95 Yes T4,T35,T51 INPUT
data_i[57] No No No INPUT
data_i[61:58] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[63:62] No No No INPUT
data_i[65:64] Yes Yes *T198,*T135,*T137 Yes T198,T135,T137 INPUT
data_i[66] No No No INPUT
data_i[71:67] Yes Yes T4,T51,T55 Yes T4,T55,T95 INPUT
data_o[7:0] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[8] No No No OUTPUT
data_o[14:9] Yes Yes T4,T55,T95 Yes T4,T35,T51 OUTPUT
data_o[15] No No No OUTPUT
data_o[19:16] Yes Yes T4,T55,T95 Yes T4,T51,T55 OUTPUT
data_o[20] No No No OUTPUT
data_o[22:21] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[26:23] No No No OUTPUT
data_o[34:27] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[35] No No No OUTPUT
data_o[43:36] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[45:44] No No No OUTPUT
data_o[47:46] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[48] No No No OUTPUT
data_o[50:49] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[51] No No No OUTPUT
data_o[52] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[53] No No No OUTPUT
data_o[56:54] Yes Yes T4,T55,T95 Yes T4,T35,T51 OUTPUT
data_o[57] No No No OUTPUT
data_o[61:58] Yes Yes T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[63:62] No No No OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 208 76.47
Total Bits 0->1 136 104 76.47
Total Bits 1->0 136 104 76.47

Ports 2 0 0.00
Port Bits 272 208 76.47
Port Bits 0->1 136 104 76.47
Port Bits 1->0 136 104 76.47

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[2:0] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[4:3] No No No INPUT
data_i[8:5] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[9] No No No INPUT
data_i[10] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[11] No No No INPUT
data_i[13:12] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[15:14] No No No INPUT
data_i[24:16] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[25] No No No INPUT
data_i[34:26] Yes Yes *T4,*T5,*T97 Yes T4,T5,T97 INPUT
data_i[35] No No No INPUT
data_i[36] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[37] No No No INPUT
data_i[39:38] Yes Yes T4,T5,T97 Yes T4,T5,T97 INPUT
data_i[40] No No No INPUT
data_i[42:41] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[43] No No No INPUT
data_i[49:44] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[50] No No No INPUT
data_i[53:51] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[55:54] No No No INPUT
data_i[59:56] Yes Yes T4,T97,T51 Yes T4,T97,T35 INPUT
data_i[61:60] No No No INPUT
data_i[71:62] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_o[2:0] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[4:3] No No No OUTPUT
data_o[8:5] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[9] No No No OUTPUT
data_o[10] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[11] No No No OUTPUT
data_o[13:12] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[15:14] No No No OUTPUT
data_o[24:16] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[25] No No No OUTPUT
data_o[34:26] Yes Yes *T4,*T5,*T97 Yes T4,T5,T97 OUTPUT
data_o[35] No No No OUTPUT
data_o[36] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[37] No No No OUTPUT
data_o[39:38] Yes Yes T4,T5,T97 Yes T4,T5,T97 OUTPUT
data_o[40] No No No OUTPUT
data_o[42:41] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[43] No No No OUTPUT
data_o[49:44] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[50] No No No OUTPUT
data_o[53:51] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[55:54] No No No OUTPUT
data_o[59:56] Yes Yes T4,T97,T51 Yes T4,T97,T35 OUTPUT
data_o[61:60] No No No OUTPUT
data_o[63:62] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 216 79.41
Total Bits 0->1 136 108 79.41
Total Bits 1->0 136 108 79.41

Ports 2 0 0.00
Port Bits 272 216 79.41
Port Bits 0->1 136 108 79.41
Port Bits 1->0 136 108 79.41

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[2:0] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[3] No No No INPUT
data_i[5:4] Yes Yes T4,T5,T51 Yes T4,T5,T12 INPUT
data_i[6] No No No INPUT
data_i[8:7] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[9] No No No INPUT
data_i[12:10] Yes Yes T4,T5,*T97 Yes T4,T5,T12 INPUT
data_i[14:13] No No No INPUT
data_i[15] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[17:16] No No No INPUT
data_i[28:18] Yes Yes T4,T5,*T97 Yes T4,T5,T12 INPUT
data_i[29] No No No INPUT
data_i[36:30] Yes Yes T4,T5,*T97 Yes T4,T5,T12 INPUT
data_i[37] No No No INPUT
data_i[38] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[39] No No No INPUT
data_i[46:40] Yes Yes T4,T5,T51 Yes T4,T5,T12 INPUT
data_i[48:47] No No No INPUT
data_i[57:49] Yes Yes T4,T5,*T97 Yes T4,T5,T12 INPUT
data_i[58] No No No INPUT
data_i[61:59] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[62] No No No INPUT
data_i[71:63] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_o[2:0] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[3] No No No OUTPUT
data_o[5:4] Yes Yes T4,T5,T51 Yes T4,T5,T12 OUTPUT
data_o[6] No No No OUTPUT
data_o[8:7] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[9] No No No OUTPUT
data_o[12:10] Yes Yes T4,T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[14:13] No No No OUTPUT
data_o[15] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[17:16] No No No OUTPUT
data_o[28:18] Yes Yes T4,T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[29] No No No OUTPUT
data_o[36:30] Yes Yes T4,T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[37] No No No OUTPUT
data_o[38] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[39] No No No OUTPUT
data_o[46:40] Yes Yes T4,T5,T51 Yes T4,T5,T12 OUTPUT
data_o[48:47] No No No OUTPUT
data_o[57:49] Yes Yes T4,T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[58] No No No OUTPUT
data_o[61:59] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[62] No No No OUTPUT
data_o[63] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 224 82.35
Total Bits 0->1 136 112 82.35
Total Bits 1->0 136 112 82.35

Ports 2 0 0.00
Port Bits 272 224 82.35
Port Bits 0->1 136 112 82.35
Port Bits 1->0 136 112 82.35

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[0] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[1] No No No INPUT
data_i[10:2] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[11] No No No INPUT
data_i[12] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[14:13] No No No INPUT
data_i[17:15] Yes Yes T4,T5,T97 Yes T4,T5,T12 INPUT
data_i[18] No No No INPUT
data_i[22:19] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[24:23] No No No INPUT
data_i[39:25] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[40] No No No INPUT
data_i[47:41] Yes Yes T4,T5,T51 Yes T4,T5,T12 INPUT
data_i[49:48] No No No INPUT
data_i[54:50] Yes Yes *T88,*T4,*T5 Yes T88,T4,T5 INPUT
data_i[55] No No No INPUT
data_i[57:56] Yes Yes T4,T5,T51 Yes T4,T5,T12 INPUT
data_i[58] No No No INPUT
data_i[71:59] Yes Yes T4,T5,T51 Yes T4,T5,T12 INPUT
data_o[0] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[1] No No No OUTPUT
data_o[10:2] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[11] No No No OUTPUT
data_o[12] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[14:13] No No No OUTPUT
data_o[17:15] Yes Yes T4,T5,T97 Yes T4,T5,T12 OUTPUT
data_o[18] No No No OUTPUT
data_o[22:19] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[24:23] No No No OUTPUT
data_o[39:25] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[40] No No No OUTPUT
data_o[47:41] Yes Yes T4,T5,T51 Yes T4,T5,T12 OUTPUT
data_o[49:48] No No No OUTPUT
data_o[54:50] Yes Yes *T88,*T4,*T5 Yes T88,T4,T5 OUTPUT
data_o[55] No No No OUTPUT
data_o[57:56] Yes Yes T4,T5,T51 Yes T4,T5,T12 OUTPUT
data_o[58] No No No OUTPUT
data_o[63:59] Yes Yes T4,T5,T51 Yes T4,T5,T12 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 0 0.00
Total Bits 272 232 85.29
Total Bits 0->1 136 116 85.29
Total Bits 1->0 136 116 85.29

Ports 2 0 0.00
Port Bits 272 232 85.29
Port Bits 0->1 136 116 85.29
Port Bits 1->0 136 116 85.29

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[5:0] Yes Yes T4,T5,T51 Yes T4,T5,T12 INPUT
data_i[6] No No No INPUT
data_i[14:7] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[15] No No No INPUT
data_i[20:16] Yes Yes *T4,*T5,*T51 Yes T4,T5,T12 INPUT
data_i[21] No No No INPUT
data_i[24:22] Yes Yes *T4,*T5,*T51 Yes T4,T5,T12 INPUT
data_i[25] No No No INPUT
data_i[29:26] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[30] No No No INPUT
data_i[33:31] Yes Yes T4,T5,T51 Yes T4,T5,T12 INPUT
data_i[34] No No No INPUT
data_i[42:35] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[43] No No No INPUT
data_i[47:44] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 INPUT
data_i[48] No No No INPUT
data_i[51:49] Yes Yes T4,T5,*T97 Yes T4,T5,T12 INPUT
data_i[52] No No No INPUT
data_i[60:53] Yes Yes T4,T5,*T97 Yes T4,T5,T12 INPUT
data_i[61] No No No INPUT
data_i[71:62] Yes Yes T77,T4,T5 Yes T77,T4,T5 INPUT
data_o[5:0] Yes Yes T4,T5,T51 Yes T4,T5,T12 OUTPUT
data_o[6] No No No OUTPUT
data_o[14:7] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[15] No No No OUTPUT
data_o[20:16] Yes Yes *T4,*T5,*T51 Yes T4,T5,T12 OUTPUT
data_o[21] No No No OUTPUT
data_o[24:22] Yes Yes *T4,*T5,*T51 Yes T4,T5,T12 OUTPUT
data_o[25] No No No OUTPUT
data_o[29:26] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[30] No No No OUTPUT
data_o[33:31] Yes Yes T4,T5,T51 Yes T4,T5,T12 OUTPUT
data_o[34] No No No OUTPUT
data_o[42:35] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[43] No No No OUTPUT
data_o[47:44] Yes Yes *T4,*T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[48] No No No OUTPUT
data_o[51:49] Yes Yes T4,T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[52] No No No OUTPUT
data_o[60:53] Yes Yes T4,T5,*T97 Yes T4,T5,T12 OUTPUT
data_o[61] No No No OUTPUT
data_o[63:62] Yes Yes T77,T4,T5 Yes T77,T4,T5 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T35,T95 Yes T4,T9,T35 INPUT
data_o[63:0] Yes Yes T4,T35,T95 Yes T4,T9,T35 OUTPUT
syndrome_o[2:0] Yes Yes T187,T188,T189 Yes T187,T188,T189 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T187,*T188,*T189 Yes T187,T188,T189 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T95,T124,T134 Yes T95,T124,T134 INPUT
data_o[63:0] Yes Yes T95,T124,T134 Yes T95,T124,T134 OUTPUT
syndrome_o[2:0] Yes Yes T177,T187,T188 Yes T177,T187,T188 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T177,*T187,*T188 Yes T177,T187,T188 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T35,T123,T124 Yes T35,T123,T124 INPUT
data_o[63:0] Yes Yes T35,T123,T124 Yes T35,T123,T124 OUTPUT
syndrome_o[2:0] Yes Yes T177 Yes T177 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T177 Yes T177 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 280 280 100.00
Total Bits 0->1 140 140 100.00
Total Bits 1->0 140 140 100.00

Ports 4 4 100.00
Port Bits 280 280 100.00
Port Bits 0->1 140 140 100.00
Port Bits 1->0 140 140 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T95,T123,T19 Yes T95,T123,T19 INPUT
data_o[63:0] Yes Yes T95,T123,T19 Yes T95,T123,T19 OUTPUT
syndrome_o[2:0] Yes Yes T177,T188,T189 Yes T177,T188,T189 OUTPUT
syndrome_o[7:3] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0] Yes Yes *T177,*T188,*T189 Yes T177,T188,T189 OUTPUT
err_o[1] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T95,T19,T101 Yes T95,T19,T101 INPUT
data_o[63:0] Yes Yes T95,T19,T101 Yes T95,T19,T101 OUTPUT
syndrome_o[7:0] Excluded Excluded T187 Excluded T187 OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded T187 Excluded T187 OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T150,T281,T58 Yes T150,T281,T58 INPUT
data_o[63:0] Yes Yes T150,T281,T58 Yes T150,T281,T58 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T95,T125,T145 Yes T95,T125,T145 INPUT
data_o[63:0] Yes Yes T95,T125,T145 Yes T95,T125,T145 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T128,T21,T228 Yes T128,T21,T228 INPUT
data_o[63:0] Yes Yes T128,T21,T228 Yes T128,T21,T228 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T235,T282,T185 Yes T235,T282,T183 INPUT
data_o[63:0] Yes Yes T235,T282,T185 Yes T235,T282,T183 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T97,T19,T150 Yes T97,T130,T19 INPUT
data_o[63:0] Yes Yes T97,T19,T150 Yes T97,T130,T19 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T44,T51,T95 Yes T44,T51,T95 INPUT
data_o[63:0] Yes Yes T44,T51,T95 Yes T44,T51,T95 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T44,T19,T183 Yes T44,T130,T19 INPUT
data_o[63:0] Yes Yes T44,T19,T183 Yes T44,T130,T19 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T24,T95,T123 Yes T24,T95,T123 INPUT
data_o[63:0] Yes Yes T24,T95,T123 Yes T24,T95,T123 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T5,T44,T97 Yes T5,T44,T97 INPUT
data_o[63:0] Yes Yes T5,T44,T97 Yes T5,T44,T97 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T5,T97,T95 Yes T5,T97,T95 INPUT
data_o[63:0] Yes Yes T5,T97,T95 Yes T5,T97,T95 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T44,T97,T131 Yes T44,T97,T131 INPUT
data_o[63:0] Yes Yes T44,T97,T131 Yes T44,T97,T131 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T44,T24 Yes T4,T44,T24 INPUT
data_o[63:0] Yes Yes T4,T44,T24 Yes T4,T44,T24 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T35,T19,T145 Yes T35,T19,T145 INPUT
data_o[63:0] Yes Yes T35,T19,T145 Yes T35,T19,T145 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T100,T283,T128 Yes T100,T283,T128 INPUT
data_o[63:0] Yes Yes T100,T283,T128 Yes T100,T283,T128 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T130,T124,T141 Yes T130,T124,T141 INPUT
data_o[63:0] Yes Yes T130,T124,T141 Yes T130,T124,T141 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T97,T24,T66 Yes T97,T24,T66 INPUT
data_o[63:0] Yes Yes T97,T24,T66 Yes T97,T24,T66 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T5,T44,T131 Yes T5,T44,T131 INPUT
data_o[63:0] Yes Yes T5,T44,T131 Yes T5,T44,T131 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T133,T19,T125 Yes T9,T133,T19 INPUT
data_o[63:0] Yes Yes T133,T19,T125 Yes T9,T133,T19 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T97,T35,T51 Yes T97,T35,T51 INPUT
data_o[63:0] Yes Yes T97,T35,T51 Yes T97,T35,T51 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T19,T150 Yes T4,T19,T150 INPUT
data_o[63:0] Yes Yes T4,T19,T150 Yes T4,T19,T150 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T97,T131 Yes T4,T97,T131 INPUT
data_o[63:0] Yes Yes T4,T97,T131 Yes T4,T97,T131 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T97,T150,T106 Yes T97,T150,T106 INPUT
data_o[63:0] Yes Yes T97,T150,T106 Yes T97,T150,T106 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T97,T95 Yes T4,T97,T95 INPUT
data_o[63:0] Yes Yes T4,T97,T95 Yes T4,T97,T95 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 2 2 100.00
Total Bits 272 272 100.00
Total Bits 0->1 136 136 100.00
Total Bits 1->0 136 136 100.00

Ports 2 2 100.00
Port Bits 272 272 100.00
Port Bits 0->1 136 136 100.00
Port Bits 1->0 136 136 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
data_i[71:0] Yes Yes T4,T95,T131 Yes T4,T95,T131 INPUT
data_o[63:0] Yes Yes T4,T95,T131 Yes T4,T95,T131 OUTPUT
syndrome_o[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

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