| T1066 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.63319958 |
|
|
Sep 24 05:23:51 PM UTC 24 |
Sep 24 05:24:00 PM UTC 24 |
467835861 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.391026962 |
|
|
Sep 24 05:23:58 PM UTC 24 |
Sep 24 05:24:05 PM UTC 24 |
502847173 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.3174023101 |
|
|
Sep 24 05:23:53 PM UTC 24 |
Sep 24 05:24:02 PM UTC 24 |
1477070957 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.588608097 |
|
|
Sep 24 05:23:53 PM UTC 24 |
Sep 24 05:24:02 PM UTC 24 |
387576104 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.2953789295 |
|
|
Sep 24 05:23:53 PM UTC 24 |
Sep 24 05:24:02 PM UTC 24 |
111641585 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.3184216845 |
|
|
Sep 24 05:23:53 PM UTC 24 |
Sep 24 05:24:03 PM UTC 24 |
436505153 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_parallel_lc_esc.743460270 |
|
|
Sep 24 05:23:16 PM UTC 24 |
Sep 24 05:24:03 PM UTC 24 |
16559080532 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.17139355 |
|
|
Sep 24 05:24:01 PM UTC 24 |
Sep 24 05:24:05 PM UTC 24 |
104787053 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.811180813 |
|
|
Sep 24 05:24:01 PM UTC 24 |
Sep 24 05:24:05 PM UTC 24 |
88881884 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.2960702854 |
|
|
Sep 24 05:23:53 PM UTC 24 |
Sep 24 05:24:03 PM UTC 24 |
169024420 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.2808130419 |
|
|
Sep 24 05:23:55 PM UTC 24 |
Sep 24 05:24:03 PM UTC 24 |
117122714 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.1722427227 |
|
|
Sep 24 05:23:53 PM UTC 24 |
Sep 24 05:24:03 PM UTC 24 |
113235786 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.4238696774 |
|
|
Sep 24 05:23:55 PM UTC 24 |
Sep 24 05:24:03 PM UTC 24 |
201581335 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.516526651 |
|
|
Sep 24 05:23:53 PM UTC 24 |
Sep 24 05:24:04 PM UTC 24 |
125063446 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.4112883955 |
|
|
Sep 24 05:23:55 PM UTC 24 |
Sep 24 05:24:04 PM UTC 24 |
205312119 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.1948677422 |
|
|
Sep 24 05:23:53 PM UTC 24 |
Sep 24 05:24:04 PM UTC 24 |
353652088 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.2512757875 |
|
|
Sep 24 05:23:55 PM UTC 24 |
Sep 24 05:24:04 PM UTC 24 |
228088180 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.2079510212 |
|
|
Sep 24 05:23:53 PM UTC 24 |
Sep 24 05:24:04 PM UTC 24 |
133378970 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.635693580 |
|
|
Sep 24 05:23:57 PM UTC 24 |
Sep 24 05:24:04 PM UTC 24 |
402675679 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.606224375 |
|
|
Sep 24 05:23:53 PM UTC 24 |
Sep 24 05:24:04 PM UTC 24 |
706146185 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.192337627 |
|
|
Sep 24 05:23:56 PM UTC 24 |
Sep 24 05:24:04 PM UTC 24 |
483021299 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.3842119520 |
|
|
Sep 24 05:23:51 PM UTC 24 |
Sep 24 05:24:04 PM UTC 24 |
1809678463 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.3044239941 |
|
|
Sep 24 05:23:56 PM UTC 24 |
Sep 24 05:24:05 PM UTC 24 |
579244300 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.1706524519 |
|
|
Sep 24 05:23:57 PM UTC 24 |
Sep 24 05:24:05 PM UTC 24 |
411508690 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.3527822852 |
|
|
Sep 24 05:23:57 PM UTC 24 |
Sep 24 05:24:05 PM UTC 24 |
330964376 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.626320478 |
|
|
Sep 24 05:23:59 PM UTC 24 |
Sep 24 05:24:05 PM UTC 24 |
144611586 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.1730875962 |
|
|
Sep 24 05:24:01 PM UTC 24 |
Sep 24 05:24:06 PM UTC 24 |
293625822 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.992936311 |
|
|
Sep 24 05:23:51 PM UTC 24 |
Sep 24 05:24:06 PM UTC 24 |
419873948 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.2327067999 |
|
|
Sep 24 05:24:01 PM UTC 24 |
Sep 24 05:24:06 PM UTC 24 |
537779070 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.532622955 |
|
|
Sep 24 05:23:55 PM UTC 24 |
Sep 24 05:24:06 PM UTC 24 |
2170349537 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.471910022 |
|
|
Sep 24 05:24:01 PM UTC 24 |
Sep 24 05:24:06 PM UTC 24 |
276067645 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.937636855 |
|
|
Sep 24 05:24:01 PM UTC 24 |
Sep 24 05:24:06 PM UTC 24 |
1592766788 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.1863675095 |
|
|
Sep 24 05:24:13 PM UTC 24 |
Sep 24 05:24:18 PM UTC 24 |
595290661 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.2184996332 |
|
|
Sep 24 05:24:10 PM UTC 24 |
Sep 24 05:24:19 PM UTC 24 |
1766863921 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.4152939058 |
|
|
Sep 24 05:24:01 PM UTC 24 |
Sep 24 05:24:06 PM UTC 24 |
443791373 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.1803256129 |
|
|
Sep 24 05:24:01 PM UTC 24 |
Sep 24 05:24:07 PM UTC 24 |
164459293 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.303495167 |
|
|
Sep 24 05:24:01 PM UTC 24 |
Sep 24 05:24:07 PM UTC 24 |
328988154 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.3851285945 |
|
|
Sep 24 05:24:01 PM UTC 24 |
Sep 24 05:24:07 PM UTC 24 |
470587112 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.281873671 |
|
|
Sep 24 05:24:01 PM UTC 24 |
Sep 24 05:24:07 PM UTC 24 |
177005975 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.1643567995 |
|
|
Sep 24 05:24:01 PM UTC 24 |
Sep 24 05:24:07 PM UTC 24 |
2462552917 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.184099019 |
|
|
Sep 24 05:15:56 PM UTC 24 |
Sep 24 05:24:07 PM UTC 24 |
60651288417 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_parallel_lc_esc.4163431190 |
|
|
Sep 24 05:23:36 PM UTC 24 |
Sep 24 05:24:08 PM UTC 24 |
10633884618 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.3157689566 |
|
|
Sep 24 05:24:04 PM UTC 24 |
Sep 24 05:24:09 PM UTC 24 |
235216135 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.3418134889 |
|
|
Sep 24 05:24:04 PM UTC 24 |
Sep 24 05:24:09 PM UTC 24 |
303341160 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.3288129920 |
|
|
Sep 24 05:24:04 PM UTC 24 |
Sep 24 05:24:09 PM UTC 24 |
291710989 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.681170160 |
|
|
Sep 24 05:24:04 PM UTC 24 |
Sep 24 05:24:09 PM UTC 24 |
114933426 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.1938147464 |
|
|
Sep 24 05:24:04 PM UTC 24 |
Sep 24 05:24:09 PM UTC 24 |
476949775 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_parallel_lc_esc.3123895906 |
|
|
Sep 24 05:23:41 PM UTC 24 |
Sep 24 05:24:09 PM UTC 24 |
1120693199 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.2700936530 |
|
|
Sep 24 05:24:04 PM UTC 24 |
Sep 24 05:24:10 PM UTC 24 |
512595136 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.218527601 |
|
|
Sep 24 05:24:04 PM UTC 24 |
Sep 24 05:24:10 PM UTC 24 |
184048177 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.1157894420 |
|
|
Sep 24 05:24:04 PM UTC 24 |
Sep 24 05:24:10 PM UTC 24 |
267283000 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.3456146375 |
|
|
Sep 24 05:24:04 PM UTC 24 |
Sep 24 05:24:10 PM UTC 24 |
1298255035 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.1275445173 |
|
|
Sep 24 05:24:04 PM UTC 24 |
Sep 24 05:24:10 PM UTC 24 |
217548856 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.3622831246 |
|
|
Sep 24 05:24:04 PM UTC 24 |
Sep 24 05:24:10 PM UTC 24 |
577698643 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.4190686257 |
|
|
Sep 24 05:24:04 PM UTC 24 |
Sep 24 05:24:11 PM UTC 24 |
1492214123 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.1928969218 |
|
|
Sep 24 05:24:04 PM UTC 24 |
Sep 24 05:24:11 PM UTC 24 |
333167656 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.329133316 |
|
|
Sep 24 05:24:07 PM UTC 24 |
Sep 24 05:24:11 PM UTC 24 |
374836028 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.2572652131 |
|
|
Sep 24 05:24:06 PM UTC 24 |
Sep 24 05:24:11 PM UTC 24 |
143589663 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.2775422346 |
|
|
Sep 24 05:24:06 PM UTC 24 |
Sep 24 05:24:11 PM UTC 24 |
551142858 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.4249245155 |
|
|
Sep 24 05:24:07 PM UTC 24 |
Sep 24 05:24:12 PM UTC 24 |
193363046 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.1968902458 |
|
|
Sep 24 05:24:06 PM UTC 24 |
Sep 24 05:24:12 PM UTC 24 |
103973716 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.863106804 |
|
|
Sep 24 05:24:07 PM UTC 24 |
Sep 24 05:24:12 PM UTC 24 |
2381558867 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.865965421 |
|
|
Sep 24 05:24:06 PM UTC 24 |
Sep 24 05:24:12 PM UTC 24 |
251053503 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.111176351 |
|
|
Sep 24 05:24:06 PM UTC 24 |
Sep 24 05:24:12 PM UTC 24 |
577110148 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.1049947832 |
|
|
Sep 24 05:24:06 PM UTC 24 |
Sep 24 05:24:12 PM UTC 24 |
2057107429 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.2664210352 |
|
|
Sep 24 05:24:07 PM UTC 24 |
Sep 24 05:24:12 PM UTC 24 |
277104803 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.2453374125 |
|
|
Sep 24 05:24:07 PM UTC 24 |
Sep 24 05:24:12 PM UTC 24 |
418134957 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.50213804 |
|
|
Sep 24 05:24:07 PM UTC 24 |
Sep 24 05:24:12 PM UTC 24 |
119207048 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.3535525431 |
|
|
Sep 24 05:24:06 PM UTC 24 |
Sep 24 05:24:12 PM UTC 24 |
1694846005 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.2587147912 |
|
|
Sep 24 05:24:07 PM UTC 24 |
Sep 24 05:24:13 PM UTC 24 |
282257832 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.3737269724 |
|
|
Sep 24 05:24:07 PM UTC 24 |
Sep 24 05:24:13 PM UTC 24 |
524447455 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.872626096 |
|
|
Sep 24 05:24:07 PM UTC 24 |
Sep 24 05:24:13 PM UTC 24 |
141828440 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.1892572655 |
|
|
Sep 24 05:24:07 PM UTC 24 |
Sep 24 05:24:13 PM UTC 24 |
151951969 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.795008626 |
|
|
Sep 24 05:24:07 PM UTC 24 |
Sep 24 05:24:13 PM UTC 24 |
2543911805 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.2596930896 |
|
|
Sep 24 05:23:43 PM UTC 24 |
Sep 24 05:24:14 PM UTC 24 |
9011941126 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.3473424625 |
|
|
Sep 24 05:24:12 PM UTC 24 |
Sep 24 05:24:19 PM UTC 24 |
266836160 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.2030264630 |
|
|
Sep 24 05:19:58 PM UTC 24 |
Sep 24 05:24:14 PM UTC 24 |
73637265051 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.1123599040 |
|
|
Sep 24 05:24:10 PM UTC 24 |
Sep 24 05:24:15 PM UTC 24 |
134796756 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.1927804456 |
|
|
Sep 24 05:23:48 PM UTC 24 |
Sep 24 05:24:15 PM UTC 24 |
11198285997 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.811326155 |
|
|
Sep 24 05:24:10 PM UTC 24 |
Sep 24 05:24:15 PM UTC 24 |
143347965 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.146309036 |
|
|
Sep 24 05:24:10 PM UTC 24 |
Sep 24 05:24:15 PM UTC 24 |
213438212 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.4262694187 |
|
|
Sep 24 05:24:10 PM UTC 24 |
Sep 24 05:24:15 PM UTC 24 |
107281808 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.603280229 |
|
|
Sep 24 05:24:10 PM UTC 24 |
Sep 24 05:24:15 PM UTC 24 |
139965778 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.1513471069 |
|
|
Sep 24 05:24:10 PM UTC 24 |
Sep 24 05:24:15 PM UTC 24 |
141350730 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.3268941467 |
|
|
Sep 24 05:24:10 PM UTC 24 |
Sep 24 05:24:15 PM UTC 24 |
103465330 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.1237491032 |
|
|
Sep 24 05:24:10 PM UTC 24 |
Sep 24 05:24:15 PM UTC 24 |
1586427375 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.1127830197 |
|
|
Sep 24 05:24:10 PM UTC 24 |
Sep 24 05:24:15 PM UTC 24 |
111289063 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.2373681023 |
|
|
Sep 24 05:24:10 PM UTC 24 |
Sep 24 05:24:15 PM UTC 24 |
151186996 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.477633924 |
|
|
Sep 24 05:24:10 PM UTC 24 |
Sep 24 05:24:16 PM UTC 24 |
257995184 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.2599903603 |
|
|
Sep 24 05:23:48 PM UTC 24 |
Sep 24 05:24:17 PM UTC 24 |
3533728472 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.1588264423 |
|
|
Sep 24 05:24:12 PM UTC 24 |
Sep 24 05:24:17 PM UTC 24 |
128782217 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.804827217 |
|
|
Sep 24 05:24:12 PM UTC 24 |
Sep 24 05:24:17 PM UTC 24 |
260696681 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.2868170378 |
|
|
Sep 24 05:24:12 PM UTC 24 |
Sep 24 05:24:17 PM UTC 24 |
153722490 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.1842265703 |
|
|
Sep 24 05:24:12 PM UTC 24 |
Sep 24 05:24:17 PM UTC 24 |
187663955 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.4082598796 |
|
|
Sep 24 05:24:12 PM UTC 24 |
Sep 24 05:24:17 PM UTC 24 |
598512484 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.3160842786 |
|
|
Sep 24 05:24:12 PM UTC 24 |
Sep 24 05:24:17 PM UTC 24 |
183226361 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.2099697522 |
|
|
Sep 24 05:24:12 PM UTC 24 |
Sep 24 05:24:18 PM UTC 24 |
154970528 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.2600253796 |
|
|
Sep 24 05:24:13 PM UTC 24 |
Sep 24 05:24:18 PM UTC 24 |
202603533 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.1228930435 |
|
|
Sep 24 05:24:13 PM UTC 24 |
Sep 24 05:24:18 PM UTC 24 |
1874208235 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.1277788102 |
|
|
Sep 24 05:23:50 PM UTC 24 |
Sep 24 05:24:18 PM UTC 24 |
1806009609 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.468546721 |
|
|
Sep 24 05:24:13 PM UTC 24 |
Sep 24 05:24:18 PM UTC 24 |
2335841355 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.2667795690 |
|
|
Sep 24 05:24:12 PM UTC 24 |
Sep 24 05:24:19 PM UTC 24 |
1493938276 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.424491947 |
|
|
Sep 24 05:21:28 PM UTC 24 |
Sep 24 05:24:20 PM UTC 24 |
14417308610 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.3810556053 |
|
|
Sep 24 05:20:28 PM UTC 24 |
Sep 24 05:24:23 PM UTC 24 |
34291979180 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.1771336915 |
|
|
Sep 24 05:22:21 PM UTC 24 |
Sep 24 05:24:25 PM UTC 24 |
64177666381 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.3187729412 |
|
|
Sep 24 05:21:36 PM UTC 24 |
Sep 24 05:24:43 PM UTC 24 |
18759834709 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.2119656234 |
|
|
Sep 24 05:21:30 PM UTC 24 |
Sep 24 05:24:51 PM UTC 24 |
10437313693 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.763363457 |
|
|
Sep 24 05:20:38 PM UTC 24 |
Sep 24 05:24:51 PM UTC 24 |
21776799491 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.2270457136 |
|
|
Sep 24 05:22:13 PM UTC 24 |
Sep 24 05:24:52 PM UTC 24 |
10482715729 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.1316800193 |
|
|
Sep 24 05:21:57 PM UTC 24 |
Sep 24 05:24:57 PM UTC 24 |
15211856559 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all.1908777178 |
|
|
Sep 24 05:20:13 PM UTC 24 |
Sep 24 05:25:24 PM UTC 24 |
103124974333 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all.1601071988 |
|
|
Sep 24 05:20:59 PM UTC 24 |
Sep 24 05:25:39 PM UTC 24 |
127476891975 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.3486666120 |
|
|
Sep 24 05:22:32 PM UTC 24 |
Sep 24 05:25:51 PM UTC 24 |
10340996192 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.3975650187 |
|
|
Sep 24 05:21:53 PM UTC 24 |
Sep 24 05:25:58 PM UTC 24 |
13105568514 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3791145714 |
|
|
Sep 24 05:24:13 PM UTC 24 |
Sep 24 05:24:16 PM UTC 24 |
35898111 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2793694963 |
|
|
Sep 24 05:24:13 PM UTC 24 |
Sep 24 05:24:16 PM UTC 24 |
69760166 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.2594377937 |
|
|
Sep 24 05:24:13 PM UTC 24 |
Sep 24 05:24:16 PM UTC 24 |
68529670 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.2633106026 |
|
|
Sep 24 05:24:13 PM UTC 24 |
Sep 24 05:24:16 PM UTC 24 |
68955663 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.296506571 |
|
|
Sep 24 05:24:13 PM UTC 24 |
Sep 24 05:24:17 PM UTC 24 |
138218225 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.3234202888 |
|
|
Sep 24 05:24:15 PM UTC 24 |
Sep 24 05:24:17 PM UTC 24 |
38950038 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.1508523750 |
|
|
Sep 24 05:24:15 PM UTC 24 |
Sep 24 05:24:17 PM UTC 24 |
68269775 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2014170108 |
|
|
Sep 24 05:24:15 PM UTC 24 |
Sep 24 05:24:17 PM UTC 24 |
137044205 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1880121680 |
|
|
Sep 24 05:24:15 PM UTC 24 |
Sep 24 05:24:18 PM UTC 24 |
91382896 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1595564198 |
|
|
Sep 24 05:24:15 PM UTC 24 |
Sep 24 05:24:18 PM UTC 24 |
72729012 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2629754974 |
|
|
Sep 24 05:24:15 PM UTC 24 |
Sep 24 05:24:18 PM UTC 24 |
1080774728 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.540544471 |
|
|
Sep 24 05:24:15 PM UTC 24 |
Sep 24 05:24:19 PM UTC 24 |
390487645 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2640547083 |
|
|
Sep 24 05:24:13 PM UTC 24 |
Sep 24 05:24:19 PM UTC 24 |
142783638 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1880116815 |
|
|
Sep 24 05:24:15 PM UTC 24 |
Sep 24 05:24:19 PM UTC 24 |
271010234 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2527260666 |
|
|
Sep 24 05:24:15 PM UTC 24 |
Sep 24 05:24:20 PM UTC 24 |
83926016 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.1876237271 |
|
|
Sep 24 05:24:17 PM UTC 24 |
Sep 24 05:24:20 PM UTC 24 |
39683229 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.3883721907 |
|
|
Sep 24 05:24:17 PM UTC 24 |
Sep 24 05:24:20 PM UTC 24 |
589157317 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.3944593681 |
|
|
Sep 24 05:24:17 PM UTC 24 |
Sep 24 05:24:20 PM UTC 24 |
137035714 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.2448541437 |
|
|
Sep 24 05:24:18 PM UTC 24 |
Sep 24 05:24:20 PM UTC 24 |
71007365 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3417431412 |
|
|
Sep 24 05:24:18 PM UTC 24 |
Sep 24 05:24:20 PM UTC 24 |
43019706 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.4074698849 |
|
|
Sep 24 05:24:17 PM UTC 24 |
Sep 24 05:24:20 PM UTC 24 |
157967075 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.2066376802 |
|
|
Sep 24 05:24:17 PM UTC 24 |
Sep 24 05:24:20 PM UTC 24 |
87831659 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.262726840 |
|
|
Sep 24 05:24:17 PM UTC 24 |
Sep 24 05:24:21 PM UTC 24 |
648677529 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1570935467 |
|
|
Sep 24 05:24:17 PM UTC 24 |
Sep 24 05:24:21 PM UTC 24 |
1535285902 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.560729103 |
|
|
Sep 24 05:24:18 PM UTC 24 |
Sep 24 05:24:22 PM UTC 24 |
215466303 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1111123277 |
|
|
Sep 24 05:24:18 PM UTC 24 |
Sep 24 05:24:22 PM UTC 24 |
223358673 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.328409402 |
|
|
Sep 24 05:24:18 PM UTC 24 |
Sep 24 05:24:22 PM UTC 24 |
388881326 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.4139150989 |
|
|
Sep 24 05:24:15 PM UTC 24 |
Sep 24 05:24:22 PM UTC 24 |
1301709723 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2990719072 |
|
|
Sep 24 05:24:17 PM UTC 24 |
Sep 24 05:24:23 PM UTC 24 |
66438113 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1005945924 |
|
|
Sep 24 05:24:21 PM UTC 24 |
Sep 24 05:24:24 PM UTC 24 |
135691908 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2008353924 |
|
|
Sep 24 05:24:18 PM UTC 24 |
Sep 24 05:24:24 PM UTC 24 |
225117346 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.4180496611 |
|
|
Sep 24 05:24:22 PM UTC 24 |
Sep 24 05:24:29 PM UTC 24 |
198506638 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3105811232 |
|
|
Sep 24 05:24:22 PM UTC 24 |
Sep 24 05:24:24 PM UTC 24 |
74303374 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.57108082 |
|
|
Sep 24 05:24:21 PM UTC 24 |
Sep 24 05:24:24 PM UTC 24 |
41664641 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.3323943077 |
|
|
Sep 24 05:24:22 PM UTC 24 |
Sep 24 05:24:24 PM UTC 24 |
143417764 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.1542986764 |
|
|
Sep 24 05:24:21 PM UTC 24 |
Sep 24 05:24:24 PM UTC 24 |
141928683 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2806197963 |
|
|
Sep 24 05:24:22 PM UTC 24 |
Sep 24 05:24:24 PM UTC 24 |
78313183 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2473603455 |
|
|
Sep 24 05:24:17 PM UTC 24 |
Sep 24 05:24:24 PM UTC 24 |
2511107999 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1669365868 |
|
|
Sep 24 05:24:15 PM UTC 24 |
Sep 24 05:24:25 PM UTC 24 |
550672240 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3404529562 |
|
|
Sep 24 05:24:21 PM UTC 24 |
Sep 24 05:24:25 PM UTC 24 |
1078298727 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1258819822 |
|
|
Sep 24 05:24:22 PM UTC 24 |
Sep 24 05:24:25 PM UTC 24 |
70054832 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2996581811 |
|
|
Sep 24 05:24:13 PM UTC 24 |
Sep 24 05:24:25 PM UTC 24 |
798138649 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.1746159514 |
|
|
Sep 24 05:24:22 PM UTC 24 |
Sep 24 05:24:25 PM UTC 24 |
36085053 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3465050578 |
|
|
Sep 24 05:24:22 PM UTC 24 |
Sep 24 05:24:25 PM UTC 24 |
76613367 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.1326187430 |
|
|
Sep 24 05:24:22 PM UTC 24 |
Sep 24 05:24:25 PM UTC 24 |
77916148 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.1986615269 |
|
|
Sep 24 05:24:22 PM UTC 24 |
Sep 24 05:24:25 PM UTC 24 |
68684536 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2557388858 |
|
|
Sep 24 05:24:21 PM UTC 24 |
Sep 24 05:24:25 PM UTC 24 |
266119741 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.492560877 |
|
|
Sep 24 05:24:21 PM UTC 24 |
Sep 24 05:24:25 PM UTC 24 |
87710189 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.4067912953 |
|
|
Sep 24 05:24:15 PM UTC 24 |
Sep 24 05:24:25 PM UTC 24 |
1257157566 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.2641511690 |
|
|
Sep 24 05:24:22 PM UTC 24 |
Sep 24 05:24:26 PM UTC 24 |
265118677 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3399621047 |
|
|
Sep 24 05:24:22 PM UTC 24 |
Sep 24 05:24:26 PM UTC 24 |
706617104 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.544191852 |
|
|
Sep 24 05:24:21 PM UTC 24 |
Sep 24 05:24:26 PM UTC 24 |
110354973 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1847067376 |
|
|
Sep 24 05:24:22 PM UTC 24 |
Sep 24 05:24:26 PM UTC 24 |
806848061 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.3057127286 |
|
|
Sep 24 05:24:22 PM UTC 24 |
Sep 24 05:24:26 PM UTC 24 |
77403123 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2733945361 |
|
|
Sep 24 05:24:21 PM UTC 24 |
Sep 24 05:24:26 PM UTC 24 |
118124829 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1449507204 |
|
|
Sep 24 05:24:22 PM UTC 24 |
Sep 24 05:24:27 PM UTC 24 |
124601240 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.1064186658 |
|
|
Sep 24 05:24:25 PM UTC 24 |
Sep 24 05:24:27 PM UTC 24 |
143386527 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3071132290 |
|
|
Sep 24 05:24:22 PM UTC 24 |
Sep 24 05:24:27 PM UTC 24 |
108349144 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3744951684 |
|
|
Sep 24 05:24:25 PM UTC 24 |
Sep 24 05:24:27 PM UTC 24 |
71469513 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.1601913916 |
|
|
Sep 24 05:24:25 PM UTC 24 |
Sep 24 05:24:28 PM UTC 24 |
42183820 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.3176034132 |
|
|
Sep 24 05:24:25 PM UTC 24 |
Sep 24 05:24:28 PM UTC 24 |
74647432 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.793567008 |
|
|
Sep 24 05:24:25 PM UTC 24 |
Sep 24 05:24:28 PM UTC 24 |
73097869 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.4151614854 |
|
|
Sep 24 05:24:25 PM UTC 24 |
Sep 24 05:24:28 PM UTC 24 |
171957760 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.2852944263 |
|
|
Sep 24 05:24:18 PM UTC 24 |
Sep 24 05:24:28 PM UTC 24 |
3079671874 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2276329017 |
|
|
Sep 24 05:24:22 PM UTC 24 |
Sep 24 05:24:28 PM UTC 24 |
240860080 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.862672410 |
|
|
Sep 24 05:24:21 PM UTC 24 |
Sep 24 05:24:28 PM UTC 24 |
233384589 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.4175793680 |
|
|
Sep 24 05:24:27 PM UTC 24 |
Sep 24 05:24:31 PM UTC 24 |
146722223 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.482682667 |
|
|
Sep 24 05:24:25 PM UTC 24 |
Sep 24 05:24:29 PM UTC 24 |
270676839 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.1387135560 |
|
|
Sep 24 05:24:25 PM UTC 24 |
Sep 24 05:24:29 PM UTC 24 |
187030487 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3831890788 |
|
|
Sep 24 05:24:25 PM UTC 24 |
Sep 24 05:24:30 PM UTC 24 |
262600712 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.2446956556 |
|
|
Sep 24 05:24:25 PM UTC 24 |
Sep 24 05:24:30 PM UTC 24 |
1604192733 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2563414383 |
|
|
Sep 24 05:24:22 PM UTC 24 |
Sep 24 05:24:30 PM UTC 24 |
625436938 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.1561486453 |
|
|
Sep 24 05:24:27 PM UTC 24 |
Sep 24 05:24:30 PM UTC 24 |
76960063 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.3665572427 |
|
|
Sep 24 05:24:27 PM UTC 24 |
Sep 24 05:24:30 PM UTC 24 |
68727316 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2425111248 |
|
|
Sep 24 05:24:25 PM UTC 24 |
Sep 24 05:24:30 PM UTC 24 |
218289009 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.1963948529 |
|
|
Sep 24 05:24:25 PM UTC 24 |
Sep 24 05:24:30 PM UTC 24 |
67449841 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.607925951 |
|
|
Sep 24 05:24:27 PM UTC 24 |
Sep 24 05:24:31 PM UTC 24 |
171088102 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.92473968 |
|
|
Sep 24 05:24:28 PM UTC 24 |
Sep 24 05:24:31 PM UTC 24 |
154721470 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.3050221218 |
|
|
Sep 24 05:24:28 PM UTC 24 |
Sep 24 05:24:31 PM UTC 24 |
147731644 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.64987279 |
|
|
Sep 24 05:24:32 PM UTC 24 |
Sep 24 05:24:36 PM UTC 24 |
535179379 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1731805512 |
|
|
Sep 24 05:24:27 PM UTC 24 |
Sep 24 05:24:31 PM UTC 24 |
675257447 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.174387828 |
|
|
Sep 24 05:24:28 PM UTC 24 |
Sep 24 05:24:31 PM UTC 24 |
564373765 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.475447869 |
|
|
Sep 24 05:24:28 PM UTC 24 |
Sep 24 05:24:31 PM UTC 24 |
556884609 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1576599346 |
|
|
Sep 24 05:24:27 PM UTC 24 |
Sep 24 05:24:31 PM UTC 24 |
75948344 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.896869487 |
|
|
Sep 24 05:24:28 PM UTC 24 |
Sep 24 05:24:31 PM UTC 24 |
88976845 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.1524709522 |
|
|
Sep 24 05:24:27 PM UTC 24 |
Sep 24 05:24:31 PM UTC 24 |
138180147 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3293770820 |
|
|
Sep 24 05:24:27 PM UTC 24 |
Sep 24 05:24:31 PM UTC 24 |
704667486 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.477512884 |
|
|
Sep 24 05:24:28 PM UTC 24 |
Sep 24 05:24:31 PM UTC 24 |
244908210 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.98468209 |
|
|
Sep 24 05:24:27 PM UTC 24 |
Sep 24 05:24:31 PM UTC 24 |
164161513 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.4099352235 |
|
|
Sep 24 05:24:27 PM UTC 24 |
Sep 24 05:24:32 PM UTC 24 |
131734964 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.2950250650 |
|
|
Sep 24 05:24:29 PM UTC 24 |
Sep 24 05:24:32 PM UTC 24 |
40331836 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2063177290 |
|
|
Sep 24 05:24:28 PM UTC 24 |
Sep 24 05:24:32 PM UTC 24 |
123339080 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2210565428 |
|
|
Sep 24 05:24:28 PM UTC 24 |
Sep 24 05:24:32 PM UTC 24 |
123984427 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.1704707529 |
|
|
Sep 24 05:24:27 PM UTC 24 |
Sep 24 05:24:32 PM UTC 24 |
197251627 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.1044501848 |
|
|
Sep 24 05:24:30 PM UTC 24 |
Sep 24 05:24:32 PM UTC 24 |
151071616 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3510384656 |
|
|
Sep 24 05:24:29 PM UTC 24 |
Sep 24 05:24:32 PM UTC 24 |
81760786 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.2780765215 |
|
|
Sep 24 05:24:29 PM UTC 24 |
Sep 24 05:24:33 PM UTC 24 |
275860351 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3851929056 |
|
|
Sep 24 05:24:30 PM UTC 24 |
Sep 24 05:24:33 PM UTC 24 |
46243091 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.363287853 |
|
|
Sep 24 05:24:29 PM UTC 24 |
Sep 24 05:24:33 PM UTC 24 |
779560845 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.2709645577 |
|
|
Sep 24 05:24:30 PM UTC 24 |
Sep 24 05:24:33 PM UTC 24 |
282078057 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.3520214287 |
|
|
Sep 24 05:24:29 PM UTC 24 |
Sep 24 05:24:33 PM UTC 24 |
200147029 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3126059038 |
|
|
Sep 24 05:24:27 PM UTC 24 |
Sep 24 05:24:33 PM UTC 24 |
149412984 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1374346355 |
|
|
Sep 24 05:24:28 PM UTC 24 |
Sep 24 05:24:34 PM UTC 24 |
73233996 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.223753305 |
|
|
Sep 24 05:24:29 PM UTC 24 |
Sep 24 05:24:34 PM UTC 24 |
440167749 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.1613441449 |
|
|
Sep 24 05:24:30 PM UTC 24 |
Sep 24 05:24:34 PM UTC 24 |
170880912 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.3537683183 |
|
|
Sep 24 05:24:32 PM UTC 24 |
Sep 24 05:24:35 PM UTC 24 |
71634574 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3065920528 |
|
|
Sep 24 05:24:32 PM UTC 24 |
Sep 24 05:24:36 PM UTC 24 |
57665755 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.1865874323 |
|
|
Sep 24 05:24:32 PM UTC 24 |
Sep 24 05:24:36 PM UTC 24 |
81175106 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.3983908036 |
|
|
Sep 24 05:24:32 PM UTC 24 |
Sep 24 05:24:36 PM UTC 24 |
561760118 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2324153503 |
|
|
Sep 24 05:24:32 PM UTC 24 |
Sep 24 05:24:36 PM UTC 24 |
50613664 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.2526318481 |
|
|
Sep 24 05:24:39 PM UTC 24 |
Sep 24 05:24:41 PM UTC 24 |
39286339 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.2796607908 |
|
|
Sep 24 05:24:29 PM UTC 24 |
Sep 24 05:24:36 PM UTC 24 |
81107816 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.2529737852 |
|
|
Sep 24 05:24:32 PM UTC 24 |
Sep 24 05:24:36 PM UTC 24 |
86774350 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.899472599 |
|
|
Sep 24 05:24:25 PM UTC 24 |
Sep 24 05:24:36 PM UTC 24 |
1587756934 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.1464523408 |
|
|
Sep 24 05:24:39 PM UTC 24 |
Sep 24 05:24:41 PM UTC 24 |
148551459 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.2692448094 |
|
|
Sep 24 05:24:32 PM UTC 24 |
Sep 24 05:24:36 PM UTC 24 |
43158809 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2827873264 |
|
|
Sep 24 05:24:29 PM UTC 24 |
Sep 24 05:24:37 PM UTC 24 |
2624104526 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.2173792615 |
|
|
Sep 24 05:24:32 PM UTC 24 |
Sep 24 05:24:37 PM UTC 24 |
250547198 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.4094471547 |
|
|
Sep 24 05:24:18 PM UTC 24 |
Sep 24 05:24:37 PM UTC 24 |
20107731471 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.2762094665 |
|
|
Sep 24 05:24:32 PM UTC 24 |
Sep 24 05:24:37 PM UTC 24 |
166088538 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.901577391 |
|
|
Sep 24 05:24:32 PM UTC 24 |
Sep 24 05:24:37 PM UTC 24 |
330262863 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.997317712 |
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|
Sep 24 05:24:34 PM UTC 24 |
Sep 24 05:24:37 PM UTC 24 |
39526664 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.3839497724 |
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|
Sep 24 05:24:34 PM UTC 24 |
Sep 24 05:24:37 PM UTC 24 |
148337768 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.4096654228 |
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|
Sep 24 05:24:34 PM UTC 24 |
Sep 24 05:24:37 PM UTC 24 |
72395706 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.1704070423 |
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|
Sep 24 05:24:34 PM UTC 24 |
Sep 24 05:24:37 PM UTC 24 |
540197014 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.3018510792 |
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|
Sep 24 05:24:34 PM UTC 24 |
Sep 24 05:24:37 PM UTC 24 |
68340447 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.4190327481 |
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Sep 24 05:24:32 PM UTC 24 |
Sep 24 05:24:37 PM UTC 24 |
68375051 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.2058977606 |
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Sep 24 05:24:32 PM UTC 24 |
Sep 24 05:24:37 PM UTC 24 |
115803011 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.3592401051 |
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Sep 24 05:24:39 PM UTC 24 |
Sep 24 05:24:42 PM UTC 24 |
74951237 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.89373605 |
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|
Sep 24 05:24:34 PM UTC 24 |
Sep 24 05:24:37 PM UTC 24 |
40370653 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3883003666 |
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|
Sep 24 05:24:32 PM UTC 24 |
Sep 24 05:24:37 PM UTC 24 |
166364803 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.2728098373 |
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|
Sep 24 05:24:34 PM UTC 24 |
Sep 24 05:24:37 PM UTC 24 |
77477292 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.1184716767 |
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Sep 24 05:24:34 PM UTC 24 |
Sep 24 05:24:38 PM UTC 24 |
54983823 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.662257723 |
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Sep 24 05:24:34 PM UTC 24 |
Sep 24 05:24:38 PM UTC 24 |
65384365 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.3107820177 |
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Sep 24 05:24:34 PM UTC 24 |
Sep 24 05:24:38 PM UTC 24 |
577256308 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2061536805 |
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Sep 24 05:24:17 PM UTC 24 |
Sep 24 05:24:38 PM UTC 24 |
2454586849 ps |