| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 95.10 | 93.68 | 96.65 | 96.02 | 92.29 | 97.50 | 96.37 | 93.21 |
| T344 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1081420057 | Sep 24 05:24:34 PM UTC 24 | Sep 24 05:24:38 PM UTC 24 | 48021514 ps | ||
| T1264 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.401669570 | Sep 24 05:24:34 PM UTC 24 | Sep 24 05:24:38 PM UTC 24 | 539047316 ps | ||
| T1265 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.2327631013 | Sep 24 05:24:34 PM UTC 24 | Sep 24 05:24:38 PM UTC 24 | 132254776 ps | ||
| T1266 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.4187861710 | Sep 24 05:24:34 PM UTC 24 | Sep 24 05:24:38 PM UTC 24 | 552349097 ps | ||
| T1267 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.3011979067 | Sep 24 05:24:35 PM UTC 24 | Sep 24 05:24:38 PM UTC 24 | 37791076 ps | ||
| T1268 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2690660027 | Sep 24 05:24:32 PM UTC 24 | Sep 24 05:24:38 PM UTC 24 | 217813383 ps | ||
| T1269 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.909736959 | Sep 24 05:24:35 PM UTC 24 | Sep 24 05:24:38 PM UTC 24 | 148013104 ps | ||
| T1270 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.4010485800 | Sep 24 05:24:35 PM UTC 24 | Sep 24 05:24:38 PM UTC 24 | 127565508 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.751904306 | Sep 24 05:24:35 PM UTC 24 | Sep 24 05:24:38 PM UTC 24 | 148791174 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.1269287746 | Sep 24 05:24:37 PM UTC 24 | Sep 24 05:24:39 PM UTC 24 | 42457511 ps | ||
| T1273 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.2637912116 | Sep 24 05:24:37 PM UTC 24 | Sep 24 05:24:39 PM UTC 24 | 150706927 ps | ||
| T1274 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.4160168697 | Sep 24 05:24:37 PM UTC 24 | Sep 24 05:24:39 PM UTC 24 | 48192878 ps | ||
| T1275 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.3820426708 | Sep 24 05:24:37 PM UTC 24 | Sep 24 05:24:39 PM UTC 24 | 38478131 ps | ||
| T1276 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.1059977615 | Sep 24 05:24:37 PM UTC 24 | Sep 24 05:24:39 PM UTC 24 | 39783260 ps | ||
| T1277 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.1898293253 | Sep 24 05:24:37 PM UTC 24 | Sep 24 05:24:40 PM UTC 24 | 628488985 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.3165412183 | Sep 24 05:24:32 PM UTC 24 | Sep 24 05:24:40 PM UTC 24 | 376809771 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1752984856 | Sep 24 05:24:21 PM UTC 24 | Sep 24 05:24:40 PM UTC 24 | 1448455749 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.3467306787 | Sep 24 05:24:28 PM UTC 24 | Sep 24 05:24:41 PM UTC 24 | 9802011402 ps | ||
| T1278 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.2333498469 | Sep 24 05:24:39 PM UTC 24 | Sep 24 05:24:41 PM UTC 24 | 39845010 ps | ||
| T1279 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.2412564135 | Sep 24 05:24:39 PM UTC 24 | Sep 24 05:24:41 PM UTC 24 | 51912848 ps | ||
| T1280 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.3425310895 | Sep 24 05:24:39 PM UTC 24 | Sep 24 05:24:41 PM UTC 24 | 57292500 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.1597935801 | Sep 24 05:24:22 PM UTC 24 | Sep 24 05:24:41 PM UTC 24 | 1266666090 ps | ||
| T1281 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.3323874471 | Sep 24 05:24:39 PM UTC 24 | Sep 24 05:24:42 PM UTC 24 | 72557636 ps | ||
| T1282 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.1904549169 | Sep 24 05:24:39 PM UTC 24 | Sep 24 05:24:42 PM UTC 24 | 133198000 ps | ||
| T1283 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.719714959 | Sep 24 05:24:39 PM UTC 24 | Sep 24 05:24:42 PM UTC 24 | 530467213 ps | ||
| T1284 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.53798031 | Sep 24 05:24:39 PM UTC 24 | Sep 24 05:24:42 PM UTC 24 | 566701022 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.728613734 | Sep 24 05:24:22 PM UTC 24 | Sep 24 05:24:42 PM UTC 24 | 2556706426 ps | ||
| T399 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1270683430 | Sep 24 05:24:29 PM UTC 24 | Sep 24 05:24:43 PM UTC 24 | 10267378769 ps | ||
| T401 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.4288649291 | Sep 24 05:24:32 PM UTC 24 | Sep 24 05:24:43 PM UTC 24 | 1209276044 ps | ||
| T1285 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1798131699 | Sep 24 05:24:33 PM UTC 24 | Sep 24 05:24:44 PM UTC 24 | 1955617395 ps | ||
| T1286 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.4127174605 | Sep 24 05:24:28 PM UTC 24 | Sep 24 05:24:44 PM UTC 24 | 9906286908 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3011361885 | Sep 24 05:24:32 PM UTC 24 | Sep 24 05:24:45 PM UTC 24 | 758476171 ps | ||
| T1287 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2239016726 | Sep 24 05:24:27 PM UTC 24 | Sep 24 05:24:45 PM UTC 24 | 1214574040 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.716778037 | Sep 24 05:24:27 PM UTC 24 | Sep 24 05:24:46 PM UTC 24 | 1281541387 ps | ||
| T402 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1738819794 | Sep 24 05:24:25 PM UTC 24 | Sep 24 05:24:47 PM UTC 24 | 18953946359 ps | ||
| T403 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1052306317 | Sep 24 05:24:30 PM UTC 24 | Sep 24 05:24:48 PM UTC 24 | 1285492700 ps | ||
| T1288 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1975069189 | Sep 24 05:24:32 PM UTC 24 | Sep 24 05:24:49 PM UTC 24 | 10255126782 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2150180178 | Sep 24 05:24:25 PM UTC 24 | Sep 24 05:24:53 PM UTC 24 | 20150751384 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_req.1878716233 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1126817622 ps |
| CPU time | 10.78 seconds |
| Started | Sep 24 05:15:04 PM UTC 24 |
| Finished | Sep 24 05:15:15 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878716233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.1878716233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_check_fail.913041485 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 631928451 ps |
| CPU time | 8.02 seconds |
| Started | Sep 24 05:15:20 PM UTC 24 |
| Finished | Sep 24 05:15:29 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913041485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.913041485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_test_access.256564066 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3323319691 ps |
| CPU time | 17.07 seconds |
| Started | Sep 24 05:15:15 PM UTC 24 |
| Finished | Sep 24 05:15:33 PM UTC 24 |
| Peak memory | 252112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256564066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.256564066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.966092685 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2126804118 ps |
| CPU time | 76.29 seconds |
| Started | Sep 24 05:15:35 PM UTC 24 |
| Finished | Sep 24 05:16:53 PM UTC 24 |
| Peak memory | 258200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=966092685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.966092685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_key_req.4058963011 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 2633566037 ps |
| CPU time | 20.69 seconds |
| Started | Sep 24 05:15:15 PM UTC 24 |
| Finished | Sep 24 05:15:37 PM UTC 24 |
| Peak memory | 252048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058963011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.4058963011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all.1909165895 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 66624759140 ps |
| CPU time | 147.91 seconds |
| Started | Sep 24 05:15:47 PM UTC 24 |
| Finished | Sep 24 05:18:18 PM UTC 24 |
| Peak memory | 268428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909165895 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.1909165895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_check_fail.2520712443 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4383436284 ps |
| CPU time | 23.77 seconds |
| Started | Sep 24 05:15:56 PM UTC 24 |
| Finished | Sep 24 05:16:21 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520712443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.2520712443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_sec_cm.1233975762 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 21849008439 ps |
| CPU time | 198.76 seconds |
| Started | Sep 24 05:15:15 PM UTC 24 |
| Finished | Sep 24 05:18:37 PM UTC 24 |
| Peak memory | 299556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233975762 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.1233975762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_esc.1575931421 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 942639522 ps |
| CPU time | 6.77 seconds |
| Started | Sep 24 05:15:09 PM UTC 24 |
| Finished | Sep 24 05:15:17 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575931421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.1575931421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_check_fail.465334556 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 662149662 ps |
| CPU time | 17.9 seconds |
| Started | Sep 24 05:15:36 PM UTC 24 |
| Finished | Sep 24 05:15:56 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465334556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.465334556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_init_fail.2153057589 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 195589491 ps |
| CPU time | 5.69 seconds |
| Started | Sep 24 05:15:36 PM UTC 24 |
| Finished | Sep 24 05:15:43 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153057589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.2153057589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all.3588113143 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 8102147640 ps |
| CPU time | 175.85 seconds |
| Started | Sep 24 05:15:20 PM UTC 24 |
| Finished | Sep 24 05:18:19 PM UTC 24 |
| Peak memory | 272452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588113143 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.3588113143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.783150939 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 7183683558 ps |
| CPU time | 140.79 seconds |
| Started | Sep 24 05:15:25 PM UTC 24 |
| Finished | Sep 24 05:17:48 PM UTC 24 |
| Peak memory | 258172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=783150939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.783150939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_macro_errs.3420585211 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 15445846681 ps |
| CPU time | 30.95 seconds |
| Started | Sep 24 05:15:25 PM UTC 24 |
| Finished | Sep 24 05:15:57 PM UTC 24 |
| Peak memory | 253960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420585211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.3420585211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_esc.150762600 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 137682635 ps |
| CPU time | 7.17 seconds |
| Started | Sep 24 05:16:20 PM UTC 24 |
| Finished | Sep 24 05:16:28 PM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150762600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.150762600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_key_req.468994894 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1190723113 ps |
| CPU time | 25.38 seconds |
| Started | Sep 24 05:15:25 PM UTC 24 |
| Finished | Sep 24 05:15:51 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468994894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.468994894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_init_fail.858427824 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 2263275234 ps |
| CPU time | 4.68 seconds |
| Started | Sep 24 05:23:36 PM UTC 24 |
| Finished | Sep 24 05:23:42 PM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858427824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.858427824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/175.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_regwen.2114371502 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 570962658 ps |
| CPU time | 7.35 seconds |
| Started | Sep 24 05:15:15 PM UTC 24 |
| Finished | Sep 24 05:15:23 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114371502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.2114371502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.4067912953 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 1257157566 ps |
| CPU time | 9.5 seconds |
| Started | Sep 24 05:24:15 PM UTC 24 |
| Finished | Sep 24 05:24:25 PM UTC 24 |
| Peak memory | 254992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067912953 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_intg_err.4067912953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_init_fail.791806062 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 175479488 ps |
| CPU time | 4.72 seconds |
| Started | Sep 24 05:16:01 PM UTC 24 |
| Finished | Sep 24 05:16:06 PM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791806062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.791806062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all.2791775740 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 8127243916 ps |
| CPU time | 132.98 seconds |
| Started | Sep 24 05:15:15 PM UTC 24 |
| Finished | Sep 24 05:17:31 PM UTC 24 |
| Peak memory | 271188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791775740 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.2791775740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_init_fail.485217722 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 123884812 ps |
| CPU time | 4.98 seconds |
| Started | Sep 24 05:23:02 PM UTC 24 |
| Finished | Sep 24 05:23:08 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485217722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.485217722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/123.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.424491947 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 14417308610 ps |
| CPU time | 168.38 seconds |
| Started | Sep 24 05:21:28 PM UTC 24 |
| Finished | Sep 24 05:24:20 PM UTC 24 |
| Peak memory | 258164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=424491947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.424491947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_init_fail.2627617645 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 478242390 ps |
| CPU time | 5.38 seconds |
| Started | Sep 24 05:15:44 PM UTC 24 |
| Finished | Sep 24 05:15:50 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627617645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.2627617645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_req.3148633787 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 9539440073 ps |
| CPU time | 20.03 seconds |
| Started | Sep 24 05:16:20 PM UTC 24 |
| Finished | Sep 24 05:16:41 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148633787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.3148633787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_background_chks.3427412249 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 2315877723 ps |
| CPU time | 29.08 seconds |
| Started | Sep 24 05:15:25 PM UTC 24 |
| Finished | Sep 24 05:15:55 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427412249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.3427412249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_alert_test.685098530 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 189320980 ps |
| CPU time | 1.66 seconds |
| Started | Sep 24 05:15:20 PM UTC 24 |
| Finished | Sep 24 05:15:23 PM UTC 24 |
| Peak memory | 250424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685098530 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.685098530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1880116815 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 271010234 ps |
| CPU time | 3.69 seconds |
| Started | Sep 24 05:24:15 PM UTC 24 |
| Finished | Sep 24 05:24:19 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880116815 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_aliasing.1880116815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_init_fail.686237708 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2325681364 ps |
| CPU time | 5.29 seconds |
| Started | Sep 24 05:15:17 PM UTC 24 |
| Finished | Sep 24 05:15:23 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686237708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.686237708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all.1010224780 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 29556680738 ps |
| CPU time | 175.58 seconds |
| Started | Sep 24 05:15:36 PM UTC 24 |
| Finished | Sep 24 05:18:35 PM UTC 24 |
| Peak memory | 288884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010224780 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.1010224780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_init_fail.421845117 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 193285684 ps |
| CPU time | 5.21 seconds |
| Started | Sep 24 05:21:30 PM UTC 24 |
| Finished | Sep 24 05:21:36 PM UTC 24 |
| Peak memory | 251736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421845117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.421845117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/66.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_macro_errs.2610520922 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 990515266 ps |
| CPU time | 30.01 seconds |
| Started | Sep 24 05:16:57 PM UTC 24 |
| Finished | Sep 24 05:17:29 PM UTC 24 |
| Peak memory | 256088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610520922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.2610520922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_init_fail.843097891 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 220735892 ps |
| CPU time | 4.38 seconds |
| Started | Sep 24 05:21:09 PM UTC 24 |
| Finished | Sep 24 05:21:14 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843097891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.843097891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/50.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.1454172621 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 3690988322 ps |
| CPU time | 145.48 seconds |
| Started | Sep 24 05:16:10 PM UTC 24 |
| Finished | Sep 24 05:18:38 PM UTC 24 |
| Peak memory | 274532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1454172621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.otp_ctrl_stress_all_with_rand_reset.1454172621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.1624815575 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 8983997969 ps |
| CPU time | 64.38 seconds |
| Started | Sep 24 05:22:23 PM UTC 24 |
| Finished | Sep 24 05:23:29 PM UTC 24 |
| Peak memory | 268336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1624815575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 91.otp_ctrl_stress_all_with_rand_reset.1624815575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all.2284581347 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 59190907162 ps |
| CPU time | 154.65 seconds |
| Started | Sep 24 05:16:46 PM UTC 24 |
| Finished | Sep 24 05:19:24 PM UTC 24 |
| Peak memory | 258056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284581347 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.2284581347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_test_access.1354315394 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 13228680555 ps |
| CPU time | 32.82 seconds |
| Started | Sep 24 05:15:32 PM UTC 24 |
| Finished | Sep 24 05:16:07 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354315394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.1354315394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_req.4031695110 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 601212936 ps |
| CPU time | 15.25 seconds |
| Started | Sep 24 05:15:17 PM UTC 24 |
| Finished | Sep 24 05:15:33 PM UTC 24 |
| Peak memory | 251952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031695110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.4031695110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_init_fail.4135921750 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 178883576 ps |
| CPU time | 4.72 seconds |
| Started | Sep 24 05:21:22 PM UTC 24 |
| Finished | Sep 24 05:21:28 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135921750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.4135921750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/59.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_check_fail.2414666271 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 7792270949 ps |
| CPU time | 25.01 seconds |
| Started | Sep 24 05:17:38 PM UTC 24 |
| Finished | Sep 24 05:18:04 PM UTC 24 |
| Peak memory | 254108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414666271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.2414666271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/21.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_errs.1256348450 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1138240191 ps |
| CPU time | 23.99 seconds |
| Started | Sep 24 05:15:25 PM UTC 24 |
| Finished | Sep 24 05:15:50 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256348450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.1256348450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.1506661292 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 13503861116 ps |
| CPU time | 148.91 seconds |
| Started | Sep 24 05:19:42 PM UTC 24 |
| Finished | Sep 24 05:22:13 PM UTC 24 |
| Peak memory | 260244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1506661292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 37.otp_ctrl_stress_all_with_rand_reset.1506661292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_init_fail.556677251 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 251641755 ps |
| CPU time | 5.52 seconds |
| Started | Sep 24 05:22:51 PM UTC 24 |
| Finished | Sep 24 05:22:57 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556677251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.556677251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/110.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_init_fail.1371896130 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 2341086719 ps |
| CPU time | 5 seconds |
| Started | Sep 24 05:21:13 PM UTC 24 |
| Finished | Sep 24 05:21:20 PM UTC 24 |
| Peak memory | 251952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371896130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.1371896130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/53.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_init_fail.3586302778 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 485934081 ps |
| CPU time | 3.73 seconds |
| Started | Sep 24 05:23:28 PM UTC 24 |
| Finished | Sep 24 05:23:33 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586302778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.3586302778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/160.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_key_req.2345116832 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1601147407 ps |
| CPU time | 27.81 seconds |
| Started | Sep 24 05:15:56 PM UTC 24 |
| Finished | Sep 24 05:16:25 PM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345116832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.2345116832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_init_fail.2202599169 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 154241847 ps |
| CPU time | 3.52 seconds |
| Started | Sep 24 05:15:20 PM UTC 24 |
| Finished | Sep 24 05:15:25 PM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202599169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.2202599169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_init_fail.1714063761 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 140449441 ps |
| CPU time | 5.51 seconds |
| Started | Sep 24 05:16:25 PM UTC 24 |
| Finished | Sep 24 05:16:32 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714063761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.1714063761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.3486666120 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 10340996192 ps |
| CPU time | 196.09 seconds |
| Started | Sep 24 05:22:32 PM UTC 24 |
| Finished | Sep 24 05:25:51 PM UTC 24 |
| Peak memory | 286932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3486666120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 97.otp_ctrl_stress_all_with_rand_reset.3486666120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/97.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_parallel_lc_esc.368130676 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 578882752 ps |
| CPU time | 7.14 seconds |
| Started | Sep 24 05:23:02 PM UTC 24 |
| Finished | Sep 24 05:23:10 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368130676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.368130676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/125.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1752984856 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 1448455749 ps |
| CPU time | 17.61 seconds |
| Started | Sep 24 05:24:21 PM UTC 24 |
| Finished | Sep 24 05:24:40 PM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752984856 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg_err.1752984856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_regwen.3695651181 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1247894175 ps |
| CPU time | 10.28 seconds |
| Started | Sep 24 05:15:20 PM UTC 24 |
| Finished | Sep 24 05:15:31 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695651181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.3695651181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_lock.614605050 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 8076595367 ps |
| CPU time | 22.24 seconds |
| Started | Sep 24 05:16:57 PM UTC 24 |
| Finished | Sep 24 05:17:21 PM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614605050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.614605050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.2191959980 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 7192073484 ps |
| CPU time | 121.5 seconds |
| Started | Sep 24 05:21:35 PM UTC 24 |
| Finished | Sep 24 05:23:39 PM UTC 24 |
| Peak memory | 268404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2191959980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 68.otp_ctrl_stress_all_with_rand_reset.2191959980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_check_fail.2668564824 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 12480138843 ps |
| CPU time | 36.74 seconds |
| Started | Sep 24 05:19:46 PM UTC 24 |
| Finished | Sep 24 05:20:25 PM UTC 24 |
| Peak memory | 252064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668564824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.2668564824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/38.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_init_fail.2225473546 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 485446833 ps |
| CPU time | 5.28 seconds |
| Started | Sep 24 05:15:50 PM UTC 24 |
| Finished | Sep 24 05:15:57 PM UTC 24 |
| Peak memory | 251724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225473546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.2225473546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_check_fail.508504478 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1803073928 ps |
| CPU time | 28.97 seconds |
| Started | Sep 24 05:16:15 PM UTC 24 |
| Finished | Sep 24 05:16:45 PM UTC 24 |
| Peak memory | 256020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508504478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.508504478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all.1840029281 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 23708757713 ps |
| CPU time | 124.52 seconds |
| Started | Sep 24 05:19:07 PM UTC 24 |
| Finished | Sep 24 05:21:14 PM UTC 24 |
| Peak memory | 270540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840029281 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.1840029281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_background_chks.2247148435 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 2800266175 ps |
| CPU time | 19.1 seconds |
| Started | Sep 24 05:15:36 PM UTC 24 |
| Finished | Sep 24 05:15:57 PM UTC 24 |
| Peak memory | 251972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247148435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.2247148435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_test_access.2022531873 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 6510989384 ps |
| CPU time | 16.9 seconds |
| Started | Sep 24 05:15:47 PM UTC 24 |
| Finished | Sep 24 05:16:05 PM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022531873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.2022531873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_regwen.431847330 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 468729848 ps |
| CPU time | 8.48 seconds |
| Started | Sep 24 05:16:01 PM UTC 24 |
| Finished | Sep 24 05:16:11 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431847330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.431847330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_init_fail.879529754 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 353415463 ps |
| CPU time | 6.03 seconds |
| Started | Sep 24 05:23:01 PM UTC 24 |
| Finished | Sep 24 05:23:09 PM UTC 24 |
| Peak memory | 251944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879529754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.879529754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/120.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_parallel_lc_esc.364218527 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 185149515 ps |
| CPU time | 4.7 seconds |
| Started | Sep 24 05:23:10 PM UTC 24 |
| Finished | Sep 24 05:23:16 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364218527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.364218527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/134.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_parallel_lc_esc.4163431190 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 10633884618 ps |
| CPU time | 30.04 seconds |
| Started | Sep 24 05:23:36 PM UTC 24 |
| Finished | Sep 24 05:24:08 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163431190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.4163431190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/172.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_parallel_lc_esc.3589954485 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 4536371870 ps |
| CPU time | 20.56 seconds |
| Started | Sep 24 05:21:51 PM UTC 24 |
| Finished | Sep 24 05:22:13 PM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589954485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.3589954485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/79.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_parallel_lc_esc.3605272132 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 766052554 ps |
| CPU time | 7.11 seconds |
| Started | Sep 24 05:22:22 PM UTC 24 |
| Finished | Sep 24 05:22:30 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605272132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.3605272132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/90.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_parallel_lc_esc.2897584457 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 4237933025 ps |
| CPU time | 11.82 seconds |
| Started | Sep 24 05:22:23 PM UTC 24 |
| Finished | Sep 24 05:22:36 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897584457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.2897584457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/92.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2150180178 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 20150751384 ps |
| CPU time | 26.78 seconds |
| Started | Sep 24 05:24:25 PM UTC 24 |
| Finished | Sep 24 05:24:53 PM UTC 24 |
| Peak memory | 255960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150180178 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_intg_err.2150180178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2793694963 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 69760166 ps |
| CPU time | 1.63 seconds |
| Started | Sep 24 05:24:13 PM UTC 24 |
| Finished | Sep 24 05:24:16 PM UTC 24 |
| Peak memory | 253344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793694963 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.2793694963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_req.2884764671 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 8139980400 ps |
| CPU time | 27.96 seconds |
| Started | Sep 24 05:15:36 PM UTC 24 |
| Finished | Sep 24 05:16:06 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884764671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.2884764671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_lock.3484805865 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 702155480 ps |
| CPU time | 11.72 seconds |
| Started | Sep 24 05:15:17 PM UTC 24 |
| Finished | Sep 24 05:15:30 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484805865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.3484805865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_check_fail.1499059949 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 3191188166 ps |
| CPU time | 23.81 seconds |
| Started | Sep 24 05:19:52 PM UTC 24 |
| Finished | Sep 24 05:20:17 PM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499059949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.1499059949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.1305846574 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 47736539793 ps |
| CPU time | 125.51 seconds |
| Started | Sep 24 05:15:56 PM UTC 24 |
| Finished | Sep 24 05:18:04 PM UTC 24 |
| Peak memory | 260268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1305846574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.otp_ctrl_stress_all_with_rand_reset.1305846574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all.1243040188 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 3427778386 ps |
| CPU time | 24.76 seconds |
| Started | Sep 24 05:20:09 PM UTC 24 |
| Finished | Sep 24 05:20:35 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243040188 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.1243040188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_check_fail.3891472036 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 832097500 ps |
| CPU time | 25.81 seconds |
| Started | Sep 24 05:17:15 PM UTC 24 |
| Finished | Sep 24 05:17:43 PM UTC 24 |
| Peak memory | 252124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891472036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.3891472036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_init_fail.3278021640 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1709564798 ps |
| CPU time | 6.44 seconds |
| Started | Sep 24 05:23:10 PM UTC 24 |
| Finished | Sep 24 05:23:18 PM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278021640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.3278021640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/132.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_key_req.1692720556 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 715915663 ps |
| CPU time | 20.01 seconds |
| Started | Sep 24 05:15:47 PM UTC 24 |
| Finished | Sep 24 05:16:08 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692720556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.1692720556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_init_fail.63467212 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2143444942 ps |
| CPU time | 6.71 seconds |
| Started | Sep 24 05:18:36 PM UTC 24 |
| Finished | Sep 24 05:18:43 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63467212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.63467212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/28.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_check_fail.487476008 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1552173843 ps |
| CPU time | 14.75 seconds |
| Started | Sep 24 05:16:25 PM UTC 24 |
| Finished | Sep 24 05:16:41 PM UTC 24 |
| Peak memory | 253972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487476008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.487476008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_background_chks.1782427709 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 7761098150 ps |
| CPU time | 10.76 seconds |
| Started | Sep 24 05:15:17 PM UTC 24 |
| Finished | Sep 24 05:15:28 PM UTC 24 |
| Peak memory | 254024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782427709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.1782427709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_esc.1354005754 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 490059270 ps |
| CPU time | 7.94 seconds |
| Started | Sep 24 05:17:44 PM UTC 24 |
| Finished | Sep 24 05:17:53 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354005754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.1354005754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.1316800193 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 15211856559 ps |
| CPU time | 176.2 seconds |
| Started | Sep 24 05:21:57 PM UTC 24 |
| Finished | Sep 24 05:24:57 PM UTC 24 |
| Peak memory | 260352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1316800193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 81.otp_ctrl_stress_all_with_rand_reset.1316800193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_macro_errs.24502409 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1916885685 ps |
| CPU time | 31.98 seconds |
| Started | Sep 24 05:16:10 PM UTC 24 |
| Finished | Sep 24 05:16:43 PM UTC 24 |
| Peak memory | 255940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24502409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.24502409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_init_fail.2622969606 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 202578374 ps |
| CPU time | 3.22 seconds |
| Started | Sep 24 05:15:04 PM UTC 24 |
| Finished | Sep 24 05:15:08 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622969606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.2622969606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_init_fail.3006530052 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 253222365 ps |
| CPU time | 4.38 seconds |
| Started | Sep 24 05:22:47 PM UTC 24 |
| Finished | Sep 24 05:22:53 PM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006530052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.3006530052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/106.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_init_fail.2595074183 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 155668736 ps |
| CPU time | 5.12 seconds |
| Started | Sep 24 05:23:01 PM UTC 24 |
| Finished | Sep 24 05:23:08 PM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595074183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.2595074183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/119.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1052306317 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1285492700 ps |
| CPU time | 17.1 seconds |
| Started | Sep 24 05:24:30 PM UTC 24 |
| Finished | Sep 24 05:24:48 PM UTC 24 |
| Peak memory | 255708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052306317 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_intg_err.1052306317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.1237491032 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 1586427375 ps |
| CPU time | 3.97 seconds |
| Started | Sep 24 05:24:10 PM UTC 24 |
| Finished | Sep 24 05:24:15 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237491032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.1237491032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/281.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_lock.3926371435 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1509796155 ps |
| CPU time | 16.07 seconds |
| Started | Sep 24 05:15:15 PM UTC 24 |
| Finished | Sep 24 05:15:32 PM UTC 24 |
| Peak memory | 252064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926371435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.3926371435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_wake_up.1986750154 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 51740699 ps |
| CPU time | 1.58 seconds |
| Started | Sep 24 05:14:52 PM UTC 24 |
| Finished | Sep 24 05:14:55 PM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986750154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes t +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.1986750154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_test_access.458931450 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1269855415 ps |
| CPU time | 30.78 seconds |
| Started | Sep 24 05:15:25 PM UTC 24 |
| Finished | Sep 24 05:15:57 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458931450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.458931450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_key_req.1622059697 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1196014193 ps |
| CPU time | 15.25 seconds |
| Started | Sep 24 05:16:44 PM UTC 24 |
| Finished | Sep 24 05:17:00 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622059697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.1622059697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_lock.1163652504 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 596714608 ps |
| CPU time | 18.03 seconds |
| Started | Sep 24 05:16:01 PM UTC 24 |
| Finished | Sep 24 05:16:20 PM UTC 24 |
| Peak memory | 251940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163652504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.1163652504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1669365868 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 550672240 ps |
| CPU time | 8.82 seconds |
| Started | Sep 24 05:24:15 PM UTC 24 |
| Finished | Sep 24 05:24:25 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669365868 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_bash.1669365868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.716778037 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 1281541387 ps |
| CPU time | 17.44 seconds |
| Started | Sep 24 05:24:27 PM UTC 24 |
| Finished | Sep 24 05:24:46 PM UTC 24 |
| Peak memory | 255636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716778037 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_intg_err.716778037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_init_fail.3746023932 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 509716418 ps |
| CPU time | 3.86 seconds |
| Started | Sep 24 05:23:05 PM UTC 24 |
| Finished | Sep 24 05:23:10 PM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746023932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.3746023932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/127.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_macro_errs.1992821747 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 4197144660 ps |
| CPU time | 32.45 seconds |
| Started | Sep 24 05:15:20 PM UTC 24 |
| Finished | Sep 24 05:15:54 PM UTC 24 |
| Peak memory | 252064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992821747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.1992821747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_check_fail.3315113621 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 618710175 ps |
| CPU time | 18.38 seconds |
| Started | Sep 24 05:18:44 PM UTC 24 |
| Finished | Sep 24 05:19:03 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315113621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.3315113621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.1803256129 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 164459293 ps |
| CPU time | 4.68 seconds |
| Started | Sep 24 05:24:01 PM UTC 24 |
| Finished | Sep 24 05:24:07 PM UTC 24 |
| Peak memory | 252012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803256129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.1803256129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/238.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_regwen.2217470385 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 288914548 ps |
| CPU time | 9.16 seconds |
| Started | Sep 24 05:15:39 PM UTC 24 |
| Finished | Sep 24 05:15:50 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217470385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.2217470385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.1730875962 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 293625822 ps |
| CPU time | 3.58 seconds |
| Started | Sep 24 05:24:01 PM UTC 24 |
| Finished | Sep 24 05:24:06 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730875962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.1730875962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/242.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all.1060655546 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 15132074329 ps |
| CPU time | 154.55 seconds |
| Started | Sep 24 05:16:25 PM UTC 24 |
| Finished | Sep 24 05:19:03 PM UTC 24 |
| Peak memory | 257996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060655546 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.1060655546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_background_chks.19076487 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 16878161879 ps |
| CPU time | 32.64 seconds |
| Started | Sep 24 05:15:04 PM UTC 24 |
| Finished | Sep 24 05:15:37 PM UTC 24 |
| Peak memory | 254148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19076487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.19076487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_smoke.3067031865 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 125437074 ps |
| CPU time | 4.25 seconds |
| Started | Sep 24 05:15:16 PM UTC 24 |
| Finished | Sep 24 05:15:22 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067031865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.3067031865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_parallel_lc_esc.3995208660 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 126904662 ps |
| CPU time | 6.09 seconds |
| Started | Sep 24 05:23:16 PM UTC 24 |
| Finished | Sep 24 05:23:26 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995208660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.3995208660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/142.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.296506571 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 138218225 ps |
| CPU time | 2.89 seconds |
| Started | Sep 24 05:24:13 PM UTC 24 |
| Finished | Sep 24 05:24:17 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296506571 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_reset.296506571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2629754974 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1080774728 ps |
| CPU time | 2.79 seconds |
| Started | Sep 24 05:24:15 PM UTC 24 |
| Finished | Sep 24 05:24:18 PM UTC 24 |
| Peak memory | 255912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2629754974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_cs r_mem_rw_with_rand_reset.2629754974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.2633106026 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 68955663 ps |
| CPU time | 1.83 seconds |
| Started | Sep 24 05:24:13 PM UTC 24 |
| Finished | Sep 24 05:24:16 PM UTC 24 |
| Peak memory | 239492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633106026 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.2633106026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3791145714 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 35898111 ps |
| CPU time | 1.62 seconds |
| Started | Sep 24 05:24:13 PM UTC 24 |
| Finished | Sep 24 05:24:16 PM UTC 24 |
| Peak memory | 239880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791145714 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_partial_access.3791145714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.2594377937 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 68529670 ps |
| CPU time | 1.78 seconds |
| Started | Sep 24 05:24:13 PM UTC 24 |
| Finished | Sep 24 05:24:16 PM UTC 24 |
| Peak memory | 241204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594377937 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.2594377937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1880121680 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 91382896 ps |
| CPU time | 1.97 seconds |
| Started | Sep 24 05:24:15 PM UTC 24 |
| Finished | Sep 24 05:24:18 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880121680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_same_csr_outstanding.1880121680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2640547083 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 142783638 ps |
| CPU time | 5.11 seconds |
| Started | Sep 24 05:24:13 PM UTC 24 |
| Finished | Sep 24 05:24:19 PM UTC 24 |
| Peak memory | 257340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640547083 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.2640547083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2996581811 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 798138649 ps |
| CPU time | 10.71 seconds |
| Started | Sep 24 05:24:13 PM UTC 24 |
| Finished | Sep 24 05:24:25 PM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996581811 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_intg_err.2996581811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2473603455 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 2511107999 ps |
| CPU time | 6.12 seconds |
| Started | Sep 24 05:24:17 PM UTC 24 |
| Finished | Sep 24 05:24:24 PM UTC 24 |
| Peak memory | 251564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473603455 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_aliasing.2473603455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2527260666 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 83926016 ps |
| CPU time | 3.69 seconds |
| Started | Sep 24 05:24:15 PM UTC 24 |
| Finished | Sep 24 05:24:20 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527260666 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_bash.2527260666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.540544471 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 390487645 ps |
| CPU time | 2.84 seconds |
| Started | Sep 24 05:24:15 PM UTC 24 |
| Finished | Sep 24 05:24:19 PM UTC 24 |
| Peak memory | 253288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540544471 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_reset.540544471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.2066376802 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 87831659 ps |
| CPU time | 2.09 seconds |
| Started | Sep 24 05:24:17 PM UTC 24 |
| Finished | Sep 24 05:24:20 PM UTC 24 |
| Peak memory | 255720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2066376802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_cs r_mem_rw_with_rand_reset.2066376802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1595564198 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 72729012 ps |
| CPU time | 1.75 seconds |
| Started | Sep 24 05:24:15 PM UTC 24 |
| Finished | Sep 24 05:24:18 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595564198 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.1595564198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.1508523750 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 68269775 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 05:24:15 PM UTC 24 |
| Finished | Sep 24 05:24:17 PM UTC 24 |
| Peak memory | 239928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508523750 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.1508523750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.3234202888 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 38950038 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 05:24:15 PM UTC 24 |
| Finished | Sep 24 05:24:17 PM UTC 24 |
| Peak memory | 238772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234202888 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_partial_access.3234202888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2014170108 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 137044205 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 05:24:15 PM UTC 24 |
| Finished | Sep 24 05:24:17 PM UTC 24 |
| Peak memory | 240412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014170108 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.2014170108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.262726840 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 648677529 ps |
| CPU time | 2.31 seconds |
| Started | Sep 24 05:24:17 PM UTC 24 |
| Finished | Sep 24 05:24:21 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262726840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_same_csr_outstanding.262726840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.4139150989 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 1301709723 ps |
| CPU time | 6.7 seconds |
| Started | Sep 24 05:24:15 PM UTC 24 |
| Finished | Sep 24 05:24:22 PM UTC 24 |
| Peak memory | 256904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139150989 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.4139150989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.1524709522 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 138180147 ps |
| CPU time | 2.52 seconds |
| Started | Sep 24 05:24:27 PM UTC 24 |
| Finished | Sep 24 05:24:31 PM UTC 24 |
| Peak memory | 257800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1524709522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_c sr_mem_rw_with_rand_reset.1524709522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3293770820 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 704667486 ps |
| CPU time | 2.88 seconds |
| Started | Sep 24 05:24:27 PM UTC 24 |
| Finished | Sep 24 05:24:31 PM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293770820 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.3293770820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.1561486453 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 76960063 ps |
| CPU time | 1.53 seconds |
| Started | Sep 24 05:24:27 PM UTC 24 |
| Finished | Sep 24 05:24:30 PM UTC 24 |
| Peak memory | 240492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561486453 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.1561486453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.98468209 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 164161513 ps |
| CPU time | 2.84 seconds |
| Started | Sep 24 05:24:27 PM UTC 24 |
| Finished | Sep 24 05:24:31 PM UTC 24 |
| Peak memory | 251620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98468209 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_same_csr_outstanding.98468209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3126059038 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 149412984 ps |
| CPU time | 4.78 seconds |
| Started | Sep 24 05:24:27 PM UTC 24 |
| Finished | Sep 24 05:24:33 PM UTC 24 |
| Peak memory | 257884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126059038 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.3126059038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2239016726 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 1214574040 ps |
| CPU time | 16.35 seconds |
| Started | Sep 24 05:24:27 PM UTC 24 |
| Finished | Sep 24 05:24:45 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239016726 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_intg_err.2239016726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.477512884 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 244908210 ps |
| CPU time | 2.62 seconds |
| Started | Sep 24 05:24:28 PM UTC 24 |
| Finished | Sep 24 05:24:31 PM UTC 24 |
| Peak memory | 257772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=477512884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_cs r_mem_rw_with_rand_reset.477512884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1731805512 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 675257447 ps |
| CPU time | 2.31 seconds |
| Started | Sep 24 05:24:27 PM UTC 24 |
| Finished | Sep 24 05:24:31 PM UTC 24 |
| Peak memory | 253748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731805512 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.1731805512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.3665572427 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 68727316 ps |
| CPU time | 1.51 seconds |
| Started | Sep 24 05:24:27 PM UTC 24 |
| Finished | Sep 24 05:24:30 PM UTC 24 |
| Peak memory | 240256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665572427 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.3665572427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.4175793680 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 146722223 ps |
| CPU time | 2.03 seconds |
| Started | Sep 24 05:24:27 PM UTC 24 |
| Finished | Sep 24 05:24:31 PM UTC 24 |
| Peak memory | 253632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175793680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_same_csr_outstanding.4175793680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.1704707529 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 197251627 ps |
| CPU time | 3.67 seconds |
| Started | Sep 24 05:24:27 PM UTC 24 |
| Finished | Sep 24 05:24:32 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704707529 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.1704707529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2063177290 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 123339080 ps |
| CPU time | 3.19 seconds |
| Started | Sep 24 05:24:28 PM UTC 24 |
| Finished | Sep 24 05:24:32 PM UTC 24 |
| Peak memory | 257720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2063177290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_c sr_mem_rw_with_rand_reset.2063177290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.92473968 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 154721470 ps |
| CPU time | 1.69 seconds |
| Started | Sep 24 05:24:28 PM UTC 24 |
| Finished | Sep 24 05:24:31 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92473968 -assert nopostproc +UVM_TESTNAME=otp_c trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.92473968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.174387828 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 564373765 ps |
| CPU time | 1.98 seconds |
| Started | Sep 24 05:24:28 PM UTC 24 |
| Finished | Sep 24 05:24:31 PM UTC 24 |
| Peak memory | 239936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174387828 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.174387828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2210565428 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 123984427 ps |
| CPU time | 3.21 seconds |
| Started | Sep 24 05:24:28 PM UTC 24 |
| Finished | Sep 24 05:24:32 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210565428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_same_csr_outstanding.2210565428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.896869487 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 88976845 ps |
| CPU time | 2.29 seconds |
| Started | Sep 24 05:24:28 PM UTC 24 |
| Finished | Sep 24 05:24:31 PM UTC 24 |
| Peak memory | 257560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896869487 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.896869487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.4127174605 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 9906286908 ps |
| CPU time | 15.12 seconds |
| Started | Sep 24 05:24:28 PM UTC 24 |
| Finished | Sep 24 05:24:44 PM UTC 24 |
| Peak memory | 255616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127174605 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_intg_err.4127174605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.2780765215 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 275860351 ps |
| CPU time | 2.31 seconds |
| Started | Sep 24 05:24:29 PM UTC 24 |
| Finished | Sep 24 05:24:33 PM UTC 24 |
| Peak memory | 257964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2780765215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_c sr_mem_rw_with_rand_reset.2780765215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.3050221218 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 147731644 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 05:24:28 PM UTC 24 |
| Finished | Sep 24 05:24:31 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050221218 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.3050221218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.475447869 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 556884609 ps |
| CPU time | 1.91 seconds |
| Started | Sep 24 05:24:28 PM UTC 24 |
| Finished | Sep 24 05:24:31 PM UTC 24 |
| Peak memory | 240348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475447869 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.475447869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.363287853 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 779560845 ps |
| CPU time | 2.99 seconds |
| Started | Sep 24 05:24:29 PM UTC 24 |
| Finished | Sep 24 05:24:33 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363287853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_same_csr_outstanding.363287853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1374346355 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 73233996 ps |
| CPU time | 4.76 seconds |
| Started | Sep 24 05:24:28 PM UTC 24 |
| Finished | Sep 24 05:24:34 PM UTC 24 |
| Peak memory | 251456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374346355 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.1374346355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.3467306787 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 9802011402 ps |
| CPU time | 11.55 seconds |
| Started | Sep 24 05:24:28 PM UTC 24 |
| Finished | Sep 24 05:24:41 PM UTC 24 |
| Peak memory | 251620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467306787 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_intg_err.3467306787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.3520214287 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 200147029 ps |
| CPU time | 2.75 seconds |
| Started | Sep 24 05:24:29 PM UTC 24 |
| Finished | Sep 24 05:24:33 PM UTC 24 |
| Peak memory | 257772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3520214287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_c sr_mem_rw_with_rand_reset.3520214287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3510384656 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 81760786 ps |
| CPU time | 1.83 seconds |
| Started | Sep 24 05:24:29 PM UTC 24 |
| Finished | Sep 24 05:24:32 PM UTC 24 |
| Peak memory | 251304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510384656 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.3510384656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.2950250650 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 40331836 ps |
| CPU time | 1.51 seconds |
| Started | Sep 24 05:24:29 PM UTC 24 |
| Finished | Sep 24 05:24:32 PM UTC 24 |
| Peak memory | 238880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950250650 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.2950250650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.223753305 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 440167749 ps |
| CPU time | 3.46 seconds |
| Started | Sep 24 05:24:29 PM UTC 24 |
| Finished | Sep 24 05:24:34 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223753305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_same_csr_outstanding.223753305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2827873264 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 2624104526 ps |
| CPU time | 6.06 seconds |
| Started | Sep 24 05:24:29 PM UTC 24 |
| Finished | Sep 24 05:24:37 PM UTC 24 |
| Peak memory | 256972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827873264 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.2827873264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1270683430 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 10267378769 ps |
| CPU time | 12.46 seconds |
| Started | Sep 24 05:24:29 PM UTC 24 |
| Finished | Sep 24 05:24:43 PM UTC 24 |
| Peak memory | 250884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270683430 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_intg_err.1270683430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.2709645577 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 282078057 ps |
| CPU time | 2.2 seconds |
| Started | Sep 24 05:24:30 PM UTC 24 |
| Finished | Sep 24 05:24:33 PM UTC 24 |
| Peak memory | 257936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2709645577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_c sr_mem_rw_with_rand_reset.2709645577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3851929056 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 46243091 ps |
| CPU time | 1.89 seconds |
| Started | Sep 24 05:24:30 PM UTC 24 |
| Finished | Sep 24 05:24:33 PM UTC 24 |
| Peak memory | 253348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851929056 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.3851929056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.1044501848 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 151071616 ps |
| CPU time | 1.64 seconds |
| Started | Sep 24 05:24:30 PM UTC 24 |
| Finished | Sep 24 05:24:32 PM UTC 24 |
| Peak memory | 239992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044501848 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.1044501848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.1613441449 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 170880912 ps |
| CPU time | 3.59 seconds |
| Started | Sep 24 05:24:30 PM UTC 24 |
| Finished | Sep 24 05:24:34 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613441449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_same_csr_outstanding.1613441449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.2796607908 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 81107816 ps |
| CPU time | 5.45 seconds |
| Started | Sep 24 05:24:29 PM UTC 24 |
| Finished | Sep 24 05:24:36 PM UTC 24 |
| Peak memory | 257900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796607908 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.2796607908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.901577391 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 330262863 ps |
| CPU time | 2.9 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:37 PM UTC 24 |
| Peak memory | 257672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=901577391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_cs r_mem_rw_with_rand_reset.901577391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3065920528 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 57665755 ps |
| CPU time | 1.74 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:36 PM UTC 24 |
| Peak memory | 253404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065920528 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.3065920528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.3537683183 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 71634574 ps |
| CPU time | 1.49 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:35 PM UTC 24 |
| Peak memory | 241076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537683183 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.3537683183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.2173792615 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 250547198 ps |
| CPU time | 2.8 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:37 PM UTC 24 |
| Peak memory | 251532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173792615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_same_csr_outstanding.2173792615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.2762094665 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 166088538 ps |
| CPU time | 3.34 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:37 PM UTC 24 |
| Peak memory | 251640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762094665 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.2762094665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1975069189 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 10255126782 ps |
| CPU time | 15.4 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:49 PM UTC 24 |
| Peak memory | 255780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975069189 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_intg_err.1975069189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.2058977606 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 115803011 ps |
| CPU time | 2.99 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:37 PM UTC 24 |
| Peak memory | 257776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2058977606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_c sr_mem_rw_with_rand_reset.2058977606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2324153503 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 50613664 ps |
| CPU time | 1.84 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:36 PM UTC 24 |
| Peak memory | 253344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324153503 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.2324153503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.3983908036 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 561760118 ps |
| CPU time | 1.87 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:36 PM UTC 24 |
| Peak memory | 239928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983908036 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.3983908036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.2529737852 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 86774350 ps |
| CPU time | 1.98 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:36 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529737852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_same_csr_outstanding.2529737852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.3165412183 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 376809771 ps |
| CPU time | 6.1 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:40 PM UTC 24 |
| Peak memory | 257684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165412183 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.3165412183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.4288649291 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1209276044 ps |
| CPU time | 9.11 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:43 PM UTC 24 |
| Peak memory | 255528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288649291 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_intg_err.4288649291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3883003666 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 166364803 ps |
| CPU time | 3.02 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:37 PM UTC 24 |
| Peak memory | 257740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3883003666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_c sr_mem_rw_with_rand_reset.3883003666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.64987279 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 535179379 ps |
| CPU time | 1.79 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:36 PM UTC 24 |
| Peak memory | 250364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64987279 -assert nopostproc +UVM_TESTNAME=otp_c trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.64987279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.1865874323 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 81175106 ps |
| CPU time | 1.45 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:36 PM UTC 24 |
| Peak memory | 241020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865874323 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.1865874323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.2692448094 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 43158809 ps |
| CPU time | 1.84 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:36 PM UTC 24 |
| Peak memory | 250240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692448094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_same_csr_outstanding.2692448094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.4190327481 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 68375051 ps |
| CPU time | 3.02 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:37 PM UTC 24 |
| Peak memory | 257804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190327481 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.4190327481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3011361885 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 758476171 ps |
| CPU time | 10.35 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:45 PM UTC 24 |
| Peak memory | 255620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011361885 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_intg_err.3011361885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.662257723 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 65384365 ps |
| CPU time | 2.06 seconds |
| Started | Sep 24 05:24:34 PM UTC 24 |
| Finished | Sep 24 05:24:38 PM UTC 24 |
| Peak memory | 255832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=662257723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_cs r_mem_rw_with_rand_reset.662257723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1081420057 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 48021514 ps |
| CPU time | 2.01 seconds |
| Started | Sep 24 05:24:34 PM UTC 24 |
| Finished | Sep 24 05:24:38 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081420057 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.1081420057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.997317712 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 39526664 ps |
| CPU time | 1.54 seconds |
| Started | Sep 24 05:24:34 PM UTC 24 |
| Finished | Sep 24 05:24:37 PM UTC 24 |
| Peak memory | 239948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997317712 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.997317712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.2327631013 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 132254776 ps |
| CPU time | 2.38 seconds |
| Started | Sep 24 05:24:34 PM UTC 24 |
| Finished | Sep 24 05:24:38 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327631013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_same_csr_outstanding.2327631013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2690660027 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 217813383 ps |
| CPU time | 3.47 seconds |
| Started | Sep 24 05:24:32 PM UTC 24 |
| Finished | Sep 24 05:24:38 PM UTC 24 |
| Peak memory | 257860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690660027 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.2690660027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1798131699 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 1955617395 ps |
| CPU time | 9.03 seconds |
| Started | Sep 24 05:24:33 PM UTC 24 |
| Finished | Sep 24 05:24:44 PM UTC 24 |
| Peak memory | 255660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798131699 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_intg_err.1798131699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.2852944263 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 3079671874 ps |
| CPU time | 9.26 seconds |
| Started | Sep 24 05:24:18 PM UTC 24 |
| Finished | Sep 24 05:24:28 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852944263 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_aliasing.2852944263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2008353924 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 225117346 ps |
| CPU time | 5.1 seconds |
| Started | Sep 24 05:24:18 PM UTC 24 |
| Finished | Sep 24 05:24:24 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008353924 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_bash.2008353924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1570935467 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 1535285902 ps |
| CPU time | 2.8 seconds |
| Started | Sep 24 05:24:17 PM UTC 24 |
| Finished | Sep 24 05:24:21 PM UTC 24 |
| Peak memory | 253480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570935467 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_reset.1570935467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.560729103 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 215466303 ps |
| CPU time | 2.98 seconds |
| Started | Sep 24 05:24:18 PM UTC 24 |
| Finished | Sep 24 05:24:22 PM UTC 24 |
| Peak memory | 257732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=560729103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr _mem_rw_with_rand_reset.560729103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.4074698849 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 157967075 ps |
| CPU time | 1.65 seconds |
| Started | Sep 24 05:24:17 PM UTC 24 |
| Finished | Sep 24 05:24:20 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074698849 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.4074698849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.3883721907 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 589157317 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 05:24:17 PM UTC 24 |
| Finished | Sep 24 05:24:20 PM UTC 24 |
| Peak memory | 239992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883721907 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.3883721907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.3944593681 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 137035714 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 05:24:17 PM UTC 24 |
| Finished | Sep 24 05:24:20 PM UTC 24 |
| Peak memory | 239816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944593681 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_partial_access.3944593681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.1876237271 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 39683229 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 05:24:17 PM UTC 24 |
| Finished | Sep 24 05:24:20 PM UTC 24 |
| Peak memory | 239188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876237271 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.1876237271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1111123277 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 223358673 ps |
| CPU time | 3.16 seconds |
| Started | Sep 24 05:24:18 PM UTC 24 |
| Finished | Sep 24 05:24:22 PM UTC 24 |
| Peak memory | 251616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111123277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_same_csr_outstanding.1111123277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2990719072 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 66438113 ps |
| CPU time | 4.37 seconds |
| Started | Sep 24 05:24:17 PM UTC 24 |
| Finished | Sep 24 05:24:23 PM UTC 24 |
| Peak memory | 257620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990719072 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.2990719072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2061536805 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2454586849 ps |
| CPU time | 19.06 seconds |
| Started | Sep 24 05:24:17 PM UTC 24 |
| Finished | Sep 24 05:24:38 PM UTC 24 |
| Peak memory | 257760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061536805 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_intg_err.2061536805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.3018510792 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 68340447 ps |
| CPU time | 1.57 seconds |
| Started | Sep 24 05:24:34 PM UTC 24 |
| Finished | Sep 24 05:24:37 PM UTC 24 |
| Peak memory | 241020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018510792 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.3018510792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/20.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.3839497724 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 148337768 ps |
| CPU time | 1.45 seconds |
| Started | Sep 24 05:24:34 PM UTC 24 |
| Finished | Sep 24 05:24:37 PM UTC 24 |
| Peak memory | 239928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839497724 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.3839497724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/21.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.4096654228 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 72395706 ps |
| CPU time | 1.64 seconds |
| Started | Sep 24 05:24:34 PM UTC 24 |
| Finished | Sep 24 05:24:37 PM UTC 24 |
| Peak memory | 241076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096654228 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.4096654228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/22.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.3107820177 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 577256308 ps |
| CPU time | 1.84 seconds |
| Started | Sep 24 05:24:34 PM UTC 24 |
| Finished | Sep 24 05:24:38 PM UTC 24 |
| Peak memory | 240196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107820177 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.3107820177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/23.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.89373605 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 40370653 ps |
| CPU time | 1.58 seconds |
| Started | Sep 24 05:24:34 PM UTC 24 |
| Finished | Sep 24 05:24:37 PM UTC 24 |
| Peak memory | 240228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89373605 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.89373605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/24.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.2728098373 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 77477292 ps |
| CPU time | 1.74 seconds |
| Started | Sep 24 05:24:34 PM UTC 24 |
| Finished | Sep 24 05:24:37 PM UTC 24 |
| Peak memory | 240968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728098373 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.2728098373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/25.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.1184716767 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 54983823 ps |
| CPU time | 1.82 seconds |
| Started | Sep 24 05:24:34 PM UTC 24 |
| Finished | Sep 24 05:24:38 PM UTC 24 |
| Peak memory | 239992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184716767 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.1184716767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/26.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.4187861710 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 552349097 ps |
| CPU time | 2.15 seconds |
| Started | Sep 24 05:24:34 PM UTC 24 |
| Finished | Sep 24 05:24:38 PM UTC 24 |
| Peak memory | 241144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187861710 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.4187861710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/27.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.401669570 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 539047316 ps |
| CPU time | 1.85 seconds |
| Started | Sep 24 05:24:34 PM UTC 24 |
| Finished | Sep 24 05:24:38 PM UTC 24 |
| Peak memory | 240192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401669570 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.401669570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/28.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.1704070423 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 540197014 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 05:24:34 PM UTC 24 |
| Finished | Sep 24 05:24:37 PM UTC 24 |
| Peak memory | 240044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704070423 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.1704070423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/29.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.544191852 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 110354973 ps |
| CPU time | 3.54 seconds |
| Started | Sep 24 05:24:21 PM UTC 24 |
| Finished | Sep 24 05:24:26 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544191852 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_aliasing.544191852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2733945361 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 118124829 ps |
| CPU time | 4.02 seconds |
| Started | Sep 24 05:24:21 PM UTC 24 |
| Finished | Sep 24 05:24:26 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733945361 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_bash.2733945361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3404529562 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1078298727 ps |
| CPU time | 2.3 seconds |
| Started | Sep 24 05:24:21 PM UTC 24 |
| Finished | Sep 24 05:24:25 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404529562 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_reset.3404529562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2557388858 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 266119741 ps |
| CPU time | 2.84 seconds |
| Started | Sep 24 05:24:21 PM UTC 24 |
| Finished | Sep 24 05:24:25 PM UTC 24 |
| Peak memory | 257704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2557388858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_cs r_mem_rw_with_rand_reset.2557388858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.57108082 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 41664641 ps |
| CPU time | 1.64 seconds |
| Started | Sep 24 05:24:21 PM UTC 24 |
| Finished | Sep 24 05:24:24 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57108082 -assert nopostproc +UVM_TESTNAME=otp_c trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.57108082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.2448541437 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 71007365 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 05:24:18 PM UTC 24 |
| Finished | Sep 24 05:24:20 PM UTC 24 |
| Peak memory | 240344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448541437 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.2448541437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1005945924 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 135691908 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 05:24:21 PM UTC 24 |
| Finished | Sep 24 05:24:24 PM UTC 24 |
| Peak memory | 239392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005945924 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_partial_access.1005945924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3417431412 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 43019706 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 05:24:18 PM UTC 24 |
| Finished | Sep 24 05:24:20 PM UTC 24 |
| Peak memory | 240412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417431412 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.3417431412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.492560877 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 87710189 ps |
| CPU time | 2.99 seconds |
| Started | Sep 24 05:24:21 PM UTC 24 |
| Finished | Sep 24 05:24:25 PM UTC 24 |
| Peak memory | 253532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492560877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_same_csr_outstanding.492560877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.328409402 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 388881326 ps |
| CPU time | 3.31 seconds |
| Started | Sep 24 05:24:18 PM UTC 24 |
| Finished | Sep 24 05:24:22 PM UTC 24 |
| Peak memory | 257668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328409402 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.328409402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.4094471547 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 20107731471 ps |
| CPU time | 17.85 seconds |
| Started | Sep 24 05:24:18 PM UTC 24 |
| Finished | Sep 24 05:24:37 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094471547 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_intg_err.4094471547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.3011979067 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 37791076 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 05:24:35 PM UTC 24 |
| Finished | Sep 24 05:24:38 PM UTC 24 |
| Peak memory | 239928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011979067 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.3011979067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/30.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.909736959 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 148013104 ps |
| CPU time | 1.47 seconds |
| Started | Sep 24 05:24:35 PM UTC 24 |
| Finished | Sep 24 05:24:38 PM UTC 24 |
| Peak memory | 241084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909736959 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.909736959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/31.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.4010485800 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 127565508 ps |
| CPU time | 1.49 seconds |
| Started | Sep 24 05:24:35 PM UTC 24 |
| Finished | Sep 24 05:24:38 PM UTC 24 |
| Peak memory | 241020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010485800 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.4010485800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/32.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.751904306 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 148791174 ps |
| CPU time | 1.58 seconds |
| Started | Sep 24 05:24:35 PM UTC 24 |
| Finished | Sep 24 05:24:38 PM UTC 24 |
| Peak memory | 239932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751904306 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.751904306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/33.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.4160168697 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 48192878 ps |
| CPU time | 1.43 seconds |
| Started | Sep 24 05:24:37 PM UTC 24 |
| Finished | Sep 24 05:24:39 PM UTC 24 |
| Peak memory | 239992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160168697 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.4160168697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/34.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.1059977615 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 39783260 ps |
| CPU time | 1.67 seconds |
| Started | Sep 24 05:24:37 PM UTC 24 |
| Finished | Sep 24 05:24:39 PM UTC 24 |
| Peak memory | 239932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059977615 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.1059977615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/35.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.2637912116 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 150706927 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 05:24:37 PM UTC 24 |
| Finished | Sep 24 05:24:39 PM UTC 24 |
| Peak memory | 239972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637912116 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.2637912116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/36.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.1269287746 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 42457511 ps |
| CPU time | 1.44 seconds |
| Started | Sep 24 05:24:37 PM UTC 24 |
| Finished | Sep 24 05:24:39 PM UTC 24 |
| Peak memory | 239992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269287746 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.1269287746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/37.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.3820426708 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 38478131 ps |
| CPU time | 1.43 seconds |
| Started | Sep 24 05:24:37 PM UTC 24 |
| Finished | Sep 24 05:24:39 PM UTC 24 |
| Peak memory | 241076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820426708 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.3820426708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/38.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.1898293253 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 628488985 ps |
| CPU time | 1.64 seconds |
| Started | Sep 24 05:24:37 PM UTC 24 |
| Finished | Sep 24 05:24:40 PM UTC 24 |
| Peak memory | 239768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898293253 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.1898293253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/39.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.4180496611 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 198506638 ps |
| CPU time | 5.85 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:29 PM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180496611 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_aliasing.4180496611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2276329017 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 240860080 ps |
| CPU time | 5.32 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:28 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276329017 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_bash.2276329017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1258819822 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 70054832 ps |
| CPU time | 1.9 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:25 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258819822 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_reset.1258819822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3071132290 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 108349144 ps |
| CPU time | 4.45 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:27 PM UTC 24 |
| Peak memory | 257932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3071132290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_cs r_mem_rw_with_rand_reset.3071132290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2806197963 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 78313183 ps |
| CPU time | 1.57 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:24 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806197963 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.2806197963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.1542986764 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 141928683 ps |
| CPU time | 1.72 seconds |
| Started | Sep 24 05:24:21 PM UTC 24 |
| Finished | Sep 24 05:24:24 PM UTC 24 |
| Peak memory | 239928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542986764 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.1542986764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3105811232 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 74303374 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:24 PM UTC 24 |
| Peak memory | 240332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105811232 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_partial_access.3105811232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.3323943077 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 143417764 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:24 PM UTC 24 |
| Peak memory | 240736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323943077 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.3323943077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.2641511690 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 265118677 ps |
| CPU time | 2.71 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:26 PM UTC 24 |
| Peak memory | 253484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641511690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_same_csr_outstanding.2641511690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.862672410 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 233384589 ps |
| CPU time | 5.87 seconds |
| Started | Sep 24 05:24:21 PM UTC 24 |
| Finished | Sep 24 05:24:28 PM UTC 24 |
| Peak memory | 257692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862672410 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.862672410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.2333498469 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 39845010 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 05:24:39 PM UTC 24 |
| Finished | Sep 24 05:24:41 PM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333498469 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.2333498469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/40.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.719714959 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 530467213 ps |
| CPU time | 1.91 seconds |
| Started | Sep 24 05:24:39 PM UTC 24 |
| Finished | Sep 24 05:24:42 PM UTC 24 |
| Peak memory | 239928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719714959 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.719714959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/41.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.3425310895 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 57292500 ps |
| CPU time | 1.43 seconds |
| Started | Sep 24 05:24:39 PM UTC 24 |
| Finished | Sep 24 05:24:41 PM UTC 24 |
| Peak memory | 239932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425310895 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.3425310895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/42.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.3323874471 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 72557636 ps |
| CPU time | 1.65 seconds |
| Started | Sep 24 05:24:39 PM UTC 24 |
| Finished | Sep 24 05:24:42 PM UTC 24 |
| Peak memory | 240192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323874471 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.3323874471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/43.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.2412564135 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 51912848 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 05:24:39 PM UTC 24 |
| Finished | Sep 24 05:24:41 PM UTC 24 |
| Peak memory | 240100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412564135 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.2412564135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/44.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.1464523408 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 148551459 ps |
| CPU time | 1.47 seconds |
| Started | Sep 24 05:24:39 PM UTC 24 |
| Finished | Sep 24 05:24:41 PM UTC 24 |
| Peak memory | 240136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464523408 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.1464523408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/45.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.1904549169 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 133198000 ps |
| CPU time | 1.51 seconds |
| Started | Sep 24 05:24:39 PM UTC 24 |
| Finished | Sep 24 05:24:42 PM UTC 24 |
| Peak memory | 241076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904549169 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.1904549169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/46.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.2526318481 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 39286339 ps |
| CPU time | 1.4 seconds |
| Started | Sep 24 05:24:39 PM UTC 24 |
| Finished | Sep 24 05:24:41 PM UTC 24 |
| Peak memory | 241076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526318481 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.2526318481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/47.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.53798031 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 566701022 ps |
| CPU time | 2.09 seconds |
| Started | Sep 24 05:24:39 PM UTC 24 |
| Finished | Sep 24 05:24:42 PM UTC 24 |
| Peak memory | 240376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53798031 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.53798031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/48.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.3592401051 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 74951237 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 05:24:39 PM UTC 24 |
| Finished | Sep 24 05:24:42 PM UTC 24 |
| Peak memory | 239928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592401051 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3592401051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/49.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.3057127286 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 77403123 ps |
| CPU time | 2.88 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:26 PM UTC 24 |
| Peak memory | 257776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3057127286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_cs r_mem_rw_with_rand_reset.3057127286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3465050578 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 76613367 ps |
| CPU time | 1.77 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:25 PM UTC 24 |
| Peak memory | 251128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465050578 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.3465050578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.1746159514 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 36085053 ps |
| CPU time | 1.75 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:25 PM UTC 24 |
| Peak memory | 240192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746159514 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.1746159514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1847067376 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 806848061 ps |
| CPU time | 2.99 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:26 PM UTC 24 |
| Peak memory | 253592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847067376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_same_csr_outstanding.1847067376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2563414383 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 625436938 ps |
| CPU time | 6.75 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:30 PM UTC 24 |
| Peak memory | 257580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563414383 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.2563414383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.1597935801 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 1266666090 ps |
| CPU time | 18.14 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:41 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597935801 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_intg_err.1597935801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.482682667 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 270676839 ps |
| CPU time | 3.05 seconds |
| Started | Sep 24 05:24:25 PM UTC 24 |
| Finished | Sep 24 05:24:29 PM UTC 24 |
| Peak memory | 257672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=482682667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr _mem_rw_with_rand_reset.482682667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.1326187430 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 77916148 ps |
| CPU time | 1.6 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:25 PM UTC 24 |
| Peak memory | 253232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326187430 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.1326187430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.1986615269 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 68684536 ps |
| CPU time | 1.71 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:25 PM UTC 24 |
| Peak memory | 239928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986615269 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.1986615269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3399621047 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 706617104 ps |
| CPU time | 2.68 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:26 PM UTC 24 |
| Peak memory | 251724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399621047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_same_csr_outstanding.3399621047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1449507204 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 124601240 ps |
| CPU time | 3.82 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:27 PM UTC 24 |
| Peak memory | 257628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449507204 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.1449507204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.728613734 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2556706426 ps |
| CPU time | 18.97 seconds |
| Started | Sep 24 05:24:22 PM UTC 24 |
| Finished | Sep 24 05:24:42 PM UTC 24 |
| Peak memory | 255980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728613734 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg_err.728613734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.2446956556 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 1604192733 ps |
| CPU time | 3.84 seconds |
| Started | Sep 24 05:24:25 PM UTC 24 |
| Finished | Sep 24 05:24:30 PM UTC 24 |
| Peak memory | 258012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2446956556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_cs r_mem_rw_with_rand_reset.2446956556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3744951684 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 71469513 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 05:24:25 PM UTC 24 |
| Finished | Sep 24 05:24:27 PM UTC 24 |
| Peak memory | 252868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744951684 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.3744951684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.1064186658 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 143386527 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 05:24:25 PM UTC 24 |
| Finished | Sep 24 05:24:27 PM UTC 24 |
| Peak memory | 240196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064186658 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.1064186658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.4151614854 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 171957760 ps |
| CPU time | 2.02 seconds |
| Started | Sep 24 05:24:25 PM UTC 24 |
| Finished | Sep 24 05:24:28 PM UTC 24 |
| Peak memory | 251432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151614854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_same_csr_outstanding.4151614854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.1963948529 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 67449841 ps |
| CPU time | 4.57 seconds |
| Started | Sep 24 05:24:25 PM UTC 24 |
| Finished | Sep 24 05:24:30 PM UTC 24 |
| Peak memory | 257816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963948529 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.1963948529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1738819794 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 18953946359 ps |
| CPU time | 20.75 seconds |
| Started | Sep 24 05:24:25 PM UTC 24 |
| Finished | Sep 24 05:24:47 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738819794 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_intg_err.1738819794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.793567008 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 73097869 ps |
| CPU time | 1.59 seconds |
| Started | Sep 24 05:24:25 PM UTC 24 |
| Finished | Sep 24 05:24:28 PM UTC 24 |
| Peak memory | 253348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793567008 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.793567008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.1601913916 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 42183820 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 05:24:25 PM UTC 24 |
| Finished | Sep 24 05:24:28 PM UTC 24 |
| Peak memory | 241080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601913916 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.1601913916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.1387135560 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 187030487 ps |
| CPU time | 2.76 seconds |
| Started | Sep 24 05:24:25 PM UTC 24 |
| Finished | Sep 24 05:24:29 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387135560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_same_csr_outstanding.1387135560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3831890788 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 262600712 ps |
| CPU time | 3.79 seconds |
| Started | Sep 24 05:24:25 PM UTC 24 |
| Finished | Sep 24 05:24:30 PM UTC 24 |
| Peak memory | 257696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831890788 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.3831890788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1576599346 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 75948344 ps |
| CPU time | 2.43 seconds |
| Started | Sep 24 05:24:27 PM UTC 24 |
| Finished | Sep 24 05:24:31 PM UTC 24 |
| Peak memory | 257576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1576599346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_cs r_mem_rw_with_rand_reset.1576599346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.607925951 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 171088102 ps |
| CPU time | 2.07 seconds |
| Started | Sep 24 05:24:27 PM UTC 24 |
| Finished | Sep 24 05:24:31 PM UTC 24 |
| Peak memory | 253552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607925951 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.607925951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.3176034132 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 74647432 ps |
| CPU time | 1.51 seconds |
| Started | Sep 24 05:24:25 PM UTC 24 |
| Finished | Sep 24 05:24:28 PM UTC 24 |
| Peak memory | 241136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176034132 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.3176034132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.4099352235 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 131734964 ps |
| CPU time | 3.45 seconds |
| Started | Sep 24 05:24:27 PM UTC 24 |
| Finished | Sep 24 05:24:32 PM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099352235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_same_csr_outstanding.4099352235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2425111248 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 218289009 ps |
| CPU time | 4.14 seconds |
| Started | Sep 24 05:24:25 PM UTC 24 |
| Finished | Sep 24 05:24:30 PM UTC 24 |
| Peak memory | 257888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425111248 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.2425111248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.899472599 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1587756934 ps |
| CPU time | 10.13 seconds |
| Started | Sep 24 05:24:25 PM UTC 24 |
| Finished | Sep 24 05:24:36 PM UTC 24 |
| Peak memory | 255432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899472599 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_intg_err.899472599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_alert_test.934365210 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 752659987 ps |
| CPU time | 2.1 seconds |
| Started | Sep 24 05:15:16 PM UTC 24 |
| Finished | Sep 24 05:15:20 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934365210 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.934365210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_check_fail.1900850973 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 958723330 ps |
| CPU time | 11.27 seconds |
| Started | Sep 24 05:15:15 PM UTC 24 |
| Finished | Sep 24 05:15:27 PM UTC 24 |
| Peak memory | 253972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900850973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.1900850973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_errs.992474911 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 6229525979 ps |
| CPU time | 26.34 seconds |
| Started | Sep 24 05:15:15 PM UTC 24 |
| Finished | Sep 24 05:15:42 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992474911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.992474911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_low_freq_read.3008420637 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7518567001 ps |
| CPU time | 18.83 seconds |
| Started | Sep 24 05:15:02 PM UTC 24 |
| Finished | Sep 24 05:15:22 PM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008420637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.3008420637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_macro_errs.1762668131 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 813363226 ps |
| CPU time | 16.79 seconds |
| Started | Sep 24 05:15:15 PM UTC 24 |
| Finished | Sep 24 05:15:33 PM UTC 24 |
| Peak memory | 254172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762668131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.1762668131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_partition_walk.3012999577 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1195062165 ps |
| CPU time | 15.99 seconds |
| Started | Sep 24 05:15:01 PM UTC 24 |
| Finished | Sep 24 05:15:18 PM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012999577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.3012999577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_smoke.1837471638 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 266633060 ps |
| CPU time | 4.46 seconds |
| Started | Sep 24 05:14:56 PM UTC 24 |
| Finished | Sep 24 05:15:02 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837471638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.1837471638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_errs.3150576817 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1394791851 ps |
| CPU time | 32.94 seconds |
| Started | Sep 24 05:15:17 PM UTC 24 |
| Finished | Sep 24 05:15:51 PM UTC 24 |
| Peak memory | 256068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150576817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.3150576817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_key_req.2302351362 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 327157855 ps |
| CPU time | 11.22 seconds |
| Started | Sep 24 05:15:20 PM UTC 24 |
| Finished | Sep 24 05:15:32 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302351362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.2302351362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_esc.394983054 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3620739722 ps |
| CPU time | 11.29 seconds |
| Started | Sep 24 05:15:17 PM UTC 24 |
| Finished | Sep 24 05:15:29 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394983054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.394983054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_sec_cm.1123506083 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 11220801585 ps |
| CPU time | 217.58 seconds |
| Started | Sep 24 05:15:20 PM UTC 24 |
| Finished | Sep 24 05:19:01 PM UTC 24 |
| Peak memory | 298908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123506083 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.1123506083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.3180229613 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 28484492441 ps |
| CPU time | 188.99 seconds |
| Started | Sep 24 05:15:20 PM UTC 24 |
| Finished | Sep 24 05:18:32 PM UTC 24 |
| Peak memory | 268716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3180229613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.otp_ctrl_stress_all_with_rand_reset.3180229613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_test_access.4267332581 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 6477074137 ps |
| CPU time | 62.31 seconds |
| Started | Sep 24 05:15:20 PM UTC 24 |
| Finished | Sep 24 05:16:24 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267332581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.4267332581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_alert_test.3149401187 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 682902048 ps |
| CPU time | 3.01 seconds |
| Started | Sep 24 05:16:19 PM UTC 24 |
| Finished | Sep 24 05:16:24 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149401187 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.3149401187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_errs.3010695506 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 534667683 ps |
| CPU time | 15.88 seconds |
| Started | Sep 24 05:16:15 PM UTC 24 |
| Finished | Sep 24 05:16:32 PM UTC 24 |
| Peak memory | 252004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010695506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.3010695506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_lock.881868026 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1832202889 ps |
| CPU time | 34.32 seconds |
| Started | Sep 24 05:16:15 PM UTC 24 |
| Finished | Sep 24 05:16:50 PM UTC 24 |
| Peak memory | 258116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881868026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.881868026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_init_fail.1410814499 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 253462593 ps |
| CPU time | 4.17 seconds |
| Started | Sep 24 05:16:15 PM UTC 24 |
| Finished | Sep 24 05:16:20 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410814499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.1410814499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_macro_errs.1983346000 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 421223910 ps |
| CPU time | 7.64 seconds |
| Started | Sep 24 05:16:15 PM UTC 24 |
| Finished | Sep 24 05:16:24 PM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983346000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.1983346000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_key_req.1903889597 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 7505949928 ps |
| CPU time | 26.79 seconds |
| Started | Sep 24 05:16:15 PM UTC 24 |
| Finished | Sep 24 05:16:43 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903889597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.1903889597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_esc.2858788809 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 3760158553 ps |
| CPU time | 34.07 seconds |
| Started | Sep 24 05:16:15 PM UTC 24 |
| Finished | Sep 24 05:16:50 PM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858788809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.2858788809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_req.830951100 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2032742019 ps |
| CPU time | 16.12 seconds |
| Started | Sep 24 05:16:15 PM UTC 24 |
| Finished | Sep 24 05:16:32 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830951100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.830951100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_regwen.4221965527 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1936955635 ps |
| CPU time | 7.15 seconds |
| Started | Sep 24 05:16:15 PM UTC 24 |
| Finished | Sep 24 05:16:23 PM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221965527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.4221965527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_smoke.3662636651 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 298269099 ps |
| CPU time | 4.25 seconds |
| Started | Sep 24 05:16:10 PM UTC 24 |
| Finished | Sep 24 05:16:16 PM UTC 24 |
| Peak memory | 252052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662636651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.3662636651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all.680954685 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 277740261 ps |
| CPU time | 5.54 seconds |
| Started | Sep 24 05:16:19 PM UTC 24 |
| Finished | Sep 24 05:16:26 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680954685 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.680954685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_test_access.1277689628 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 823458537 ps |
| CPU time | 18.1 seconds |
| Started | Sep 24 05:16:15 PM UTC 24 |
| Finished | Sep 24 05:16:34 PM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277689628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.1277689628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/10.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_init_fail.1283878889 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 105315446 ps |
| CPU time | 5.17 seconds |
| Started | Sep 24 05:22:38 PM UTC 24 |
| Finished | Sep 24 05:22:45 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283878889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.1283878889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/100.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_parallel_lc_esc.1138812686 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 522381054 ps |
| CPU time | 6.56 seconds |
| Started | Sep 24 05:22:39 PM UTC 24 |
| Finished | Sep 24 05:22:46 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138812686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.1138812686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/100.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_init_fail.2238348356 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 167196454 ps |
| CPU time | 6.64 seconds |
| Started | Sep 24 05:22:39 PM UTC 24 |
| Finished | Sep 24 05:22:46 PM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238348356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.2238348356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/101.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_parallel_lc_esc.4038199120 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 671626078 ps |
| CPU time | 8.21 seconds |
| Started | Sep 24 05:22:39 PM UTC 24 |
| Finished | Sep 24 05:22:48 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038199120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.4038199120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/101.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_init_fail.454200636 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 469713145 ps |
| CPU time | 5.85 seconds |
| Started | Sep 24 05:22:39 PM UTC 24 |
| Finished | Sep 24 05:22:46 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454200636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.454200636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/102.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_parallel_lc_esc.3785972673 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 617135951 ps |
| CPU time | 4.42 seconds |
| Started | Sep 24 05:22:39 PM UTC 24 |
| Finished | Sep 24 05:22:44 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785972673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.3785972673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/102.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_init_fail.566644190 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 289501834 ps |
| CPU time | 5.39 seconds |
| Started | Sep 24 05:22:39 PM UTC 24 |
| Finished | Sep 24 05:22:45 PM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566644190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.566644190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/103.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_parallel_lc_esc.2929607848 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 179991815 ps |
| CPU time | 5.84 seconds |
| Started | Sep 24 05:22:41 PM UTC 24 |
| Finished | Sep 24 05:22:48 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929607848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.2929607848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/103.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_init_fail.3146098030 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 2466899024 ps |
| CPU time | 8.03 seconds |
| Started | Sep 24 05:22:41 PM UTC 24 |
| Finished | Sep 24 05:22:51 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146098030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.3146098030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/104.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_parallel_lc_esc.3933718954 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 310459126 ps |
| CPU time | 14.7 seconds |
| Started | Sep 24 05:22:41 PM UTC 24 |
| Finished | Sep 24 05:22:57 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933718954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.3933718954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/104.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_init_fail.3039498998 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 1651538800 ps |
| CPU time | 6.66 seconds |
| Started | Sep 24 05:22:41 PM UTC 24 |
| Finished | Sep 24 05:22:49 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039498998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.3039498998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/105.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_parallel_lc_esc.1264711566 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 394741723 ps |
| CPU time | 13.36 seconds |
| Started | Sep 24 05:22:44 PM UTC 24 |
| Finished | Sep 24 05:22:59 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264711566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.1264711566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/105.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_parallel_lc_esc.59130158 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 278276964 ps |
| CPU time | 4.93 seconds |
| Started | Sep 24 05:22:47 PM UTC 24 |
| Finished | Sep 24 05:22:53 PM UTC 24 |
| Peak memory | 251704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59130158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.59130158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/106.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_init_fail.13603730 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 535095916 ps |
| CPU time | 3.74 seconds |
| Started | Sep 24 05:22:47 PM UTC 24 |
| Finished | Sep 24 05:22:52 PM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13603730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.13603730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/107.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_parallel_lc_esc.3764619467 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 203445850 ps |
| CPU time | 5.77 seconds |
| Started | Sep 24 05:22:47 PM UTC 24 |
| Finished | Sep 24 05:22:54 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764619467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.3764619467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/107.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_init_fail.3027264496 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 627264759 ps |
| CPU time | 5.22 seconds |
| Started | Sep 24 05:22:47 PM UTC 24 |
| Finished | Sep 24 05:22:54 PM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027264496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.3027264496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/108.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_parallel_lc_esc.3068950047 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 425032133 ps |
| CPU time | 7.82 seconds |
| Started | Sep 24 05:22:47 PM UTC 24 |
| Finished | Sep 24 05:22:56 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068950047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3068950047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/108.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_init_fail.973771302 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 265599939 ps |
| CPU time | 6.21 seconds |
| Started | Sep 24 05:22:47 PM UTC 24 |
| Finished | Sep 24 05:22:55 PM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973771302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.973771302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/109.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_parallel_lc_esc.3069656594 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 506421111 ps |
| CPU time | 8.01 seconds |
| Started | Sep 24 05:22:51 PM UTC 24 |
| Finished | Sep 24 05:23:00 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069656594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.3069656594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/109.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_alert_test.2959347615 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 55151922 ps |
| CPU time | 1.98 seconds |
| Started | Sep 24 05:16:25 PM UTC 24 |
| Finished | Sep 24 05:16:28 PM UTC 24 |
| Peak memory | 250420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959347615 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.2959347615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_errs.3444401362 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 902091120 ps |
| CPU time | 15.78 seconds |
| Started | Sep 24 05:16:20 PM UTC 24 |
| Finished | Sep 24 05:16:37 PM UTC 24 |
| Peak memory | 251872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444401362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.3444401362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_lock.1860375478 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 463445549 ps |
| CPU time | 16.25 seconds |
| Started | Sep 24 05:16:20 PM UTC 24 |
| Finished | Sep 24 05:16:37 PM UTC 24 |
| Peak memory | 251940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860375478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.1860375478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_init_fail.3078095274 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 124437594 ps |
| CPU time | 5.44 seconds |
| Started | Sep 24 05:16:20 PM UTC 24 |
| Finished | Sep 24 05:16:26 PM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078095274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.3078095274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_macro_errs.4135835222 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 448278310 ps |
| CPU time | 9.43 seconds |
| Started | Sep 24 05:16:25 PM UTC 24 |
| Finished | Sep 24 05:16:36 PM UTC 24 |
| Peak memory | 254040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135835222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.4135835222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_key_req.291839825 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 837017503 ps |
| CPU time | 14.49 seconds |
| Started | Sep 24 05:16:25 PM UTC 24 |
| Finished | Sep 24 05:16:41 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291839825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.291839825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_regwen.1576665770 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 492697283 ps |
| CPU time | 7.85 seconds |
| Started | Sep 24 05:16:25 PM UTC 24 |
| Finished | Sep 24 05:16:34 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576665770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.1576665770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_smoke.1880585708 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 317078926 ps |
| CPU time | 6.67 seconds |
| Started | Sep 24 05:16:20 PM UTC 24 |
| Finished | Sep 24 05:16:27 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880585708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.1880585708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.3957548721 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 9164793993 ps |
| CPU time | 178.3 seconds |
| Started | Sep 24 05:16:25 PM UTC 24 |
| Finished | Sep 24 05:19:27 PM UTC 24 |
| Peak memory | 272596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3957548721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.otp_ctrl_stress_all_with_rand_reset.3957548721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_test_access.2615828949 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 144785057 ps |
| CPU time | 5.49 seconds |
| Started | Sep 24 05:16:25 PM UTC 24 |
| Finished | Sep 24 05:16:32 PM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615828949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.2615828949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/11.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_parallel_lc_esc.46352915 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 137977646 ps |
| CPU time | 6.28 seconds |
| Started | Sep 24 05:22:51 PM UTC 24 |
| Finished | Sep 24 05:22:58 PM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46352915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.46352915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/110.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_init_fail.2150978632 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 111997845 ps |
| CPU time | 4.97 seconds |
| Started | Sep 24 05:22:51 PM UTC 24 |
| Finished | Sep 24 05:22:57 PM UTC 24 |
| Peak memory | 251804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150978632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.2150978632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/111.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_parallel_lc_esc.3197430900 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 664910934 ps |
| CPU time | 7.37 seconds |
| Started | Sep 24 05:22:51 PM UTC 24 |
| Finished | Sep 24 05:23:00 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197430900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.3197430900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/111.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_init_fail.804059930 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 450375748 ps |
| CPU time | 5.16 seconds |
| Started | Sep 24 05:22:51 PM UTC 24 |
| Finished | Sep 24 05:22:58 PM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804059930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.804059930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/112.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_parallel_lc_esc.471969093 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 433112473 ps |
| CPU time | 5.08 seconds |
| Started | Sep 24 05:22:51 PM UTC 24 |
| Finished | Sep 24 05:22:58 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471969093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.471969093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/112.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_init_fail.3263811651 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 328697605 ps |
| CPU time | 4.3 seconds |
| Started | Sep 24 05:22:51 PM UTC 24 |
| Finished | Sep 24 05:22:57 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263811651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.3263811651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/113.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_parallel_lc_esc.2125646155 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 341402424 ps |
| CPU time | 7.77 seconds |
| Started | Sep 24 05:22:56 PM UTC 24 |
| Finished | Sep 24 05:23:05 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125646155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.2125646155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/113.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_init_fail.2215045294 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 624375382 ps |
| CPU time | 3.93 seconds |
| Started | Sep 24 05:22:56 PM UTC 24 |
| Finished | Sep 24 05:23:01 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215045294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.2215045294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/114.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_parallel_lc_esc.4142151731 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 697648030 ps |
| CPU time | 18.1 seconds |
| Started | Sep 24 05:22:56 PM UTC 24 |
| Finished | Sep 24 05:23:15 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142151731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.4142151731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/114.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_init_fail.1156362876 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 492422921 ps |
| CPU time | 5.14 seconds |
| Started | Sep 24 05:22:56 PM UTC 24 |
| Finished | Sep 24 05:23:02 PM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156362876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.1156362876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/115.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_parallel_lc_esc.2676343473 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 1317313434 ps |
| CPU time | 3.31 seconds |
| Started | Sep 24 05:22:56 PM UTC 24 |
| Finished | Sep 24 05:23:01 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676343473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.2676343473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/115.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_init_fail.3784380967 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 313466439 ps |
| CPU time | 5.31 seconds |
| Started | Sep 24 05:22:56 PM UTC 24 |
| Finished | Sep 24 05:23:03 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784380967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.3784380967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/116.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_parallel_lc_esc.4250709220 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 350520809 ps |
| CPU time | 9.68 seconds |
| Started | Sep 24 05:23:01 PM UTC 24 |
| Finished | Sep 24 05:23:12 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250709220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.4250709220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/116.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_init_fail.1729033770 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 263827255 ps |
| CPU time | 4.83 seconds |
| Started | Sep 24 05:23:01 PM UTC 24 |
| Finished | Sep 24 05:23:07 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729033770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.1729033770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/117.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_parallel_lc_esc.2125089609 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 5504216038 ps |
| CPU time | 12.34 seconds |
| Started | Sep 24 05:23:01 PM UTC 24 |
| Finished | Sep 24 05:23:15 PM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125089609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.2125089609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/117.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_init_fail.1309630775 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 97910027 ps |
| CPU time | 4.98 seconds |
| Started | Sep 24 05:23:01 PM UTC 24 |
| Finished | Sep 24 05:23:07 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309630775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.1309630775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/118.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_parallel_lc_esc.2329456760 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 3284176076 ps |
| CPU time | 20.34 seconds |
| Started | Sep 24 05:23:01 PM UTC 24 |
| Finished | Sep 24 05:23:23 PM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329456760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.2329456760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/118.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_parallel_lc_esc.3168985768 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 188713023 ps |
| CPU time | 4.69 seconds |
| Started | Sep 24 05:23:01 PM UTC 24 |
| Finished | Sep 24 05:23:07 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168985768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.3168985768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/119.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_alert_test.1270018198 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 56230061 ps |
| CPU time | 2.81 seconds |
| Started | Sep 24 05:16:32 PM UTC 24 |
| Finished | Sep 24 05:16:36 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270018198 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.1270018198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_check_fail.76493683 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 426064315 ps |
| CPU time | 11.55 seconds |
| Started | Sep 24 05:16:29 PM UTC 24 |
| Finished | Sep 24 05:16:42 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76493683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.76493683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_errs.1594303279 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 12568796622 ps |
| CPU time | 39.77 seconds |
| Started | Sep 24 05:16:29 PM UTC 24 |
| Finished | Sep 24 05:17:11 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594303279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.1594303279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_lock.873090242 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2047102149 ps |
| CPU time | 17.6 seconds |
| Started | Sep 24 05:16:29 PM UTC 24 |
| Finished | Sep 24 05:16:48 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873090242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.873090242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_macro_errs.2068456283 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 3163541472 ps |
| CPU time | 41.53 seconds |
| Started | Sep 24 05:16:29 PM UTC 24 |
| Finished | Sep 24 05:17:13 PM UTC 24 |
| Peak memory | 258132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068456283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.2068456283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_key_req.1094136174 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1665949043 ps |
| CPU time | 41.63 seconds |
| Started | Sep 24 05:16:29 PM UTC 24 |
| Finished | Sep 24 05:17:13 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094136174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.1094136174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_esc.2595676805 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 639231064 ps |
| CPU time | 16.61 seconds |
| Started | Sep 24 05:16:26 PM UTC 24 |
| Finished | Sep 24 05:16:44 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595676805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.2595676805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_req.2083789326 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 861827023 ps |
| CPU time | 12.11 seconds |
| Started | Sep 24 05:16:25 PM UTC 24 |
| Finished | Sep 24 05:16:39 PM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083789326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.2083789326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_regwen.1714631668 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 3844631970 ps |
| CPU time | 10.79 seconds |
| Started | Sep 24 05:16:29 PM UTC 24 |
| Finished | Sep 24 05:16:42 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714631668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.1714631668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_smoke.2666992283 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 263595985 ps |
| CPU time | 7.88 seconds |
| Started | Sep 24 05:16:25 PM UTC 24 |
| Finished | Sep 24 05:16:35 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666992283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.2666992283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all.2913786511 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 12763978794 ps |
| CPU time | 58.01 seconds |
| Started | Sep 24 05:16:30 PM UTC 24 |
| Finished | Sep 24 05:17:30 PM UTC 24 |
| Peak memory | 253948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913786511 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.2913786511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_test_access.4049959870 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 13694845609 ps |
| CPU time | 36.5 seconds |
| Started | Sep 24 05:16:30 PM UTC 24 |
| Finished | Sep 24 05:17:08 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049959870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.4049959870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/12.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_parallel_lc_esc.3961288476 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 155250513 ps |
| CPU time | 5.43 seconds |
| Started | Sep 24 05:23:01 PM UTC 24 |
| Finished | Sep 24 05:23:08 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961288476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.3961288476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/120.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_init_fail.1964548610 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 119741387 ps |
| CPU time | 4.53 seconds |
| Started | Sep 24 05:23:01 PM UTC 24 |
| Finished | Sep 24 05:23:07 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964548610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.1964548610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/121.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_parallel_lc_esc.3066251104 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 1822712696 ps |
| CPU time | 11.63 seconds |
| Started | Sep 24 05:23:01 PM UTC 24 |
| Finished | Sep 24 05:23:14 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066251104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.3066251104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/121.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_init_fail.893556578 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 249506344 ps |
| CPU time | 3.26 seconds |
| Started | Sep 24 05:23:01 PM UTC 24 |
| Finished | Sep 24 05:23:06 PM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893556578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.893556578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/122.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_parallel_lc_esc.881651246 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 1916524880 ps |
| CPU time | 11.47 seconds |
| Started | Sep 24 05:23:01 PM UTC 24 |
| Finished | Sep 24 05:23:14 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881651246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.881651246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/122.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_parallel_lc_esc.1851534833 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 430893490 ps |
| CPU time | 12.9 seconds |
| Started | Sep 24 05:23:02 PM UTC 24 |
| Finished | Sep 24 05:23:16 PM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851534833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.1851534833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/123.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_init_fail.1756322066 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 108036466 ps |
| CPU time | 3.45 seconds |
| Started | Sep 24 05:23:02 PM UTC 24 |
| Finished | Sep 24 05:23:06 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756322066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.1756322066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/124.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_parallel_lc_esc.1897678008 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 3005044148 ps |
| CPU time | 10.66 seconds |
| Started | Sep 24 05:23:02 PM UTC 24 |
| Finished | Sep 24 05:23:14 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897678008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.1897678008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/124.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_init_fail.1580218246 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 131620994 ps |
| CPU time | 4.14 seconds |
| Started | Sep 24 05:23:02 PM UTC 24 |
| Finished | Sep 24 05:23:07 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580218246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.1580218246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/125.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_init_fail.129685164 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 200535596 ps |
| CPU time | 5.05 seconds |
| Started | Sep 24 05:23:02 PM UTC 24 |
| Finished | Sep 24 05:23:08 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129685164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.129685164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/126.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_parallel_lc_esc.2627954924 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2594791654 ps |
| CPU time | 17.3 seconds |
| Started | Sep 24 05:23:05 PM UTC 24 |
| Finished | Sep 24 05:23:24 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627954924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.2627954924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/126.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_parallel_lc_esc.3995445086 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 841555700 ps |
| CPU time | 12.67 seconds |
| Started | Sep 24 05:23:05 PM UTC 24 |
| Finished | Sep 24 05:23:19 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995445086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.3995445086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/127.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_init_fail.483773558 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 384839959 ps |
| CPU time | 5.8 seconds |
| Started | Sep 24 05:23:05 PM UTC 24 |
| Finished | Sep 24 05:23:12 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483773558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.483773558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/128.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_parallel_lc_esc.166282370 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 565745015 ps |
| CPU time | 6.75 seconds |
| Started | Sep 24 05:23:05 PM UTC 24 |
| Finished | Sep 24 05:23:13 PM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166282370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.166282370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/128.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_init_fail.4194311488 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 293391788 ps |
| CPU time | 4.78 seconds |
| Started | Sep 24 05:23:05 PM UTC 24 |
| Finished | Sep 24 05:23:11 PM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194311488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.4194311488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/129.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_parallel_lc_esc.105029907 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 385442924 ps |
| CPU time | 5.69 seconds |
| Started | Sep 24 05:23:10 PM UTC 24 |
| Finished | Sep 24 05:23:17 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105029907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.105029907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/129.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_alert_test.3116387511 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 165021345 ps |
| CPU time | 3.14 seconds |
| Started | Sep 24 05:16:39 PM UTC 24 |
| Finished | Sep 24 05:16:44 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116387511 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.3116387511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_check_fail.535328610 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 8909219406 ps |
| CPU time | 17 seconds |
| Started | Sep 24 05:16:36 PM UTC 24 |
| Finished | Sep 24 05:16:55 PM UTC 24 |
| Peak memory | 258256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535328610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.535328610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_errs.1959305439 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 2175645750 ps |
| CPU time | 32.92 seconds |
| Started | Sep 24 05:16:36 PM UTC 24 |
| Finished | Sep 24 05:17:11 PM UTC 24 |
| Peak memory | 251940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959305439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.1959305439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_lock.600852210 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 229527589 ps |
| CPU time | 7.63 seconds |
| Started | Sep 24 05:16:36 PM UTC 24 |
| Finished | Sep 24 05:16:45 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600852210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.600852210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_init_fail.2859710614 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 189460653 ps |
| CPU time | 4.45 seconds |
| Started | Sep 24 05:16:32 PM UTC 24 |
| Finished | Sep 24 05:16:38 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859710614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.2859710614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_macro_errs.2925785428 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 7550101417 ps |
| CPU time | 16.99 seconds |
| Started | Sep 24 05:16:36 PM UTC 24 |
| Finished | Sep 24 05:16:55 PM UTC 24 |
| Peak memory | 254112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925785428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.2925785428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_key_req.1865212766 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 213319597 ps |
| CPU time | 6.55 seconds |
| Started | Sep 24 05:16:39 PM UTC 24 |
| Finished | Sep 24 05:16:47 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865212766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.1865212766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_esc.3133833937 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 595481229 ps |
| CPU time | 7.31 seconds |
| Started | Sep 24 05:16:36 PM UTC 24 |
| Finished | Sep 24 05:16:45 PM UTC 24 |
| Peak memory | 252028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133833937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.3133833937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_req.2830108184 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 618142016 ps |
| CPU time | 13.26 seconds |
| Started | Sep 24 05:16:36 PM UTC 24 |
| Finished | Sep 24 05:16:51 PM UTC 24 |
| Peak memory | 258108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830108184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.2830108184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_regwen.2329028152 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 802087367 ps |
| CPU time | 9.11 seconds |
| Started | Sep 24 05:16:39 PM UTC 24 |
| Finished | Sep 24 05:16:50 PM UTC 24 |
| Peak memory | 250532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329028152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.2329028152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_smoke.3885692040 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 241109156 ps |
| CPU time | 5.44 seconds |
| Started | Sep 24 05:16:32 PM UTC 24 |
| Finished | Sep 24 05:16:38 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885692040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.3885692040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all.1710096946 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 10952295940 ps |
| CPU time | 100.79 seconds |
| Started | Sep 24 05:16:39 PM UTC 24 |
| Finished | Sep 24 05:18:22 PM UTC 24 |
| Peak memory | 255868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710096946 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.1710096946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_test_access.1266656180 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 947535202 ps |
| CPU time | 26.12 seconds |
| Started | Sep 24 05:16:39 PM UTC 24 |
| Finished | Sep 24 05:17:07 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266656180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.1266656180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/13.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_init_fail.828071969 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 161493353 ps |
| CPU time | 4.14 seconds |
| Started | Sep 24 05:23:10 PM UTC 24 |
| Finished | Sep 24 05:23:15 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828071969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.828071969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/130.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_parallel_lc_esc.2233076483 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 1092977346 ps |
| CPU time | 10.01 seconds |
| Started | Sep 24 05:23:10 PM UTC 24 |
| Finished | Sep 24 05:23:21 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233076483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.2233076483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/130.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_init_fail.553019389 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 420779056 ps |
| CPU time | 4.86 seconds |
| Started | Sep 24 05:23:10 PM UTC 24 |
| Finished | Sep 24 05:23:16 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553019389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.553019389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/131.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_parallel_lc_esc.4006613946 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 192945715 ps |
| CPU time | 5.76 seconds |
| Started | Sep 24 05:23:10 PM UTC 24 |
| Finished | Sep 24 05:23:17 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006613946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.4006613946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/131.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_parallel_lc_esc.950072956 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 2481155755 ps |
| CPU time | 21.1 seconds |
| Started | Sep 24 05:23:10 PM UTC 24 |
| Finished | Sep 24 05:23:33 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950072956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.950072956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/132.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_init_fail.807503537 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 279970235 ps |
| CPU time | 5.34 seconds |
| Started | Sep 24 05:23:10 PM UTC 24 |
| Finished | Sep 24 05:23:17 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807503537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.807503537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/133.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_parallel_lc_esc.757350342 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1119101053 ps |
| CPU time | 10.68 seconds |
| Started | Sep 24 05:23:10 PM UTC 24 |
| Finished | Sep 24 05:23:22 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757350342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.757350342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/133.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_init_fail.142960107 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 210172205 ps |
| CPU time | 5.81 seconds |
| Started | Sep 24 05:23:10 PM UTC 24 |
| Finished | Sep 24 05:23:17 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142960107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.142960107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/134.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_init_fail.3184305286 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 332899269 ps |
| CPU time | 4.5 seconds |
| Started | Sep 24 05:23:10 PM UTC 24 |
| Finished | Sep 24 05:23:16 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184305286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.3184305286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/135.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_parallel_lc_esc.2957747979 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 675963545 ps |
| CPU time | 9.74 seconds |
| Started | Sep 24 05:23:10 PM UTC 24 |
| Finished | Sep 24 05:23:22 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957747979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.2957747979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/135.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_init_fail.707217842 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 544615549 ps |
| CPU time | 4.38 seconds |
| Started | Sep 24 05:23:10 PM UTC 24 |
| Finished | Sep 24 05:23:16 PM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707217842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.707217842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/136.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_parallel_lc_esc.3794976762 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1373183519 ps |
| CPU time | 5.6 seconds |
| Started | Sep 24 05:23:13 PM UTC 24 |
| Finished | Sep 24 05:23:21 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794976762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.3794976762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/136.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_init_fail.3649116978 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 1999644396 ps |
| CPU time | 7.18 seconds |
| Started | Sep 24 05:23:13 PM UTC 24 |
| Finished | Sep 24 05:23:23 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649116978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.3649116978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/137.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_parallel_lc_esc.564648462 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 4040624335 ps |
| CPU time | 9.6 seconds |
| Started | Sep 24 05:23:13 PM UTC 24 |
| Finished | Sep 24 05:23:26 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564648462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.564648462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/137.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_init_fail.3721880764 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 2307410753 ps |
| CPU time | 4.17 seconds |
| Started | Sep 24 05:23:13 PM UTC 24 |
| Finished | Sep 24 05:23:21 PM UTC 24 |
| Peak memory | 251812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721880764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.3721880764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/138.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_parallel_lc_esc.408726238 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 255382521 ps |
| CPU time | 5.68 seconds |
| Started | Sep 24 05:23:13 PM UTC 24 |
| Finished | Sep 24 05:23:22 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408726238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.408726238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/138.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_init_fail.892047030 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 515209404 ps |
| CPU time | 3.84 seconds |
| Started | Sep 24 05:23:13 PM UTC 24 |
| Finished | Sep 24 05:23:21 PM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892047030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.892047030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/139.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_parallel_lc_esc.743460270 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 16559080532 ps |
| CPU time | 42.41 seconds |
| Started | Sep 24 05:23:16 PM UTC 24 |
| Finished | Sep 24 05:24:03 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743460270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.743460270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/139.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_alert_test.136440414 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 42672225 ps |
| CPU time | 2.17 seconds |
| Started | Sep 24 05:16:46 PM UTC 24 |
| Finished | Sep 24 05:16:50 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136440414 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.136440414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_check_fail.3020541324 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 258270072 ps |
| CPU time | 5.44 seconds |
| Started | Sep 24 05:16:42 PM UTC 24 |
| Finished | Sep 24 05:16:48 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020541324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.3020541324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_errs.283889215 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 11218961912 ps |
| CPU time | 43.71 seconds |
| Started | Sep 24 05:16:42 PM UTC 24 |
| Finished | Sep 24 05:17:27 PM UTC 24 |
| Peak memory | 254148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283889215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.283889215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_lock.676855199 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1985415897 ps |
| CPU time | 21.48 seconds |
| Started | Sep 24 05:16:41 PM UTC 24 |
| Finished | Sep 24 05:17:04 PM UTC 24 |
| Peak memory | 252064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676855199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.676855199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_init_fail.2531561409 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 324493213 ps |
| CPU time | 4.54 seconds |
| Started | Sep 24 05:16:40 PM UTC 24 |
| Finished | Sep 24 05:16:45 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531561409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.2531561409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_macro_errs.1872609002 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 407716241 ps |
| CPU time | 10.93 seconds |
| Started | Sep 24 05:16:44 PM UTC 24 |
| Finished | Sep 24 05:16:56 PM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872609002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.1872609002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_esc.748534498 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 2315227874 ps |
| CPU time | 15.65 seconds |
| Started | Sep 24 05:16:40 PM UTC 24 |
| Finished | Sep 24 05:16:57 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748534498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.748534498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_req.3821937694 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 11787277508 ps |
| CPU time | 39.21 seconds |
| Started | Sep 24 05:16:40 PM UTC 24 |
| Finished | Sep 24 05:17:20 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821937694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.3821937694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_regwen.14454734 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 282976705 ps |
| CPU time | 9.27 seconds |
| Started | Sep 24 05:16:44 PM UTC 24 |
| Finished | Sep 24 05:16:54 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14454734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ot p_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.14454734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_smoke.1615165693 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 244768104 ps |
| CPU time | 5.6 seconds |
| Started | Sep 24 05:16:39 PM UTC 24 |
| Finished | Sep 24 05:16:46 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615165693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.1615165693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_test_access.505678065 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1735061665 ps |
| CPU time | 19.9 seconds |
| Started | Sep 24 05:16:44 PM UTC 24 |
| Finished | Sep 24 05:17:05 PM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505678065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.505678065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/14.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_init_fail.1804865980 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 461954551 ps |
| CPU time | 4.63 seconds |
| Started | Sep 24 05:23:16 PM UTC 24 |
| Finished | Sep 24 05:23:25 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804865980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.1804865980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/140.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_parallel_lc_esc.528130676 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 826430780 ps |
| CPU time | 13.91 seconds |
| Started | Sep 24 05:23:16 PM UTC 24 |
| Finished | Sep 24 05:23:34 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528130676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.528130676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/140.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_init_fail.4128163532 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 241750190 ps |
| CPU time | 4.39 seconds |
| Started | Sep 24 05:23:16 PM UTC 24 |
| Finished | Sep 24 05:23:24 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128163532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.4128163532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/141.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_parallel_lc_esc.2976450010 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 712057189 ps |
| CPU time | 5.62 seconds |
| Started | Sep 24 05:23:16 PM UTC 24 |
| Finished | Sep 24 05:23:26 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976450010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.2976450010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/141.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_init_fail.21957956 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 90999489 ps |
| CPU time | 3.39 seconds |
| Started | Sep 24 05:23:16 PM UTC 24 |
| Finished | Sep 24 05:23:23 PM UTC 24 |
| Peak memory | 251804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21957956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.21957956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/142.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_init_fail.2653039146 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 273882005 ps |
| CPU time | 4.63 seconds |
| Started | Sep 24 05:23:18 PM UTC 24 |
| Finished | Sep 24 05:23:25 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653039146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.2653039146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/143.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_parallel_lc_esc.585019935 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 2279654933 ps |
| CPU time | 6.19 seconds |
| Started | Sep 24 05:23:19 PM UTC 24 |
| Finished | Sep 24 05:23:26 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585019935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.585019935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/143.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_init_fail.3698863254 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 205916995 ps |
| CPU time | 3.59 seconds |
| Started | Sep 24 05:23:19 PM UTC 24 |
| Finished | Sep 24 05:23:24 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698863254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.3698863254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/144.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_parallel_lc_esc.3311647131 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 2034844665 ps |
| CPU time | 12.9 seconds |
| Started | Sep 24 05:23:19 PM UTC 24 |
| Finished | Sep 24 05:23:33 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311647131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.3311647131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/144.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_init_fail.3198268758 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 149042449 ps |
| CPU time | 4.14 seconds |
| Started | Sep 24 05:23:19 PM UTC 24 |
| Finished | Sep 24 05:23:24 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198268758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.3198268758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/145.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_parallel_lc_esc.981904134 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 301559740 ps |
| CPU time | 4.47 seconds |
| Started | Sep 24 05:23:19 PM UTC 24 |
| Finished | Sep 24 05:23:25 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981904134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.981904134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/145.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_init_fail.2504303494 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 1650273556 ps |
| CPU time | 5.22 seconds |
| Started | Sep 24 05:23:19 PM UTC 24 |
| Finished | Sep 24 05:23:26 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504303494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.2504303494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/146.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_parallel_lc_esc.1718685367 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 234541839 ps |
| CPU time | 4.4 seconds |
| Started | Sep 24 05:23:23 PM UTC 24 |
| Finished | Sep 24 05:23:28 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718685367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.1718685367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/146.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_init_fail.2688772596 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 178302461 ps |
| CPU time | 3.04 seconds |
| Started | Sep 24 05:23:23 PM UTC 24 |
| Finished | Sep 24 05:23:27 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688772596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.2688772596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/147.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_parallel_lc_esc.756316769 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 2143611559 ps |
| CPU time | 19.22 seconds |
| Started | Sep 24 05:23:23 PM UTC 24 |
| Finished | Sep 24 05:23:43 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756316769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.756316769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/147.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_init_fail.2742378637 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 249652943 ps |
| CPU time | 3.14 seconds |
| Started | Sep 24 05:23:23 PM UTC 24 |
| Finished | Sep 24 05:23:27 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742378637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.2742378637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/148.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_parallel_lc_esc.3794459292 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 569838924 ps |
| CPU time | 5.04 seconds |
| Started | Sep 24 05:23:23 PM UTC 24 |
| Finished | Sep 24 05:23:29 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794459292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.3794459292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/148.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_init_fail.2844675789 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 141143734 ps |
| CPU time | 3.9 seconds |
| Started | Sep 24 05:23:23 PM UTC 24 |
| Finished | Sep 24 05:23:28 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844675789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.2844675789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/149.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_parallel_lc_esc.2634460242 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 410747472 ps |
| CPU time | 7.24 seconds |
| Started | Sep 24 05:23:23 PM UTC 24 |
| Finished | Sep 24 05:23:32 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634460242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.2634460242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/149.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_alert_test.830013153 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1388280133 ps |
| CPU time | 3.28 seconds |
| Started | Sep 24 05:16:52 PM UTC 24 |
| Finished | Sep 24 05:16:57 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830013153 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.830013153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_check_fail.1743559353 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 555021174 ps |
| CPU time | 7.15 seconds |
| Started | Sep 24 05:16:49 PM UTC 24 |
| Finished | Sep 24 05:16:58 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743559353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.1743559353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_errs.2428156303 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 633852162 ps |
| CPU time | 11.03 seconds |
| Started | Sep 24 05:16:49 PM UTC 24 |
| Finished | Sep 24 05:17:02 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428156303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.2428156303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_lock.3074860672 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 434334541 ps |
| CPU time | 9.92 seconds |
| Started | Sep 24 05:16:47 PM UTC 24 |
| Finished | Sep 24 05:16:58 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074860672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.3074860672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_init_fail.1307290351 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 278696631 ps |
| CPU time | 5.43 seconds |
| Started | Sep 24 05:16:47 PM UTC 24 |
| Finished | Sep 24 05:16:53 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307290351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.1307290351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_macro_errs.2026756429 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 940461783 ps |
| CPU time | 25.33 seconds |
| Started | Sep 24 05:16:50 PM UTC 24 |
| Finished | Sep 24 05:17:16 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026756429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.2026756429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_key_req.1003770819 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 200929834 ps |
| CPU time | 11.21 seconds |
| Started | Sep 24 05:16:50 PM UTC 24 |
| Finished | Sep 24 05:17:02 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003770819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.1003770819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_esc.77962787 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 191627780 ps |
| CPU time | 7.29 seconds |
| Started | Sep 24 05:16:47 PM UTC 24 |
| Finished | Sep 24 05:16:55 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77962787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.77962787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_req.951325469 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 388537183 ps |
| CPU time | 14.44 seconds |
| Started | Sep 24 05:16:47 PM UTC 24 |
| Finished | Sep 24 05:17:02 PM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951325469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.951325469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_regwen.1135115835 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 291466053 ps |
| CPU time | 7.23 seconds |
| Started | Sep 24 05:16:50 PM UTC 24 |
| Finished | Sep 24 05:16:58 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135115835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.1135115835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_smoke.4098381511 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 955557923 ps |
| CPU time | 12.46 seconds |
| Started | Sep 24 05:16:47 PM UTC 24 |
| Finished | Sep 24 05:17:00 PM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098381511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.4098381511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all.2651855299 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 23468938970 ps |
| CPU time | 379.39 seconds |
| Started | Sep 24 05:16:52 PM UTC 24 |
| Finished | Sep 24 05:23:17 PM UTC 24 |
| Peak memory | 273208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651855299 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.2651855299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.2621989764 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 3002904994 ps |
| CPU time | 54.08 seconds |
| Started | Sep 24 05:16:52 PM UTC 24 |
| Finished | Sep 24 05:17:48 PM UTC 24 |
| Peak memory | 268496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2621989764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.otp_ctrl_stress_all_with_rand_reset.2621989764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_test_access.2262354587 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 867980347 ps |
| CPU time | 10.67 seconds |
| Started | Sep 24 05:16:50 PM UTC 24 |
| Finished | Sep 24 05:17:01 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262354587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.2262354587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/15.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_init_fail.632750850 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 150834517 ps |
| CPU time | 3.5 seconds |
| Started | Sep 24 05:23:27 PM UTC 24 |
| Finished | Sep 24 05:23:32 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632750850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.632750850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/150.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_parallel_lc_esc.3670866051 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 502715420 ps |
| CPU time | 4.24 seconds |
| Started | Sep 24 05:23:27 PM UTC 24 |
| Finished | Sep 24 05:23:33 PM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670866051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.3670866051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/150.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_init_fail.1198573629 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 2151080632 ps |
| CPU time | 4.74 seconds |
| Started | Sep 24 05:23:27 PM UTC 24 |
| Finished | Sep 24 05:23:33 PM UTC 24 |
| Peak memory | 252012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198573629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.1198573629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/151.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_parallel_lc_esc.4004855173 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 1117898669 ps |
| CPU time | 15.23 seconds |
| Started | Sep 24 05:23:27 PM UTC 24 |
| Finished | Sep 24 05:23:44 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004855173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.4004855173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/151.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_init_fail.2418578172 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 147306096 ps |
| CPU time | 4.73 seconds |
| Started | Sep 24 05:23:27 PM UTC 24 |
| Finished | Sep 24 05:23:33 PM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418578172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.2418578172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/152.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_parallel_lc_esc.3210098888 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 4020030556 ps |
| CPU time | 16.21 seconds |
| Started | Sep 24 05:23:27 PM UTC 24 |
| Finished | Sep 24 05:23:45 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210098888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.3210098888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/152.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_init_fail.1486709889 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 165528793 ps |
| CPU time | 4.72 seconds |
| Started | Sep 24 05:23:28 PM UTC 24 |
| Finished | Sep 24 05:23:33 PM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486709889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.1486709889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/153.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_parallel_lc_esc.4168160954 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 452617597 ps |
| CPU time | 13.77 seconds |
| Started | Sep 24 05:23:28 PM UTC 24 |
| Finished | Sep 24 05:23:43 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168160954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.4168160954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/153.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_init_fail.1600174158 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 153606457 ps |
| CPU time | 4.93 seconds |
| Started | Sep 24 05:23:28 PM UTC 24 |
| Finished | Sep 24 05:23:34 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600174158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.1600174158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/154.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_parallel_lc_esc.2249612720 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 165493123 ps |
| CPU time | 5.86 seconds |
| Started | Sep 24 05:23:28 PM UTC 24 |
| Finished | Sep 24 05:23:35 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249612720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.2249612720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/154.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_init_fail.704513364 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 150911257 ps |
| CPU time | 5.2 seconds |
| Started | Sep 24 05:23:28 PM UTC 24 |
| Finished | Sep 24 05:23:34 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704513364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.704513364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/155.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_parallel_lc_esc.3501252845 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 319274669 ps |
| CPU time | 3.32 seconds |
| Started | Sep 24 05:23:28 PM UTC 24 |
| Finished | Sep 24 05:23:32 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501252845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.3501252845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/155.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_init_fail.390547260 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 376572598 ps |
| CPU time | 5.02 seconds |
| Started | Sep 24 05:23:28 PM UTC 24 |
| Finished | Sep 24 05:23:34 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390547260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.390547260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/156.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_parallel_lc_esc.772975186 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 200813216 ps |
| CPU time | 9.9 seconds |
| Started | Sep 24 05:23:28 PM UTC 24 |
| Finished | Sep 24 05:23:39 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772975186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.772975186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/156.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_init_fail.2591029475 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 145561089 ps |
| CPU time | 3.96 seconds |
| Started | Sep 24 05:23:28 PM UTC 24 |
| Finished | Sep 24 05:23:33 PM UTC 24 |
| Peak memory | 251464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591029475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.2591029475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/157.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_parallel_lc_esc.2595754018 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 233104931 ps |
| CPU time | 4.96 seconds |
| Started | Sep 24 05:23:28 PM UTC 24 |
| Finished | Sep 24 05:23:34 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595754018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.2595754018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/157.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_init_fail.529180866 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 151193915 ps |
| CPU time | 5.22 seconds |
| Started | Sep 24 05:23:28 PM UTC 24 |
| Finished | Sep 24 05:23:34 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529180866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.529180866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/158.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_parallel_lc_esc.671890341 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 1001304249 ps |
| CPU time | 12.5 seconds |
| Started | Sep 24 05:23:28 PM UTC 24 |
| Finished | Sep 24 05:23:42 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671890341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.671890341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/158.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_init_fail.1689668305 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 2391979871 ps |
| CPU time | 4.52 seconds |
| Started | Sep 24 05:23:28 PM UTC 24 |
| Finished | Sep 24 05:23:34 PM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689668305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.1689668305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/159.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_parallel_lc_esc.833067283 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 293739484 ps |
| CPU time | 5.68 seconds |
| Started | Sep 24 05:23:28 PM UTC 24 |
| Finished | Sep 24 05:23:35 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833067283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.833067283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/159.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_alert_test.3013387237 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 222044707 ps |
| CPU time | 2.97 seconds |
| Started | Sep 24 05:16:59 PM UTC 24 |
| Finished | Sep 24 05:17:03 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013387237 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.3013387237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_check_fail.1200066304 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1105131610 ps |
| CPU time | 16.28 seconds |
| Started | Sep 24 05:16:57 PM UTC 24 |
| Finished | Sep 24 05:17:15 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200066304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.1200066304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_errs.1911369348 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 17051274242 ps |
| CPU time | 58.97 seconds |
| Started | Sep 24 05:16:57 PM UTC 24 |
| Finished | Sep 24 05:17:58 PM UTC 24 |
| Peak memory | 258268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911369348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.1911369348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_init_fail.1033991016 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 217515988 ps |
| CPU time | 5.13 seconds |
| Started | Sep 24 05:16:52 PM UTC 24 |
| Finished | Sep 24 05:16:59 PM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033991016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.1033991016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_key_req.2172917779 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 217101246 ps |
| CPU time | 4.71 seconds |
| Started | Sep 24 05:16:57 PM UTC 24 |
| Finished | Sep 24 05:17:03 PM UTC 24 |
| Peak memory | 252024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172917779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.2172917779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_esc.3551120470 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 208091750 ps |
| CPU time | 8.05 seconds |
| Started | Sep 24 05:16:54 PM UTC 24 |
| Finished | Sep 24 05:17:03 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551120470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.3551120470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_req.2090844003 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 1710113648 ps |
| CPU time | 25.01 seconds |
| Started | Sep 24 05:16:54 PM UTC 24 |
| Finished | Sep 24 05:17:20 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090844003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.2090844003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_regwen.938746117 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 883911364 ps |
| CPU time | 12.13 seconds |
| Started | Sep 24 05:16:57 PM UTC 24 |
| Finished | Sep 24 05:17:11 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938746117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.938746117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_smoke.2979201168 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 1798865365 ps |
| CPU time | 10.62 seconds |
| Started | Sep 24 05:16:52 PM UTC 24 |
| Finished | Sep 24 05:17:04 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979201168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.2979201168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all.1125157339 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 13344459999 ps |
| CPU time | 148.97 seconds |
| Started | Sep 24 05:16:59 PM UTC 24 |
| Finished | Sep 24 05:19:31 PM UTC 24 |
| Peak memory | 282776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125157339 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.1125157339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.1672128710 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 5730631669 ps |
| CPU time | 65.13 seconds |
| Started | Sep 24 05:16:59 PM UTC 24 |
| Finished | Sep 24 05:18:06 PM UTC 24 |
| Peak memory | 272136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1672128710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.otp_ctrl_stress_all_with_rand_reset.1672128710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_test_access.2342971747 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 556526971 ps |
| CPU time | 19.2 seconds |
| Started | Sep 24 05:16:57 PM UTC 24 |
| Finished | Sep 24 05:17:18 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342971747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.2342971747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/16.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_parallel_lc_esc.3391228561 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 663997424 ps |
| CPU time | 3.74 seconds |
| Started | Sep 24 05:23:28 PM UTC 24 |
| Finished | Sep 24 05:23:33 PM UTC 24 |
| Peak memory | 251708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391228561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.3391228561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/160.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_init_fail.271963700 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 196574847 ps |
| CPU time | 5.61 seconds |
| Started | Sep 24 05:23:31 PM UTC 24 |
| Finished | Sep 24 05:23:38 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271963700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.271963700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/161.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_parallel_lc_esc.246677788 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 591979739 ps |
| CPU time | 19.07 seconds |
| Started | Sep 24 05:23:31 PM UTC 24 |
| Finished | Sep 24 05:23:51 PM UTC 24 |
| Peak memory | 252052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246677788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.246677788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/161.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_init_fail.1861127537 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 133433495 ps |
| CPU time | 3.6 seconds |
| Started | Sep 24 05:23:31 PM UTC 24 |
| Finished | Sep 24 05:23:36 PM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861127537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.1861127537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/162.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_parallel_lc_esc.17658251 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 136661535 ps |
| CPU time | 3.9 seconds |
| Started | Sep 24 05:23:31 PM UTC 24 |
| Finished | Sep 24 05:23:36 PM UTC 24 |
| Peak memory | 251704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17658251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.17658251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/162.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_init_fail.3494762249 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 1495137682 ps |
| CPU time | 6.16 seconds |
| Started | Sep 24 05:23:31 PM UTC 24 |
| Finished | Sep 24 05:23:38 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494762249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.3494762249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/163.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_parallel_lc_esc.3150903730 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 480621613 ps |
| CPU time | 4.31 seconds |
| Started | Sep 24 05:23:31 PM UTC 24 |
| Finished | Sep 24 05:23:36 PM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150903730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.3150903730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/163.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_init_fail.3254697396 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 333312875 ps |
| CPU time | 4.75 seconds |
| Started | Sep 24 05:23:31 PM UTC 24 |
| Finished | Sep 24 05:23:37 PM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254697396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.3254697396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/164.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_parallel_lc_esc.836987283 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 1253919594 ps |
| CPU time | 15.75 seconds |
| Started | Sep 24 05:23:31 PM UTC 24 |
| Finished | Sep 24 05:23:48 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836987283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.836987283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/164.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_init_fail.2731660671 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 622598141 ps |
| CPU time | 6.28 seconds |
| Started | Sep 24 05:23:31 PM UTC 24 |
| Finished | Sep 24 05:23:39 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731660671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.2731660671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/165.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_parallel_lc_esc.719703094 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 1076618278 ps |
| CPU time | 9.66 seconds |
| Started | Sep 24 05:23:31 PM UTC 24 |
| Finished | Sep 24 05:23:42 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719703094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.719703094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/165.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_init_fail.930984253 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 128712271 ps |
| CPU time | 3.82 seconds |
| Started | Sep 24 05:23:31 PM UTC 24 |
| Finished | Sep 24 05:23:36 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930984253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.930984253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/166.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_parallel_lc_esc.1933321305 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 331917825 ps |
| CPU time | 13.73 seconds |
| Started | Sep 24 05:23:33 PM UTC 24 |
| Finished | Sep 24 05:23:48 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933321305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.1933321305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/166.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_init_fail.3846004554 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 1447744374 ps |
| CPU time | 5.16 seconds |
| Started | Sep 24 05:23:33 PM UTC 24 |
| Finished | Sep 24 05:23:39 PM UTC 24 |
| Peak memory | 252020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846004554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.3846004554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/167.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_parallel_lc_esc.4027673687 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 542426554 ps |
| CPU time | 8.55 seconds |
| Started | Sep 24 05:23:33 PM UTC 24 |
| Finished | Sep 24 05:23:42 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027673687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.4027673687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/167.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_init_fail.1727391962 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 104223386 ps |
| CPU time | 4.17 seconds |
| Started | Sep 24 05:23:36 PM UTC 24 |
| Finished | Sep 24 05:23:41 PM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727391962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.1727391962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/168.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_parallel_lc_esc.3462199583 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 236400857 ps |
| CPU time | 7.47 seconds |
| Started | Sep 24 05:23:36 PM UTC 24 |
| Finished | Sep 24 05:23:44 PM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462199583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.3462199583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/168.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_init_fail.142177833 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 304283412 ps |
| CPU time | 5.61 seconds |
| Started | Sep 24 05:23:36 PM UTC 24 |
| Finished | Sep 24 05:23:42 PM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142177833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.142177833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/169.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_parallel_lc_esc.4162327074 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 1397598105 ps |
| CPU time | 14 seconds |
| Started | Sep 24 05:23:36 PM UTC 24 |
| Finished | Sep 24 05:23:51 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162327074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.4162327074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/169.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_alert_test.4033456557 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 819031447 ps |
| CPU time | 3.95 seconds |
| Started | Sep 24 05:17:06 PM UTC 24 |
| Finished | Sep 24 05:17:11 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033456557 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.4033456557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_check_fail.3281853649 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 630067111 ps |
| CPU time | 13.54 seconds |
| Started | Sep 24 05:17:04 PM UTC 24 |
| Finished | Sep 24 05:17:19 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281853649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.3281853649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_errs.593061384 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1573696861 ps |
| CPU time | 36.39 seconds |
| Started | Sep 24 05:17:04 PM UTC 24 |
| Finished | Sep 24 05:17:42 PM UTC 24 |
| Peak memory | 253944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593061384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.593061384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_lock.871566963 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 9084527252 ps |
| CPU time | 29.08 seconds |
| Started | Sep 24 05:17:04 PM UTC 24 |
| Finished | Sep 24 05:17:34 PM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871566963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.871566963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_init_fail.3258661064 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 149189436 ps |
| CPU time | 5.44 seconds |
| Started | Sep 24 05:16:59 PM UTC 24 |
| Finished | Sep 24 05:17:06 PM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258661064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.3258661064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_macro_errs.3548467911 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 1067919540 ps |
| CPU time | 38.91 seconds |
| Started | Sep 24 05:17:04 PM UTC 24 |
| Finished | Sep 24 05:17:44 PM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548467911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.3548467911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_key_req.3123348889 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 116773273 ps |
| CPU time | 4.95 seconds |
| Started | Sep 24 05:17:04 PM UTC 24 |
| Finished | Sep 24 05:17:10 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123348889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.3123348889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_esc.314214995 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 268809714 ps |
| CPU time | 7.86 seconds |
| Started | Sep 24 05:17:02 PM UTC 24 |
| Finished | Sep 24 05:17:11 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314214995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.314214995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_req.1046477007 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 515736946 ps |
| CPU time | 13.69 seconds |
| Started | Sep 24 05:17:02 PM UTC 24 |
| Finished | Sep 24 05:17:17 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046477007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.1046477007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_regwen.14924815 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 262928977 ps |
| CPU time | 9.61 seconds |
| Started | Sep 24 05:17:04 PM UTC 24 |
| Finished | Sep 24 05:17:15 PM UTC 24 |
| Peak memory | 251616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14924815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ot p_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.14924815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_smoke.2871801993 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 271490759 ps |
| CPU time | 14.02 seconds |
| Started | Sep 24 05:16:59 PM UTC 24 |
| Finished | Sep 24 05:17:15 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871801993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.2871801993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all.4166617772 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 3098628523 ps |
| CPU time | 46.19 seconds |
| Started | Sep 24 05:17:06 PM UTC 24 |
| Finished | Sep 24 05:17:54 PM UTC 24 |
| Peak memory | 254076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166617772 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.4166617772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_test_access.772022484 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 320558082 ps |
| CPU time | 7.83 seconds |
| Started | Sep 24 05:17:04 PM UTC 24 |
| Finished | Sep 24 05:17:13 PM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772022484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.772022484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/17.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_init_fail.1969969981 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 90320504 ps |
| CPU time | 3.45 seconds |
| Started | Sep 24 05:23:36 PM UTC 24 |
| Finished | Sep 24 05:23:40 PM UTC 24 |
| Peak memory | 251876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969969981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.1969969981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/170.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_parallel_lc_esc.3318466199 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 1298474761 ps |
| CPU time | 11.48 seconds |
| Started | Sep 24 05:23:36 PM UTC 24 |
| Finished | Sep 24 05:23:49 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318466199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.3318466199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/170.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_init_fail.785378262 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1669395459 ps |
| CPU time | 6.3 seconds |
| Started | Sep 24 05:23:36 PM UTC 24 |
| Finished | Sep 24 05:23:43 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785378262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.785378262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/171.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_parallel_lc_esc.2805636939 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 228259226 ps |
| CPU time | 5.86 seconds |
| Started | Sep 24 05:23:36 PM UTC 24 |
| Finished | Sep 24 05:23:43 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805636939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.2805636939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/171.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_init_fail.1669155706 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 295180264 ps |
| CPU time | 6.88 seconds |
| Started | Sep 24 05:23:36 PM UTC 24 |
| Finished | Sep 24 05:23:44 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669155706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.1669155706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/172.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_init_fail.1672082846 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 144046268 ps |
| CPU time | 4.94 seconds |
| Started | Sep 24 05:23:36 PM UTC 24 |
| Finished | Sep 24 05:23:42 PM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672082846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.1672082846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/173.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_parallel_lc_esc.4028609022 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 152588348 ps |
| CPU time | 4.47 seconds |
| Started | Sep 24 05:23:36 PM UTC 24 |
| Finished | Sep 24 05:23:42 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028609022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.4028609022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/173.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_init_fail.870535503 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 435838130 ps |
| CPU time | 4.75 seconds |
| Started | Sep 24 05:23:36 PM UTC 24 |
| Finished | Sep 24 05:23:42 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870535503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.870535503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/174.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_parallel_lc_esc.3038252166 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 256473918 ps |
| CPU time | 6.39 seconds |
| Started | Sep 24 05:23:36 PM UTC 24 |
| Finished | Sep 24 05:23:44 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038252166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.3038252166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/174.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_parallel_lc_esc.2903581234 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 388049659 ps |
| CPU time | 11 seconds |
| Started | Sep 24 05:23:36 PM UTC 24 |
| Finished | Sep 24 05:23:49 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903581234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.2903581234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/175.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_init_fail.3215941362 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 464263767 ps |
| CPU time | 5.36 seconds |
| Started | Sep 24 05:23:36 PM UTC 24 |
| Finished | Sep 24 05:23:43 PM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215941362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.3215941362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/176.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_parallel_lc_esc.3702842769 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 109735296 ps |
| CPU time | 2.71 seconds |
| Started | Sep 24 05:23:37 PM UTC 24 |
| Finished | Sep 24 05:23:40 PM UTC 24 |
| Peak memory | 251708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702842769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.3702842769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/176.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_init_fail.1998367217 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 117115403 ps |
| CPU time | 4.09 seconds |
| Started | Sep 24 05:23:38 PM UTC 24 |
| Finished | Sep 24 05:23:44 PM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998367217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.1998367217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/177.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_parallel_lc_esc.677240550 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 311479808 ps |
| CPU time | 4.57 seconds |
| Started | Sep 24 05:23:39 PM UTC 24 |
| Finished | Sep 24 05:23:44 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677240550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.677240550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/177.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_init_fail.518646854 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 134238616 ps |
| CPU time | 5.21 seconds |
| Started | Sep 24 05:23:39 PM UTC 24 |
| Finished | Sep 24 05:23:45 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518646854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.518646854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/178.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_parallel_lc_esc.2882394734 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 331297533 ps |
| CPU time | 4.5 seconds |
| Started | Sep 24 05:23:39 PM UTC 24 |
| Finished | Sep 24 05:23:44 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882394734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.2882394734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/178.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_init_fail.3371294386 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 168266238 ps |
| CPU time | 4.25 seconds |
| Started | Sep 24 05:23:39 PM UTC 24 |
| Finished | Sep 24 05:23:44 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371294386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.3371294386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/179.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_parallel_lc_esc.818584966 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 283294101 ps |
| CPU time | 14.39 seconds |
| Started | Sep 24 05:23:39 PM UTC 24 |
| Finished | Sep 24 05:23:54 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818584966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.818584966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/179.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_alert_test.2673150810 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 63437493 ps |
| CPU time | 2.91 seconds |
| Started | Sep 24 05:17:19 PM UTC 24 |
| Finished | Sep 24 05:17:23 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673150810 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.2673150810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_errs.3995290805 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 6930238186 ps |
| CPU time | 27.68 seconds |
| Started | Sep 24 05:17:15 PM UTC 24 |
| Finished | Sep 24 05:17:44 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995290805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.3995290805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_lock.3266259210 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 673869469 ps |
| CPU time | 8.08 seconds |
| Started | Sep 24 05:17:15 PM UTC 24 |
| Finished | Sep 24 05:17:25 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266259210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.3266259210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_init_fail.3233427943 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 198351096 ps |
| CPU time | 5.55 seconds |
| Started | Sep 24 05:17:09 PM UTC 24 |
| Finished | Sep 24 05:17:16 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233427943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.3233427943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_macro_errs.1956709087 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 1062105223 ps |
| CPU time | 11.44 seconds |
| Started | Sep 24 05:17:16 PM UTC 24 |
| Finished | Sep 24 05:17:28 PM UTC 24 |
| Peak memory | 254044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956709087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.1956709087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_key_req.1464921109 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 186150699 ps |
| CPU time | 5.38 seconds |
| Started | Sep 24 05:17:16 PM UTC 24 |
| Finished | Sep 24 05:17:22 PM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464921109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.1464921109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_esc.3760441550 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 701564946 ps |
| CPU time | 6.81 seconds |
| Started | Sep 24 05:17:10 PM UTC 24 |
| Finished | Sep 24 05:17:18 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760441550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.3760441550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_req.3833083880 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 606336819 ps |
| CPU time | 10.38 seconds |
| Started | Sep 24 05:17:09 PM UTC 24 |
| Finished | Sep 24 05:17:21 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833083880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.3833083880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_regwen.3178366902 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 503639561 ps |
| CPU time | 7.03 seconds |
| Started | Sep 24 05:17:16 PM UTC 24 |
| Finished | Sep 24 05:17:24 PM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178366902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.3178366902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_smoke.4238707725 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 715665547 ps |
| CPU time | 7.29 seconds |
| Started | Sep 24 05:17:07 PM UTC 24 |
| Finished | Sep 24 05:17:16 PM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238707725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.4238707725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all.3045414663 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 808222070 ps |
| CPU time | 17.12 seconds |
| Started | Sep 24 05:17:19 PM UTC 24 |
| Finished | Sep 24 05:17:38 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045414663 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.3045414663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_test_access.2126298587 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 3232079506 ps |
| CPU time | 21.47 seconds |
| Started | Sep 24 05:17:19 PM UTC 24 |
| Finished | Sep 24 05:17:42 PM UTC 24 |
| Peak memory | 251620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126298587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.2126298587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/18.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_init_fail.2088155264 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 113654514 ps |
| CPU time | 3.49 seconds |
| Started | Sep 24 05:23:41 PM UTC 24 |
| Finished | Sep 24 05:23:46 PM UTC 24 |
| Peak memory | 252012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088155264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.2088155264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/180.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_parallel_lc_esc.3123895906 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 1120693199 ps |
| CPU time | 26.91 seconds |
| Started | Sep 24 05:23:41 PM UTC 24 |
| Finished | Sep 24 05:24:09 PM UTC 24 |
| Peak memory | 251872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123895906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.3123895906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_init_fail.596611287 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 132770923 ps |
| CPU time | 4.52 seconds |
| Started | Sep 24 05:23:41 PM UTC 24 |
| Finished | Sep 24 05:23:47 PM UTC 24 |
| Peak memory | 252020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596611287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.596611287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/181.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_parallel_lc_esc.279942069 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 304791312 ps |
| CPU time | 8.11 seconds |
| Started | Sep 24 05:23:41 PM UTC 24 |
| Finished | Sep 24 05:23:50 PM UTC 24 |
| Peak memory | 252044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279942069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.279942069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/181.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_init_fail.15863130 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 333955273 ps |
| CPU time | 3.25 seconds |
| Started | Sep 24 05:23:41 PM UTC 24 |
| Finished | Sep 24 05:23:46 PM UTC 24 |
| Peak memory | 251940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15863130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.15863130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/182.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_parallel_lc_esc.2089631057 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 246877403 ps |
| CPU time | 6.04 seconds |
| Started | Sep 24 05:23:41 PM UTC 24 |
| Finished | Sep 24 05:23:48 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089631057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.2089631057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/182.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_init_fail.783542511 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 391853021 ps |
| CPU time | 4.16 seconds |
| Started | Sep 24 05:23:43 PM UTC 24 |
| Finished | Sep 24 05:23:48 PM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783542511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.783542511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/183.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_parallel_lc_esc.591825948 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 258567762 ps |
| CPU time | 7.1 seconds |
| Started | Sep 24 05:23:43 PM UTC 24 |
| Finished | Sep 24 05:23:51 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591825948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.591825948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/183.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_init_fail.3169801609 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 131753054 ps |
| CPU time | 3.46 seconds |
| Started | Sep 24 05:23:43 PM UTC 24 |
| Finished | Sep 24 05:23:47 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169801609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.3169801609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/184.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_parallel_lc_esc.1577649149 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 139867658 ps |
| CPU time | 5.6 seconds |
| Started | Sep 24 05:23:43 PM UTC 24 |
| Finished | Sep 24 05:23:50 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577649149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.1577649149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/184.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_init_fail.3414256714 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 327411464 ps |
| CPU time | 3.89 seconds |
| Started | Sep 24 05:23:43 PM UTC 24 |
| Finished | Sep 24 05:23:48 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414256714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.3414256714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/185.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.4138868454 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 367082154 ps |
| CPU time | 6.55 seconds |
| Started | Sep 24 05:23:43 PM UTC 24 |
| Finished | Sep 24 05:23:51 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138868454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.4138868454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/185.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_init_fail.355577030 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 746330502 ps |
| CPU time | 4.9 seconds |
| Started | Sep 24 05:23:43 PM UTC 24 |
| Finished | Sep 24 05:23:49 PM UTC 24 |
| Peak memory | 251952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355577030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.355577030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/186.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.2596930896 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 9011941126 ps |
| CPU time | 29.51 seconds |
| Started | Sep 24 05:23:43 PM UTC 24 |
| Finished | Sep 24 05:24:14 PM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596930896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.2596930896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/186.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_init_fail.1212458005 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 280637583 ps |
| CPU time | 4.01 seconds |
| Started | Sep 24 05:23:43 PM UTC 24 |
| Finished | Sep 24 05:23:48 PM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212458005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.1212458005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/187.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.2941967463 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 598151192 ps |
| CPU time | 7.48 seconds |
| Started | Sep 24 05:23:47 PM UTC 24 |
| Finished | Sep 24 05:23:56 PM UTC 24 |
| Peak memory | 251632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941967463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.2941967463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/187.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_init_fail.2881676171 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 222747813 ps |
| CPU time | 4.03 seconds |
| Started | Sep 24 05:23:47 PM UTC 24 |
| Finished | Sep 24 05:23:52 PM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881676171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.2881676171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/188.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.698676500 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 200344531 ps |
| CPU time | 5.49 seconds |
| Started | Sep 24 05:23:47 PM UTC 24 |
| Finished | Sep 24 05:23:54 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698676500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.698676500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/188.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_init_fail.3679590109 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 1899088984 ps |
| CPU time | 6.89 seconds |
| Started | Sep 24 05:23:47 PM UTC 24 |
| Finished | Sep 24 05:23:55 PM UTC 24 |
| Peak memory | 252012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679590109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.3679590109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/189.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.846377818 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 145300368 ps |
| CPU time | 6.54 seconds |
| Started | Sep 24 05:23:47 PM UTC 24 |
| Finished | Sep 24 05:23:55 PM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846377818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.846377818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/189.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_alert_test.1529499774 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 99556362 ps |
| CPU time | 2.87 seconds |
| Started | Sep 24 05:17:23 PM UTC 24 |
| Finished | Sep 24 05:17:27 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529499774 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.1529499774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_check_fail.3831803344 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2677042763 ps |
| CPU time | 17.93 seconds |
| Started | Sep 24 05:17:20 PM UTC 24 |
| Finished | Sep 24 05:17:39 PM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831803344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.3831803344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_errs.2738272913 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 689983354 ps |
| CPU time | 18.98 seconds |
| Started | Sep 24 05:17:20 PM UTC 24 |
| Finished | Sep 24 05:17:40 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738272913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.2738272913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_lock.2842939921 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 127381188 ps |
| CPU time | 5.29 seconds |
| Started | Sep 24 05:17:20 PM UTC 24 |
| Finished | Sep 24 05:17:26 PM UTC 24 |
| Peak memory | 251940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842939921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.2842939921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_init_fail.1877943233 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 538954875 ps |
| CPU time | 5.04 seconds |
| Started | Sep 24 05:17:20 PM UTC 24 |
| Finished | Sep 24 05:17:26 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877943233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.1877943233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_macro_errs.3263979154 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 326271316 ps |
| CPU time | 8.76 seconds |
| Started | Sep 24 05:17:20 PM UTC 24 |
| Finished | Sep 24 05:17:30 PM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263979154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.3263979154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_key_req.2330228527 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1377592867 ps |
| CPU time | 27.8 seconds |
| Started | Sep 24 05:17:20 PM UTC 24 |
| Finished | Sep 24 05:17:49 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330228527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.2330228527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_esc.1114392400 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 251632971 ps |
| CPU time | 5.99 seconds |
| Started | Sep 24 05:17:20 PM UTC 24 |
| Finished | Sep 24 05:17:27 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114392400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.1114392400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_req.876389112 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 128879664 ps |
| CPU time | 4.36 seconds |
| Started | Sep 24 05:17:20 PM UTC 24 |
| Finished | Sep 24 05:17:25 PM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876389112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.876389112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_regwen.2882143425 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 345943699 ps |
| CPU time | 9.74 seconds |
| Started | Sep 24 05:17:23 PM UTC 24 |
| Finished | Sep 24 05:17:34 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882143425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.2882143425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_smoke.502163004 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1327505105 ps |
| CPU time | 11.99 seconds |
| Started | Sep 24 05:17:20 PM UTC 24 |
| Finished | Sep 24 05:17:33 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502163004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.502163004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all.532753533 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 25149844357 ps |
| CPU time | 213.22 seconds |
| Started | Sep 24 05:17:23 PM UTC 24 |
| Finished | Sep 24 05:21:00 PM UTC 24 |
| Peak memory | 268276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532753533 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.532753533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_test_access.3929364542 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 12535865133 ps |
| CPU time | 40.99 seconds |
| Started | Sep 24 05:17:23 PM UTC 24 |
| Finished | Sep 24 05:18:05 PM UTC 24 |
| Peak memory | 254036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929364542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.3929364542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/19.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.888927889 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 134508004 ps |
| CPU time | 3.74 seconds |
| Started | Sep 24 05:23:47 PM UTC 24 |
| Finished | Sep 24 05:23:52 PM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888927889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.888927889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/190.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.3949744772 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 370270236 ps |
| CPU time | 9.54 seconds |
| Started | Sep 24 05:23:47 PM UTC 24 |
| Finished | Sep 24 05:23:58 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949744772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.3949744772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/190.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_init_fail.682339114 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 236800630 ps |
| CPU time | 4.39 seconds |
| Started | Sep 24 05:23:47 PM UTC 24 |
| Finished | Sep 24 05:23:53 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682339114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.682339114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/191.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.1965423965 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 1997688579 ps |
| CPU time | 7.78 seconds |
| Started | Sep 24 05:23:47 PM UTC 24 |
| Finished | Sep 24 05:23:56 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965423965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.1965423965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/191.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_init_fail.822198432 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 627056881 ps |
| CPU time | 4.39 seconds |
| Started | Sep 24 05:23:47 PM UTC 24 |
| Finished | Sep 24 05:23:53 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822198432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.822198432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/192.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.1927804456 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 11198285997 ps |
| CPU time | 25.83 seconds |
| Started | Sep 24 05:23:48 PM UTC 24 |
| Finished | Sep 24 05:24:15 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927804456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.1927804456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/192.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.529779329 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 366771442 ps |
| CPU time | 3.89 seconds |
| Started | Sep 24 05:23:48 PM UTC 24 |
| Finished | Sep 24 05:23:52 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529779329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.529779329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/193.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.3304021425 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 124084749 ps |
| CPU time | 4.88 seconds |
| Started | Sep 24 05:23:48 PM UTC 24 |
| Finished | Sep 24 05:23:54 PM UTC 24 |
| Peak memory | 252028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304021425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.3304021425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/193.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_init_fail.3434697321 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 2485860099 ps |
| CPU time | 6.51 seconds |
| Started | Sep 24 05:23:48 PM UTC 24 |
| Finished | Sep 24 05:23:55 PM UTC 24 |
| Peak memory | 251944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434697321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.3434697321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/194.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.1823160490 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 153485516 ps |
| CPU time | 5.15 seconds |
| Started | Sep 24 05:23:48 PM UTC 24 |
| Finished | Sep 24 05:23:54 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823160490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.1823160490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/194.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.2210105822 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 265112152 ps |
| CPU time | 4.62 seconds |
| Started | Sep 24 05:23:48 PM UTC 24 |
| Finished | Sep 24 05:23:54 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210105822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.2210105822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/195.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.2599903603 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 3533728472 ps |
| CPU time | 27.69 seconds |
| Started | Sep 24 05:23:48 PM UTC 24 |
| Finished | Sep 24 05:24:17 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599903603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.2599903603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/195.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.1428303652 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 102527053 ps |
| CPU time | 3.53 seconds |
| Started | Sep 24 05:23:48 PM UTC 24 |
| Finished | Sep 24 05:23:53 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428303652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.1428303652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/196.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.1277788102 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 1806009609 ps |
| CPU time | 24.84 seconds |
| Started | Sep 24 05:23:50 PM UTC 24 |
| Finished | Sep 24 05:24:18 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277788102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.1277788102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/196.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.3005930799 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 187043596 ps |
| CPU time | 3.59 seconds |
| Started | Sep 24 05:23:50 PM UTC 24 |
| Finished | Sep 24 05:23:57 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005930799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.3005930799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/197.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.1854032895 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 167024114 ps |
| CPU time | 6.16 seconds |
| Started | Sep 24 05:23:50 PM UTC 24 |
| Finished | Sep 24 05:24:00 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854032895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.1854032895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/197.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.3054077875 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 139273886 ps |
| CPU time | 3.65 seconds |
| Started | Sep 24 05:23:51 PM UTC 24 |
| Finished | Sep 24 05:23:57 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054077875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.3054077875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/198.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.3842119520 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 1809678463 ps |
| CPU time | 10.96 seconds |
| Started | Sep 24 05:23:51 PM UTC 24 |
| Finished | Sep 24 05:24:04 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842119520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.3842119520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/198.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.955510039 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 122768186 ps |
| CPU time | 3.61 seconds |
| Started | Sep 24 05:23:51 PM UTC 24 |
| Finished | Sep 24 05:23:58 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955510039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.955510039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/199.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.992936311 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 419873948 ps |
| CPU time | 11.03 seconds |
| Started | Sep 24 05:23:51 PM UTC 24 |
| Finished | Sep 24 05:24:06 PM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992936311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.992936311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/199.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_alert_test.1343474811 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 768740649 ps |
| CPU time | 3.32 seconds |
| Started | Sep 24 05:15:25 PM UTC 24 |
| Finished | Sep 24 05:15:29 PM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343474811 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.1343474811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_background_chks.478365848 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 688962709 ps |
| CPU time | 12.02 seconds |
| Started | Sep 24 05:15:21 PM UTC 24 |
| Finished | Sep 24 05:15:35 PM UTC 24 |
| Peak memory | 257800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478365848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.478365848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_check_fail.404742183 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 682871857 ps |
| CPU time | 10.56 seconds |
| Started | Sep 24 05:15:25 PM UTC 24 |
| Finished | Sep 24 05:15:36 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404742183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.404742183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_errs.3961862163 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4159987459 ps |
| CPU time | 24.28 seconds |
| Started | Sep 24 05:15:21 PM UTC 24 |
| Finished | Sep 24 05:15:47 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961862163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.3961862163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_lock.1739465532 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 436154568 ps |
| CPU time | 12.49 seconds |
| Started | Sep 24 05:15:21 PM UTC 24 |
| Finished | Sep 24 05:15:35 PM UTC 24 |
| Peak memory | 251612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739465532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.1739465532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_esc.2148923287 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 334488522 ps |
| CPU time | 6.82 seconds |
| Started | Sep 24 05:15:21 PM UTC 24 |
| Finished | Sep 24 05:15:29 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148923287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.2148923287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_req.4051753841 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 507660621 ps |
| CPU time | 13.24 seconds |
| Started | Sep 24 05:15:21 PM UTC 24 |
| Finished | Sep 24 05:15:36 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051753841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.4051753841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_regwen.2244445804 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 153749471 ps |
| CPU time | 6.14 seconds |
| Started | Sep 24 05:15:25 PM UTC 24 |
| Finished | Sep 24 05:15:32 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244445804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.2244445804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_sec_cm.2500081186 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 165390720326 ps |
| CPU time | 441.71 seconds |
| Started | Sep 24 05:15:25 PM UTC 24 |
| Finished | Sep 24 05:22:53 PM UTC 24 |
| Peak memory | 293480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500081186 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.2500081186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_smoke.3391836000 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 187583715 ps |
| CPU time | 5.08 seconds |
| Started | Sep 24 05:15:20 PM UTC 24 |
| Finished | Sep 24 05:15:26 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391836000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.3391836000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all.2949964575 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 15357432033 ps |
| CPU time | 218.97 seconds |
| Started | Sep 24 05:15:25 PM UTC 24 |
| Finished | Sep 24 05:19:07 PM UTC 24 |
| Peak memory | 258292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949964575 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.2949964575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_alert_test.345139504 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 74492547 ps |
| CPU time | 2.78 seconds |
| Started | Sep 24 05:17:31 PM UTC 24 |
| Finished | Sep 24 05:17:35 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345139504 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.345139504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/20.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_check_fail.1468763685 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 2693676172 ps |
| CPU time | 26.26 seconds |
| Started | Sep 24 05:17:27 PM UTC 24 |
| Finished | Sep 24 05:17:54 PM UTC 24 |
| Peak memory | 252048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468763685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.1468763685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_errs.2126452276 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 302480299 ps |
| CPU time | 19.64 seconds |
| Started | Sep 24 05:17:27 PM UTC 24 |
| Finished | Sep 24 05:17:48 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126452276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.2126452276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/20.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_lock.1314847268 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 7059712104 ps |
| CPU time | 19.57 seconds |
| Started | Sep 24 05:17:27 PM UTC 24 |
| Finished | Sep 24 05:17:47 PM UTC 24 |
| Peak memory | 253900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314847268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.1314847268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/20.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_init_fail.1889717858 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 513500851 ps |
| CPU time | 3.66 seconds |
| Started | Sep 24 05:17:25 PM UTC 24 |
| Finished | Sep 24 05:17:30 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889717858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.1889717858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/20.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_macro_errs.333796512 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 26569883649 ps |
| CPU time | 55.41 seconds |
| Started | Sep 24 05:17:28 PM UTC 24 |
| Finished | Sep 24 05:18:26 PM UTC 24 |
| Peak memory | 274592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333796512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.333796512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/20.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_key_req.1719804237 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 2746523562 ps |
| CPU time | 19.01 seconds |
| Started | Sep 24 05:17:28 PM UTC 24 |
| Finished | Sep 24 05:17:49 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719804237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.1719804237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_esc.2374653938 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 94707950 ps |
| CPU time | 4.48 seconds |
| Started | Sep 24 05:17:25 PM UTC 24 |
| Finished | Sep 24 05:17:31 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374653938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.2374653938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_req.2723955433 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 3029284612 ps |
| CPU time | 8.94 seconds |
| Started | Sep 24 05:17:25 PM UTC 24 |
| Finished | Sep 24 05:17:35 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723955433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.2723955433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_regwen.1974103832 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 236203282 ps |
| CPU time | 8.04 seconds |
| Started | Sep 24 05:17:29 PM UTC 24 |
| Finished | Sep 24 05:17:38 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974103832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.1974103832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/20.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_smoke.3507909992 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1603385476 ps |
| CPU time | 12.1 seconds |
| Started | Sep 24 05:17:24 PM UTC 24 |
| Finished | Sep 24 05:17:37 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507909992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.3507909992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/20.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all.3511747300 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 27800501618 ps |
| CPU time | 149.57 seconds |
| Started | Sep 24 05:17:31 PM UTC 24 |
| Finished | Sep 24 05:20:03 PM UTC 24 |
| Peak memory | 274520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511747300 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.3511747300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_test_access.3606580105 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 432155316 ps |
| CPU time | 6.45 seconds |
| Started | Sep 24 05:17:31 PM UTC 24 |
| Finished | Sep 24 05:17:38 PM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606580105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.3606580105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/20.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.1421153906 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 269149367 ps |
| CPU time | 4.03 seconds |
| Started | Sep 24 05:23:51 PM UTC 24 |
| Finished | Sep 24 05:23:59 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421153906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.1421153906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/200.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.63319958 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 467835861 ps |
| CPU time | 5.27 seconds |
| Started | Sep 24 05:23:51 PM UTC 24 |
| Finished | Sep 24 05:24:00 PM UTC 24 |
| Peak memory | 251868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63319958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.63319958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/201.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.483375277 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 2975967421 ps |
| CPU time | 5.16 seconds |
| Started | Sep 24 05:23:51 PM UTC 24 |
| Finished | Sep 24 05:24:00 PM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483375277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.483375277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/202.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.1058042617 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 250167955 ps |
| CPU time | 3.45 seconds |
| Started | Sep 24 05:23:51 PM UTC 24 |
| Finished | Sep 24 05:23:58 PM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058042617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.1058042617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/203.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.3397672987 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 150373911 ps |
| CPU time | 3.42 seconds |
| Started | Sep 24 05:23:51 PM UTC 24 |
| Finished | Sep 24 05:23:58 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397672987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.3397672987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/204.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.2075270559 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 1808990811 ps |
| CPU time | 4.23 seconds |
| Started | Sep 24 05:23:51 PM UTC 24 |
| Finished | Sep 24 05:23:59 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075270559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.2075270559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/205.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.629345515 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 118357502 ps |
| CPU time | 2.88 seconds |
| Started | Sep 24 05:23:51 PM UTC 24 |
| Finished | Sep 24 05:23:58 PM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629345515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.629345515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/206.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.934651897 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 143733620 ps |
| CPU time | 3.96 seconds |
| Started | Sep 24 05:23:51 PM UTC 24 |
| Finished | Sep 24 05:23:59 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934651897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.934651897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/207.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.3346577973 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 130846295 ps |
| CPU time | 3.14 seconds |
| Started | Sep 24 05:23:51 PM UTC 24 |
| Finished | Sep 24 05:23:58 PM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346577973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.3346577973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/208.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.3174023101 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1477070957 ps |
| CPU time | 4.26 seconds |
| Started | Sep 24 05:23:53 PM UTC 24 |
| Finished | Sep 24 05:24:02 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174023101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.3174023101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/209.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_alert_test.3806549416 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 765036002 ps |
| CPU time | 3.67 seconds |
| Started | Sep 24 05:17:42 PM UTC 24 |
| Finished | Sep 24 05:17:46 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806549416 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.3806549416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/21.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_errs.1654563793 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 438428179 ps |
| CPU time | 11.98 seconds |
| Started | Sep 24 05:17:38 PM UTC 24 |
| Finished | Sep 24 05:17:51 PM UTC 24 |
| Peak memory | 252036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654563793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.1654563793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/21.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_lock.3922747401 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 276583728 ps |
| CPU time | 8.73 seconds |
| Started | Sep 24 05:17:38 PM UTC 24 |
| Finished | Sep 24 05:17:48 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922747401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.3922747401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/21.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_init_fail.3317686598 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 226755243 ps |
| CPU time | 4.49 seconds |
| Started | Sep 24 05:17:36 PM UTC 24 |
| Finished | Sep 24 05:17:41 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317686598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.3317686598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/21.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_macro_errs.667193274 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 520394467 ps |
| CPU time | 12.2 seconds |
| Started | Sep 24 05:17:38 PM UTC 24 |
| Finished | Sep 24 05:17:51 PM UTC 24 |
| Peak memory | 252048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667193274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.667193274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/21.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_key_req.2848033997 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 859350273 ps |
| CPU time | 29.04 seconds |
| Started | Sep 24 05:17:38 PM UTC 24 |
| Finished | Sep 24 05:18:09 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848033997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.2848033997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_esc.3065640238 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 415758401 ps |
| CPU time | 15.08 seconds |
| Started | Sep 24 05:17:38 PM UTC 24 |
| Finished | Sep 24 05:17:54 PM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065640238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.3065640238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_req.3229710740 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 570912293 ps |
| CPU time | 18.77 seconds |
| Started | Sep 24 05:17:36 PM UTC 24 |
| Finished | Sep 24 05:17:56 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229710740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.3229710740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_regwen.4182537072 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 169196307 ps |
| CPU time | 5.69 seconds |
| Started | Sep 24 05:17:40 PM UTC 24 |
| Finished | Sep 24 05:17:47 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182537072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.4182537072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/21.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_smoke.1019535809 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 1911937997 ps |
| CPU time | 6.27 seconds |
| Started | Sep 24 05:17:36 PM UTC 24 |
| Finished | Sep 24 05:17:43 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019535809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.1019535809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/21.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all.2060691844 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 11288677906 ps |
| CPU time | 124.77 seconds |
| Started | Sep 24 05:17:40 PM UTC 24 |
| Finished | Sep 24 05:19:47 PM UTC 24 |
| Peak memory | 268412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060691844 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.2060691844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_test_access.1003908491 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 3733947812 ps |
| CPU time | 45.29 seconds |
| Started | Sep 24 05:17:40 PM UTC 24 |
| Finished | Sep 24 05:18:27 PM UTC 24 |
| Peak memory | 254088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003908491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.1003908491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/21.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.3184216845 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 436505153 ps |
| CPU time | 3.77 seconds |
| Started | Sep 24 05:23:53 PM UTC 24 |
| Finished | Sep 24 05:24:03 PM UTC 24 |
| Peak memory | 251868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184216845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.3184216845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/210.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.1722427227 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 113235786 ps |
| CPU time | 4.38 seconds |
| Started | Sep 24 05:23:53 PM UTC 24 |
| Finished | Sep 24 05:24:03 PM UTC 24 |
| Peak memory | 252024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722427227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.1722427227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/211.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.2960702854 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 169024420 ps |
| CPU time | 4.01 seconds |
| Started | Sep 24 05:23:53 PM UTC 24 |
| Finished | Sep 24 05:24:03 PM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960702854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.2960702854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/212.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.2953789295 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 111641585 ps |
| CPU time | 3.68 seconds |
| Started | Sep 24 05:23:53 PM UTC 24 |
| Finished | Sep 24 05:24:02 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953789295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.2953789295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/213.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.516526651 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 125063446 ps |
| CPU time | 4.66 seconds |
| Started | Sep 24 05:23:53 PM UTC 24 |
| Finished | Sep 24 05:24:04 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516526651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.516526651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/214.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.606224375 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 706146185 ps |
| CPU time | 5.32 seconds |
| Started | Sep 24 05:23:53 PM UTC 24 |
| Finished | Sep 24 05:24:04 PM UTC 24 |
| Peak memory | 251668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606224375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.606224375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/215.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.588608097 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 387576104 ps |
| CPU time | 3.28 seconds |
| Started | Sep 24 05:23:53 PM UTC 24 |
| Finished | Sep 24 05:24:02 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588608097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.588608097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/216.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.2079510212 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 133378970 ps |
| CPU time | 4.93 seconds |
| Started | Sep 24 05:23:53 PM UTC 24 |
| Finished | Sep 24 05:24:04 PM UTC 24 |
| Peak memory | 252024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079510212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.2079510212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/217.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.1948677422 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 353652088 ps |
| CPU time | 4.77 seconds |
| Started | Sep 24 05:23:53 PM UTC 24 |
| Finished | Sep 24 05:24:04 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948677422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.1948677422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/218.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.532622955 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 2170349537 ps |
| CPU time | 6.55 seconds |
| Started | Sep 24 05:23:55 PM UTC 24 |
| Finished | Sep 24 05:24:06 PM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532622955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.532622955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/219.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_alert_test.1813216221 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 68917377 ps |
| CPU time | 2.64 seconds |
| Started | Sep 24 05:17:50 PM UTC 24 |
| Finished | Sep 24 05:17:54 PM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813216221 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.1813216221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/22.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_check_fail.4081794034 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 386611633 ps |
| CPU time | 7.95 seconds |
| Started | Sep 24 05:17:50 PM UTC 24 |
| Finished | Sep 24 05:17:59 PM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081794034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.4081794034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/22.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_errs.3412477954 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 499691712 ps |
| CPU time | 15.99 seconds |
| Started | Sep 24 05:17:50 PM UTC 24 |
| Finished | Sep 24 05:18:07 PM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412477954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.3412477954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/22.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_lock.3131626511 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 498896322 ps |
| CPU time | 11.51 seconds |
| Started | Sep 24 05:17:44 PM UTC 24 |
| Finished | Sep 24 05:17:57 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131626511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.3131626511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/22.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_init_fail.244242042 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2915236750 ps |
| CPU time | 12.13 seconds |
| Started | Sep 24 05:17:44 PM UTC 24 |
| Finished | Sep 24 05:17:58 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244242042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.244242042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/22.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_macro_errs.3973935485 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1294364046 ps |
| CPU time | 13.83 seconds |
| Started | Sep 24 05:17:50 PM UTC 24 |
| Finished | Sep 24 05:18:05 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973935485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.3973935485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/22.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_key_req.622374903 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 620119155 ps |
| CPU time | 19.79 seconds |
| Started | Sep 24 05:17:50 PM UTC 24 |
| Finished | Sep 24 05:18:11 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622374903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.622374903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_req.1542182467 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 440584428 ps |
| CPU time | 7.83 seconds |
| Started | Sep 24 05:17:44 PM UTC 24 |
| Finished | Sep 24 05:17:53 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542182467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.1542182467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_regwen.4152521451 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 232411896 ps |
| CPU time | 8.29 seconds |
| Started | Sep 24 05:17:50 PM UTC 24 |
| Finished | Sep 24 05:18:00 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152521451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.4152521451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/22.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_smoke.1908190219 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 271237926 ps |
| CPU time | 7.96 seconds |
| Started | Sep 24 05:17:44 PM UTC 24 |
| Finished | Sep 24 05:17:53 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908190219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.1908190219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/22.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all.3179388360 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 6537858172 ps |
| CPU time | 50.98 seconds |
| Started | Sep 24 05:17:50 PM UTC 24 |
| Finished | Sep 24 05:18:43 PM UTC 24 |
| Peak memory | 258036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179388360 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.3179388360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_test_access.4047570557 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 377487270 ps |
| CPU time | 7.65 seconds |
| Started | Sep 24 05:17:50 PM UTC 24 |
| Finished | Sep 24 05:17:59 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047570557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.4047570557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/22.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.2512757875 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 228088180 ps |
| CPU time | 4.35 seconds |
| Started | Sep 24 05:23:55 PM UTC 24 |
| Finished | Sep 24 05:24:04 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512757875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.2512757875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/220.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.4112883955 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 205312119 ps |
| CPU time | 4.01 seconds |
| Started | Sep 24 05:23:55 PM UTC 24 |
| Finished | Sep 24 05:24:04 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112883955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.4112883955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/221.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.2460662434 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 1475643291 ps |
| CPU time | 5.57 seconds |
| Started | Sep 24 05:23:55 PM UTC 24 |
| Finished | Sep 24 05:24:05 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460662434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.2460662434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/222.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.2808130419 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 117122714 ps |
| CPU time | 3.35 seconds |
| Started | Sep 24 05:23:55 PM UTC 24 |
| Finished | Sep 24 05:24:03 PM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808130419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.2808130419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/223.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.4238696774 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 201581335 ps |
| CPU time | 3.64 seconds |
| Started | Sep 24 05:23:55 PM UTC 24 |
| Finished | Sep 24 05:24:03 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238696774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.4238696774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/224.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.192337627 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 483021299 ps |
| CPU time | 3.85 seconds |
| Started | Sep 24 05:23:56 PM UTC 24 |
| Finished | Sep 24 05:24:04 PM UTC 24 |
| Peak memory | 251704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192337627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.192337627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/225.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.3044239941 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 579244300 ps |
| CPU time | 4.07 seconds |
| Started | Sep 24 05:23:56 PM UTC 24 |
| Finished | Sep 24 05:24:05 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044239941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.3044239941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/226.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.1706524519 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 411508690 ps |
| CPU time | 4.22 seconds |
| Started | Sep 24 05:23:57 PM UTC 24 |
| Finished | Sep 24 05:24:05 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706524519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.1706524519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/227.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.635693580 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 402675679 ps |
| CPU time | 3.53 seconds |
| Started | Sep 24 05:23:57 PM UTC 24 |
| Finished | Sep 24 05:24:04 PM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635693580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.635693580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/228.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.3527822852 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 330964376 ps |
| CPU time | 4.51 seconds |
| Started | Sep 24 05:23:57 PM UTC 24 |
| Finished | Sep 24 05:24:05 PM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527822852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.3527822852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/229.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_alert_test.1067349108 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 737971889 ps |
| CPU time | 4.92 seconds |
| Started | Sep 24 05:17:59 PM UTC 24 |
| Finished | Sep 24 05:18:05 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067349108 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.1067349108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/23.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_check_fail.3834280518 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 1499023932 ps |
| CPU time | 22.95 seconds |
| Started | Sep 24 05:17:59 PM UTC 24 |
| Finished | Sep 24 05:18:23 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834280518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.3834280518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/23.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_errs.583601524 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 4204672397 ps |
| CPU time | 21.69 seconds |
| Started | Sep 24 05:17:55 PM UTC 24 |
| Finished | Sep 24 05:18:19 PM UTC 24 |
| Peak memory | 251972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583601524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.583601524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/23.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_lock.3212120711 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 844298590 ps |
| CPU time | 27.66 seconds |
| Started | Sep 24 05:17:55 PM UTC 24 |
| Finished | Sep 24 05:18:25 PM UTC 24 |
| Peak memory | 252068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212120711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.3212120711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/23.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_init_fail.3807553623 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1922728944 ps |
| CPU time | 6.89 seconds |
| Started | Sep 24 05:17:55 PM UTC 24 |
| Finished | Sep 24 05:18:03 PM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807553623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.3807553623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/23.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_macro_errs.4033004227 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 234042564 ps |
| CPU time | 3.5 seconds |
| Started | Sep 24 05:17:59 PM UTC 24 |
| Finished | Sep 24 05:18:03 PM UTC 24 |
| Peak memory | 252128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033004227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.4033004227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/23.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_key_req.3087265269 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 7297923471 ps |
| CPU time | 22.86 seconds |
| Started | Sep 24 05:17:59 PM UTC 24 |
| Finished | Sep 24 05:18:23 PM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087265269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.3087265269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_esc.144856212 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 118455345 ps |
| CPU time | 3 seconds |
| Started | Sep 24 05:17:55 PM UTC 24 |
| Finished | Sep 24 05:18:00 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144856212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.144856212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_req.1042402265 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2000172927 ps |
| CPU time | 25.05 seconds |
| Started | Sep 24 05:17:55 PM UTC 24 |
| Finished | Sep 24 05:18:22 PM UTC 24 |
| Peak memory | 252024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042402265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.1042402265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_regwen.3542297434 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 662837569 ps |
| CPU time | 8.13 seconds |
| Started | Sep 24 05:17:59 PM UTC 24 |
| Finished | Sep 24 05:18:08 PM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542297434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.3542297434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/23.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_smoke.4098702060 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 3565992553 ps |
| CPU time | 12.27 seconds |
| Started | Sep 24 05:17:55 PM UTC 24 |
| Finished | Sep 24 05:18:09 PM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098702060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.4098702060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/23.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all.1567889134 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 22022945012 ps |
| CPU time | 149.36 seconds |
| Started | Sep 24 05:17:59 PM UTC 24 |
| Finished | Sep 24 05:20:31 PM UTC 24 |
| Peak memory | 270420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567889134 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.1567889134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_test_access.863966292 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 815043735 ps |
| CPU time | 8.95 seconds |
| Started | Sep 24 05:17:59 PM UTC 24 |
| Finished | Sep 24 05:18:09 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863966292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.863966292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/23.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.391026962 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 502847173 ps |
| CPU time | 4.42 seconds |
| Started | Sep 24 05:23:58 PM UTC 24 |
| Finished | Sep 24 05:24:05 PM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391026962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.391026962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/230.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.626320478 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 144611586 ps |
| CPU time | 4.68 seconds |
| Started | Sep 24 05:23:59 PM UTC 24 |
| Finished | Sep 24 05:24:05 PM UTC 24 |
| Peak memory | 251952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626320478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.626320478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/231.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.17139355 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 104787053 ps |
| CPU time | 3.08 seconds |
| Started | Sep 24 05:24:01 PM UTC 24 |
| Finished | Sep 24 05:24:05 PM UTC 24 |
| Peak memory | 251664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17139355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.17139355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/232.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.303495167 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 328988154 ps |
| CPU time | 5.23 seconds |
| Started | Sep 24 05:24:01 PM UTC 24 |
| Finished | Sep 24 05:24:07 PM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303495167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.303495167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/233.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.471910022 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 276067645 ps |
| CPU time | 4.37 seconds |
| Started | Sep 24 05:24:01 PM UTC 24 |
| Finished | Sep 24 05:24:06 PM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471910022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.471910022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/234.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.811180813 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 88881884 ps |
| CPU time | 3.4 seconds |
| Started | Sep 24 05:24:01 PM UTC 24 |
| Finished | Sep 24 05:24:05 PM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811180813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.811180813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/235.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.3851285945 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 470587112 ps |
| CPU time | 5.15 seconds |
| Started | Sep 24 05:24:01 PM UTC 24 |
| Finished | Sep 24 05:24:07 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851285945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.3851285945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/236.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.4152939058 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 443791373 ps |
| CPU time | 4.51 seconds |
| Started | Sep 24 05:24:01 PM UTC 24 |
| Finished | Sep 24 05:24:06 PM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152939058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.4152939058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/237.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.1643567995 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 2462552917 ps |
| CPU time | 5.15 seconds |
| Started | Sep 24 05:24:01 PM UTC 24 |
| Finished | Sep 24 05:24:07 PM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643567995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.1643567995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/239.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_alert_test.3598776588 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 829209950 ps |
| CPU time | 2.52 seconds |
| Started | Sep 24 05:18:07 PM UTC 24 |
| Finished | Sep 24 05:18:10 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598776588 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.3598776588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/24.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_check_fail.901203866 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 9296230280 ps |
| CPU time | 27.34 seconds |
| Started | Sep 24 05:18:02 PM UTC 24 |
| Finished | Sep 24 05:18:31 PM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901203866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.901203866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/24.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_errs.3456616018 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 630016631 ps |
| CPU time | 19.16 seconds |
| Started | Sep 24 05:18:02 PM UTC 24 |
| Finished | Sep 24 05:18:23 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456616018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.3456616018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/24.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_lock.2880351299 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 1452870965 ps |
| CPU time | 29.15 seconds |
| Started | Sep 24 05:18:02 PM UTC 24 |
| Finished | Sep 24 05:18:33 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880351299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.2880351299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/24.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_init_fail.3395671056 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 152452102 ps |
| CPU time | 3.82 seconds |
| Started | Sep 24 05:17:59 PM UTC 24 |
| Finished | Sep 24 05:18:05 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395671056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.3395671056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/24.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_macro_errs.1042787221 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 2224981599 ps |
| CPU time | 27.27 seconds |
| Started | Sep 24 05:18:02 PM UTC 24 |
| Finished | Sep 24 05:18:31 PM UTC 24 |
| Peak memory | 253968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042787221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.1042787221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/24.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_key_req.434014233 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 20142414624 ps |
| CPU time | 50.14 seconds |
| Started | Sep 24 05:18:02 PM UTC 24 |
| Finished | Sep 24 05:18:55 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434014233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.434014233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_esc.3383194848 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1323896519 ps |
| CPU time | 21.27 seconds |
| Started | Sep 24 05:17:59 PM UTC 24 |
| Finished | Sep 24 05:18:22 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383194848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.3383194848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_req.536417132 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2116785602 ps |
| CPU time | 17.46 seconds |
| Started | Sep 24 05:17:59 PM UTC 24 |
| Finished | Sep 24 05:18:18 PM UTC 24 |
| Peak memory | 251952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536417132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.536417132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_regwen.175615271 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 250709705 ps |
| CPU time | 7.27 seconds |
| Started | Sep 24 05:18:04 PM UTC 24 |
| Finished | Sep 24 05:18:13 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175615271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.175615271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/24.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_smoke.1033300410 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 688980570 ps |
| CPU time | 8.58 seconds |
| Started | Sep 24 05:17:59 PM UTC 24 |
| Finished | Sep 24 05:18:09 PM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033300410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.1033300410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/24.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all.1094562408 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 14208383028 ps |
| CPU time | 162.26 seconds |
| Started | Sep 24 05:18:07 PM UTC 24 |
| Finished | Sep 24 05:20:52 PM UTC 24 |
| Peak memory | 274612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094562408 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all.1094562408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.842944949 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 17131497803 ps |
| CPU time | 77.66 seconds |
| Started | Sep 24 05:18:07 PM UTC 24 |
| Finished | Sep 24 05:19:26 PM UTC 24 |
| Peak memory | 258104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=842944949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.842944949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_test_access.3835759549 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 604622201 ps |
| CPU time | 12.72 seconds |
| Started | Sep 24 05:18:04 PM UTC 24 |
| Finished | Sep 24 05:18:18 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835759549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.3835759549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/24.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.2327067999 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 537779070 ps |
| CPU time | 3.82 seconds |
| Started | Sep 24 05:24:01 PM UTC 24 |
| Finished | Sep 24 05:24:06 PM UTC 24 |
| Peak memory | 251944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327067999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.2327067999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/240.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.937636855 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1592766788 ps |
| CPU time | 4.29 seconds |
| Started | Sep 24 05:24:01 PM UTC 24 |
| Finished | Sep 24 05:24:06 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937636855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.937636855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/241.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.281873671 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 177005975 ps |
| CPU time | 4.94 seconds |
| Started | Sep 24 05:24:01 PM UTC 24 |
| Finished | Sep 24 05:24:07 PM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281873671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.281873671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/243.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.3157689566 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 235216135 ps |
| CPU time | 3.36 seconds |
| Started | Sep 24 05:24:04 PM UTC 24 |
| Finished | Sep 24 05:24:09 PM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157689566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.3157689566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/244.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.3456146375 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 1298255035 ps |
| CPU time | 4.44 seconds |
| Started | Sep 24 05:24:04 PM UTC 24 |
| Finished | Sep 24 05:24:10 PM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456146375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.3456146375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/245.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.1275445173 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 217548856 ps |
| CPU time | 4.43 seconds |
| Started | Sep 24 05:24:04 PM UTC 24 |
| Finished | Sep 24 05:24:10 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275445173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.1275445173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/246.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.3622831246 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 577698643 ps |
| CPU time | 4.76 seconds |
| Started | Sep 24 05:24:04 PM UTC 24 |
| Finished | Sep 24 05:24:10 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622831246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.3622831246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/247.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.3288129920 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 291710989 ps |
| CPU time | 3.39 seconds |
| Started | Sep 24 05:24:04 PM UTC 24 |
| Finished | Sep 24 05:24:09 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288129920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.3288129920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/248.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.1938147464 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 476949775 ps |
| CPU time | 3.84 seconds |
| Started | Sep 24 05:24:04 PM UTC 24 |
| Finished | Sep 24 05:24:09 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938147464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.1938147464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/249.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_alert_test.3903800801 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 45591489 ps |
| CPU time | 2.76 seconds |
| Started | Sep 24 05:18:14 PM UTC 24 |
| Finished | Sep 24 05:18:18 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903800801 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.3903800801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/25.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_check_fail.2599398932 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 7517984703 ps |
| CPU time | 15.53 seconds |
| Started | Sep 24 05:18:12 PM UTC 24 |
| Finished | Sep 24 05:18:29 PM UTC 24 |
| Peak memory | 254032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599398932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.2599398932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/25.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_errs.109643884 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1056914560 ps |
| CPU time | 21.98 seconds |
| Started | Sep 24 05:18:09 PM UTC 24 |
| Finished | Sep 24 05:18:33 PM UTC 24 |
| Peak memory | 252048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109643884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.109643884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/25.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_lock.3617490180 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 2789808517 ps |
| CPU time | 23.56 seconds |
| Started | Sep 24 05:18:09 PM UTC 24 |
| Finished | Sep 24 05:18:34 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617490180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.3617490180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/25.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_init_fail.4122856908 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 183962120 ps |
| CPU time | 5.17 seconds |
| Started | Sep 24 05:18:07 PM UTC 24 |
| Finished | Sep 24 05:18:13 PM UTC 24 |
| Peak memory | 252028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122856908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.4122856908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/25.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_macro_errs.1449750357 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2098182477 ps |
| CPU time | 20.52 seconds |
| Started | Sep 24 05:18:12 PM UTC 24 |
| Finished | Sep 24 05:18:34 PM UTC 24 |
| Peak memory | 256148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449750357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.1449750357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/25.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_key_req.3111166382 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 189901189 ps |
| CPU time | 6.39 seconds |
| Started | Sep 24 05:18:12 PM UTC 24 |
| Finished | Sep 24 05:18:20 PM UTC 24 |
| Peak memory | 251664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111166382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.3111166382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_esc.2287856893 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 173925097 ps |
| CPU time | 3.71 seconds |
| Started | Sep 24 05:18:09 PM UTC 24 |
| Finished | Sep 24 05:18:14 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287856893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.2287856893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_req.2242685036 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 1096358686 ps |
| CPU time | 23.82 seconds |
| Started | Sep 24 05:18:07 PM UTC 24 |
| Finished | Sep 24 05:18:32 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242685036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.2242685036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_regwen.2462537380 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 150186349 ps |
| CPU time | 6.18 seconds |
| Started | Sep 24 05:18:12 PM UTC 24 |
| Finished | Sep 24 05:18:20 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462537380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.2462537380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/25.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_smoke.3144316566 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 544395323 ps |
| CPU time | 13.52 seconds |
| Started | Sep 24 05:18:07 PM UTC 24 |
| Finished | Sep 24 05:18:22 PM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144316566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.3144316566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/25.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all.1493204853 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 7926932640 ps |
| CPU time | 139.48 seconds |
| Started | Sep 24 05:18:14 PM UTC 24 |
| Finished | Sep 24 05:20:36 PM UTC 24 |
| Peak memory | 268280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493204853 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.1493204853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_test_access.2969622326 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 861321657 ps |
| CPU time | 16.81 seconds |
| Started | Sep 24 05:18:12 PM UTC 24 |
| Finished | Sep 24 05:18:30 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969622326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.2969622326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/25.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.3418134889 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 303341160 ps |
| CPU time | 3.16 seconds |
| Started | Sep 24 05:24:04 PM UTC 24 |
| Finished | Sep 24 05:24:09 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418134889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.3418134889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/250.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.4190686257 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 1492214123 ps |
| CPU time | 4.84 seconds |
| Started | Sep 24 05:24:04 PM UTC 24 |
| Finished | Sep 24 05:24:11 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190686257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.4190686257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/251.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.218527601 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 184048177 ps |
| CPU time | 3.85 seconds |
| Started | Sep 24 05:24:04 PM UTC 24 |
| Finished | Sep 24 05:24:10 PM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218527601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.218527601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/252.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.681170160 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 114933426 ps |
| CPU time | 3.47 seconds |
| Started | Sep 24 05:24:04 PM UTC 24 |
| Finished | Sep 24 05:24:09 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681170160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.681170160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/253.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.1157894420 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 267283000 ps |
| CPU time | 4.06 seconds |
| Started | Sep 24 05:24:04 PM UTC 24 |
| Finished | Sep 24 05:24:10 PM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157894420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.1157894420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/254.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.1928969218 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 333167656 ps |
| CPU time | 4.73 seconds |
| Started | Sep 24 05:24:04 PM UTC 24 |
| Finished | Sep 24 05:24:11 PM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928969218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.1928969218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/255.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.2700936530 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 512595136 ps |
| CPU time | 3.7 seconds |
| Started | Sep 24 05:24:04 PM UTC 24 |
| Finished | Sep 24 05:24:10 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700936530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.2700936530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/256.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.111176351 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 577110148 ps |
| CPU time | 4.62 seconds |
| Started | Sep 24 05:24:06 PM UTC 24 |
| Finished | Sep 24 05:24:12 PM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111176351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.111176351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/257.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.1049947832 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 2057107429 ps |
| CPU time | 4.7 seconds |
| Started | Sep 24 05:24:06 PM UTC 24 |
| Finished | Sep 24 05:24:12 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049947832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.1049947832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/258.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.2572652131 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 143589663 ps |
| CPU time | 3.67 seconds |
| Started | Sep 24 05:24:06 PM UTC 24 |
| Finished | Sep 24 05:24:11 PM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572652131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.2572652131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/259.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_alert_test.3182021130 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 972770340 ps |
| CPU time | 3.02 seconds |
| Started | Sep 24 05:18:31 PM UTC 24 |
| Finished | Sep 24 05:18:35 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182021130 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.3182021130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/26.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_check_fail.695324221 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 437353222 ps |
| CPU time | 12.89 seconds |
| Started | Sep 24 05:18:24 PM UTC 24 |
| Finished | Sep 24 05:18:38 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695324221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.695324221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_errs.3117291526 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 281880686 ps |
| CPU time | 14.97 seconds |
| Started | Sep 24 05:18:24 PM UTC 24 |
| Finished | Sep 24 05:18:40 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117291526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.3117291526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/26.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_lock.3677372138 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1635150212 ps |
| CPU time | 22.86 seconds |
| Started | Sep 24 05:18:24 PM UTC 24 |
| Finished | Sep 24 05:18:48 PM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677372138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.3677372138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/26.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_init_fail.2695337038 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 1572476685 ps |
| CPU time | 5.82 seconds |
| Started | Sep 24 05:18:15 PM UTC 24 |
| Finished | Sep 24 05:18:23 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695337038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.2695337038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_macro_errs.1467456814 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 1672831234 ps |
| CPU time | 20.95 seconds |
| Started | Sep 24 05:18:24 PM UTC 24 |
| Finished | Sep 24 05:18:46 PM UTC 24 |
| Peak memory | 256088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467456814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.1467456814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/26.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_key_req.3642825223 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 1425570714 ps |
| CPU time | 38.62 seconds |
| Started | Sep 24 05:18:24 PM UTC 24 |
| Finished | Sep 24 05:19:04 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642825223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.3642825223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_esc.1297762859 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 434155429 ps |
| CPU time | 11.82 seconds |
| Started | Sep 24 05:18:24 PM UTC 24 |
| Finished | Sep 24 05:18:37 PM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297762859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.1297762859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_req.3397365214 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 962329338 ps |
| CPU time | 26.37 seconds |
| Started | Sep 24 05:18:24 PM UTC 24 |
| Finished | Sep 24 05:18:52 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397365214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.3397365214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_regwen.3912706865 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 4930438254 ps |
| CPU time | 13.55 seconds |
| Started | Sep 24 05:18:24 PM UTC 24 |
| Finished | Sep 24 05:18:39 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912706865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.3912706865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/26.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_smoke.2729814483 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 6440644252 ps |
| CPU time | 15.45 seconds |
| Started | Sep 24 05:18:14 PM UTC 24 |
| Finished | Sep 24 05:18:31 PM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729814483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.2729814483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/26.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all.2833150162 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 25584231193 ps |
| CPU time | 138.24 seconds |
| Started | Sep 24 05:18:31 PM UTC 24 |
| Finished | Sep 24 05:20:52 PM UTC 24 |
| Peak memory | 270408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833150162 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.2833150162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_test_access.3966973994 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 595291240 ps |
| CPU time | 6.66 seconds |
| Started | Sep 24 05:18:24 PM UTC 24 |
| Finished | Sep 24 05:18:32 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966973994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.3966973994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/26.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.1968902458 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 103973716 ps |
| CPU time | 4.15 seconds |
| Started | Sep 24 05:24:06 PM UTC 24 |
| Finished | Sep 24 05:24:12 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968902458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.1968902458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/260.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.865965421 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 251053503 ps |
| CPU time | 4.4 seconds |
| Started | Sep 24 05:24:06 PM UTC 24 |
| Finished | Sep 24 05:24:12 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865965421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.865965421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/261.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.2775422346 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 551142858 ps |
| CPU time | 3.87 seconds |
| Started | Sep 24 05:24:06 PM UTC 24 |
| Finished | Sep 24 05:24:11 PM UTC 24 |
| Peak memory | 251876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775422346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.2775422346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/262.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.3535525431 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 1694846005 ps |
| CPU time | 4.8 seconds |
| Started | Sep 24 05:24:06 PM UTC 24 |
| Finished | Sep 24 05:24:12 PM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535525431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.3535525431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/263.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.1892572655 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 151951969 ps |
| CPU time | 5.13 seconds |
| Started | Sep 24 05:24:07 PM UTC 24 |
| Finished | Sep 24 05:24:13 PM UTC 24 |
| Peak memory | 251812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892572655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.1892572655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/264.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.4249245155 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 193363046 ps |
| CPU time | 3.88 seconds |
| Started | Sep 24 05:24:07 PM UTC 24 |
| Finished | Sep 24 05:24:12 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249245155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.4249245155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/265.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.3737269724 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 524447455 ps |
| CPU time | 4.96 seconds |
| Started | Sep 24 05:24:07 PM UTC 24 |
| Finished | Sep 24 05:24:13 PM UTC 24 |
| Peak memory | 252092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737269724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.3737269724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/266.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.872626096 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 141828440 ps |
| CPU time | 4.85 seconds |
| Started | Sep 24 05:24:07 PM UTC 24 |
| Finished | Sep 24 05:24:13 PM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872626096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.872626096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/267.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.329133316 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 374836028 ps |
| CPU time | 3.13 seconds |
| Started | Sep 24 05:24:07 PM UTC 24 |
| Finished | Sep 24 05:24:11 PM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329133316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.329133316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/268.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.795008626 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 2543911805 ps |
| CPU time | 5.29 seconds |
| Started | Sep 24 05:24:07 PM UTC 24 |
| Finished | Sep 24 05:24:13 PM UTC 24 |
| Peak memory | 251812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795008626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.795008626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/269.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_alert_test.4194233973 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 125914195 ps |
| CPU time | 2.39 seconds |
| Started | Sep 24 05:18:35 PM UTC 24 |
| Finished | Sep 24 05:18:39 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194233973 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.4194233973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/27.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_check_fail.819467514 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 1135448789 ps |
| CPU time | 7.87 seconds |
| Started | Sep 24 05:18:32 PM UTC 24 |
| Finished | Sep 24 05:18:41 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819467514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.819467514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/27.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_errs.1584502702 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 760889514 ps |
| CPU time | 23.88 seconds |
| Started | Sep 24 05:18:32 PM UTC 24 |
| Finished | Sep 24 05:18:57 PM UTC 24 |
| Peak memory | 252064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584502702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.1584502702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/27.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_lock.1527990263 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1767276863 ps |
| CPU time | 24.6 seconds |
| Started | Sep 24 05:18:32 PM UTC 24 |
| Finished | Sep 24 05:18:58 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527990263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.1527990263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/27.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_init_fail.1444269904 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 2045091685 ps |
| CPU time | 5 seconds |
| Started | Sep 24 05:18:31 PM UTC 24 |
| Finished | Sep 24 05:18:38 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444269904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.1444269904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/27.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_macro_errs.2690472529 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 4224766914 ps |
| CPU time | 52.9 seconds |
| Started | Sep 24 05:18:32 PM UTC 24 |
| Finished | Sep 24 05:19:26 PM UTC 24 |
| Peak memory | 258160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690472529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.2690472529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/27.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_key_req.2856899528 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2319419945 ps |
| CPU time | 25.45 seconds |
| Started | Sep 24 05:18:32 PM UTC 24 |
| Finished | Sep 24 05:18:59 PM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856899528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.2856899528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_esc.429509025 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 86013153 ps |
| CPU time | 3.07 seconds |
| Started | Sep 24 05:18:32 PM UTC 24 |
| Finished | Sep 24 05:18:36 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429509025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.429509025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_req.298623474 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 5762001852 ps |
| CPU time | 15.92 seconds |
| Started | Sep 24 05:18:31 PM UTC 24 |
| Finished | Sep 24 05:18:49 PM UTC 24 |
| Peak memory | 251520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298623474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.298623474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_regwen.1237459424 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 389903107 ps |
| CPU time | 4.64 seconds |
| Started | Sep 24 05:18:32 PM UTC 24 |
| Finished | Sep 24 05:18:38 PM UTC 24 |
| Peak memory | 251656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237459424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.1237459424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/27.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_smoke.2763249554 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 1679554508 ps |
| CPU time | 13.1 seconds |
| Started | Sep 24 05:18:31 PM UTC 24 |
| Finished | Sep 24 05:18:46 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763249554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.2763249554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/27.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all.1183841301 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 8919069475 ps |
| CPU time | 155.71 seconds |
| Started | Sep 24 05:18:35 PM UTC 24 |
| Finished | Sep 24 05:21:14 PM UTC 24 |
| Peak memory | 268492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183841301 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.1183841301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.3526993689 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2985592366 ps |
| CPU time | 84.6 seconds |
| Started | Sep 24 05:18:32 PM UTC 24 |
| Finished | Sep 24 05:19:59 PM UTC 24 |
| Peak memory | 268432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3526993689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 27.otp_ctrl_stress_all_with_rand_reset.3526993689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_test_access.1427064308 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 790247189 ps |
| CPU time | 20.51 seconds |
| Started | Sep 24 05:18:32 PM UTC 24 |
| Finished | Sep 24 05:18:54 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427064308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.1427064308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/27.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.2453374125 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 418134957 ps |
| CPU time | 4.3 seconds |
| Started | Sep 24 05:24:07 PM UTC 24 |
| Finished | Sep 24 05:24:12 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453374125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.2453374125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/270.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.2587147912 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 282257832 ps |
| CPU time | 4.6 seconds |
| Started | Sep 24 05:24:07 PM UTC 24 |
| Finished | Sep 24 05:24:13 PM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587147912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.2587147912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/271.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.2664210352 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 277104803 ps |
| CPU time | 4.17 seconds |
| Started | Sep 24 05:24:07 PM UTC 24 |
| Finished | Sep 24 05:24:12 PM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664210352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.2664210352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/272.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.863106804 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 2381558867 ps |
| CPU time | 3.84 seconds |
| Started | Sep 24 05:24:07 PM UTC 24 |
| Finished | Sep 24 05:24:12 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863106804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.863106804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/273.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.50213804 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 119207048 ps |
| CPU time | 4.23 seconds |
| Started | Sep 24 05:24:07 PM UTC 24 |
| Finished | Sep 24 05:24:12 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50213804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.50213804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/274.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.1127830197 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 111289063 ps |
| CPU time | 4.22 seconds |
| Started | Sep 24 05:24:10 PM UTC 24 |
| Finished | Sep 24 05:24:15 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127830197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.1127830197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/275.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.4262694187 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 107281808 ps |
| CPU time | 3.78 seconds |
| Started | Sep 24 05:24:10 PM UTC 24 |
| Finished | Sep 24 05:24:15 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262694187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.4262694187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/276.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.3268941467 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 103465330 ps |
| CPU time | 3.96 seconds |
| Started | Sep 24 05:24:10 PM UTC 24 |
| Finished | Sep 24 05:24:15 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268941467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.3268941467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/277.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.811326155 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 143347965 ps |
| CPU time | 3.71 seconds |
| Started | Sep 24 05:24:10 PM UTC 24 |
| Finished | Sep 24 05:24:15 PM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811326155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.811326155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/278.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.2373681023 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 151186996 ps |
| CPU time | 4.2 seconds |
| Started | Sep 24 05:24:10 PM UTC 24 |
| Finished | Sep 24 05:24:15 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373681023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.2373681023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/279.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_alert_test.755886802 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 188577664 ps |
| CPU time | 2.58 seconds |
| Started | Sep 24 05:18:43 PM UTC 24 |
| Finished | Sep 24 05:18:47 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755886802 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.755886802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/28.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_check_fail.1122582608 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 683348686 ps |
| CPU time | 13.53 seconds |
| Started | Sep 24 05:18:36 PM UTC 24 |
| Finished | Sep 24 05:18:51 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122582608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.1122582608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/28.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_errs.1691602755 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 269080299 ps |
| CPU time | 13.92 seconds |
| Started | Sep 24 05:18:36 PM UTC 24 |
| Finished | Sep 24 05:18:51 PM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691602755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.1691602755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/28.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_lock.266378531 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 989016063 ps |
| CPU time | 13.11 seconds |
| Started | Sep 24 05:18:36 PM UTC 24 |
| Finished | Sep 24 05:18:50 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266378531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.266378531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/28.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_macro_errs.1324516251 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 4121670049 ps |
| CPU time | 32.76 seconds |
| Started | Sep 24 05:18:36 PM UTC 24 |
| Finished | Sep 24 05:19:10 PM UTC 24 |
| Peak memory | 258200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324516251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.1324516251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/28.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_key_req.2608057198 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 279355227 ps |
| CPU time | 4.53 seconds |
| Started | Sep 24 05:18:43 PM UTC 24 |
| Finished | Sep 24 05:18:49 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608057198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.2608057198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_esc.104706978 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 268687180 ps |
| CPU time | 13.84 seconds |
| Started | Sep 24 05:18:36 PM UTC 24 |
| Finished | Sep 24 05:18:51 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104706978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.104706978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_req.3185470457 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 222638726 ps |
| CPU time | 6.45 seconds |
| Started | Sep 24 05:18:36 PM UTC 24 |
| Finished | Sep 24 05:18:43 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185470457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.3185470457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_regwen.2012478733 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 282962904 ps |
| CPU time | 7.33 seconds |
| Started | Sep 24 05:18:43 PM UTC 24 |
| Finished | Sep 24 05:18:52 PM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012478733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.2012478733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/28.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_smoke.3810596299 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 7738295578 ps |
| CPU time | 16.46 seconds |
| Started | Sep 24 05:18:36 PM UTC 24 |
| Finished | Sep 24 05:18:53 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810596299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.3810596299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/28.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all.1226380577 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 27938670758 ps |
| CPU time | 111.11 seconds |
| Started | Sep 24 05:18:43 PM UTC 24 |
| Finished | Sep 24 05:20:37 PM UTC 24 |
| Peak memory | 268292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226380577 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.1226380577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_test_access.2668669152 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 532872916 ps |
| CPU time | 17.93 seconds |
| Started | Sep 24 05:18:43 PM UTC 24 |
| Finished | Sep 24 05:19:02 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668669152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.2668669152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/28.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.603280229 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 139965778 ps |
| CPU time | 3.54 seconds |
| Started | Sep 24 05:24:10 PM UTC 24 |
| Finished | Sep 24 05:24:15 PM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603280229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.603280229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/280.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.2184996332 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 1766863921 ps |
| CPU time | 7.28 seconds |
| Started | Sep 24 05:24:10 PM UTC 24 |
| Finished | Sep 24 05:24:19 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184996332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.2184996332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/282.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.146309036 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 213438212 ps |
| CPU time | 3.42 seconds |
| Started | Sep 24 05:24:10 PM UTC 24 |
| Finished | Sep 24 05:24:15 PM UTC 24 |
| Peak memory | 251944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146309036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.146309036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/283.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.1513471069 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 141350730 ps |
| CPU time | 3.52 seconds |
| Started | Sep 24 05:24:10 PM UTC 24 |
| Finished | Sep 24 05:24:15 PM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513471069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.1513471069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/284.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.1123599040 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 134796756 ps |
| CPU time | 3.26 seconds |
| Started | Sep 24 05:24:10 PM UTC 24 |
| Finished | Sep 24 05:24:15 PM UTC 24 |
| Peak memory | 251736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123599040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.1123599040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/285.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.477633924 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 257995184 ps |
| CPU time | 3.36 seconds |
| Started | Sep 24 05:24:10 PM UTC 24 |
| Finished | Sep 24 05:24:16 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477633924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.477633924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/286.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.4082598796 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 598512484 ps |
| CPU time | 4.03 seconds |
| Started | Sep 24 05:24:12 PM UTC 24 |
| Finished | Sep 24 05:24:17 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082598796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.4082598796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/287.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.2868170378 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 153722490 ps |
| CPU time | 3.79 seconds |
| Started | Sep 24 05:24:12 PM UTC 24 |
| Finished | Sep 24 05:24:17 PM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868170378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.2868170378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/288.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.2099697522 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 154970528 ps |
| CPU time | 4.32 seconds |
| Started | Sep 24 05:24:12 PM UTC 24 |
| Finished | Sep 24 05:24:18 PM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099697522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.2099697522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/289.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_alert_test.3709378494 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 745383102 ps |
| CPU time | 4.57 seconds |
| Started | Sep 24 05:18:46 PM UTC 24 |
| Finished | Sep 24 05:18:52 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709378494 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.3709378494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/29.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_errs.3855397098 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 18416147227 ps |
| CPU time | 46.45 seconds |
| Started | Sep 24 05:18:44 PM UTC 24 |
| Finished | Sep 24 05:19:31 PM UTC 24 |
| Peak memory | 258076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855397098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.3855397098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/29.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_lock.249605286 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 176731191 ps |
| CPU time | 7 seconds |
| Started | Sep 24 05:18:44 PM UTC 24 |
| Finished | Sep 24 05:18:52 PM UTC 24 |
| Peak memory | 251940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249605286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.249605286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/29.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_init_fail.1830487501 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 2962241516 ps |
| CPU time | 9.95 seconds |
| Started | Sep 24 05:18:43 PM UTC 24 |
| Finished | Sep 24 05:18:54 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830487501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.1830487501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/29.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_macro_errs.754681596 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 2376317336 ps |
| CPU time | 23.5 seconds |
| Started | Sep 24 05:18:44 PM UTC 24 |
| Finished | Sep 24 05:19:08 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754681596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.754681596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/29.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_key_req.566953580 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 296272119 ps |
| CPU time | 7.06 seconds |
| Started | Sep 24 05:18:44 PM UTC 24 |
| Finished | Sep 24 05:18:52 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566953580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.566953580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_esc.2985637086 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 670503820 ps |
| CPU time | 19.73 seconds |
| Started | Sep 24 05:18:43 PM UTC 24 |
| Finished | Sep 24 05:19:05 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985637086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.2985637086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_req.1070854549 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 372653861 ps |
| CPU time | 12.46 seconds |
| Started | Sep 24 05:18:43 PM UTC 24 |
| Finished | Sep 24 05:18:57 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070854549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.1070854549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_regwen.1252098690 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 345132479 ps |
| CPU time | 14.83 seconds |
| Started | Sep 24 05:18:44 PM UTC 24 |
| Finished | Sep 24 05:19:00 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252098690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.1252098690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/29.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_smoke.3923093679 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 632710275 ps |
| CPU time | 7.63 seconds |
| Started | Sep 24 05:18:43 PM UTC 24 |
| Finished | Sep 24 05:18:52 PM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923093679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.3923093679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/29.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all.799259080 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 11883458112 ps |
| CPU time | 123.08 seconds |
| Started | Sep 24 05:18:46 PM UTC 24 |
| Finished | Sep 24 05:20:51 PM UTC 24 |
| Peak memory | 256144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799259080 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.799259080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.2471649416 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 4470916688 ps |
| CPU time | 69.68 seconds |
| Started | Sep 24 05:18:46 PM UTC 24 |
| Finished | Sep 24 05:19:57 PM UTC 24 |
| Peak memory | 268400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2471649416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 29.otp_ctrl_stress_all_with_rand_reset.2471649416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_test_access.2816877828 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 21536709404 ps |
| CPU time | 37.74 seconds |
| Started | Sep 24 05:18:44 PM UTC 24 |
| Finished | Sep 24 05:19:23 PM UTC 24 |
| Peak memory | 253964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816877828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.2816877828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/29.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.1842265703 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 187663955 ps |
| CPU time | 3.93 seconds |
| Started | Sep 24 05:24:12 PM UTC 24 |
| Finished | Sep 24 05:24:17 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842265703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.1842265703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/290.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.2667795690 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 1493938276 ps |
| CPU time | 5.3 seconds |
| Started | Sep 24 05:24:12 PM UTC 24 |
| Finished | Sep 24 05:24:19 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667795690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.2667795690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/291.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.1588264423 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 128782217 ps |
| CPU time | 3.52 seconds |
| Started | Sep 24 05:24:12 PM UTC 24 |
| Finished | Sep 24 05:24:17 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588264423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.1588264423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/292.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.3160842786 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 183226361 ps |
| CPU time | 3.95 seconds |
| Started | Sep 24 05:24:12 PM UTC 24 |
| Finished | Sep 24 05:24:17 PM UTC 24 |
| Peak memory | 252012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160842786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.3160842786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/293.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.804827217 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 260696681 ps |
| CPU time | 3.5 seconds |
| Started | Sep 24 05:24:12 PM UTC 24 |
| Finished | Sep 24 05:24:17 PM UTC 24 |
| Peak memory | 251804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804827217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.804827217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/294.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.3473424625 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 266836160 ps |
| CPU time | 5.05 seconds |
| Started | Sep 24 05:24:12 PM UTC 24 |
| Finished | Sep 24 05:24:19 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473424625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.3473424625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/295.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.2600253796 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 202603533 ps |
| CPU time | 4.15 seconds |
| Started | Sep 24 05:24:13 PM UTC 24 |
| Finished | Sep 24 05:24:18 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600253796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.2600253796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/296.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.1228930435 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 1874208235 ps |
| CPU time | 4.24 seconds |
| Started | Sep 24 05:24:13 PM UTC 24 |
| Finished | Sep 24 05:24:18 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228930435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.1228930435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/297.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.1863675095 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 595290661 ps |
| CPU time | 4.7 seconds |
| Started | Sep 24 05:24:13 PM UTC 24 |
| Finished | Sep 24 05:24:18 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863675095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.1863675095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/298.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.468546721 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 2335841355 ps |
| CPU time | 4.65 seconds |
| Started | Sep 24 05:24:13 PM UTC 24 |
| Finished | Sep 24 05:24:18 PM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468546721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.468546721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/299.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_alert_test.1906034796 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 696484395 ps |
| CPU time | 2.79 seconds |
| Started | Sep 24 05:15:28 PM UTC 24 |
| Finished | Sep 24 05:15:32 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906034796 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.1906034796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_check_fail.233810750 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 216335199 ps |
| CPU time | 6.79 seconds |
| Started | Sep 24 05:15:25 PM UTC 24 |
| Finished | Sep 24 05:15:33 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233810750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.233810750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_lock.273822574 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 18082943954 ps |
| CPU time | 29.77 seconds |
| Started | Sep 24 05:15:25 PM UTC 24 |
| Finished | Sep 24 05:15:56 PM UTC 24 |
| Peak memory | 253972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273822574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.273822574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_init_fail.3767484350 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 2426860718 ps |
| CPU time | 6.82 seconds |
| Started | Sep 24 05:15:25 PM UTC 24 |
| Finished | Sep 24 05:15:33 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767484350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.3767484350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_macro_errs.3623125258 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 731899766 ps |
| CPU time | 16.44 seconds |
| Started | Sep 24 05:15:28 PM UTC 24 |
| Finished | Sep 24 05:15:46 PM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623125258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.3623125258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_key_req.451025447 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 3884723821 ps |
| CPU time | 29.85 seconds |
| Started | Sep 24 05:15:28 PM UTC 24 |
| Finished | Sep 24 05:15:59 PM UTC 24 |
| Peak memory | 253960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451025447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.451025447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_esc.4253020856 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 2071781551 ps |
| CPU time | 7.08 seconds |
| Started | Sep 24 05:15:25 PM UTC 24 |
| Finished | Sep 24 05:15:33 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253020856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.4253020856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_req.2470493540 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 820371528 ps |
| CPU time | 13.29 seconds |
| Started | Sep 24 05:15:25 PM UTC 24 |
| Finished | Sep 24 05:15:39 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470493540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.2470493540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_regwen.2996548306 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 290032871 ps |
| CPU time | 11.02 seconds |
| Started | Sep 24 05:15:28 PM UTC 24 |
| Finished | Sep 24 05:15:40 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996548306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.2996548306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_sec_cm.1511178488 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 21498364943 ps |
| CPU time | 182.2 seconds |
| Started | Sep 24 05:15:28 PM UTC 24 |
| Finished | Sep 24 05:18:34 PM UTC 24 |
| Peak memory | 286376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511178488 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.1511178488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_smoke.654048356 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 6720348353 ps |
| CPU time | 16.18 seconds |
| Started | Sep 24 05:15:25 PM UTC 24 |
| Finished | Sep 24 05:15:42 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654048356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.654048356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all.1459144564 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 15131931412 ps |
| CPU time | 194.57 seconds |
| Started | Sep 24 05:15:28 PM UTC 24 |
| Finished | Sep 24 05:18:46 PM UTC 24 |
| Peak memory | 309312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459144564 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.1459144564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_test_access.1485878093 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 3174590907 ps |
| CPU time | 39.25 seconds |
| Started | Sep 24 05:15:28 PM UTC 24 |
| Finished | Sep 24 05:16:09 PM UTC 24 |
| Peak memory | 252112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485878093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.1485878093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_alert_test.1309630039 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 895279115 ps |
| CPU time | 2.96 seconds |
| Started | Sep 24 05:18:55 PM UTC 24 |
| Finished | Sep 24 05:18:59 PM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309630039 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.1309630039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/30.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_check_fail.1796306281 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 736130691 ps |
| CPU time | 13.19 seconds |
| Started | Sep 24 05:18:54 PM UTC 24 |
| Finished | Sep 24 05:19:09 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796306281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.1796306281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/30.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_errs.1358482176 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 2756490943 ps |
| CPU time | 23.54 seconds |
| Started | Sep 24 05:18:54 PM UTC 24 |
| Finished | Sep 24 05:19:19 PM UTC 24 |
| Peak memory | 252068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358482176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.1358482176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/30.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_lock.2799630867 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 1795191576 ps |
| CPU time | 27.59 seconds |
| Started | Sep 24 05:18:54 PM UTC 24 |
| Finished | Sep 24 05:19:23 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799630867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.2799630867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/30.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_init_fail.1502279043 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 269678831 ps |
| CPU time | 6.14 seconds |
| Started | Sep 24 05:18:54 PM UTC 24 |
| Finished | Sep 24 05:19:02 PM UTC 24 |
| Peak memory | 251872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502279043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.1502279043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/30.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_macro_errs.4271477314 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 999436896 ps |
| CPU time | 13.71 seconds |
| Started | Sep 24 05:18:55 PM UTC 24 |
| Finished | Sep 24 05:19:09 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271477314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.4271477314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/30.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_key_req.869858079 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 13833655009 ps |
| CPU time | 42.49 seconds |
| Started | Sep 24 05:18:55 PM UTC 24 |
| Finished | Sep 24 05:19:39 PM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869858079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.869858079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_esc.756505646 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 239473496 ps |
| CPU time | 7.72 seconds |
| Started | Sep 24 05:18:54 PM UTC 24 |
| Finished | Sep 24 05:19:03 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756505646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.756505646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_req.113546731 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 1979472395 ps |
| CPU time | 14.8 seconds |
| Started | Sep 24 05:18:54 PM UTC 24 |
| Finished | Sep 24 05:19:10 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113546731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.113546731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_regwen.1425016334 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 3892447588 ps |
| CPU time | 12.14 seconds |
| Started | Sep 24 05:18:55 PM UTC 24 |
| Finished | Sep 24 05:19:08 PM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425016334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.1425016334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/30.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_smoke.1651701847 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 2305674486 ps |
| CPU time | 7.61 seconds |
| Started | Sep 24 05:18:54 PM UTC 24 |
| Finished | Sep 24 05:19:03 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651701847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.1651701847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/30.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all.2232327528 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 14067195746 ps |
| CPU time | 157.86 seconds |
| Started | Sep 24 05:18:55 PM UTC 24 |
| Finished | Sep 24 05:21:36 PM UTC 24 |
| Peak memory | 257956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232327528 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.2232327528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_test_access.594422138 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 2263286094 ps |
| CPU time | 17.85 seconds |
| Started | Sep 24 05:18:55 PM UTC 24 |
| Finished | Sep 24 05:19:14 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594422138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.594422138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/30.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_alert_test.3406275216 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 178092647 ps |
| CPU time | 2.55 seconds |
| Started | Sep 24 05:19:01 PM UTC 24 |
| Finished | Sep 24 05:19:05 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406275216 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.3406275216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/31.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_check_fail.3810753592 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1629207315 ps |
| CPU time | 15.37 seconds |
| Started | Sep 24 05:18:58 PM UTC 24 |
| Finished | Sep 24 05:19:14 PM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810753592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.3810753592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/31.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_errs.2667701184 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 743873094 ps |
| CPU time | 11.98 seconds |
| Started | Sep 24 05:18:58 PM UTC 24 |
| Finished | Sep 24 05:19:11 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667701184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.2667701184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/31.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_lock.3935670258 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1253368368 ps |
| CPU time | 24.47 seconds |
| Started | Sep 24 05:18:55 PM UTC 24 |
| Finished | Sep 24 05:19:21 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935670258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.3935670258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/31.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_init_fail.971576380 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 486782762 ps |
| CPU time | 5.15 seconds |
| Started | Sep 24 05:18:55 PM UTC 24 |
| Finished | Sep 24 05:19:01 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971576380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.971576380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/31.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_macro_errs.2702275428 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 570951266 ps |
| CPU time | 10.59 seconds |
| Started | Sep 24 05:18:58 PM UTC 24 |
| Finished | Sep 24 05:19:09 PM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702275428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.2702275428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/31.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_key_req.268949344 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 295249528 ps |
| CPU time | 8.27 seconds |
| Started | Sep 24 05:18:58 PM UTC 24 |
| Finished | Sep 24 05:19:07 PM UTC 24 |
| Peak memory | 251812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268949344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.268949344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_esc.3624424936 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 4861762137 ps |
| CPU time | 16.49 seconds |
| Started | Sep 24 05:18:55 PM UTC 24 |
| Finished | Sep 24 05:19:13 PM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624424936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.3624424936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_req.1744492103 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 556078495 ps |
| CPU time | 12.55 seconds |
| Started | Sep 24 05:18:55 PM UTC 24 |
| Finished | Sep 24 05:19:09 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744492103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.1744492103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_regwen.693575655 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 994473956 ps |
| CPU time | 11.43 seconds |
| Started | Sep 24 05:18:58 PM UTC 24 |
| Finished | Sep 24 05:19:10 PM UTC 24 |
| Peak memory | 252012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693575655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.693575655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/31.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_smoke.893994184 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 307827567 ps |
| CPU time | 7.51 seconds |
| Started | Sep 24 05:18:55 PM UTC 24 |
| Finished | Sep 24 05:19:04 PM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893994184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.893994184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/31.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all.760983221 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 24297627444 ps |
| CPU time | 115.34 seconds |
| Started | Sep 24 05:19:01 PM UTC 24 |
| Finished | Sep 24 05:20:59 PM UTC 24 |
| Peak memory | 268476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760983221 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.760983221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_test_access.2379751237 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 4871512578 ps |
| CPU time | 39.84 seconds |
| Started | Sep 24 05:18:58 PM UTC 24 |
| Finished | Sep 24 05:19:39 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379751237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.2379751237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/31.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_alert_test.967349849 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 139432208 ps |
| CPU time | 2.44 seconds |
| Started | Sep 24 05:19:07 PM UTC 24 |
| Finished | Sep 24 05:19:11 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967349849 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.967349849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/32.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_check_fail.3544949281 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 276030140 ps |
| CPU time | 7.32 seconds |
| Started | Sep 24 05:19:07 PM UTC 24 |
| Finished | Sep 24 05:19:15 PM UTC 24 |
| Peak memory | 251812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544949281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.3544949281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/32.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_errs.1423629492 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 1043425346 ps |
| CPU time | 23.18 seconds |
| Started | Sep 24 05:19:07 PM UTC 24 |
| Finished | Sep 24 05:19:31 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423629492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.1423629492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/32.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_lock.1452254586 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 1931986193 ps |
| CPU time | 17.96 seconds |
| Started | Sep 24 05:19:03 PM UTC 24 |
| Finished | Sep 24 05:19:22 PM UTC 24 |
| Peak memory | 252064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452254586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.1452254586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/32.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_init_fail.1218436326 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 1850607139 ps |
| CPU time | 4.89 seconds |
| Started | Sep 24 05:19:01 PM UTC 24 |
| Finished | Sep 24 05:19:07 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218436326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.1218436326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/32.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_macro_errs.1110953814 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 16085132124 ps |
| CPU time | 36.51 seconds |
| Started | Sep 24 05:19:07 PM UTC 24 |
| Finished | Sep 24 05:19:45 PM UTC 24 |
| Peak memory | 252064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110953814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.1110953814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/32.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_key_req.527537680 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 782504162 ps |
| CPU time | 10.42 seconds |
| Started | Sep 24 05:19:07 PM UTC 24 |
| Finished | Sep 24 05:19:19 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527537680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.527537680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_esc.1607511644 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 5594778139 ps |
| CPU time | 14.32 seconds |
| Started | Sep 24 05:19:03 PM UTC 24 |
| Finished | Sep 24 05:19:18 PM UTC 24 |
| Peak memory | 252104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607511644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.1607511644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_req.3430646980 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 327288737 ps |
| CPU time | 9.57 seconds |
| Started | Sep 24 05:19:02 PM UTC 24 |
| Finished | Sep 24 05:19:13 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430646980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.3430646980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_regwen.1839421052 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 267057659 ps |
| CPU time | 6.54 seconds |
| Started | Sep 24 05:19:07 PM UTC 24 |
| Finished | Sep 24 05:19:15 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839421052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.1839421052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/32.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_smoke.3960165522 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 318894406 ps |
| CPU time | 7.35 seconds |
| Started | Sep 24 05:19:01 PM UTC 24 |
| Finished | Sep 24 05:19:10 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960165522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.3960165522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/32.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.3708911104 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 6060671045 ps |
| CPU time | 70.15 seconds |
| Started | Sep 24 05:19:07 PM UTC 24 |
| Finished | Sep 24 05:20:19 PM UTC 24 |
| Peak memory | 268500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3708911104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 32.otp_ctrl_stress_all_with_rand_reset.3708911104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_test_access.957409413 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 1119152448 ps |
| CPU time | 28.5 seconds |
| Started | Sep 24 05:19:07 PM UTC 24 |
| Finished | Sep 24 05:19:37 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957409413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.957409413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/32.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_alert_test.3066371746 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 99815724 ps |
| CPU time | 2.15 seconds |
| Started | Sep 24 05:19:15 PM UTC 24 |
| Finished | Sep 24 05:19:18 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066371746 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.3066371746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/33.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_check_fail.4135347713 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 2842406993 ps |
| CPU time | 9.96 seconds |
| Started | Sep 24 05:19:15 PM UTC 24 |
| Finished | Sep 24 05:19:26 PM UTC 24 |
| Peak memory | 258268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135347713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.4135347713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/33.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_errs.3274139235 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 385784863 ps |
| CPU time | 9.36 seconds |
| Started | Sep 24 05:19:15 PM UTC 24 |
| Finished | Sep 24 05:19:25 PM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274139235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.3274139235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/33.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_lock.2624836563 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 736984291 ps |
| CPU time | 16.76 seconds |
| Started | Sep 24 05:19:14 PM UTC 24 |
| Finished | Sep 24 05:19:33 PM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624836563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.2624836563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/33.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_init_fail.4281112914 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 375807645 ps |
| CPU time | 3.83 seconds |
| Started | Sep 24 05:19:12 PM UTC 24 |
| Finished | Sep 24 05:19:17 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281112914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.4281112914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/33.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_macro_errs.4045534532 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1383022131 ps |
| CPU time | 16.37 seconds |
| Started | Sep 24 05:19:15 PM UTC 24 |
| Finished | Sep 24 05:19:32 PM UTC 24 |
| Peak memory | 251940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045534532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.4045534532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/33.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_key_req.261698739 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 347257494 ps |
| CPU time | 11.98 seconds |
| Started | Sep 24 05:19:15 PM UTC 24 |
| Finished | Sep 24 05:19:28 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261698739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.261698739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_esc.2643923847 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 799917966 ps |
| CPU time | 14.43 seconds |
| Started | Sep 24 05:19:12 PM UTC 24 |
| Finished | Sep 24 05:19:27 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643923847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.2643923847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_req.3564972679 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 893678828 ps |
| CPU time | 10.15 seconds |
| Started | Sep 24 05:19:12 PM UTC 24 |
| Finished | Sep 24 05:19:23 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564972679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.3564972679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_regwen.4226394654 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 352866365 ps |
| CPU time | 8.58 seconds |
| Started | Sep 24 05:19:15 PM UTC 24 |
| Finished | Sep 24 05:19:24 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226394654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.4226394654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/33.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_smoke.2427605586 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 864377652 ps |
| CPU time | 6.84 seconds |
| Started | Sep 24 05:19:12 PM UTC 24 |
| Finished | Sep 24 05:19:20 PM UTC 24 |
| Peak memory | 252056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427605586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.2427605586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/33.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all.3391885195 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 22908644037 ps |
| CPU time | 61.02 seconds |
| Started | Sep 24 05:19:15 PM UTC 24 |
| Finished | Sep 24 05:20:18 PM UTC 24 |
| Peak memory | 255992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391885195 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all.3391885195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.1492033457 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 30772006064 ps |
| CPU time | 102.17 seconds |
| Started | Sep 24 05:19:15 PM UTC 24 |
| Finished | Sep 24 05:20:59 PM UTC 24 |
| Peak memory | 274644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1492033457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 33.otp_ctrl_stress_all_with_rand_reset.1492033457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_test_access.213969984 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 11875726252 ps |
| CPU time | 30.5 seconds |
| Started | Sep 24 05:19:15 PM UTC 24 |
| Finished | Sep 24 05:19:47 PM UTC 24 |
| Peak memory | 253968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213969984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.213969984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/33.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_alert_test.1340240928 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 118560089 ps |
| CPU time | 2.76 seconds |
| Started | Sep 24 05:19:23 PM UTC 24 |
| Finished | Sep 24 05:19:27 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340240928 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.1340240928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/34.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_check_fail.4240604054 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 345728124 ps |
| CPU time | 9.84 seconds |
| Started | Sep 24 05:19:17 PM UTC 24 |
| Finished | Sep 24 05:19:28 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240604054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.4240604054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/34.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_errs.3473119626 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 635333310 ps |
| CPU time | 10.09 seconds |
| Started | Sep 24 05:19:17 PM UTC 24 |
| Finished | Sep 24 05:19:28 PM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473119626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.3473119626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/34.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_lock.3814607536 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 1500309373 ps |
| CPU time | 14.42 seconds |
| Started | Sep 24 05:19:17 PM UTC 24 |
| Finished | Sep 24 05:19:32 PM UTC 24 |
| Peak memory | 252068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814607536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.3814607536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/34.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_init_fail.397328558 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 198848992 ps |
| CPU time | 6.4 seconds |
| Started | Sep 24 05:19:15 PM UTC 24 |
| Finished | Sep 24 05:19:23 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397328558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.397328558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/34.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_macro_errs.858208937 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 493826572 ps |
| CPU time | 9.03 seconds |
| Started | Sep 24 05:19:18 PM UTC 24 |
| Finished | Sep 24 05:19:28 PM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858208937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.858208937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/34.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_key_req.964017400 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 574291569 ps |
| CPU time | 15.13 seconds |
| Started | Sep 24 05:19:19 PM UTC 24 |
| Finished | Sep 24 05:19:36 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964017400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.964017400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_esc.74900709 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 156882219 ps |
| CPU time | 5.8 seconds |
| Started | Sep 24 05:19:17 PM UTC 24 |
| Finished | Sep 24 05:19:23 PM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74900709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.74900709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_req.3371548686 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 357152984 ps |
| CPU time | 13.17 seconds |
| Started | Sep 24 05:19:15 PM UTC 24 |
| Finished | Sep 24 05:19:29 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371548686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.3371548686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_regwen.2773337680 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 1689062696 ps |
| CPU time | 5.71 seconds |
| Started | Sep 24 05:19:19 PM UTC 24 |
| Finished | Sep 24 05:19:26 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773337680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.2773337680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/34.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_smoke.1485836108 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 478163712 ps |
| CPU time | 12.99 seconds |
| Started | Sep 24 05:19:15 PM UTC 24 |
| Finished | Sep 24 05:19:29 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485836108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.1485836108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/34.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all.2899767097 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2839271225 ps |
| CPU time | 45.27 seconds |
| Started | Sep 24 05:19:21 PM UTC 24 |
| Finished | Sep 24 05:20:09 PM UTC 24 |
| Peak memory | 268504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899767097 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.2899767097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_test_access.1369854419 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 8319478967 ps |
| CPU time | 46.37 seconds |
| Started | Sep 24 05:19:20 PM UTC 24 |
| Finished | Sep 24 05:20:07 PM UTC 24 |
| Peak memory | 253892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369854419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.1369854419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/34.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_alert_test.3853244779 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 70635483 ps |
| CPU time | 2.36 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:19:34 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853244779 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.3853244779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/35.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_check_fail.3449327782 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 346351336 ps |
| CPU time | 9.6 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:19:41 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449327782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.3449327782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/35.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_errs.1214477276 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 727742040 ps |
| CPU time | 23.62 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:19:55 PM UTC 24 |
| Peak memory | 252004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214477276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.1214477276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/35.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_lock.1701797262 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 1158271644 ps |
| CPU time | 9.96 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:19:41 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701797262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.1701797262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/35.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_init_fail.2607123008 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 119008876 ps |
| CPU time | 4.65 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:19:36 PM UTC 24 |
| Peak memory | 251724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607123008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.2607123008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/35.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_macro_errs.2604061555 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 768357560 ps |
| CPU time | 15.62 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:19:47 PM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604061555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.2604061555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/35.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_key_req.1848812076 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 433051713 ps |
| CPU time | 11.28 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:19:43 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848812076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1848812076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_esc.1225561128 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 125948777 ps |
| CPU time | 3.43 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:19:35 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225561128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.1225561128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_req.2807310011 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 4554509173 ps |
| CPU time | 11.42 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:19:43 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807310011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.2807310011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_regwen.1538418376 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 162348327 ps |
| CPU time | 7.71 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:19:39 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538418376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.1538418376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/35.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_smoke.972783563 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 139192414 ps |
| CPU time | 4.4 seconds |
| Started | Sep 24 05:19:23 PM UTC 24 |
| Finished | Sep 24 05:19:29 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972783563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.972783563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/35.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all.3939892579 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 11207814708 ps |
| CPU time | 61.94 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:20:34 PM UTC 24 |
| Peak memory | 254036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939892579 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.3939892579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_test_access.3419775647 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 1981214586 ps |
| CPU time | 16.29 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:19:48 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419775647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.3419775647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/35.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_alert_test.2620253347 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 596072930 ps |
| CPU time | 2.77 seconds |
| Started | Sep 24 05:19:37 PM UTC 24 |
| Finished | Sep 24 05:19:41 PM UTC 24 |
| Peak memory | 250640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620253347 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.2620253347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/36.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_check_fail.1728595000 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 13959398842 ps |
| CPU time | 34.21 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:20:07 PM UTC 24 |
| Peak memory | 254032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728595000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.1728595000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/36.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_errs.1194868849 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 13094234969 ps |
| CPU time | 36.97 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:20:09 PM UTC 24 |
| Peak memory | 256284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194868849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.1194868849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/36.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_lock.2937987960 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 33259855845 ps |
| CPU time | 60.29 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:20:33 PM UTC 24 |
| Peak memory | 253972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937987960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.2937987960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/36.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_init_fail.1105937768 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 236458704 ps |
| CPU time | 4.95 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:19:37 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105937768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.1105937768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/36.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_macro_errs.242603086 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 1504425382 ps |
| CPU time | 20.32 seconds |
| Started | Sep 24 05:19:37 PM UTC 24 |
| Finished | Sep 24 05:19:59 PM UTC 24 |
| Peak memory | 256016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242603086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.242603086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/36.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_key_req.3285046996 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 2401917606 ps |
| CPU time | 31.67 seconds |
| Started | Sep 24 05:19:37 PM UTC 24 |
| Finished | Sep 24 05:20:10 PM UTC 24 |
| Peak memory | 252032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285046996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.3285046996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_esc.1984579789 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 529945902 ps |
| CPU time | 8.23 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:19:40 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984579789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.1984579789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_req.3052374748 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1113528155 ps |
| CPU time | 23.7 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:19:56 PM UTC 24 |
| Peak memory | 257928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052374748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.3052374748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_regwen.3907167789 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 290726582 ps |
| CPU time | 9.31 seconds |
| Started | Sep 24 05:19:37 PM UTC 24 |
| Finished | Sep 24 05:19:48 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907167789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.3907167789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/36.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_smoke.446944967 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 4176123988 ps |
| CPU time | 16.78 seconds |
| Started | Sep 24 05:19:30 PM UTC 24 |
| Finished | Sep 24 05:19:49 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446944967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.446944967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/36.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all.2587319057 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 17858213608 ps |
| CPU time | 190.8 seconds |
| Started | Sep 24 05:19:37 PM UTC 24 |
| Finished | Sep 24 05:22:52 PM UTC 24 |
| Peak memory | 258168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587319057 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.2587319057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.2266085572 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 3606307500 ps |
| CPU time | 45.23 seconds |
| Started | Sep 24 05:19:37 PM UTC 24 |
| Finished | Sep 24 05:20:24 PM UTC 24 |
| Peak memory | 258128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2266085572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.otp_ctrl_stress_all_with_rand_reset.2266085572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_test_access.9188057 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 257161753 ps |
| CPU time | 7.27 seconds |
| Started | Sep 24 05:19:37 PM UTC 24 |
| Finished | Sep 24 05:19:46 PM UTC 24 |
| Peak memory | 252088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9188057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.9188057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/36.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_alert_test.1446463420 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 59423166 ps |
| CPU time | 2.96 seconds |
| Started | Sep 24 05:19:44 PM UTC 24 |
| Finished | Sep 24 05:19:48 PM UTC 24 |
| Peak memory | 251708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446463420 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.1446463420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/37.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_check_fail.1851140830 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 1348863093 ps |
| CPU time | 25.35 seconds |
| Started | Sep 24 05:19:38 PM UTC 24 |
| Finished | Sep 24 05:20:04 PM UTC 24 |
| Peak memory | 251972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851140830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.1851140830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/37.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_errs.2238467969 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 5329008376 ps |
| CPU time | 25.53 seconds |
| Started | Sep 24 05:19:37 PM UTC 24 |
| Finished | Sep 24 05:20:05 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238467969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.2238467969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/37.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_lock.2883069960 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 4460490126 ps |
| CPU time | 10.42 seconds |
| Started | Sep 24 05:19:37 PM UTC 24 |
| Finished | Sep 24 05:19:49 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883069960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.2883069960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/37.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_init_fail.2083930611 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 288549745 ps |
| CPU time | 4.36 seconds |
| Started | Sep 24 05:19:37 PM UTC 24 |
| Finished | Sep 24 05:19:43 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083930611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.2083930611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/37.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_macro_errs.2884936002 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 2496227958 ps |
| CPU time | 26.34 seconds |
| Started | Sep 24 05:19:39 PM UTC 24 |
| Finished | Sep 24 05:20:07 PM UTC 24 |
| Peak memory | 258136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884936002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.2884936002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/37.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_key_req.4092489789 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 1311469028 ps |
| CPU time | 16.08 seconds |
| Started | Sep 24 05:19:39 PM UTC 24 |
| Finished | Sep 24 05:19:57 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092489789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.4092489789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_esc.1151033787 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 676860798 ps |
| CPU time | 10.21 seconds |
| Started | Sep 24 05:19:37 PM UTC 24 |
| Finished | Sep 24 05:19:49 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151033787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.1151033787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_req.824358566 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 508004083 ps |
| CPU time | 10.94 seconds |
| Started | Sep 24 05:19:37 PM UTC 24 |
| Finished | Sep 24 05:19:50 PM UTC 24 |
| Peak memory | 258052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824358566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.824358566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_regwen.3162801205 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 4503351065 ps |
| CPU time | 17.69 seconds |
| Started | Sep 24 05:19:42 PM UTC 24 |
| Finished | Sep 24 05:20:01 PM UTC 24 |
| Peak memory | 252040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162801205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.3162801205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/37.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_smoke.178312245 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 1384264941 ps |
| CPU time | 9.88 seconds |
| Started | Sep 24 05:19:37 PM UTC 24 |
| Finished | Sep 24 05:19:49 PM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178312245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.178312245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/37.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.3797905151 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 8585995604 ps |
| CPU time | 84.99 seconds |
| Started | Sep 24 05:19:42 PM UTC 24 |
| Finished | Sep 24 05:21:09 PM UTC 24 |
| Peak memory | 268368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797905151 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.3797905151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_test_access.4024814579 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 2211532004 ps |
| CPU time | 34.87 seconds |
| Started | Sep 24 05:19:42 PM UTC 24 |
| Finished | Sep 24 05:20:18 PM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024814579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.4024814579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/37.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_alert_test.1884733052 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 50158319 ps |
| CPU time | 2.72 seconds |
| Started | Sep 24 05:19:52 PM UTC 24 |
| Finished | Sep 24 05:19:56 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884733052 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.1884733052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/38.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_errs.3975303025 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 305586361 ps |
| CPU time | 17.86 seconds |
| Started | Sep 24 05:19:44 PM UTC 24 |
| Finished | Sep 24 05:20:04 PM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975303025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.3975303025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/38.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_lock.1679082892 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 789583699 ps |
| CPU time | 14.07 seconds |
| Started | Sep 24 05:19:44 PM UTC 24 |
| Finished | Sep 24 05:20:00 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679082892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.1679082892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/38.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_init_fail.3810132274 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 259776804 ps |
| CPU time | 4.88 seconds |
| Started | Sep 24 05:19:44 PM UTC 24 |
| Finished | Sep 24 05:19:50 PM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810132274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.3810132274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/38.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_macro_errs.2095626943 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 877203755 ps |
| CPU time | 30.18 seconds |
| Started | Sep 24 05:19:47 PM UTC 24 |
| Finished | Sep 24 05:20:19 PM UTC 24 |
| Peak memory | 256076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095626943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.2095626943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/38.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_key_req.1532243390 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 1201069003 ps |
| CPU time | 29.11 seconds |
| Started | Sep 24 05:19:48 PM UTC 24 |
| Finished | Sep 24 05:20:18 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532243390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.1532243390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_esc.2970379589 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 2313123361 ps |
| CPU time | 19.05 seconds |
| Started | Sep 24 05:19:44 PM UTC 24 |
| Finished | Sep 24 05:20:05 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970379589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.2970379589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_req.732428018 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 8213300924 ps |
| CPU time | 21.87 seconds |
| Started | Sep 24 05:19:44 PM UTC 24 |
| Finished | Sep 24 05:20:08 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732428018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.732428018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_regwen.1478515180 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 1121387863 ps |
| CPU time | 9.4 seconds |
| Started | Sep 24 05:19:52 PM UTC 24 |
| Finished | Sep 24 05:20:02 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478515180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.1478515180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/38.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_smoke.1135131306 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 3633053151 ps |
| CPU time | 9.42 seconds |
| Started | Sep 24 05:19:44 PM UTC 24 |
| Finished | Sep 24 05:19:55 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135131306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.1135131306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/38.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all.1486791709 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 8601259224 ps |
| CPU time | 48.81 seconds |
| Started | Sep 24 05:19:52 PM UTC 24 |
| Finished | Sep 24 05:20:42 PM UTC 24 |
| Peak memory | 255840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486791709 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.1486791709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_test_access.2759420663 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 1676356481 ps |
| CPU time | 16.53 seconds |
| Started | Sep 24 05:19:52 PM UTC 24 |
| Finished | Sep 24 05:20:10 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759420663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.2759420663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/38.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_alert_test.955193596 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 148505674 ps |
| CPU time | 3.51 seconds |
| Started | Sep 24 05:20:00 PM UTC 24 |
| Finished | Sep 24 05:20:05 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955193596 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.955193596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/39.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_errs.3379832247 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 4953126364 ps |
| CPU time | 27.03 seconds |
| Started | Sep 24 05:19:52 PM UTC 24 |
| Finished | Sep 24 05:20:21 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379832247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.3379832247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/39.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_lock.1708457473 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 5194484777 ps |
| CPU time | 39.75 seconds |
| Started | Sep 24 05:19:52 PM UTC 24 |
| Finished | Sep 24 05:20:33 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708457473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.1708457473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/39.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_init_fail.2232628573 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 138690773 ps |
| CPU time | 5.05 seconds |
| Started | Sep 24 05:19:52 PM UTC 24 |
| Finished | Sep 24 05:19:58 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232628573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.2232628573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/39.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_macro_errs.1720791365 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 3288301040 ps |
| CPU time | 26.12 seconds |
| Started | Sep 24 05:19:52 PM UTC 24 |
| Finished | Sep 24 05:20:20 PM UTC 24 |
| Peak memory | 256084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720791365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.1720791365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/39.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_key_req.412091697 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 12508115082 ps |
| CPU time | 39.89 seconds |
| Started | Sep 24 05:19:58 PM UTC 24 |
| Finished | Sep 24 05:20:39 PM UTC 24 |
| Peak memory | 253896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412091697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.412091697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_esc.3763538101 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 206911375 ps |
| CPU time | 5.98 seconds |
| Started | Sep 24 05:19:52 PM UTC 24 |
| Finished | Sep 24 05:19:59 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763538101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.3763538101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_req.2424797307 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 473244175 ps |
| CPU time | 9.47 seconds |
| Started | Sep 24 05:19:52 PM UTC 24 |
| Finished | Sep 24 05:20:03 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424797307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.2424797307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_regwen.3308669727 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 113220373 ps |
| CPU time | 5.66 seconds |
| Started | Sep 24 05:19:58 PM UTC 24 |
| Finished | Sep 24 05:20:04 PM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308669727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.3308669727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/39.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_smoke.3440448681 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 3116576276 ps |
| CPU time | 12.71 seconds |
| Started | Sep 24 05:19:52 PM UTC 24 |
| Finished | Sep 24 05:20:06 PM UTC 24 |
| Peak memory | 252044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440448681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.3440448681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/39.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all.3818265268 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 1599244983 ps |
| CPU time | 12.88 seconds |
| Started | Sep 24 05:19:58 PM UTC 24 |
| Finished | Sep 24 05:20:12 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818265268 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.3818265268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.2030264630 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 73637265051 ps |
| CPU time | 252.72 seconds |
| Started | Sep 24 05:19:58 PM UTC 24 |
| Finished | Sep 24 05:24:14 PM UTC 24 |
| Peak memory | 260848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2030264630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 39.otp_ctrl_stress_all_with_rand_reset.2030264630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_test_access.1510364380 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 922390546 ps |
| CPU time | 9.31 seconds |
| Started | Sep 24 05:19:58 PM UTC 24 |
| Finished | Sep 24 05:20:08 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510364380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.1510364380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/39.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_alert_test.2375809415 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 200765737 ps |
| CPU time | 3.08 seconds |
| Started | Sep 24 05:15:36 PM UTC 24 |
| Finished | Sep 24 05:15:40 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375809415 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.2375809415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_background_chks.1177276088 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1639898362 ps |
| CPU time | 13.45 seconds |
| Started | Sep 24 05:15:28 PM UTC 24 |
| Finished | Sep 24 05:15:43 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177276088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.1177276088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_check_fail.631690034 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 5916668076 ps |
| CPU time | 9.84 seconds |
| Started | Sep 24 05:15:32 PM UTC 24 |
| Finished | Sep 24 05:15:43 PM UTC 24 |
| Peak memory | 251640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631690034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.631690034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_errs.3749832572 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 1475119511 ps |
| CPU time | 23.38 seconds |
| Started | Sep 24 05:15:32 PM UTC 24 |
| Finished | Sep 24 05:15:57 PM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749832572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.3749832572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_lock.4256533429 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 3490594262 ps |
| CPU time | 10.13 seconds |
| Started | Sep 24 05:15:32 PM UTC 24 |
| Finished | Sep 24 05:15:43 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256533429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.4256533429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_init_fail.189207020 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 310710206 ps |
| CPU time | 4.82 seconds |
| Started | Sep 24 05:15:28 PM UTC 24 |
| Finished | Sep 24 05:15:34 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189207020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.189207020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_macro_errs.864393735 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 9070100946 ps |
| CPU time | 22.77 seconds |
| Started | Sep 24 05:15:32 PM UTC 24 |
| Finished | Sep 24 05:15:56 PM UTC 24 |
| Peak memory | 254300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864393735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.864393735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_key_req.3706551096 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1735795751 ps |
| CPU time | 14.77 seconds |
| Started | Sep 24 05:15:32 PM UTC 24 |
| Finished | Sep 24 05:15:48 PM UTC 24 |
| Peak memory | 251568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706551096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.3706551096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_esc.901208046 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 472728215 ps |
| CPU time | 7.03 seconds |
| Started | Sep 24 05:15:32 PM UTC 24 |
| Finished | Sep 24 05:15:40 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901208046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.901208046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_req.682003918 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 2083185953 ps |
| CPU time | 16.51 seconds |
| Started | Sep 24 05:15:32 PM UTC 24 |
| Finished | Sep 24 05:15:50 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682003918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.682003918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_regwen.2902156389 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 288321295 ps |
| CPU time | 9.85 seconds |
| Started | Sep 24 05:15:32 PM UTC 24 |
| Finished | Sep 24 05:15:43 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902156389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.2902156389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_sec_cm.1143671969 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 21664013765 ps |
| CPU time | 223.98 seconds |
| Started | Sep 24 05:15:36 PM UTC 24 |
| Finished | Sep 24 05:19:24 PM UTC 24 |
| Peak memory | 288504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143671969 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.1143671969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_smoke.3079965615 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 4434164294 ps |
| CPU time | 14.46 seconds |
| Started | Sep 24 05:15:28 PM UTC 24 |
| Finished | Sep 24 05:15:44 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079965615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.3079965615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/4.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_alert_test.1032242917 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 104279443 ps |
| CPU time | 2.85 seconds |
| Started | Sep 24 05:20:09 PM UTC 24 |
| Finished | Sep 24 05:20:13 PM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032242917 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.1032242917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/40.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_check_fail.1024429130 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 1061697770 ps |
| CPU time | 7.49 seconds |
| Started | Sep 24 05:20:09 PM UTC 24 |
| Finished | Sep 24 05:20:17 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024429130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.1024429130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/40.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_errs.3472637106 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 893078406 ps |
| CPU time | 22.02 seconds |
| Started | Sep 24 05:20:03 PM UTC 24 |
| Finished | Sep 24 05:20:26 PM UTC 24 |
| Peak memory | 251872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472637106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.3472637106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/40.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_lock.2592354527 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 1413580994 ps |
| CPU time | 13.56 seconds |
| Started | Sep 24 05:20:02 PM UTC 24 |
| Finished | Sep 24 05:20:17 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592354527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.2592354527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/40.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_init_fail.2659276124 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 2083535827 ps |
| CPU time | 5.66 seconds |
| Started | Sep 24 05:20:00 PM UTC 24 |
| Finished | Sep 24 05:20:07 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659276124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.2659276124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/40.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_macro_errs.3273025062 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 9304471559 ps |
| CPU time | 18.03 seconds |
| Started | Sep 24 05:20:09 PM UTC 24 |
| Finished | Sep 24 05:20:28 PM UTC 24 |
| Peak memory | 253648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273025062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.3273025062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/40.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_key_req.907068082 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 5336143317 ps |
| CPU time | 13.08 seconds |
| Started | Sep 24 05:20:09 PM UTC 24 |
| Finished | Sep 24 05:20:23 PM UTC 24 |
| Peak memory | 251648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907068082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.907068082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_esc.1891096110 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 6362553615 ps |
| CPU time | 17.94 seconds |
| Started | Sep 24 05:20:02 PM UTC 24 |
| Finished | Sep 24 05:20:22 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891096110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.1891096110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_req.568871434 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 450958898 ps |
| CPU time | 17.83 seconds |
| Started | Sep 24 05:20:00 PM UTC 24 |
| Finished | Sep 24 05:20:19 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568871434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.568871434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_regwen.3056465863 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 284087500 ps |
| CPU time | 4.86 seconds |
| Started | Sep 24 05:20:09 PM UTC 24 |
| Finished | Sep 24 05:20:15 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056465863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.3056465863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/40.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_smoke.2213527414 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 4475854903 ps |
| CPU time | 13.09 seconds |
| Started | Sep 24 05:20:00 PM UTC 24 |
| Finished | Sep 24 05:20:14 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213527414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.2213527414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/40.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_test_access.4044360364 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 8288971027 ps |
| CPU time | 21.22 seconds |
| Started | Sep 24 05:20:09 PM UTC 24 |
| Finished | Sep 24 05:20:31 PM UTC 24 |
| Peak memory | 254040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044360364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.4044360364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/40.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_alert_test.1428379341 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 135712278 ps |
| CPU time | 3.72 seconds |
| Started | Sep 24 05:20:14 PM UTC 24 |
| Finished | Sep 24 05:20:19 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428379341 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.1428379341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/41.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_check_fail.717122667 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 749042361 ps |
| CPU time | 8.51 seconds |
| Started | Sep 24 05:20:13 PM UTC 24 |
| Finished | Sep 24 05:20:22 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717122667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.717122667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_errs.4044508206 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 1259514625 ps |
| CPU time | 35.46 seconds |
| Started | Sep 24 05:20:13 PM UTC 24 |
| Finished | Sep 24 05:20:49 PM UTC 24 |
| Peak memory | 251872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044508206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.4044508206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/41.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_lock.60573687 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 2432357047 ps |
| CPU time | 23.33 seconds |
| Started | Sep 24 05:20:09 PM UTC 24 |
| Finished | Sep 24 05:20:34 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60573687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.60573687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/41.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_init_fail.3353900428 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 123284944 ps |
| CPU time | 3.6 seconds |
| Started | Sep 24 05:20:09 PM UTC 24 |
| Finished | Sep 24 05:20:14 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353900428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.3353900428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/41.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_macro_errs.1157810927 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 845340369 ps |
| CPU time | 20.56 seconds |
| Started | Sep 24 05:20:13 PM UTC 24 |
| Finished | Sep 24 05:20:34 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157810927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.1157810927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/41.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_key_req.3206185319 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 3637161874 ps |
| CPU time | 28.37 seconds |
| Started | Sep 24 05:20:13 PM UTC 24 |
| Finished | Sep 24 05:20:43 PM UTC 24 |
| Peak memory | 252112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206185319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.3206185319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_esc.1143417640 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 116437136 ps |
| CPU time | 4 seconds |
| Started | Sep 24 05:20:09 PM UTC 24 |
| Finished | Sep 24 05:20:14 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143417640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.1143417640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_req.2222103154 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 13173525691 ps |
| CPU time | 32.96 seconds |
| Started | Sep 24 05:20:09 PM UTC 24 |
| Finished | Sep 24 05:20:43 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222103154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.2222103154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_regwen.4221856021 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 445177817 ps |
| CPU time | 6.67 seconds |
| Started | Sep 24 05:20:13 PM UTC 24 |
| Finished | Sep 24 05:20:21 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221856021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.4221856021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/41.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_smoke.2046643672 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 130221290 ps |
| CPU time | 6.29 seconds |
| Started | Sep 24 05:20:09 PM UTC 24 |
| Finished | Sep 24 05:20:16 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046643672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.2046643672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/41.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all.1908777178 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 103124974333 ps |
| CPU time | 306.77 seconds |
| Started | Sep 24 05:20:13 PM UTC 24 |
| Finished | Sep 24 05:25:24 PM UTC 24 |
| Peak memory | 287620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908777178 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.1908777178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.2680344881 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 9156615193 ps |
| CPU time | 136.02 seconds |
| Started | Sep 24 05:20:13 PM UTC 24 |
| Finished | Sep 24 05:22:32 PM UTC 24 |
| Peak memory | 272580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2680344881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 41.otp_ctrl_stress_all_with_rand_reset.2680344881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_test_access.949044269 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 8082422775 ps |
| CPU time | 24.89 seconds |
| Started | Sep 24 05:20:13 PM UTC 24 |
| Finished | Sep 24 05:20:39 PM UTC 24 |
| Peak memory | 252124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949044269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.949044269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/41.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_alert_test.3710432640 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 577324230 ps |
| CPU time | 2.3 seconds |
| Started | Sep 24 05:20:23 PM UTC 24 |
| Finished | Sep 24 05:20:26 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710432640 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.3710432640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/42.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_check_fail.1289897548 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 17568309072 ps |
| CPU time | 53.12 seconds |
| Started | Sep 24 05:20:19 PM UTC 24 |
| Finished | Sep 24 05:21:13 PM UTC 24 |
| Peak memory | 254160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289897548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.1289897548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_errs.1150040008 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 1132257327 ps |
| CPU time | 21.73 seconds |
| Started | Sep 24 05:20:19 PM UTC 24 |
| Finished | Sep 24 05:20:42 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150040008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.1150040008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/42.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_lock.3387677496 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 252328830 ps |
| CPU time | 7.65 seconds |
| Started | Sep 24 05:20:19 PM UTC 24 |
| Finished | Sep 24 05:20:27 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387677496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.3387677496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/42.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_init_fail.897561227 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 129211348 ps |
| CPU time | 3.63 seconds |
| Started | Sep 24 05:20:16 PM UTC 24 |
| Finished | Sep 24 05:20:20 PM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897561227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.897561227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/42.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_macro_errs.4046748058 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 1927199660 ps |
| CPU time | 33.05 seconds |
| Started | Sep 24 05:20:19 PM UTC 24 |
| Finished | Sep 24 05:20:53 PM UTC 24 |
| Peak memory | 253968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046748058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.4046748058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/42.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_key_req.2770075449 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 651349889 ps |
| CPU time | 16.16 seconds |
| Started | Sep 24 05:20:23 PM UTC 24 |
| Finished | Sep 24 05:20:40 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770075449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.2770075449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_esc.1433497996 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 358998355 ps |
| CPU time | 8.1 seconds |
| Started | Sep 24 05:20:16 PM UTC 24 |
| Finished | Sep 24 05:20:25 PM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433497996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.1433497996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_req.3753487710 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 376221027 ps |
| CPU time | 7.22 seconds |
| Started | Sep 24 05:20:16 PM UTC 24 |
| Finished | Sep 24 05:20:24 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753487710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.3753487710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_regwen.457296015 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 442837397 ps |
| CPU time | 6.51 seconds |
| Started | Sep 24 05:20:23 PM UTC 24 |
| Finished | Sep 24 05:20:30 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457296015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.457296015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/42.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_smoke.1199994456 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 281973878 ps |
| CPU time | 7.57 seconds |
| Started | Sep 24 05:20:14 PM UTC 24 |
| Finished | Sep 24 05:20:23 PM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199994456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.1199994456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/42.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all.494787580 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 4173965193 ps |
| CPU time | 99.57 seconds |
| Started | Sep 24 05:20:23 PM UTC 24 |
| Finished | Sep 24 05:22:04 PM UTC 24 |
| Peak memory | 268376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494787580 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.494787580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.854270357 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 3145626620 ps |
| CPU time | 113.76 seconds |
| Started | Sep 24 05:20:23 PM UTC 24 |
| Finished | Sep 24 05:22:19 PM UTC 24 |
| Peak memory | 268532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=854270357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.854270357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_test_access.3676442039 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 1598979347 ps |
| CPU time | 11.17 seconds |
| Started | Sep 24 05:20:23 PM UTC 24 |
| Finished | Sep 24 05:20:35 PM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676442039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.3676442039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/42.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_alert_test.2559574233 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 78553592 ps |
| CPU time | 3.28 seconds |
| Started | Sep 24 05:20:28 PM UTC 24 |
| Finished | Sep 24 05:20:32 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559574233 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.2559574233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/43.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_check_fail.4218988517 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 15445199186 ps |
| CPU time | 31.18 seconds |
| Started | Sep 24 05:20:25 PM UTC 24 |
| Finished | Sep 24 05:20:57 PM UTC 24 |
| Peak memory | 254028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218988517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.4218988517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/43.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_errs.3118467212 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 7851051044 ps |
| CPU time | 24.7 seconds |
| Started | Sep 24 05:20:23 PM UTC 24 |
| Finished | Sep 24 05:20:49 PM UTC 24 |
| Peak memory | 252068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118467212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.3118467212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/43.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_lock.4094033032 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 1959020504 ps |
| CPU time | 16.39 seconds |
| Started | Sep 24 05:20:23 PM UTC 24 |
| Finished | Sep 24 05:20:41 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094033032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.4094033032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/43.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_init_fail.1193117701 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 240357732 ps |
| CPU time | 4.61 seconds |
| Started | Sep 24 05:20:23 PM UTC 24 |
| Finished | Sep 24 05:20:29 PM UTC 24 |
| Peak memory | 252032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193117701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.1193117701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/43.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_macro_errs.1129961567 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 327809817 ps |
| CPU time | 12.42 seconds |
| Started | Sep 24 05:20:25 PM UTC 24 |
| Finished | Sep 24 05:20:38 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129961567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.1129961567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/43.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_key_req.4194838497 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 262618514 ps |
| CPU time | 9.74 seconds |
| Started | Sep 24 05:20:25 PM UTC 24 |
| Finished | Sep 24 05:20:36 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194838497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.4194838497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_esc.2532060613 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 259837124 ps |
| CPU time | 7.41 seconds |
| Started | Sep 24 05:20:23 PM UTC 24 |
| Finished | Sep 24 05:20:32 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532060613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.2532060613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_req.1628818244 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 954726694 ps |
| CPU time | 12.96 seconds |
| Started | Sep 24 05:20:23 PM UTC 24 |
| Finished | Sep 24 05:20:37 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628818244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.1628818244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_regwen.907733781 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 159366733 ps |
| CPU time | 7.53 seconds |
| Started | Sep 24 05:20:25 PM UTC 24 |
| Finished | Sep 24 05:20:33 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907733781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.907733781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/43.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_smoke.2403510212 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 528945367 ps |
| CPU time | 11.74 seconds |
| Started | Sep 24 05:20:23 PM UTC 24 |
| Finished | Sep 24 05:20:36 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403510212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.2403510212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/43.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.3810556053 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 34291979180 ps |
| CPU time | 231.34 seconds |
| Started | Sep 24 05:20:28 PM UTC 24 |
| Finished | Sep 24 05:24:23 PM UTC 24 |
| Peak memory | 272472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810556053 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.3810556053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_test_access.2955634692 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 4966465050 ps |
| CPU time | 9.68 seconds |
| Started | Sep 24 05:20:27 PM UTC 24 |
| Finished | Sep 24 05:20:38 PM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955634692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.2955634692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/43.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_alert_test.1921539533 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 287924807 ps |
| CPU time | 2.69 seconds |
| Started | Sep 24 05:20:38 PM UTC 24 |
| Finished | Sep 24 05:20:42 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921539533 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.1921539533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/44.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_check_fail.2066122658 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 8942546546 ps |
| CPU time | 22.45 seconds |
| Started | Sep 24 05:20:37 PM UTC 24 |
| Finished | Sep 24 05:21:01 PM UTC 24 |
| Peak memory | 253968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066122658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.2066122658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/44.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_errs.465331750 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 252632206 ps |
| CPU time | 13.09 seconds |
| Started | Sep 24 05:20:37 PM UTC 24 |
| Finished | Sep 24 05:20:52 PM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465331750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.465331750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/44.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_lock.2883706895 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 787948629 ps |
| CPU time | 17.4 seconds |
| Started | Sep 24 05:20:32 PM UTC 24 |
| Finished | Sep 24 05:20:50 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883706895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.2883706895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/44.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_init_fail.73866765 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 466393789 ps |
| CPU time | 5.41 seconds |
| Started | Sep 24 05:20:29 PM UTC 24 |
| Finished | Sep 24 05:20:36 PM UTC 24 |
| Peak memory | 251952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73866765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.73866765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/44.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_macro_errs.2708899759 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 2545604048 ps |
| CPU time | 31.04 seconds |
| Started | Sep 24 05:20:38 PM UTC 24 |
| Finished | Sep 24 05:21:10 PM UTC 24 |
| Peak memory | 272304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708899759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.2708899759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/44.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_key_req.1773163923 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 2106556216 ps |
| CPU time | 30.01 seconds |
| Started | Sep 24 05:20:38 PM UTC 24 |
| Finished | Sep 24 05:21:09 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773163923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.1773163923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_esc.1547298440 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 3362983612 ps |
| CPU time | 16.48 seconds |
| Started | Sep 24 05:20:29 PM UTC 24 |
| Finished | Sep 24 05:20:47 PM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547298440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.1547298440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_req.113305846 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 1459632630 ps |
| CPU time | 19.15 seconds |
| Started | Sep 24 05:20:29 PM UTC 24 |
| Finished | Sep 24 05:20:50 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113305846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.113305846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_regwen.2894657544 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 158031983 ps |
| CPU time | 5.62 seconds |
| Started | Sep 24 05:20:38 PM UTC 24 |
| Finished | Sep 24 05:20:44 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894657544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.2894657544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/44.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_smoke.1447023027 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 357907196 ps |
| CPU time | 7.11 seconds |
| Started | Sep 24 05:20:28 PM UTC 24 |
| Finished | Sep 24 05:20:36 PM UTC 24 |
| Peak memory | 252056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447023027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.1447023027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/44.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.763363457 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 21776799491 ps |
| CPU time | 249.78 seconds |
| Started | Sep 24 05:20:38 PM UTC 24 |
| Finished | Sep 24 05:24:51 PM UTC 24 |
| Peak memory | 286868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763363457 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.763363457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.2136955204 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 25284931752 ps |
| CPU time | 166.23 seconds |
| Started | Sep 24 05:20:38 PM UTC 24 |
| Finished | Sep 24 05:23:27 PM UTC 24 |
| Peak memory | 274556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2136955204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 44.otp_ctrl_stress_all_with_rand_reset.2136955204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_test_access.742851272 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 1074470446 ps |
| CPU time | 20.98 seconds |
| Started | Sep 24 05:20:38 PM UTC 24 |
| Finished | Sep 24 05:21:00 PM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742851272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.742851272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/44.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_alert_test.3827707565 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 136746438 ps |
| CPU time | 2.77 seconds |
| Started | Sep 24 05:20:43 PM UTC 24 |
| Finished | Sep 24 05:20:46 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827707565 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.3827707565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/45.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_check_fail.141992437 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1267955406 ps |
| CPU time | 26.38 seconds |
| Started | Sep 24 05:20:38 PM UTC 24 |
| Finished | Sep 24 05:21:06 PM UTC 24 |
| Peak memory | 254092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141992437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.141992437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_errs.2484775086 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 1893064471 ps |
| CPU time | 34.82 seconds |
| Started | Sep 24 05:20:38 PM UTC 24 |
| Finished | Sep 24 05:21:14 PM UTC 24 |
| Peak memory | 253968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484775086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.2484775086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/45.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_lock.2960404664 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 9649153051 ps |
| CPU time | 50.83 seconds |
| Started | Sep 24 05:20:38 PM UTC 24 |
| Finished | Sep 24 05:21:31 PM UTC 24 |
| Peak memory | 253968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960404664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.2960404664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/45.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_init_fail.2731947812 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 237459510 ps |
| CPU time | 4.55 seconds |
| Started | Sep 24 05:20:38 PM UTC 24 |
| Finished | Sep 24 05:20:44 PM UTC 24 |
| Peak memory | 252032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731947812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.2731947812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/45.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_macro_errs.2590189429 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 14373604075 ps |
| CPU time | 20.41 seconds |
| Started | Sep 24 05:20:38 PM UTC 24 |
| Finished | Sep 24 05:21:00 PM UTC 24 |
| Peak memory | 256280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590189429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.2590189429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/45.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_key_req.346640234 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 4718237034 ps |
| CPU time | 13.3 seconds |
| Started | Sep 24 05:20:38 PM UTC 24 |
| Finished | Sep 24 05:20:53 PM UTC 24 |
| Peak memory | 252044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346640234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.346640234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_esc.1966787209 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 991796410 ps |
| CPU time | 11.94 seconds |
| Started | Sep 24 05:20:38 PM UTC 24 |
| Finished | Sep 24 05:20:51 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966787209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.1966787209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_req.973461382 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 1223034630 ps |
| CPU time | 19.81 seconds |
| Started | Sep 24 05:20:38 PM UTC 24 |
| Finished | Sep 24 05:20:59 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973461382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.973461382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_regwen.2564755506 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 730259124 ps |
| CPU time | 11.04 seconds |
| Started | Sep 24 05:20:42 PM UTC 24 |
| Finished | Sep 24 05:20:55 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564755506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.2564755506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/45.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_smoke.613746904 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 1287052095 ps |
| CPU time | 9.42 seconds |
| Started | Sep 24 05:20:38 PM UTC 24 |
| Finished | Sep 24 05:20:48 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613746904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.613746904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/45.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.1213701186 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 11220713381 ps |
| CPU time | 71.15 seconds |
| Started | Sep 24 05:20:43 PM UTC 24 |
| Finished | Sep 24 05:21:56 PM UTC 24 |
| Peak memory | 256016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213701186 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.1213701186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.482200511 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 14017173079 ps |
| CPU time | 67.24 seconds |
| Started | Sep 24 05:20:43 PM UTC 24 |
| Finished | Sep 24 05:21:51 PM UTC 24 |
| Peak memory | 258100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=482200511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.482200511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_test_access.397683689 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 5625036822 ps |
| CPU time | 12.96 seconds |
| Started | Sep 24 05:20:42 PM UTC 24 |
| Finished | Sep 24 05:20:57 PM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397683689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.397683689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/45.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_alert_test.1072493140 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 67951936 ps |
| CPU time | 2.4 seconds |
| Started | Sep 24 05:20:50 PM UTC 24 |
| Finished | Sep 24 05:20:53 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072493140 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.1072493140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/46.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_check_fail.3893561242 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 19443146664 ps |
| CPU time | 31.29 seconds |
| Started | Sep 24 05:20:46 PM UTC 24 |
| Finished | Sep 24 05:21:19 PM UTC 24 |
| Peak memory | 253996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893561242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.3893561242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_errs.2678370983 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 1175461411 ps |
| CPU time | 18.79 seconds |
| Started | Sep 24 05:20:46 PM UTC 24 |
| Finished | Sep 24 05:21:06 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678370983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.2678370983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/46.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_lock.2075806794 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 10934418628 ps |
| CPU time | 31.56 seconds |
| Started | Sep 24 05:20:43 PM UTC 24 |
| Finished | Sep 24 05:21:16 PM UTC 24 |
| Peak memory | 254044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075806794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.2075806794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/46.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_init_fail.3755379980 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 140590389 ps |
| CPU time | 5.88 seconds |
| Started | Sep 24 05:20:43 PM UTC 24 |
| Finished | Sep 24 05:20:50 PM UTC 24 |
| Peak memory | 251808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755379980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.3755379980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/46.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_macro_errs.2630680439 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 1284977507 ps |
| CPU time | 9.83 seconds |
| Started | Sep 24 05:20:46 PM UTC 24 |
| Finished | Sep 24 05:20:57 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630680439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.2630680439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/46.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_key_req.1269216066 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 519893365 ps |
| CPU time | 8.48 seconds |
| Started | Sep 24 05:20:46 PM UTC 24 |
| Finished | Sep 24 05:20:56 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269216066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.1269216066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_esc.3420054899 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 635625208 ps |
| CPU time | 9.28 seconds |
| Started | Sep 24 05:20:43 PM UTC 24 |
| Finished | Sep 24 05:20:53 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420054899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.3420054899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_req.4144368808 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 561506023 ps |
| CPU time | 15.58 seconds |
| Started | Sep 24 05:20:43 PM UTC 24 |
| Finished | Sep 24 05:21:00 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144368808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.4144368808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_regwen.4009819667 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 4124359944 ps |
| CPU time | 9.72 seconds |
| Started | Sep 24 05:20:46 PM UTC 24 |
| Finished | Sep 24 05:20:57 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009819667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.4009819667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/46.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_smoke.3523574763 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 507758465 ps |
| CPU time | 6.45 seconds |
| Started | Sep 24 05:20:43 PM UTC 24 |
| Finished | Sep 24 05:20:50 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523574763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.3523574763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/46.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all.2309574433 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 13929351690 ps |
| CPU time | 82.08 seconds |
| Started | Sep 24 05:20:50 PM UTC 24 |
| Finished | Sep 24 05:22:14 PM UTC 24 |
| Peak memory | 256128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309574433 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.2309574433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_test_access.3239963837 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 2071515346 ps |
| CPU time | 17.55 seconds |
| Started | Sep 24 05:20:47 PM UTC 24 |
| Finished | Sep 24 05:21:05 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239963837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.3239963837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/46.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_alert_test.886508407 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 156676933 ps |
| CPU time | 2.54 seconds |
| Started | Sep 24 05:20:59 PM UTC 24 |
| Finished | Sep 24 05:21:03 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886508407 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.886508407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/47.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_check_fail.1143874200 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 9061038604 ps |
| CPU time | 27.55 seconds |
| Started | Sep 24 05:20:53 PM UTC 24 |
| Finished | Sep 24 05:21:22 PM UTC 24 |
| Peak memory | 252192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143874200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.1143874200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/47.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_errs.3072130023 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 1285322270 ps |
| CPU time | 22.72 seconds |
| Started | Sep 24 05:20:53 PM UTC 24 |
| Finished | Sep 24 05:21:17 PM UTC 24 |
| Peak memory | 251736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072130023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.3072130023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/47.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_lock.1111781306 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 5266272558 ps |
| CPU time | 40.5 seconds |
| Started | Sep 24 05:20:53 PM UTC 24 |
| Finished | Sep 24 05:21:35 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111781306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.1111781306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/47.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_init_fail.4284251058 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 161895385 ps |
| CPU time | 5.11 seconds |
| Started | Sep 24 05:20:53 PM UTC 24 |
| Finished | Sep 24 05:20:59 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284251058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.4284251058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/47.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_macro_errs.1113426940 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 219034172 ps |
| CPU time | 6.04 seconds |
| Started | Sep 24 05:20:53 PM UTC 24 |
| Finished | Sep 24 05:21:00 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113426940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.1113426940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/47.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_key_req.1538346627 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2393842941 ps |
| CPU time | 24.31 seconds |
| Started | Sep 24 05:20:53 PM UTC 24 |
| Finished | Sep 24 05:21:19 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538346627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.1538346627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_esc.1302107969 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 201810415 ps |
| CPU time | 5.76 seconds |
| Started | Sep 24 05:20:53 PM UTC 24 |
| Finished | Sep 24 05:21:00 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302107969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.1302107969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_req.899833040 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 1444118839 ps |
| CPU time | 11.97 seconds |
| Started | Sep 24 05:20:53 PM UTC 24 |
| Finished | Sep 24 05:21:06 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899833040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.899833040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_regwen.3571373308 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 1011957000 ps |
| CPU time | 8.87 seconds |
| Started | Sep 24 05:20:59 PM UTC 24 |
| Finished | Sep 24 05:21:09 PM UTC 24 |
| Peak memory | 251532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571373308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.3571373308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/47.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_smoke.3651094203 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 268095918 ps |
| CPU time | 7.24 seconds |
| Started | Sep 24 05:20:50 PM UTC 24 |
| Finished | Sep 24 05:20:58 PM UTC 24 |
| Peak memory | 251872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651094203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.3651094203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/47.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all.1601071988 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 127476891975 ps |
| CPU time | 276.21 seconds |
| Started | Sep 24 05:20:59 PM UTC 24 |
| Finished | Sep 24 05:25:39 PM UTC 24 |
| Peak memory | 274600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601071988 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.1601071988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.4232821196 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 5513294290 ps |
| CPU time | 82.75 seconds |
| Started | Sep 24 05:20:59 PM UTC 24 |
| Finished | Sep 24 05:22:24 PM UTC 24 |
| Peak memory | 258260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4232821196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 47.otp_ctrl_stress_all_with_rand_reset.4232821196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_test_access.2649604162 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 3575742618 ps |
| CPU time | 35.8 seconds |
| Started | Sep 24 05:20:59 PM UTC 24 |
| Finished | Sep 24 05:21:36 PM UTC 24 |
| Peak memory | 253960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649604162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.2649604162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/47.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_alert_test.295520186 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 718571282 ps |
| CPU time | 3.75 seconds |
| Started | Sep 24 05:21:07 PM UTC 24 |
| Finished | Sep 24 05:21:12 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295520186 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.295520186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/48.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_check_fail.3999507626 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 665018428 ps |
| CPU time | 22.58 seconds |
| Started | Sep 24 05:20:59 PM UTC 24 |
| Finished | Sep 24 05:21:23 PM UTC 24 |
| Peak memory | 253972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999507626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.3999507626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/48.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_errs.952372503 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 302536521 ps |
| CPU time | 19.31 seconds |
| Started | Sep 24 05:20:59 PM UTC 24 |
| Finished | Sep 24 05:21:20 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952372503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.952372503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/48.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_lock.274303666 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 630671938 ps |
| CPU time | 8.76 seconds |
| Started | Sep 24 05:20:59 PM UTC 24 |
| Finished | Sep 24 05:21:09 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274303666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.274303666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/48.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_init_fail.1219337932 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 126760420 ps |
| CPU time | 3.66 seconds |
| Started | Sep 24 05:20:59 PM UTC 24 |
| Finished | Sep 24 05:21:04 PM UTC 24 |
| Peak memory | 251944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219337932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.1219337932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/48.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_macro_errs.2132207293 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 4110775602 ps |
| CPU time | 7.98 seconds |
| Started | Sep 24 05:20:59 PM UTC 24 |
| Finished | Sep 24 05:21:08 PM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132207293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.2132207293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/48.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_key_req.2968086563 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 1031240461 ps |
| CPU time | 10.36 seconds |
| Started | Sep 24 05:20:59 PM UTC 24 |
| Finished | Sep 24 05:21:11 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968086563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.2968086563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_esc.1733464000 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 937233895 ps |
| CPU time | 16.17 seconds |
| Started | Sep 24 05:20:59 PM UTC 24 |
| Finished | Sep 24 05:21:17 PM UTC 24 |
| Peak memory | 252040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733464000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.1733464000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_req.2694072645 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 878900672 ps |
| CPU time | 15.53 seconds |
| Started | Sep 24 05:20:59 PM UTC 24 |
| Finished | Sep 24 05:21:16 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694072645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.2694072645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_regwen.4131283895 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 676590170 ps |
| CPU time | 6.29 seconds |
| Started | Sep 24 05:20:59 PM UTC 24 |
| Finished | Sep 24 05:21:07 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131283895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.4131283895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/48.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_smoke.996198671 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 4346538972 ps |
| CPU time | 13.33 seconds |
| Started | Sep 24 05:20:59 PM UTC 24 |
| Finished | Sep 24 05:21:14 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996198671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.996198671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/48.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.3447409717 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 12689058017 ps |
| CPU time | 154.21 seconds |
| Started | Sep 24 05:21:07 PM UTC 24 |
| Finished | Sep 24 05:23:44 PM UTC 24 |
| Peak memory | 274712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447409717 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.3447409717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_test_access.2823870174 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 532443559 ps |
| CPU time | 6.86 seconds |
| Started | Sep 24 05:20:59 PM UTC 24 |
| Finished | Sep 24 05:21:07 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823870174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.2823870174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/48.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_alert_test.3604692853 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 690280169 ps |
| CPU time | 2.87 seconds |
| Started | Sep 24 05:21:09 PM UTC 24 |
| Finished | Sep 24 05:21:13 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604692853 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.3604692853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/49.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_check_fail.3910129886 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2563633754 ps |
| CPU time | 16.33 seconds |
| Started | Sep 24 05:21:07 PM UTC 24 |
| Finished | Sep 24 05:21:25 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910129886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.3910129886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/49.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_errs.273991481 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 762255586 ps |
| CPU time | 13.28 seconds |
| Started | Sep 24 05:21:07 PM UTC 24 |
| Finished | Sep 24 05:21:22 PM UTC 24 |
| Peak memory | 258084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273991481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.273991481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/49.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_lock.2468244879 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 11465081738 ps |
| CPU time | 50.07 seconds |
| Started | Sep 24 05:21:07 PM UTC 24 |
| Finished | Sep 24 05:21:59 PM UTC 24 |
| Peak memory | 253972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468244879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.2468244879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/49.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_init_fail.672755489 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 518758065 ps |
| CPU time | 4.24 seconds |
| Started | Sep 24 05:21:07 PM UTC 24 |
| Finished | Sep 24 05:21:12 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672755489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.672755489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/49.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_macro_errs.2999757159 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 1033395626 ps |
| CPU time | 23.63 seconds |
| Started | Sep 24 05:21:07 PM UTC 24 |
| Finished | Sep 24 05:21:32 PM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999757159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.2999757159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/49.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_key_req.4089227528 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 25732287499 ps |
| CPU time | 52.68 seconds |
| Started | Sep 24 05:21:07 PM UTC 24 |
| Finished | Sep 24 05:22:02 PM UTC 24 |
| Peak memory | 253964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089227528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.4089227528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_esc.1280067952 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 208057885 ps |
| CPU time | 8.24 seconds |
| Started | Sep 24 05:21:07 PM UTC 24 |
| Finished | Sep 24 05:21:16 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280067952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.1280067952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_req.2465188248 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 248268387 ps |
| CPU time | 8.21 seconds |
| Started | Sep 24 05:21:07 PM UTC 24 |
| Finished | Sep 24 05:21:16 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465188248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.2465188248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_regwen.608341025 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 4435266087 ps |
| CPU time | 15.95 seconds |
| Started | Sep 24 05:21:07 PM UTC 24 |
| Finished | Sep 24 05:21:25 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608341025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.608341025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/49.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_smoke.2745730311 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 429462927 ps |
| CPU time | 8.97 seconds |
| Started | Sep 24 05:21:07 PM UTC 24 |
| Finished | Sep 24 05:21:17 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745730311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.2745730311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/49.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all.815202908 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 5326747547 ps |
| CPU time | 103.19 seconds |
| Started | Sep 24 05:21:09 PM UTC 24 |
| Finished | Sep 24 05:22:54 PM UTC 24 |
| Peak memory | 258196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815202908 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.815202908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.33641209 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 9654008264 ps |
| CPU time | 68.31 seconds |
| Started | Sep 24 05:21:07 PM UTC 24 |
| Finished | Sep 24 05:22:18 PM UTC 24 |
| Peak memory | 268624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=33641209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.33641209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_test_access.1863800848 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 1208773830 ps |
| CPU time | 12.35 seconds |
| Started | Sep 24 05:21:07 PM UTC 24 |
| Finished | Sep 24 05:21:21 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863800848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.1863800848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/49.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_alert_test.4191841370 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 92821596 ps |
| CPU time | 2.24 seconds |
| Started | Sep 24 05:15:44 PM UTC 24 |
| Finished | Sep 24 05:15:47 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191841370 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.4191841370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_errs.4029272030 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1273835730 ps |
| CPU time | 24.02 seconds |
| Started | Sep 24 05:15:36 PM UTC 24 |
| Finished | Sep 24 05:16:02 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029272030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.4029272030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_lock.1496674054 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 238829534 ps |
| CPU time | 6.63 seconds |
| Started | Sep 24 05:15:36 PM UTC 24 |
| Finished | Sep 24 05:15:44 PM UTC 24 |
| Peak memory | 251972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496674054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.1496674054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_macro_errs.2984630305 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 5808882363 ps |
| CPU time | 40.36 seconds |
| Started | Sep 24 05:15:39 PM UTC 24 |
| Finished | Sep 24 05:16:21 PM UTC 24 |
| Peak memory | 258200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984630305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.2984630305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_key_req.3091916409 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 359778421 ps |
| CPU time | 9.82 seconds |
| Started | Sep 24 05:15:39 PM UTC 24 |
| Finished | Sep 24 05:15:50 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091916409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.3091916409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_esc.1265050393 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 133386666 ps |
| CPU time | 8.09 seconds |
| Started | Sep 24 05:15:36 PM UTC 24 |
| Finished | Sep 24 05:15:46 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265050393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.1265050393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_smoke.2089273584 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 3950145208 ps |
| CPU time | 11.53 seconds |
| Started | Sep 24 05:15:36 PM UTC 24 |
| Finished | Sep 24 05:15:49 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089273584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.2089273584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all.1065638809 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 3866121094 ps |
| CPU time | 30.65 seconds |
| Started | Sep 24 05:15:39 PM UTC 24 |
| Finished | Sep 24 05:16:11 PM UTC 24 |
| Peak memory | 253872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065638809 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.1065638809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_test_access.4227447106 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 1572080658 ps |
| CPU time | 20.62 seconds |
| Started | Sep 24 05:15:39 PM UTC 24 |
| Finished | Sep 24 05:16:01 PM UTC 24 |
| Peak memory | 254032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227447106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.4227447106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/5.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_parallel_lc_esc.699737688 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 2461615567 ps |
| CPU time | 20.19 seconds |
| Started | Sep 24 05:21:09 PM UTC 24 |
| Finished | Sep 24 05:21:31 PM UTC 24 |
| Peak memory | 252048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699737688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.699737688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/50.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.608000816 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 2540614165 ps |
| CPU time | 73.88 seconds |
| Started | Sep 24 05:21:09 PM UTC 24 |
| Finished | Sep 24 05:22:25 PM UTC 24 |
| Peak memory | 258168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=608000816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.608000816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_init_fail.120129527 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 395885039 ps |
| CPU time | 4.27 seconds |
| Started | Sep 24 05:21:13 PM UTC 24 |
| Finished | Sep 24 05:21:19 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120129527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.120129527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/51.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_parallel_lc_esc.3070494829 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 129227457 ps |
| CPU time | 5.7 seconds |
| Started | Sep 24 05:21:13 PM UTC 24 |
| Finished | Sep 24 05:21:20 PM UTC 24 |
| Peak memory | 251640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070494829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.3070494829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/51.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.3295766502 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 9397177064 ps |
| CPU time | 129.88 seconds |
| Started | Sep 24 05:21:13 PM UTC 24 |
| Finished | Sep 24 05:23:26 PM UTC 24 |
| Peak memory | 268480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3295766502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 51.otp_ctrl_stress_all_with_rand_reset.3295766502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_init_fail.2155488083 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 105318987 ps |
| CPU time | 4.5 seconds |
| Started | Sep 24 05:21:13 PM UTC 24 |
| Finished | Sep 24 05:21:19 PM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155488083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.2155488083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/52.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_parallel_lc_esc.4104874230 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 476561495 ps |
| CPU time | 6.73 seconds |
| Started | Sep 24 05:21:13 PM UTC 24 |
| Finished | Sep 24 05:21:21 PM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104874230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.4104874230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/52.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.631899003 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 7528395200 ps |
| CPU time | 139.83 seconds |
| Started | Sep 24 05:21:13 PM UTC 24 |
| Finished | Sep 24 05:23:36 PM UTC 24 |
| Peak memory | 258116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=631899003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.631899003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_parallel_lc_esc.1977249980 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 18028924549 ps |
| CPU time | 34.68 seconds |
| Started | Sep 24 05:21:13 PM UTC 24 |
| Finished | Sep 24 05:21:50 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977249980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.1977249980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/53.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.275906145 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 5337331615 ps |
| CPU time | 99.26 seconds |
| Started | Sep 24 05:21:19 PM UTC 24 |
| Finished | Sep 24 05:23:01 PM UTC 24 |
| Peak memory | 274564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=275906145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.275906145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_init_fail.3437133191 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 147040605 ps |
| CPU time | 3.85 seconds |
| Started | Sep 24 05:21:19 PM UTC 24 |
| Finished | Sep 24 05:21:24 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437133191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.3437133191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/54.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_parallel_lc_esc.1032949103 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 168935162 ps |
| CPU time | 6.47 seconds |
| Started | Sep 24 05:21:19 PM UTC 24 |
| Finished | Sep 24 05:21:27 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032949103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.1032949103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/54.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.3777516904 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 7611979150 ps |
| CPU time | 103.68 seconds |
| Started | Sep 24 05:21:19 PM UTC 24 |
| Finished | Sep 24 05:23:05 PM UTC 24 |
| Peak memory | 258176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3777516904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 54.otp_ctrl_stress_all_with_rand_reset.3777516904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/54.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_init_fail.425643349 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 2554634536 ps |
| CPU time | 10.06 seconds |
| Started | Sep 24 05:21:19 PM UTC 24 |
| Finished | Sep 24 05:21:31 PM UTC 24 |
| Peak memory | 252052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425643349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.425643349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/55.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_parallel_lc_esc.2604184562 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 312524756 ps |
| CPU time | 9.84 seconds |
| Started | Sep 24 05:21:19 PM UTC 24 |
| Finished | Sep 24 05:21:31 PM UTC 24 |
| Peak memory | 251808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604184562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.2604184562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/55.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_init_fail.4150701266 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 242490167 ps |
| CPU time | 5.16 seconds |
| Started | Sep 24 05:21:19 PM UTC 24 |
| Finished | Sep 24 05:21:26 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150701266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.4150701266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/56.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_parallel_lc_esc.3945625541 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 6690053090 ps |
| CPU time | 18.08 seconds |
| Started | Sep 24 05:21:19 PM UTC 24 |
| Finished | Sep 24 05:21:39 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945625541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.3945625541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/56.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_init_fail.275266933 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 283435772 ps |
| CPU time | 4.35 seconds |
| Started | Sep 24 05:21:20 PM UTC 24 |
| Finished | Sep 24 05:21:26 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275266933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.275266933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/57.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_parallel_lc_esc.260278720 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 254922957 ps |
| CPU time | 15.29 seconds |
| Started | Sep 24 05:21:20 PM UTC 24 |
| Finished | Sep 24 05:21:37 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260278720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.260278720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/57.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.2174999644 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3223511705 ps |
| CPU time | 86.16 seconds |
| Started | Sep 24 05:21:20 PM UTC 24 |
| Finished | Sep 24 05:22:48 PM UTC 24 |
| Peak memory | 268628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2174999644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 57.otp_ctrl_stress_all_with_rand_reset.2174999644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/57.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_init_fail.2035619080 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2961075253 ps |
| CPU time | 9.42 seconds |
| Started | Sep 24 05:21:20 PM UTC 24 |
| Finished | Sep 24 05:21:31 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035619080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.2035619080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/58.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_parallel_lc_esc.920092829 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 122544179 ps |
| CPU time | 4.84 seconds |
| Started | Sep 24 05:21:20 PM UTC 24 |
| Finished | Sep 24 05:21:26 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920092829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.920092829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/58.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_parallel_lc_esc.3239555740 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 394040448 ps |
| CPU time | 5.02 seconds |
| Started | Sep 24 05:21:22 PM UTC 24 |
| Finished | Sep 24 05:21:29 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239555740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.3239555740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_alert_test.2928506160 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 56712057 ps |
| CPU time | 2.33 seconds |
| Started | Sep 24 05:15:47 PM UTC 24 |
| Finished | Sep 24 05:15:50 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928506160 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.2928506160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_background_chks.2626998082 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 7814158915 ps |
| CPU time | 15.02 seconds |
| Started | Sep 24 05:15:44 PM UTC 24 |
| Finished | Sep 24 05:16:00 PM UTC 24 |
| Peak memory | 252020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626998082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.2626998082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_check_fail.2507850058 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 736923187 ps |
| CPU time | 10.07 seconds |
| Started | Sep 24 05:15:47 PM UTC 24 |
| Finished | Sep 24 05:15:58 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507850058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.2507850058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_errs.3999279389 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 1162576522 ps |
| CPU time | 19.69 seconds |
| Started | Sep 24 05:15:47 PM UTC 24 |
| Finished | Sep 24 05:16:09 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999279389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.3999279389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_lock.4015729551 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 754441979 ps |
| CPU time | 15.16 seconds |
| Started | Sep 24 05:15:47 PM UTC 24 |
| Finished | Sep 24 05:16:03 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015729551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.4015729551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_macro_errs.1117146889 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1824119376 ps |
| CPU time | 25.66 seconds |
| Started | Sep 24 05:15:47 PM UTC 24 |
| Finished | Sep 24 05:16:14 PM UTC 24 |
| Peak memory | 255944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117146889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.1117146889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_esc.3272120121 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 117121169 ps |
| CPU time | 4.71 seconds |
| Started | Sep 24 05:15:44 PM UTC 24 |
| Finished | Sep 24 05:15:50 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272120121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.3272120121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_req.3148337005 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1011035761 ps |
| CPU time | 12.88 seconds |
| Started | Sep 24 05:15:44 PM UTC 24 |
| Finished | Sep 24 05:15:58 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148337005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.3148337005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_regwen.1360578062 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 186072308 ps |
| CPU time | 6.36 seconds |
| Started | Sep 24 05:15:47 PM UTC 24 |
| Finished | Sep 24 05:15:54 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360578062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.1360578062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_smoke.1770396331 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 1658122160 ps |
| CPU time | 22.42 seconds |
| Started | Sep 24 05:15:44 PM UTC 24 |
| Finished | Sep 24 05:16:07 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770396331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.1770396331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/6.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_init_fail.468031199 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 227564845 ps |
| CPU time | 5.17 seconds |
| Started | Sep 24 05:21:22 PM UTC 24 |
| Finished | Sep 24 05:21:29 PM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468031199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.468031199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/60.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_parallel_lc_esc.1437211728 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 303792533 ps |
| CPU time | 14.15 seconds |
| Started | Sep 24 05:21:22 PM UTC 24 |
| Finished | Sep 24 05:21:38 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437211728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1437211728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/60.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_init_fail.4143854438 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2677313364 ps |
| CPU time | 7.26 seconds |
| Started | Sep 24 05:21:23 PM UTC 24 |
| Finished | Sep 24 05:21:31 PM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143854438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.4143854438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/61.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_parallel_lc_esc.480222976 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 211931942 ps |
| CPU time | 6.74 seconds |
| Started | Sep 24 05:21:27 PM UTC 24 |
| Finished | Sep 24 05:21:35 PM UTC 24 |
| Peak memory | 251568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480222976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.480222976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/61.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_init_fail.3154444772 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 105759344 ps |
| CPU time | 4.35 seconds |
| Started | Sep 24 05:21:27 PM UTC 24 |
| Finished | Sep 24 05:21:32 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154444772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.3154444772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/62.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_parallel_lc_esc.4086205916 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 262829766 ps |
| CPU time | 7.04 seconds |
| Started | Sep 24 05:21:27 PM UTC 24 |
| Finished | Sep 24 05:21:35 PM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086205916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.4086205916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/62.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_init_fail.2940076013 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 161556407 ps |
| CPU time | 6.4 seconds |
| Started | Sep 24 05:21:27 PM UTC 24 |
| Finished | Sep 24 05:21:34 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940076013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.2940076013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/63.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_parallel_lc_esc.1261812766 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 1292636164 ps |
| CPU time | 3.98 seconds |
| Started | Sep 24 05:21:27 PM UTC 24 |
| Finished | Sep 24 05:21:32 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261812766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.1261812766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/63.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_init_fail.2329681635 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 189276276 ps |
| CPU time | 3.78 seconds |
| Started | Sep 24 05:21:27 PM UTC 24 |
| Finished | Sep 24 05:21:32 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329681635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.2329681635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/64.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_parallel_lc_esc.1292937243 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 1147855701 ps |
| CPU time | 10.47 seconds |
| Started | Sep 24 05:21:28 PM UTC 24 |
| Finished | Sep 24 05:21:40 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292937243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.1292937243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/64.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_init_fail.3539735447 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 278130469 ps |
| CPU time | 5.25 seconds |
| Started | Sep 24 05:21:28 PM UTC 24 |
| Finished | Sep 24 05:21:35 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539735447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.3539735447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/65.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_parallel_lc_esc.3725273221 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 1071904820 ps |
| CPU time | 19.18 seconds |
| Started | Sep 24 05:21:28 PM UTC 24 |
| Finished | Sep 24 05:21:49 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725273221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.3725273221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/65.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.2119656234 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 10437313693 ps |
| CPU time | 197.66 seconds |
| Started | Sep 24 05:21:30 PM UTC 24 |
| Finished | Sep 24 05:24:51 PM UTC 24 |
| Peak memory | 274548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2119656234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 65.otp_ctrl_stress_all_with_rand_reset.2119656234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_parallel_lc_esc.2721722670 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 756694663 ps |
| CPU time | 16.23 seconds |
| Started | Sep 24 05:21:30 PM UTC 24 |
| Finished | Sep 24 05:21:48 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721722670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.2721722670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/66.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.472231405 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 15836678513 ps |
| CPU time | 74.02 seconds |
| Started | Sep 24 05:21:31 PM UTC 24 |
| Finished | Sep 24 05:22:47 PM UTC 24 |
| Peak memory | 258196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=472231405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.472231405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_init_fail.983152165 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 307519972 ps |
| CPU time | 5.58 seconds |
| Started | Sep 24 05:21:34 PM UTC 24 |
| Finished | Sep 24 05:21:41 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983152165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.983152165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/67.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_parallel_lc_esc.883544486 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 559798662 ps |
| CPU time | 9.19 seconds |
| Started | Sep 24 05:21:34 PM UTC 24 |
| Finished | Sep 24 05:21:45 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883544486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.883544486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/67.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_init_fail.1042516000 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 495456165 ps |
| CPU time | 5.82 seconds |
| Started | Sep 24 05:21:35 PM UTC 24 |
| Finished | Sep 24 05:21:42 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042516000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.1042516000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/68.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_parallel_lc_esc.3014637748 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 2040124721 ps |
| CPU time | 25.08 seconds |
| Started | Sep 24 05:21:35 PM UTC 24 |
| Finished | Sep 24 05:22:01 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014637748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.3014637748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/68.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_init_fail.4291349560 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 236253640 ps |
| CPU time | 4.53 seconds |
| Started | Sep 24 05:21:35 PM UTC 24 |
| Finished | Sep 24 05:21:41 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291349560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.4291349560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/69.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_parallel_lc_esc.2209393384 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 3479890507 ps |
| CPU time | 37.29 seconds |
| Started | Sep 24 05:21:35 PM UTC 24 |
| Finished | Sep 24 05:22:14 PM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209393384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.2209393384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/69.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_alert_test.321395092 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 90096766 ps |
| CPU time | 2.36 seconds |
| Started | Sep 24 05:15:56 PM UTC 24 |
| Finished | Sep 24 05:16:00 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321395092 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.321395092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_background_chks.1983806434 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 5367335618 ps |
| CPU time | 20.15 seconds |
| Started | Sep 24 05:15:50 PM UTC 24 |
| Finished | Sep 24 05:16:12 PM UTC 24 |
| Peak memory | 252048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983806434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.1983806434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_errs.1928370867 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1803562433 ps |
| CPU time | 15.96 seconds |
| Started | Sep 24 05:15:56 PM UTC 24 |
| Finished | Sep 24 05:16:13 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928370867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.1928370867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_lock.1853871126 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 398122956 ps |
| CPU time | 9.09 seconds |
| Started | Sep 24 05:15:51 PM UTC 24 |
| Finished | Sep 24 05:16:01 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853871126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.1853871126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_macro_errs.1556091099 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 8421391089 ps |
| CPU time | 53.79 seconds |
| Started | Sep 24 05:15:56 PM UTC 24 |
| Finished | Sep 24 05:16:51 PM UTC 24 |
| Peak memory | 270492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556091099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.1556091099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_esc.1561729861 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 390898424 ps |
| CPU time | 6.4 seconds |
| Started | Sep 24 05:15:51 PM UTC 24 |
| Finished | Sep 24 05:15:58 PM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561729861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.1561729861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_req.3811851978 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 2032942395 ps |
| CPU time | 22.49 seconds |
| Started | Sep 24 05:15:50 PM UTC 24 |
| Finished | Sep 24 05:16:14 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811851978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.3811851978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_regwen.2368724325 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 184714581 ps |
| CPU time | 3.89 seconds |
| Started | Sep 24 05:15:56 PM UTC 24 |
| Finished | Sep 24 05:16:01 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368724325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.2368724325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_smoke.1419014192 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 4178087224 ps |
| CPU time | 9.82 seconds |
| Started | Sep 24 05:15:50 PM UTC 24 |
| Finished | Sep 24 05:16:01 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419014192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.1419014192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.184099019 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 60651288417 ps |
| CPU time | 484.89 seconds |
| Started | Sep 24 05:15:56 PM UTC 24 |
| Finished | Sep 24 05:24:07 PM UTC 24 |
| Peak memory | 291652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184099019 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.184099019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_test_access.2989077700 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 3267823609 ps |
| CPU time | 24.85 seconds |
| Started | Sep 24 05:15:56 PM UTC 24 |
| Finished | Sep 24 05:16:22 PM UTC 24 |
| Peak memory | 252044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989077700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2989077700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/7.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_init_fail.1923549941 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 392270747 ps |
| CPU time | 5.33 seconds |
| Started | Sep 24 05:21:35 PM UTC 24 |
| Finished | Sep 24 05:21:42 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923549941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.1923549941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/70.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_parallel_lc_esc.2409812576 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 795858240 ps |
| CPU time | 9.67 seconds |
| Started | Sep 24 05:21:36 PM UTC 24 |
| Finished | Sep 24 05:21:48 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409812576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.2409812576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/70.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.3187729412 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 18759834709 ps |
| CPU time | 183.04 seconds |
| Started | Sep 24 05:21:36 PM UTC 24 |
| Finished | Sep 24 05:24:43 PM UTC 24 |
| Peak memory | 270548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3187729412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 70.otp_ctrl_stress_all_with_rand_reset.3187729412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/70.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_init_fail.3395148281 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 270387168 ps |
| CPU time | 6.39 seconds |
| Started | Sep 24 05:21:36 PM UTC 24 |
| Finished | Sep 24 05:21:44 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395148281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.3395148281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/71.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_parallel_lc_esc.3357802145 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 100579843 ps |
| CPU time | 4.34 seconds |
| Started | Sep 24 05:21:37 PM UTC 24 |
| Finished | Sep 24 05:21:42 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357802145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.3357802145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/71.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_init_fail.28240797 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 2040865086 ps |
| CPU time | 7.67 seconds |
| Started | Sep 24 05:21:41 PM UTC 24 |
| Finished | Sep 24 05:21:50 PM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28240797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.28240797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/72.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_parallel_lc_esc.2853003733 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 218750064 ps |
| CPU time | 6.7 seconds |
| Started | Sep 24 05:21:41 PM UTC 24 |
| Finished | Sep 24 05:21:49 PM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853003733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.2853003733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/72.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_init_fail.1172282135 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 421173156 ps |
| CPU time | 5.64 seconds |
| Started | Sep 24 05:21:41 PM UTC 24 |
| Finished | Sep 24 05:21:48 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172282135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.1172282135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/73.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_parallel_lc_esc.1995063450 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 327113512 ps |
| CPU time | 7.17 seconds |
| Started | Sep 24 05:21:41 PM UTC 24 |
| Finished | Sep 24 05:21:49 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995063450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.1995063450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/73.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_init_fail.2079895413 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 150161496 ps |
| CPU time | 6.19 seconds |
| Started | Sep 24 05:21:41 PM UTC 24 |
| Finished | Sep 24 05:21:49 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079895413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.2079895413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/74.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_parallel_lc_esc.3412811872 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 4287280764 ps |
| CPU time | 12.53 seconds |
| Started | Sep 24 05:21:42 PM UTC 24 |
| Finished | Sep 24 05:21:56 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412811872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.3412811872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/74.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_init_fail.3422586692 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 160988080 ps |
| CPU time | 6.1 seconds |
| Started | Sep 24 05:21:42 PM UTC 24 |
| Finished | Sep 24 05:21:50 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422586692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.3422586692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/75.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_parallel_lc_esc.1364212316 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 166092424 ps |
| CPU time | 7.78 seconds |
| Started | Sep 24 05:21:43 PM UTC 24 |
| Finished | Sep 24 05:21:52 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364212316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.1364212316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/75.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.419739533 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 1764331327 ps |
| CPU time | 52.97 seconds |
| Started | Sep 24 05:21:44 PM UTC 24 |
| Finished | Sep 24 05:22:38 PM UTC 24 |
| Peak memory | 268376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=419739533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.419739533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/75.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_init_fail.2551621334 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 311990679 ps |
| CPU time | 6.09 seconds |
| Started | Sep 24 05:21:45 PM UTC 24 |
| Finished | Sep 24 05:21:52 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551621334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.2551621334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/76.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_parallel_lc_esc.598908393 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 1584516406 ps |
| CPU time | 28.84 seconds |
| Started | Sep 24 05:21:46 PM UTC 24 |
| Finished | Sep 24 05:22:17 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598908393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.598908393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/76.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_init_fail.2204072268 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 485682789 ps |
| CPU time | 5.61 seconds |
| Started | Sep 24 05:21:49 PM UTC 24 |
| Finished | Sep 24 05:21:56 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204072268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.2204072268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/77.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_parallel_lc_esc.4246552610 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 5701324438 ps |
| CPU time | 38.89 seconds |
| Started | Sep 24 05:21:49 PM UTC 24 |
| Finished | Sep 24 05:22:29 PM UTC 24 |
| Peak memory | 253540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246552610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.4246552610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/77.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_init_fail.2260873930 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 548804467 ps |
| CPU time | 6.15 seconds |
| Started | Sep 24 05:21:49 PM UTC 24 |
| Finished | Sep 24 05:21:57 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260873930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.2260873930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/78.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_parallel_lc_esc.3461815309 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 208431197 ps |
| CPU time | 10.16 seconds |
| Started | Sep 24 05:21:51 PM UTC 24 |
| Finished | Sep 24 05:22:03 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461815309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.3461815309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/78.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.4180099643 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 50517113863 ps |
| CPU time | 116.33 seconds |
| Started | Sep 24 05:21:51 PM UTC 24 |
| Finished | Sep 24 05:23:50 PM UTC 24 |
| Peak memory | 268408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4180099643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 78.otp_ctrl_stress_all_with_rand_reset.4180099643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/78.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_init_fail.2297091330 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 398605532 ps |
| CPU time | 5.93 seconds |
| Started | Sep 24 05:21:51 PM UTC 24 |
| Finished | Sep 24 05:21:58 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297091330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.2297091330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/79.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.2993286751 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 8199837718 ps |
| CPU time | 78.09 seconds |
| Started | Sep 24 05:21:51 PM UTC 24 |
| Finished | Sep 24 05:23:12 PM UTC 24 |
| Peak memory | 258100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2993286751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 79.otp_ctrl_stress_all_with_rand_reset.2993286751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_alert_test.3895710890 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 75067547 ps |
| CPU time | 2.69 seconds |
| Started | Sep 24 05:16:03 PM UTC 24 |
| Finished | Sep 24 05:16:07 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895710890 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.3895710890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_background_chks.3652640250 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 828101209 ps |
| CPU time | 12.21 seconds |
| Started | Sep 24 05:16:01 PM UTC 24 |
| Finished | Sep 24 05:16:14 PM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652640250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.3652640250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_check_fail.2505912661 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 24022335966 ps |
| CPU time | 42.81 seconds |
| Started | Sep 24 05:16:01 PM UTC 24 |
| Finished | Sep 24 05:16:45 PM UTC 24 |
| Peak memory | 258128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505912661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.2505912661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_errs.1518733569 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 513685079 ps |
| CPU time | 12.81 seconds |
| Started | Sep 24 05:16:01 PM UTC 24 |
| Finished | Sep 24 05:16:15 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518733569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.1518733569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_macro_errs.750129302 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1654382557 ps |
| CPU time | 26.66 seconds |
| Started | Sep 24 05:16:01 PM UTC 24 |
| Finished | Sep 24 05:16:29 PM UTC 24 |
| Peak memory | 254028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750129302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.750129302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_key_req.161522592 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1235143398 ps |
| CPU time | 14.79 seconds |
| Started | Sep 24 05:16:01 PM UTC 24 |
| Finished | Sep 24 05:16:17 PM UTC 24 |
| Peak memory | 252020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161522592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.161522592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_esc.4276162382 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 178977334 ps |
| CPU time | 7.93 seconds |
| Started | Sep 24 05:16:01 PM UTC 24 |
| Finished | Sep 24 05:16:10 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276162382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.4276162382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_req.1868443063 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 278871069 ps |
| CPU time | 8.45 seconds |
| Started | Sep 24 05:16:01 PM UTC 24 |
| Finished | Sep 24 05:16:10 PM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868443063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.1868443063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_smoke.3151769270 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 1595040198 ps |
| CPU time | 6.99 seconds |
| Started | Sep 24 05:16:01 PM UTC 24 |
| Finished | Sep 24 05:16:09 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151769270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.3151769270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all.1805960957 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 15146469433 ps |
| CPU time | 101.24 seconds |
| Started | Sep 24 05:16:01 PM UTC 24 |
| Finished | Sep 24 05:17:45 PM UTC 24 |
| Peak memory | 256008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805960957 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.1805960957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_test_access.3391713538 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 8524466441 ps |
| CPU time | 19.93 seconds |
| Started | Sep 24 05:16:01 PM UTC 24 |
| Finished | Sep 24 05:16:22 PM UTC 24 |
| Peak memory | 252124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391713538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.3391713538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/8.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_init_fail.2329189883 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 196747227 ps |
| CPU time | 4.9 seconds |
| Started | Sep 24 05:21:52 PM UTC 24 |
| Finished | Sep 24 05:21:58 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329189883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.2329189883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/80.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_parallel_lc_esc.1642324121 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 181375887 ps |
| CPU time | 10.57 seconds |
| Started | Sep 24 05:21:52 PM UTC 24 |
| Finished | Sep 24 05:22:03 PM UTC 24 |
| Peak memory | 251972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642324121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.1642324121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/80.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.3975650187 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 13105568514 ps |
| CPU time | 240.91 seconds |
| Started | Sep 24 05:21:53 PM UTC 24 |
| Finished | Sep 24 05:25:58 PM UTC 24 |
| Peak memory | 272632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3975650187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 80.otp_ctrl_stress_all_with_rand_reset.3975650187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_init_fail.2380292917 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 3304622003 ps |
| CPU time | 15.2 seconds |
| Started | Sep 24 05:21:53 PM UTC 24 |
| Finished | Sep 24 05:22:10 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380292917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.2380292917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/81.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_parallel_lc_esc.2110262464 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 972524179 ps |
| CPU time | 4.59 seconds |
| Started | Sep 24 05:21:53 PM UTC 24 |
| Finished | Sep 24 05:21:59 PM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110262464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.2110262464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/81.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_init_fail.4026626616 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 527179699 ps |
| CPU time | 6.43 seconds |
| Started | Sep 24 05:21:57 PM UTC 24 |
| Finished | Sep 24 05:22:05 PM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026626616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.4026626616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/82.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_parallel_lc_esc.3783952294 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 274731170 ps |
| CPU time | 7.17 seconds |
| Started | Sep 24 05:21:58 PM UTC 24 |
| Finished | Sep 24 05:22:06 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783952294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.3783952294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/82.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.968029059 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 8401851504 ps |
| CPU time | 73.43 seconds |
| Started | Sep 24 05:21:58 PM UTC 24 |
| Finished | Sep 24 05:23:13 PM UTC 24 |
| Peak memory | 258176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=968029059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.968029059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/82.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_init_fail.1963216813 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 130534369 ps |
| CPU time | 3.84 seconds |
| Started | Sep 24 05:21:58 PM UTC 24 |
| Finished | Sep 24 05:22:03 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963216813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.1963216813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/83.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_parallel_lc_esc.3704371274 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 226322726 ps |
| CPU time | 11.7 seconds |
| Started | Sep 24 05:21:59 PM UTC 24 |
| Finished | Sep 24 05:22:12 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704371274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.3704371274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/83.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_init_fail.3951542501 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 185572750 ps |
| CPU time | 5.34 seconds |
| Started | Sep 24 05:22:00 PM UTC 24 |
| Finished | Sep 24 05:22:07 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951542501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.3951542501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/84.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_parallel_lc_esc.2347913495 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 196284471 ps |
| CPU time | 3.99 seconds |
| Started | Sep 24 05:22:00 PM UTC 24 |
| Finished | Sep 24 05:22:05 PM UTC 24 |
| Peak memory | 251704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347913495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.2347913495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/84.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_init_fail.2700184071 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 201448970 ps |
| CPU time | 5.33 seconds |
| Started | Sep 24 05:22:04 PM UTC 24 |
| Finished | Sep 24 05:22:11 PM UTC 24 |
| Peak memory | 251868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700184071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.2700184071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/85.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_parallel_lc_esc.1290011789 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 358772819 ps |
| CPU time | 13 seconds |
| Started | Sep 24 05:22:04 PM UTC 24 |
| Finished | Sep 24 05:22:19 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290011789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.1290011789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_init_fail.999687395 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 320016525 ps |
| CPU time | 6.61 seconds |
| Started | Sep 24 05:22:04 PM UTC 24 |
| Finished | Sep 24 05:22:12 PM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999687395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.999687395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/86.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_parallel_lc_esc.1462253303 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 1090558293 ps |
| CPU time | 5.48 seconds |
| Started | Sep 24 05:22:08 PM UTC 24 |
| Finished | Sep 24 05:22:15 PM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462253303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.1462253303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/86.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_init_fail.1860811887 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 331343253 ps |
| CPU time | 6.83 seconds |
| Started | Sep 24 05:22:08 PM UTC 24 |
| Finished | Sep 24 05:22:16 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860811887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.1860811887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/87.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_parallel_lc_esc.3288115724 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 872326641 ps |
| CPU time | 9.82 seconds |
| Started | Sep 24 05:22:08 PM UTC 24 |
| Finished | Sep 24 05:22:19 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288115724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.3288115724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/87.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_init_fail.601791700 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 186525514 ps |
| CPU time | 5.41 seconds |
| Started | Sep 24 05:22:10 PM UTC 24 |
| Finished | Sep 24 05:22:17 PM UTC 24 |
| Peak memory | 251868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601791700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.601791700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/88.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_parallel_lc_esc.2447497487 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 337056732 ps |
| CPU time | 19.27 seconds |
| Started | Sep 24 05:22:12 PM UTC 24 |
| Finished | Sep 24 05:22:32 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447497487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.2447497487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/88.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.2270457136 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 10482715729 ps |
| CPU time | 156.18 seconds |
| Started | Sep 24 05:22:13 PM UTC 24 |
| Finished | Sep 24 05:24:52 PM UTC 24 |
| Peak memory | 268404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2270457136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 88.otp_ctrl_stress_all_with_rand_reset.2270457136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/88.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_init_fail.3644331693 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 436264331 ps |
| CPU time | 5.82 seconds |
| Started | Sep 24 05:22:13 PM UTC 24 |
| Finished | Sep 24 05:22:20 PM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644331693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.3644331693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/89.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_parallel_lc_esc.2703260759 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 272345491 ps |
| CPU time | 13.61 seconds |
| Started | Sep 24 05:22:13 PM UTC 24 |
| Finished | Sep 24 05:22:28 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703260759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.2703260759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/89.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.1771336915 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 64177666381 ps |
| CPU time | 121.92 seconds |
| Started | Sep 24 05:22:21 PM UTC 24 |
| Finished | Sep 24 05:24:25 PM UTC 24 |
| Peak memory | 274640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1771336915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 89.otp_ctrl_stress_all_with_rand_reset.1771336915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/89.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_alert_test.681062857 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 127305233 ps |
| CPU time | 2.29 seconds |
| Started | Sep 24 05:16:10 PM UTC 24 |
| Finished | Sep 24 05:16:14 PM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681062857 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.681062857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_background_chks.454815372 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 1214984404 ps |
| CPU time | 25.1 seconds |
| Started | Sep 24 05:16:04 PM UTC 24 |
| Finished | Sep 24 05:16:31 PM UTC 24 |
| Peak memory | 252040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454815372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.454815372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_check_fail.3500999333 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 898553566 ps |
| CPU time | 10.71 seconds |
| Started | Sep 24 05:16:06 PM UTC 24 |
| Finished | Sep 24 05:16:18 PM UTC 24 |
| Peak memory | 252044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500999333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.3500999333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_errs.2310304414 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 484918276 ps |
| CPU time | 15.14 seconds |
| Started | Sep 24 05:16:06 PM UTC 24 |
| Finished | Sep 24 05:16:22 PM UTC 24 |
| Peak memory | 252032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310304414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.2310304414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_lock.437091708 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 1378825500 ps |
| CPU time | 19.39 seconds |
| Started | Sep 24 05:16:04 PM UTC 24 |
| Finished | Sep 24 05:16:25 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437091708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.437091708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_init_fail.867931968 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 2245207383 ps |
| CPU time | 6.51 seconds |
| Started | Sep 24 05:16:04 PM UTC 24 |
| Finished | Sep 24 05:16:12 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867931968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.867931968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_key_req.2005280797 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3635949353 ps |
| CPU time | 25.5 seconds |
| Started | Sep 24 05:16:10 PM UTC 24 |
| Finished | Sep 24 05:16:37 PM UTC 24 |
| Peak memory | 253880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005280797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.2005280797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_esc.4251597269 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 383902502 ps |
| CPU time | 14.17 seconds |
| Started | Sep 24 05:16:04 PM UTC 24 |
| Finished | Sep 24 05:16:20 PM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251597269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.4251597269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_req.767466655 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2279879939 ps |
| CPU time | 21.69 seconds |
| Started | Sep 24 05:16:04 PM UTC 24 |
| Finished | Sep 24 05:16:27 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767466655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.767466655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_regwen.3587740683 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1942047399 ps |
| CPU time | 6.15 seconds |
| Started | Sep 24 05:16:10 PM UTC 24 |
| Finished | Sep 24 05:16:17 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587740683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.3587740683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_smoke.1814386881 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 131985980 ps |
| CPU time | 5.07 seconds |
| Started | Sep 24 05:16:04 PM UTC 24 |
| Finished | Sep 24 05:16:10 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814386881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.1814386881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all.3189230459 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 56629878441 ps |
| CPU time | 144.92 seconds |
| Started | Sep 24 05:16:10 PM UTC 24 |
| Finished | Sep 24 05:18:38 PM UTC 24 |
| Peak memory | 258036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189230459 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.3189230459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_test_access.1723048534 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1448691796 ps |
| CPU time | 27.49 seconds |
| Started | Sep 24 05:16:10 PM UTC 24 |
| Finished | Sep 24 05:16:39 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723048534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.1723048534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/9.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_init_fail.11392233 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 338217107 ps |
| CPU time | 4.45 seconds |
| Started | Sep 24 05:22:22 PM UTC 24 |
| Finished | Sep 24 05:22:28 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11392233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.11392233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/90.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_init_fail.1446275655 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 550543875 ps |
| CPU time | 5.59 seconds |
| Started | Sep 24 05:22:22 PM UTC 24 |
| Finished | Sep 24 05:22:29 PM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446275655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.1446275655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/91.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_parallel_lc_esc.891082828 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 504489267 ps |
| CPU time | 9.55 seconds |
| Started | Sep 24 05:22:22 PM UTC 24 |
| Finished | Sep 24 05:22:33 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891082828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.891082828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/91.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_init_fail.1667689351 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 117339267 ps |
| CPU time | 5.21 seconds |
| Started | Sep 24 05:22:23 PM UTC 24 |
| Finished | Sep 24 05:22:29 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667689351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.1667689351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/92.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_init_fail.161095978 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 207070019 ps |
| CPU time | 5.4 seconds |
| Started | Sep 24 05:22:23 PM UTC 24 |
| Finished | Sep 24 05:22:29 PM UTC 24 |
| Peak memory | 252032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161095978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.161095978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/93.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_parallel_lc_esc.51792155 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 201474739 ps |
| CPU time | 12.2 seconds |
| Started | Sep 24 05:22:23 PM UTC 24 |
| Finished | Sep 24 05:22:36 PM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51792155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.51792155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/93.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_init_fail.1283300572 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 389704523 ps |
| CPU time | 5.88 seconds |
| Started | Sep 24 05:22:23 PM UTC 24 |
| Finished | Sep 24 05:22:30 PM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283300572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.1283300572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/94.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_parallel_lc_esc.2196867530 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 319821538 ps |
| CPU time | 3.32 seconds |
| Started | Sep 24 05:22:26 PM UTC 24 |
| Finished | Sep 24 05:22:30 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196867530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.2196867530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/94.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.1004093829 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2318058987 ps |
| CPU time | 91.63 seconds |
| Started | Sep 24 05:22:26 PM UTC 24 |
| Finished | Sep 24 05:24:00 PM UTC 24 |
| Peak memory | 258128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1004093829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 94.otp_ctrl_stress_all_with_rand_reset.1004093829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_init_fail.3127217936 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 2514662304 ps |
| CPU time | 7.9 seconds |
| Started | Sep 24 05:22:26 PM UTC 24 |
| Finished | Sep 24 05:22:35 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127217936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.3127217936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/95.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_parallel_lc_esc.1226171097 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 3184917317 ps |
| CPU time | 9.32 seconds |
| Started | Sep 24 05:22:26 PM UTC 24 |
| Finished | Sep 24 05:22:37 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226171097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.1226171097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_init_fail.2925297218 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 269118633 ps |
| CPU time | 4.74 seconds |
| Started | Sep 24 05:22:31 PM UTC 24 |
| Finished | Sep 24 05:22:37 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925297218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.2925297218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/96.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_parallel_lc_esc.3325559024 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 3472420589 ps |
| CPU time | 27.8 seconds |
| Started | Sep 24 05:22:31 PM UTC 24 |
| Finished | Sep 24 05:23:01 PM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325559024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.3325559024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/96.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.2417041835 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 1335740324 ps |
| CPU time | 40.3 seconds |
| Started | Sep 24 05:22:31 PM UTC 24 |
| Finished | Sep 24 05:23:13 PM UTC 24 |
| Peak memory | 257876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2417041835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 96.otp_ctrl_stress_all_with_rand_reset.2417041835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/96.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_init_fail.3539954977 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 130861808 ps |
| CPU time | 4.98 seconds |
| Started | Sep 24 05:22:31 PM UTC 24 |
| Finished | Sep 24 05:22:38 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539954977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.3539954977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/97.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_parallel_lc_esc.1144907201 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 173460460 ps |
| CPU time | 6.73 seconds |
| Started | Sep 24 05:22:32 PM UTC 24 |
| Finished | Sep 24 05:22:39 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144907201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.1144907201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/97.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_init_fail.1291282924 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 1857727743 ps |
| CPU time | 7.51 seconds |
| Started | Sep 24 05:22:32 PM UTC 24 |
| Finished | Sep 24 05:22:40 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291282924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.1291282924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/98.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_parallel_lc_esc.3536723132 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 207207591 ps |
| CPU time | 6.14 seconds |
| Started | Sep 24 05:22:32 PM UTC 24 |
| Finished | Sep 24 05:22:39 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536723132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.3536723132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/98.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_init_fail.2973280945 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 108624297 ps |
| CPU time | 5.88 seconds |
| Started | Sep 24 05:22:35 PM UTC 24 |
| Finished | Sep 24 05:22:42 PM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973280945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.2973280945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/99.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_parallel_lc_esc.2124337697 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 262085992 ps |
| CPU time | 10.31 seconds |
| Started | Sep 24 05:22:35 PM UTC 24 |
| Finished | Sep 24 05:22:47 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124337697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.2124337697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/99.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.3592173873 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 11582164708 ps |
| CPU time | 70.24 seconds |
| Started | Sep 24 05:22:36 PM UTC 24 |
| Finished | Sep 24 05:23:48 PM UTC 24 |
| Peak memory | 258160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3592173873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 99.otp_ctrl_stress_all_with_rand_reset.3592173873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/99.otp_ctrl_stress_all_with_rand_reset/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |