Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	44826	1			T4	60		T6	163		T92	69
access_err	48938	1			T4	19		T6	9		T5	25
write_blank_err	329	1			T91	1		T25	1		T26	1
ecc_uncorr_err	53676	1			T91	516		T25	222		T121	221
ecc_corr_err	1238	1			T4	4		T121	10		T125	2
no_err	65763	1			T3	126		T4	43		T6	18

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	552	1			T25	2		T26	2		T27	2
secret2	19655	1			T3	19		T4	13		T6	4
secret1	23580	1			T3	24		T4	10		T6	7
secret0	28401	1			T3	11		T4	2		T6	4
hw_cfg1	28630	1			T3	7		T4	5		T6	2
hw_cfg0	21885	1			T3	10		T4	6		T5	8
rot_creator_auth_state	17623	1			T3	14		T4	5		T6	2
rot_creator_auth_codesign	17476	1			T3	19		T4	11		T6	5
owner_sw_cfg	15621	1			T3	5		T4	7		T5	9
creator_sw_cfg	15967	1			T3	4		T4	1		T6	2
vendor_test	25380	1			T3	13		T4	66		T6	164

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2747	1			T250	172		T242	443		T375	32
fsm_err	secret1	4446	1			T92	69		T197	27		T234	93
fsm_err	secret0	3751	1			T237	121		T272	219		T376	208
fsm_err	hw_cfg1	3139	1			T267	52		T246	372		T377	149
fsm_err	hw_cfg0	6254	1			T378	37		T379	258		T245	221
fsm_err	rot_creator_auth_state	3855	1			T161	36		T107	297		T380	21
fsm_err	rot_creator_auth_codesign	3313	1			T125	29		T153	13		T161	44
fsm_err	owner_sw_cfg	2419	1			T12	195		T161	37		T157	20
fsm_err	creator_sw_cfg	2602	1			T155	59		T227	134		T156	77
fsm_err	vendor_test	12300	1			T4	60		T6	163		T36	130
access_err	life_cycle	552	1			T25	2		T26	2		T27	2
access_err	secret2	8006	1			T4	12		T6	4		T5	2
access_err	secret1	5625	1			T5	3		T15	6		T85	1
access_err	secret0	4591	1			T6	1		T15	10		T92	1
access_err	hw_cfg1	1007	1			T4	1		T6	2		T5	6
access_err	hw_cfg0	2008	1			T5	1		T15	1		T88	3
access_err	rot_creator_auth_state	4167	1			T5	1		T92	3		T25	3
access_err	rot_creator_auth_codesign	6368	1			T4	2		T5	3		T15	4
access_err	owner_sw_cfg	5212	1			T4	3		T5	1		T92	1
access_err	creator_sw_cfg	5924	1			T6	2		T5	5		T15	1
access_err	vendor_test	5478	1			T4	1		T5	3		T15	1
write_blank_err	secret2	10	1			T267	1		T381	1		T382	1
write_blank_err	secret1	16	1			T26	1		T383	1		T384	1
write_blank_err	secret0	38	1			T25	1		T252	1		T385	1
write_blank_err	hw_cfg1	46	1			T91	1		T27	1		T209	1
write_blank_err	hw_cfg0	15	1			T256	1		T372	1		T257	1
write_blank_err	rot_creator_auth_state	129	1			T209	6		T383	3		T110	1
write_blank_err	rot_creator_auth_codesign	31	1			T12	4		T13	1		T267	1
write_blank_err	owner_sw_cfg	17	1			T385	4		T256	1		T205	1
write_blank_err	creator_sw_cfg	7	1			T372	2		T386	1		T387	2
write_blank_err	vendor_test	20	1			T12	2		T257	1		T388	1
ecc_uncorr_err	secret2	4396	1			T153	41		T389	8		T267	135
ecc_uncorr_err	secret1	7673	1			T121	116		T26	428		T389	7
ecc_uncorr_err	secret0	14420	1			T25	222		T153	14		T252	333
ecc_uncorr_err	hw_cfg1	16459	1			T91	516		T121	44		T153	19
ecc_uncorr_err	hw_cfg0	4283	1			T125	32		T154	67		T214	23
ecc_uncorr_err	rot_creator_auth_state	2767	1			T121	61		T153	15		T110	588
ecc_uncorr_err	rot_creator_auth_codesign	1169	1			T253	40		T214	31		T210	51
ecc_uncorr_err	owner_sw_cfg	1045	1			T154	59		T253	32		T389	7
ecc_uncorr_err	creator_sw_cfg	1464	1			T154	61		T389	9		T390	35
ecc_corr_err	secret2	70	1			T116	1		T153	1		T154	1
ecc_corr_err	secret1	134	1			T116	3		T153	2		T154	1
ecc_corr_err	secret0	131	1			T36	2		T116	1		T153	1
ecc_corr_err	hw_cfg1	198	1			T36	3		T116	5		T34	6
ecc_corr_err	hw_cfg0	205	1			T4	2		T121	2		T36	9
ecc_corr_err	rot_creator_auth_state	113	1			T4	1		T121	6		T36	1
ecc_corr_err	rot_creator_auth_codesign	112	1			T36	1		T116	4		T153	1
ecc_corr_err	owner_sw_cfg	159	1			T121	2		T125	2		T253	1
ecc_corr_err	creator_sw_cfg	116	1			T4	1		T116	1		T154	3
no_err	secret2	4426	1			T3	19		T4	1		T5	10
no_err	secret1	5686	1			T3	24		T4	10		T6	7
no_err	secret0	5470	1			T3	11		T4	2		T6	3
no_err	hw_cfg1	7781	1			T3	7		T4	4		T5	4
no_err	hw_cfg0	9120	1			T3	10		T4	4		T5	7
no_err	rot_creator_auth_state	6592	1			T3	14		T4	4		T6	2
no_err	rot_creator_auth_codesign	6483	1			T3	19		T4	9		T6	5
no_err	owner_sw_cfg	6769	1			T3	5		T4	4		T5	8
no_err	creator_sw_cfg	5854	1			T3	4		T5	2		T24	6
no_err	vendor_test	7582	1			T3	13		T4	5		T6	1

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded