Unified Coverage Report :: Group :: dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg

Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	98.53	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv

34 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
status_csr_cg::OtpBusIntegErrorIdx	50.00	1	100	1	64	64
lc_prog_cg	100.00	1	100	1	64	64
otbn_req_cg	100.00	1	100	1	64	64
status_csr_cg::OtpCheckPendingIdx	100.00	1	100	1	64	64
status_csr_cg::OtpCreatorSwCfgErrIdx	100.00	1	100	1	64	64
status_csr_cg::OtpDaiErrIdx	100.00	1	100	1	64	64
status_csr_cg::OtpDaiIdleIdx	100.00	1	100	1	64	64
status_csr_cg::OtpDerivKeyFsmErrIdx	100.00	1	100	1	64	64
status_csr_cg::OtpHwCfg0ErrIdx	100.00	1	100	1	64	64
status_csr_cg::OtpHwCfg1ErrIdx	100.00	1	100	1	64	64
status_csr_cg::OtpLciErrIdx	100.00	1	100	1	64	64
status_csr_cg::OtpLfsrFsmErrIdx	100.00	1	100	1	64	64
status_csr_cg::OtpLifeCycleErrIdx	100.00	1	100	1	64	64
status_csr_cg::OtpOwnerSwCfgErrIdx	100.00	1	100	1	64	64
status_csr_cg::OtpRotCreatorAuthCodesignErrIdx	100.00	1	100	1	64	64
status_csr_cg::OtpRotCreatorAuthStateErrIdx	100.00	1	100	1	64	64
status_csr_cg::OtpScramblingFsmErrIdx	100.00	1	100	1	64	64
status_csr_cg::OtpSecret0ErrIdx	100.00	1	100	1	64	64
status_csr_cg::OtpSecret1ErrIdx	100.00	1	100	1	64	64
status_csr_cg::OtpSecret2ErrIdx	100.00	1	100	1	64	64
status_csr_cg::OtpTimeoutErrIdx	100.00	1	100	1	64	64
status_csr_cg::OtpVendorTestErrIdx	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::addr_not_align_mask	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::addr_not_align_size	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::invalid_a_opcode	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::size_over_max	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::PutFullData_mask_not_match_size	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::addr_not_align_mask	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::addr_not_align_size	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::invalid_a_opcode	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::mask_not_in_enabled_lanes	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::size_over_max	100.00	1	100	1	64	64

---

Group Instance : status_csr_cg::OtpBusIntegErrorIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpBusIntegErrorIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	3	1	50.00

Variables for Group Instance status_csr_cg::OtpBusIntegErrorIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	2	0	0.00	100	0	1	0
cp_value	2	1	1	50.00	100	1	1	2

---

Group Instance : lc_prog_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lc_prog_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance lc_prog_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : otbn_req_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance otbn_req_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance otbn_req_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpCheckPendingIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpCheckPendingIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpCheckPendingIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpCreatorSwCfgErrIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpCreatorSwCfgErrIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpCreatorSwCfgErrIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpDaiErrIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpDaiErrIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpDaiErrIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpDaiIdleIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpDaiIdleIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpDaiIdleIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpDerivKeyFsmErrIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpDerivKeyFsmErrIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpDerivKeyFsmErrIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpHwCfg0ErrIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpHwCfg0ErrIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpHwCfg0ErrIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpHwCfg1ErrIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpHwCfg1ErrIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpHwCfg1ErrIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpLciErrIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpLciErrIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpLciErrIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpLfsrFsmErrIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpLfsrFsmErrIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpLfsrFsmErrIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpLifeCycleErrIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpLifeCycleErrIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpLifeCycleErrIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpOwnerSwCfgErrIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpOwnerSwCfgErrIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpOwnerSwCfgErrIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpRotCreatorAuthCodesignErrIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpRotCreatorAuthCodesignErrIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpRotCreatorAuthCodesignErrIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpRotCreatorAuthStateErrIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpRotCreatorAuthStateErrIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpRotCreatorAuthStateErrIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpScramblingFsmErrIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpScramblingFsmErrIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpScramblingFsmErrIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpSecret0ErrIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpSecret0ErrIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpSecret0ErrIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpSecret1ErrIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpSecret1ErrIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpSecret1ErrIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpSecret2ErrIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpSecret2ErrIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpSecret2ErrIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpTimeoutErrIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpTimeoutErrIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpTimeoutErrIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : status_csr_cg::OtpVendorTestErrIdx

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance status_csr_cg::OtpVendorTestErrIdx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance status_csr_cg::OtpVendorTestErrIdx

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::addr_not_align_mask

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::addr_not_align_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::addr_not_align_mask

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::addr_not_align_size

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::addr_not_align_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::addr_not_align_size

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::invalid_a_opcode

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::invalid_a_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::invalid_a_opcode

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::size_over_max

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::size_over_max

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::size_over_max

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::PutFullData_mask_not_match_size

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::PutFullData_mask_not_match_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::PutFullData_mask_not_match_size

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::addr_not_align_mask

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::addr_not_align_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::addr_not_align_mask

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::addr_not_align_size

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::addr_not_align_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::addr_not_align_size

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::invalid_a_opcode

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::invalid_a_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::invalid_a_opcode

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::mask_not_in_enabled_lanes

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::mask_not_in_enabled_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::mask_not_in_enabled_lanes

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::size_over_max

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::size_over_max

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::size_over_max

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	2	0	0.00

User Defined Bins for cp_transitions

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
falling	0	1	1
rising	0	1	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2128387

1

T2

416

T3

90

T7

391

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

18

1

T134

2

T139

1

T92

1

rising

34

1

T265

1

T134

2

T139

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11284

1

T2

1

T4

9

T6

1

auto[1]

34

1

T265

1

T134

2

T139

1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

36

1

T138

1

T368

1

T287

7

rising

52

1

T24

1

T100

1

T411

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239

1

T24

1

T130

1

T8

1

auto[1]

281

1

T24

2

T20

1

T116

8

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

2701

1

T4

2

T6

1

T10

1

rising

2340

1

T4

1

T10

1

T90

4

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1079734

1

T2

416

T3

90

T7

391

auto[1]

1048653

1

T4

305

T6

905

T10

763

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

1471

1

T12

3

T90

6

T24

1

rising

1928

1

T3

1

T5

1

T12

4

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1676236

1

T2

416

T3

33

T7

391

auto[1]

452151

1

T3

57

T5

341

T12

760

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

18873

1

T4

10

T5

28

T6

1

rising

19401

1

T3

1

T4

11

T5

29

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1840693

1

T2

416

T3

33

T7

391

auto[1]

287694

1

T3

57

T4

32

T5

234

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

70024

1

T2

27

T3

4

T7

63

rising

70073

1

T2

27

T3

3

T7

64

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

899572

1

T2

373

T3

86

T7

252

auto[1]

1228815

1

T2

43

T3

4

T7

139

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

67

1

T13

1

T263

1

T300

1

rising

263

1

T3

1

T125

1

T222

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2051175

1

T2

416

T3

33

T7

391

auto[1]

77212

1

T3

57

T125

260

T222

123

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

431

1

T12

1

T145

1

T146

7

rising

753

1

T3

1

T5

1

T12

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1926665

1

T2

416

T3

33

T7

391

auto[1]

201722

1

T3

57

T5

163

T12

758

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

428

1

T145

1

T146

7

T49

1

rising

751

1

T3

1

T5

1

T125

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1927885

1

T2

416

T3

33

T7

391

auto[1]

200502

1

T3

57

T5

163

T125

260

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

426

1

T145

1

T146

7

T49

1

rising

745

1

T3

1

T5

1

T125

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1922143

1

T2

416

T3

33

T7

391

auto[1]

206244

1

T3

57

T5

163

T125

260

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

67

1

T13

1

T263

1

T300

1

rising

263

1

T3

1

T125

1

T222

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2051175

1

T2

416

T3

33

T7

391

auto[1]

77212

1

T3

57

T125

260

T222

123

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

429

1

T145

1

T146

7

T49

1

rising

752

1

T3

1

T5

1

T125

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1927891

1

T2

416

T3

33

T7

391

auto[1]

200496

1

T3

57

T5

163

T125

260

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

1461

1

T12

2

T90

3

T93

5

rising

1910

1

T3

1

T5

1

T12

3

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1677497

1

T2

416

T3

33

T7

391

auto[1]

450890

1

T3

57

T5

522

T12

691

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

1489

1

T12

3

T90

4

T93

5

rising

1943

1

T3

1

T5

1

T12

4

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1674320

1

T2

416

T3

33

T7

391

auto[1]

454067

1

T3

57

T5

608

T12

815

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

1486

1

T12

2

T90

5

T24

2

rising

1946

1

T3

1

T5

1

T12

3

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1661629

1

T2

416

T3

33

T7

391

auto[1]

466758

1

T3

57

T5

644

T12

922

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

67

1

T13

1

T263

1

T300

1

rising

263

1

T3

1

T125

1

T222

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2051175

1

T2

416

T3

33

T7

391

auto[1]

77212

1

T3

57

T125

260

T222

123

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

428

1

T145

1

T146

7

T49

1

rising

750

1

T3

1

T5

1

T125

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1927997

1

T2

416

T3

33

T7

391

auto[1]

200390

1

T3

57

T5

163

T125

260

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

430

1

T145

1

T146

7

T49

1

rising

753

1

T3

1

T5

1

T125

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1927575

1

T2

416

T3

33

T7

391

auto[1]

200812

1

T3

57

T5

163

T125

260

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

430

1

T145

1

T146

7

T49

1

rising

755

1

T3

1

T5

1

T125

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1926317

1

T2

416

T3

33

T7

391

auto[1]

202070

1

T3

57

T5

163

T125

260

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

64

1

T100

4

T35

3

T76

1

rising

73

1

T49

1

T50

1

T100

4

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2125792

1

T2

416

T3

90

T7

391

auto[1]

2595

1

T49

38

T50

11

T100

252

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

1455

1

T12

2

T90

2

T24

1

rising

1904

1

T3

1

T5

1

T12

2

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1675139

1

T2

416

T3

33

T7

391

auto[1]

453248

1

T3

57

T5

276

T12

624

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

160767

1

T13

1355

T14

1878

T15

744

rising

160754

1

T13

1355

T14

1879

T15

744

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

621282

1

T13

4682

T14

7084

T15

2933

auto[1]

218315

1

T13

1896

T14

2650

T15

1007

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

190977

1

T13

1417

T14

2169

T15

883

rising

190985

1

T13

1416

T14

2168

T15

883

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

543478

1

T13

4483

T14

6476

T15

2559

auto[1]

296119

1

T13

2095

T14

3258

T15

1381

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

190977

1

T13

1417

T14

2169

T15

883

rising

190985

1

T13

1416

T14

2168

T15

883

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

543478

1

T13

4483

T14

6476

T15

2559

auto[1]

296119

1

T13

2095

T14

3258

T15

1381

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

193562

1

T13

1401

T14

2060

T15

912

rising

193555

1

T13

1401

T14

2060

T15

912

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

528933

1

T13

4415

T14

6483

T15

2468

auto[1]

310664

1

T13

2163

T14

3251

T15

1472

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

181217

1

T13

1410

T14

2114

T15

846

rising

181221

1

T13

1411

T14

2114

T15

845

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

573749

1

T13

4483

T14

6589

T15

2714

auto[1]

265848

1

T13

2095

T14

3145

T15

1226

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

162295

1

T13

1290

T14

1875

T15

739

rising

162301

1

T13

1290

T14

1875

T15

739

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

619610

1

T13

4831

T14

7183

T15

2907

auto[1]

219987

1

T13

1747

T14

2551

T15

1033

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

60910

1

T13

675

T14

651

T15

340

rising

60899

1

T13

675

T14

651

T15

340

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

354250

1

T13

3600

T14

3520

T15

1852

auto[1]

76779

1

T13

849

T14

818

T15

425

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

87529

1

T13

900

T14

888

T15

441

rising

87527

1

T13

899

T14

888

T15

441

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

307779

1

T13

3165

T14

3055

T15

1641

auto[1]

123250

1

T13

1284

T14

1283

T15

636

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

87529

1

T13

900

T14

888

T15

441

rising

87527

1

T13

899

T14

888

T15

441

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

307779

1

T13

3165

T14

3055

T15

1641

auto[1]

123250

1

T13

1284

T14

1283

T15

636

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

90593

1

T13

909

T14

899

T15

485

rising

90612

1

T13

910

T14

900

T15

485

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

296264

1

T13

3155

T14

3027

T15

1540

auto[1]

134765

1

T13

1294

T14

1311

T15

737

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

76613

1

T13

784

T14

743

T15

411

rising

76614

1

T13

784

T14

744

T15

411

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

328689

1

T13

3403

T14

3340

T15

1705

auto[1]

102340

1

T13

1046

T14

998

T15

572

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

72510

1

T13

732

T14

748

T15

393

rising

72503

1

T13

732

T14

748

T15

393

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

338314

1

T13

3504

T14

3388

T15

1772

auto[1]

92715

1

T13

945

T14

950

T15

505