Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4737727	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2539736

1

T1

4

T2

380

T3

457

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6164069	1			T1	4		T2	1091		T3	850
values[0x0]	524977	1			T1	8		T2	47		T3	68
values[0x1]	588417	1			T1	7		T2	52		T3	66

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3477121	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3800342

1

T1

7

T2

584

T3

580

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	35012	1			T7	6		T4	5		T5	16
valid_sources[0x01]	29045	1			T2	9		T3	5		T7	1
valid_sources[0x02]	28232	1			T2	1		T3	1		T7	4
valid_sources[0x03]	23143	1			T2	3		T7	5		T4	13
valid_sources[0x04]	25415	1			T2	1		T7	1		T4	19
valid_sources[0x05]	21050	1			T2	9		T7	1		T4	9
valid_sources[0x06]	97856	1			T2	3		T3	2		T7	4
valid_sources[0x07]	23083	1			T1	1		T2	3		T7	5
valid_sources[0x08]	21965	1			T2	2		T3	5		T7	8
valid_sources[0x09]	36955	1			T2	9		T7	4		T4	8
valid_sources[0x0a]	20667	1			T2	2		T7	2		T4	6
valid_sources[0x0b]	20064	1			T2	5		T7	5		T4	13
valid_sources[0x0c]	25038	1			T2	3		T7	4		T4	14
valid_sources[0x0d]	20759	1			T2	5		T3	8		T7	2
valid_sources[0x0e]	20099	1			T2	3		T7	3		T4	11
valid_sources[0x0f]	19944	1			T2	5		T7	2		T4	14
valid_sources[0x10]	31117	1			T2	3		T3	14		T7	6
valid_sources[0x11]	25754	1			T2	5		T7	2		T4	14
valid_sources[0x12]	30312	1			T2	2		T3	4		T7	1
valid_sources[0x13]	21180	1			T2	3		T3	4		T7	3
valid_sources[0x14]	19762	1			T2	4		T7	7		T4	7
valid_sources[0x15]	21180	1			T1	2		T2	9		T3	18
valid_sources[0x16]	26376	1			T2	3		T7	5		T4	11
valid_sources[0x17]	21839	1			T2	6		T7	4		T4	8
valid_sources[0x18]	20162	1			T2	3		T3	8		T7	2
valid_sources[0x19]	20366	1			T2	5		T3	1		T7	2
valid_sources[0x1a]	21904	1			T2	1		T7	1		T4	12
valid_sources[0x1b]	19539	1			T2	3		T3	11		T7	2
valid_sources[0x1c]	20909	1			T2	6		T7	3		T4	8
valid_sources[0x1d]	20330	1			T2	1		T3	7		T7	6
valid_sources[0x1e]	41978	1			T2	6		T3	11		T7	5
valid_sources[0x1f]	20600	1			T2	4		T3	13		T7	1
valid_sources[0x20]	30463	1			T2	5		T3	8		T7	4
valid_sources[0x21]	37829	1			T2	3		T7	8		T4	10
valid_sources[0x22]	21745	1			T2	4		T7	4		T4	13
valid_sources[0x23]	19484	1			T2	3		T3	9		T7	3
valid_sources[0x24]	32878	1			T2	5		T7	6		T4	18
valid_sources[0x25]	32011	1			T2	1		T7	4		T4	12
valid_sources[0x26]	20776	1			T2	6		T3	26		T7	8
valid_sources[0x27]	21804	1			T2	3		T7	4		T4	10
valid_sources[0x28]	20133	1			T2	4		T7	2		T4	11
valid_sources[0x29]	25995	1			T2	5		T7	3		T4	9
valid_sources[0x2a]	26303	1			T2	5		T3	1		T7	3
valid_sources[0x2b]	23304	1			T2	6		T3	2		T7	9
valid_sources[0x2c]	19873	1			T2	3		T3	3		T4	13
valid_sources[0x2d]	21234	1			T1	2		T2	3		T3	14
valid_sources[0x2e]	20807	1			T2	10		T3	9		T7	4
valid_sources[0x2f]	38925	1			T2	4		T4	7		T5	23
valid_sources[0x30]	22770	1			T2	1		T7	6		T4	14
valid_sources[0x31]	30144	1			T2	7		T3	5		T7	2
valid_sources[0x32]	31725	1			T2	5		T3	13		T7	3
valid_sources[0x33]	21169	1			T2	4		T3	13		T7	2
valid_sources[0x34]	19594	1			T2	3		T3	9		T7	7
valid_sources[0x35]	24873	1			T2	3		T4	6		T5	21
valid_sources[0x36]	23926	1			T2	1		T3	4		T7	3
valid_sources[0x37]	35195	1			T2	4		T7	3		T4	10
valid_sources[0x38]	34571	1			T2	3		T7	6		T4	4
valid_sources[0x39]	28789	1			T2	8		T7	3		T4	11
valid_sources[0x3a]	20133	1			T1	3		T2	6		T7	2
valid_sources[0x3b]	25172	1			T2	8		T7	4		T4	6
valid_sources[0x3c]	29604	1			T2	10		T7	2		T4	7
valid_sources[0x3d]	20360	1			T2	9		T3	1		T7	2
valid_sources[0x3e]	107153	1			T2	3		T7	3		T4	9
valid_sources[0x3f]	104150	1			T2	3		T7	3		T4	21
valid_sources[0x40]	21084	1			T2	3		T7	1		T4	14
valid_sources[0x41]	21221	1			T2	4		T7	3		T4	8
valid_sources[0x42]	20373	1			T2	1		T3	2		T7	3
valid_sources[0x43]	19529	1			T2	3		T3	2		T7	6
valid_sources[0x44]	21329	1			T2	2		T7	2		T4	8
valid_sources[0x45]	19076	1			T2	12		T7	6		T4	9
valid_sources[0x46]	29159	1			T2	3		T3	7		T7	3
valid_sources[0x47]	22440	1			T2	4		T7	3		T4	7
valid_sources[0x48]	22863	1			T2	1		T7	4		T4	16
valid_sources[0x49]	24155	1			T1	1		T2	1		T7	6
valid_sources[0x4a]	32064	1			T2	4		T3	16		T7	4
valid_sources[0x4b]	30802	1			T7	3		T4	14		T5	15
valid_sources[0x4c]	32903	1			T2	1		T7	7		T4	11
valid_sources[0x4d]	32862	1			T2	7		T4	8		T5	19
valid_sources[0x4e]	21520	1			T2	4		T3	9		T7	3
valid_sources[0x4f]	20815	1			T2	7		T3	1		T7	3
valid_sources[0x50]	26424	1			T1	2		T2	1		T7	1
valid_sources[0x51]	19758	1			T2	9		T3	6		T7	9
valid_sources[0x52]	23102	1			T2	9		T3	20		T7	3
valid_sources[0x53]	22122	1			T2	5		T3	8		T7	4
valid_sources[0x54]	22599	1			T1	1		T2	3		T3	5
valid_sources[0x55]	21237	1			T2	3		T3	5		T7	3
valid_sources[0x56]	21279	1			T2	1		T7	5		T4	14
valid_sources[0x57]	22873	1			T2	12		T7	1		T4	9
valid_sources[0x58]	26377	1			T2	2		T3	25		T7	1
valid_sources[0x59]	24258	1			T2	5		T3	14		T7	1
valid_sources[0x5a]	20793	1			T2	1		T3	3		T7	3
valid_sources[0x5b]	23220	1			T2	6		T3	3		T7	2
valid_sources[0x5c]	20073	1			T2	5		T3	16		T7	3
valid_sources[0x5d]	22869	1			T2	8		T4	8		T5	24
valid_sources[0x5e]	24058	1			T2	7		T7	7		T4	8
valid_sources[0x5f]	25421	1			T2	5		T7	4		T4	10
valid_sources[0x60]	21781	1			T2	8		T3	2		T7	6
valid_sources[0x61]	100959	1			T2	3		T7	2		T4	5
valid_sources[0x62]	20072	1			T2	5		T3	4		T7	3
valid_sources[0x63]	33579	1			T2	9		T3	26		T7	6
valid_sources[0x64]	25727	1			T2	9		T7	3		T4	7
valid_sources[0x65]	29221	1			T2	3		T7	3		T4	10
valid_sources[0x66]	27013	1			T2	8		T3	11		T7	2
valid_sources[0x67]	19672	1			T2	5		T3	11		T7	4
valid_sources[0x68]	23262	1			T2	3		T7	4		T4	6
valid_sources[0x69]	23245	1			T2	2		T3	3		T7	4
valid_sources[0x6a]	24633	1			T2	1		T3	3		T7	5
valid_sources[0x6b]	20311	1			T2	1		T7	3		T4	15
valid_sources[0x6c]	21444	1			T2	4		T3	24		T7	2
valid_sources[0x6d]	20876	1			T2	8		T7	3		T4	4
valid_sources[0x6e]	23487	1			T2	3		T3	9		T7	2
valid_sources[0x6f]	20816	1			T2	2		T3	3		T7	2
valid_sources[0x70]	20571	1			T2	10		T7	5		T4	8
valid_sources[0x71]	35307	1			T2	4		T7	5		T4	14
valid_sources[0x72]	27205	1			T2	9		T3	2		T7	2
valid_sources[0x73]	68904	1			T2	8		T3	4		T7	3
valid_sources[0x74]	29055	1			T2	9		T7	2		T4	7
valid_sources[0x75]	22299	1			T2	2		T7	4		T4	16
valid_sources[0x76]	19995	1			T2	4		T7	5		T4	10
valid_sources[0x77]	20470	1			T2	4		T3	30		T7	6
valid_sources[0x78]	20156	1			T2	3		T3	3		T7	2
valid_sources[0x79]	32843	1			T2	5		T7	5		T4	11
valid_sources[0x7a]	67692	1			T2	7		T7	3		T4	11
valid_sources[0x7b]	24180	1			T2	4		T3	1		T7	4
valid_sources[0x7c]	19735	1			T1	1		T2	6		T7	3
valid_sources[0x7d]	28101	1			T2	1		T3	2		T7	3
valid_sources[0x7e]	25657	1			T2	3		T7	3		T4	4
valid_sources[0x7f]	20063	1			T1	1		T2	6		T3	4
valid_sources[0x80]	19429	1			T2	3		T3	7		T7	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2018417

1

T2

341

T3

397

T7

131

values[0x0]

all_enables

biggest_size

293166

1

T1

3

T2

26

T3

32

values[0x1]

all_enables

biggest_size

228153

1

T1

1

T2

13

T3

28

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25842	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

522766

1

T2

20

T3

100

T4

100

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	176145	1			T2	10		T3	50		T4	50
values[0x0]	181570	1			T2	7		T3	24		T4	24
values[0x1]	190893	1			T2	3		T3	26		T4	26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14181	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

534427

1

T2

20

T3

100

T4

100

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1963	1			T18	1		T130	1		T118	1
valid_sources[0x01]	2131	1			T130	1		T8	5		T233	1
valid_sources[0x02]	2154	1			T23	2		T97	3		T49	2
valid_sources[0x03]	2179	1			T12	2		T90	3		T124	2
valid_sources[0x04]	2412	1			T4	2		T90	1		T125	2
valid_sources[0x05]	1818	1			T118	1		T128	1		T266	1
valid_sources[0x06]	1929	1			T4	1		T12	3		T124	1
valid_sources[0x07]	1940	1			T90	3		T124	2		T97	3
valid_sources[0x08]	2073	1			T125	9		T97	1		T94	1
valid_sources[0x09]	2415	1			T3	2		T146	10		T49	2
valid_sources[0x0a]	2470	1			T146	15		T266	1		T119	2
valid_sources[0x0b]	2485	1			T50	1		T9	1		T119	2
valid_sources[0x0c]	1799	1			T4	1		T146	8		T18	1
valid_sources[0x0d]	2320	1			T173	1		T177	1		T167	1
valid_sources[0x0e]	2217	1			T3	1		T4	1		T90	2
valid_sources[0x0f]	2926	1			T128	1		T266	1		T196	1
valid_sources[0x10]	2216	1			T3	1		T4	1		T12	1
valid_sources[0x11]	1944	1			T4	1		T10	1		T124	1
valid_sources[0x12]	2117	1			T3	1		T94	2		T19	2
valid_sources[0x13]	2129	1			T4	3		T12	2		T130	1
valid_sources[0x14]	1927	1			T90	3		T128	5		T266	1
valid_sources[0x15]	2051	1			T124	1		T125	9		T130	1
valid_sources[0x16]	2206	1			T4	1		T125	10		T173	1
valid_sources[0x17]	2668	1			T49	1		T94	1		T266	1
valid_sources[0x18]	2148	1			T18	1		T94	2		T233	1
valid_sources[0x19]	2174	1			T10	1		T18	1		T50	1
valid_sources[0x1a]	2297	1			T49	1		T50	1		T233	1
valid_sources[0x1b]	1661	1			T4	1		T97	1		T50	1
valid_sources[0x1c]	2053	1			T4	1		T145	5		T130	1
valid_sources[0x1d]	2160	1			T97	5		T266	1		T117	1
valid_sources[0x1e]	1947	1			T119	1		T176	2		T177	3
valid_sources[0x1f]	1980	1			T4	1		T124	1		T97	3
valid_sources[0x20]	2696	1			T10	2		T90	2		T146	6
valid_sources[0x21]	1980	1			T4	1		T10	1		T124	2
valid_sources[0x22]	2398	1			T3	1		T23	1		T125	23
valid_sources[0x23]	2259	1			T4	1		T90	6		T49	1
valid_sources[0x24]	2014	1			T4	3		T125	8		T94	3
valid_sources[0x25]	1834	1			T130	1		T49	1		T266	1
valid_sources[0x26]	1934	1			T97	3		T240	2		T122	58
valid_sources[0x27]	2679	1			T125	7		T127	48		T266	2
valid_sources[0x28]	2055	1			T10	1		T97	2		T126	6
valid_sources[0x29]	1967	1			T130	1		T94	1		T9	1
valid_sources[0x2a]	2162	1			T10	1		T90	4		T97	1
valid_sources[0x2b]	1942	1			T146	28		T19	4		T266	1
valid_sources[0x2c]	2518	1			T125	4		T97	2		T130	1
valid_sources[0x2d]	2121	1			T124	1		T18	1		T94	5
valid_sources[0x2e]	2030	1			T4	1		T12	2		T97	3
valid_sources[0x2f]	1832	1			T49	1		T121	1		T113	5
valid_sources[0x30]	2173	1			T10	1		T126	4		T266	1
valid_sources[0x31]	1812	1			T90	3		T233	1		T196	3
valid_sources[0x32]	2477	1			T4	3		T50	1		T173	1
valid_sources[0x33]	2315	1			T97	8		T130	1		T174	2
valid_sources[0x34]	2445	1			T90	4		T49	1		T266	1
valid_sources[0x35]	1804	1			T49	1		T119	2		T116	1
valid_sources[0x36]	2240	1			T4	1		T130	1		T50	1
valid_sources[0x37]	2127	1			T125	3		T49	1		T176	1
valid_sources[0x38]	1816	1			T146	3		T128	6		T266	1
valid_sources[0x39]	2042	1			T23	2		T128	4		T119	1
valid_sources[0x3a]	2095	1			T125	4		T146	4		T50	1
valid_sources[0x3b]	1885	1			T4	1		T49	1		T113	1
valid_sources[0x3c]	2045	1			T3	3		T130	1		T266	1
valid_sources[0x3d]	2191	1			T90	3		T146	16		T18	1
valid_sources[0x3e]	1863	1			T18	1		T130	1		T49	1
valid_sources[0x3f]	2591	1			T4	2		T18	1		T130	1
valid_sources[0x40]	2514	1			T118	2		T234	1		T19	2
valid_sources[0x41]	2000	1			T10	1		T23	1		T49	1
valid_sources[0x42]	1862	1			T125	1		T130	1		T49	1
valid_sources[0x43]	2186	1			T4	2		T12	7		T126	3
valid_sources[0x44]	1978	1			T173	2		T94	1		T128	6
valid_sources[0x45]	1756	1			T118	1		T174	5		T119	1
valid_sources[0x46]	3871	1			T4	1		T90	1		T23	1
valid_sources[0x47]	2011	1			T50	1		T94	1		T175	1
valid_sources[0x48]	2499	1			T10	1		T49	2		T94	1
valid_sources[0x49]	1787	1			T18	1		T94	2		T234	2
valid_sources[0x4a]	2060	1			T146	3		T130	1		T196	1
valid_sources[0x4b]	1833	1			T125	7		T49	1		T94	1
valid_sources[0x4c]	2038	1			T4	1		T90	4		T146	3
valid_sources[0x4d]	2562	1			T5	20		T10	1		T125	1
valid_sources[0x4e]	2214	1			T4	1		T266	2		T113	1
valid_sources[0x4f]	2548	1			T4	1		T125	1		T97	2
valid_sources[0x50]	2044	1			T124	1		T125	2		T266	1
valid_sources[0x51]	2036	1			T12	1		T97	1		T49	2
valid_sources[0x52]	2140	1			T23	1		T50	1		T118	2
valid_sources[0x53]	1916	1			T130	1		T118	3		T119	1
valid_sources[0x54]	1986	1			T146	3		T49	1		T223	40
valid_sources[0x55]	1864	1			T4	1		T12	1		T23	1
valid_sources[0x56]	2430	1			T125	6		T173	2		T176	1
valid_sources[0x57]	2268	1			T124	1		T50	1		T299	1
valid_sources[0x58]	2842	1			T125	7		T50	1		T94	1
valid_sources[0x59]	2043	1			T3	5		T94	2		T128	2
valid_sources[0x5a]	2080	1			T124	1		T18	3		T49	1
valid_sources[0x5b]	1918	1			T3	9		T90	3		T124	2
valid_sources[0x5c]	2298	1			T128	2		T119	2		T117	1
valid_sources[0x5d]	2461	1			T146	2		T8	2		T173	2
valid_sources[0x5e]	1896	1			T97	2		T119	1		T196	1
valid_sources[0x5f]	2093	1			T124	1		T97	6		T49	1
valid_sources[0x60]	2106	1			T90	4		T125	2		T49	3
valid_sources[0x61]	2121	1			T49	1		T173	2		T266	1
valid_sources[0x62]	2142	1			T4	1		T173	1		T233	1
valid_sources[0x63]	2087	1			T124	2		T49	1		T266	4
valid_sources[0x64]	2615	1			T4	2		T90	4		T49	1
valid_sources[0x65]	2288	1			T4	1		T23	1		T50	1
valid_sources[0x66]	1820	1			T4	2		T90	1		T97	1
valid_sources[0x67]	1965	1			T10	1		T94	1		T233	1
valid_sources[0x68]	1988	1			T146	7		T18	1		T266	3
valid_sources[0x69]	2251	1			T3	4		T4	4		T113	1
valid_sources[0x6a]	1997	1			T90	1		T124	1		T94	1
valid_sources[0x6b]	2017	1			T90	1		T124	1		T125	4
valid_sources[0x6c]	2045	1			T4	1		T90	9		T23	1
valid_sources[0x6d]	2132	1			T90	1		T124	2		T240	1
valid_sources[0x6e]	2006	1			T90	1		T125	8		T94	1
valid_sources[0x6f]	2004	1			T6	7		T23	1		T97	7
valid_sources[0x70]	2028	1			T3	1		T90	1		T130	2
valid_sources[0x71]	2153	1			T10	4		T124	1		T146	1
valid_sources[0x72]	2103	1			T4	1		T145	4		T94	1
valid_sources[0x73]	1900	1			T130	1		T50	1		T119	6
valid_sources[0x74]	1927	1			T10	2		T90	1		T23	1
valid_sources[0x75]	2054	1			T49	1		T118	2		T94	2
valid_sources[0x76]	2186	1			T124	1		T49	2		T174	1
valid_sources[0x77]	2246	1			T23	3		T124	1		T222	2
valid_sources[0x78]	2056	1			T12	7		T90	4		T222	1
valid_sources[0x79]	1942	1			T3	6		T4	1		T23	1
valid_sources[0x7a]	1901	1			T18	1		T49	2		T175	1
valid_sources[0x7b]	2142	1			T4	1		T10	1		T124	3
valid_sources[0x7c]	2134	1			T97	2		T50	1		T118	3
valid_sources[0x7d]	1786	1			T145	4		T266	1		T196	4
valid_sources[0x7e]	1810	1			T10	1		T97	4		T49	1
valid_sources[0x7f]	3301	1			T4	2		T18	1		T50	1
valid_sources[0x80]	1998	1			T3	4		T4	4		T10	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

163070

1

T2

10

T3

50

T4

50

values[0x0]

all_enables

biggest_size

180162

1

T2

7

T3

24

T4

24

values[0x1]

all_enables

biggest_size

179534

1

T2

3

T3

26

T4

26