Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5529605

1

T1

15

T2

810

T3

527

full_word

2587455

1

T1

4

T2

380

T3

457

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8116760	1			T1	19		T2	1190		T3	984
auto[TlIntgErrCmd]	108	1			T303	6		T304	4		T305	6
auto[TlIntgErrData]	89	1			T303	2		T304	1		T305	6
auto[TlIntgErrBoth]	103	1			T303	2		T304	5		T305	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6222107

1

T1

4

T2

1091

T3

850

auto[1]

1894953

1

T1

15

T2

99

T3

134

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	4197746	1			T1	4		T2	750		T3	453
auto[TlIntgErrNone]	partial	auto[1]	1331587	1			T1	11		T2	60		T3	74
auto[TlIntgErrNone]	full_word	auto[0]	2024226	1			T2	341		T3	397		T7	131
auto[TlIntgErrNone]	full_word	auto[1]	563201	1			T1	4		T2	39		T3	60
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T303	3		T304	3		T305	4
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T303	3		T304	1		T305	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T387	1		T394	1		T396	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T397	1		T388	2		T389	2
auto[TlIntgErrData]	partial	auto[0]	41	1			T303	2		T304	1		T305	3
auto[TlIntgErrData]	partial	auto[1]	37	1			T305	2		T386	2		T387	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T386	1		T390	1		T394	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T305	1		T398	3		T392	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T304	3		T305	2		T386	2
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T303	2		T304	2		T305	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T386	1		T399	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T305	1		T400	1		T389	2