Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.02	94.16	95.24	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	89417027	363176	0	0
check_regwen_rd_A	89417027	1229	0	0
check_timeout_rd_A	89417027	750	0	0
check_trigger_regwen_rd_A	89417027	1309	0	0
consistency_check_period_rd_A	89417027	1213	0	0
creator_sw_cfg_read_lock_rd_A	89417027	749	0	0
direct_access_address_rd_A	89417027	548	0	0
direct_access_wdata_0_rd_A	89417027	57	0	0
direct_access_wdata_1_rd_A	89417027	91	0	0
integrity_check_period_rd_A	89417027	1355	0	0
intr_enable_rd_A	89417027	2216	0	0
owner_sw_cfg_read_lock_rd_A	89417027	743	0	0
rot_creator_auth_codesign_read_lock_rd_A	89417027	722	0	0
rot_creator_auth_state_read_lock_rd_A	89417027	648	0	0
vendor_test_read_lock_rd_A	89417027	748	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89417027	363176	0	0
T13	178747	3081	0	0
T14	0	3844	0	0
T15	0	1638	0	0
T21	0	3032	0	0
T25	0	5098	0	0
T61	10502	0	0	0
T88	0	6996	0	0
T89	0	8076	0	0
T91	0	12307	0	0
T92	0	5624	0	0
T169	0	4680	0	0
T184	67076	0	0	0
T263	51041	0	0	0
T264	49934	0	0	0
T267	31732	0	0	0
T318	66613	0	0	0
T319	40065	0	0	0
T320	73089	0	0	0
T321	107942	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89417027	1229	0	0
T13	178747	22	0	0
T21	0	15	0	0
T61	10502	0	0	0
T169	0	28	0	0
T184	67076	0	0	0
T263	51041	0	0	0
T264	49934	0	0	0
T267	31732	0	0	0
T279	0	10	0	0
T318	66613	0	0	0
T319	40065	0	0	0
T320	73089	0	0	0
T321	107942	0	0	0
T359	0	32	0	0
T360	0	24	0	0
T361	0	26	0	0
T362	0	30	0	0
T363	0	13	0	0
T364	0	31	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89417027	750	0	0
T13	178747	23	0	0
T61	10502	0	0	0
T169	0	9	0	0
T184	67076	0	0	0
T263	51041	0	0	0
T264	49934	0	0	0
T267	31732	0	0	0
T279	0	26	0	0
T318	66613	0	0	0
T319	40065	0	0	0
T320	73089	0	0	0
T321	107942	0	0	0
T359	0	28	0	0
T360	0	26	0	0
T361	0	44	0	0
T362	0	18	0	0
T363	0	24	0	0
T364	0	22	0	0
T365	0	35	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89417027	1309	0	0
T13	178747	30	0	0
T21	0	17	0	0
T61	10502	0	0	0
T169	0	22	0	0
T184	67076	0	0	0
T263	51041	0	0	0
T264	49934	0	0	0
T267	31732	0	0	0
T318	66613	0	0	0
T319	40065	0	0	0
T320	73089	0	0	0
T321	107942	0	0	0
T359	0	28	0	0
T360	0	13	0	0
T361	0	12	0	0
T362	0	22	0	0
T363	0	23	0	0
T364	0	21	0	0
T365	0	44	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89417027	1213	0	0
T13	178747	25	0	0
T21	0	2	0	0
T61	10502	0	0	0
T169	0	19	0	0
T184	67076	0	0	0
T263	51041	0	0	0
T264	49934	0	0	0
T267	31732	0	0	0
T279	0	13	0	0
T318	66613	0	0	0
T319	40065	0	0	0
T320	73089	0	0	0
T321	107942	0	0	0
T359	0	14	0	0
T360	0	30	0	0
T361	0	20	0	0
T362	0	25	0	0
T363	0	38	0	0
T364	0	9	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89417027	749	0	0
T13	178747	9	0	0
T21	0	9	0	0
T61	10502	0	0	0
T169	0	21	0	0
T184	67076	0	0	0
T263	51041	0	0	0
T264	49934	0	0	0
T267	31732	0	0	0
T279	0	2	0	0
T318	66613	0	0	0
T319	40065	0	0	0
T320	73089	0	0	0
T321	107942	0	0	0
T359	0	17	0	0
T360	0	20	0	0
T361	0	31	0	0
T362	0	39	0	0
T363	0	29	0	0
T364	0	33	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89417027	548	0	0
T13	178747	15	0	0
T21	0	5	0	0
T61	10502	0	0	0
T169	0	36	0	0
T184	67076	0	0	0
T263	51041	0	0	0
T264	49934	0	0	0
T267	31732	0	0	0
T279	0	4	0	0
T318	66613	0	0	0
T319	40065	0	0	0
T320	73089	0	0	0
T321	107942	0	0	0
T359	0	20	0	0
T360	0	28	0	0
T361	0	33	0	0
T362	0	30	0	0
T363	0	24	0	0
T364	0	24	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89417027	57	0	0
T13	178747	9	0	0
T61	10502	0	0	0
T169	0	11	0	0
T184	67076	0	0	0
T215	0	2	0	0
T263	51041	0	0	0
T264	49934	0	0	0
T267	31732	0	0	0
T279	0	4	0	0
T318	66613	0	0	0
T319	40065	0	0	0
T320	73089	0	0	0
T321	107942	0	0	0
T359	0	1	0	0
T360	0	15	0	0
T363	0	3	0	0
T365	0	3	0	0
T366	0	4	0	0
T367	0	3	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89417027	91	0	0
T13	178747	1	0	0
T21	0	5	0	0
T61	10502	0	0	0
T169	0	4	0	0
T184	67076	0	0	0
T263	51041	0	0	0
T264	49934	0	0	0
T267	31732	0	0	0
T279	0	2	0	0
T318	66613	0	0	0
T319	40065	0	0	0
T320	73089	0	0	0
T321	107942	0	0	0
T360	0	3	0	0
T362	0	1	0	0
T363	0	18	0	0
T364	0	2	0	0
T365	0	9	0	0
T366	0	10	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89417027	1355	0	0
T13	178747	21	0	0
T21	0	20	0	0
T61	10502	0	0	0
T169	0	29	0	0
T184	67076	0	0	0
T263	51041	0	0	0
T264	49934	0	0	0
T267	31732	0	0	0
T279	0	6	0	0
T318	66613	0	0	0
T319	40065	0	0	0
T320	73089	0	0	0
T321	107942	0	0	0
T359	0	27	0	0
T360	0	38	0	0
T361	0	16	0	0
T362	0	19	0	0
T363	0	19	0	0
T364	0	19	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89417027	2216	0	0
T13	178747	19	0	0
T21	0	23	0	0
T61	10502	0	0	0
T169	0	25	0	0
T184	67076	0	0	0
T263	51041	0	0	0
T264	49934	0	0	0
T267	31732	0	0	0
T318	66613	0	0	0
T319	40065	0	0	0
T320	73089	0	0	0
T321	107942	0	0	0
T359	0	52	0	0
T360	0	48	0	0
T361	0	32	0	0
T362	0	32	0	0
T368	0	16	0	0
T369	0	38	0	0
T370	0	3	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89417027	743	0	0
T13	178747	13	0	0
T21	0	9	0	0
T61	10502	0	0	0
T169	0	23	0	0
T184	67076	0	0	0
T263	51041	0	0	0
T264	49934	0	0	0
T267	31732	0	0	0
T279	0	3	0	0
T318	66613	0	0	0
T319	40065	0	0	0
T320	73089	0	0	0
T321	107942	0	0	0
T359	0	17	0	0
T360	0	32	0	0
T361	0	39	0	0
T362	0	27	0	0
T363	0	28	0	0
T364	0	19	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89417027	722	0	0
T13	178747	13	0	0
T21	0	25	0	0
T61	10502	0	0	0
T169	0	38	0	0
T184	67076	0	0	0
T263	51041	0	0	0
T264	49934	0	0	0
T267	31732	0	0	0
T279	0	13	0	0
T318	66613	0	0	0
T319	40065	0	0	0
T320	73089	0	0	0
T321	107942	0	0	0
T359	0	9	0	0
T360	0	32	0	0
T361	0	25	0	0
T362	0	26	0	0
T363	0	22	0	0
T364	0	16	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89417027	648	0	0
T13	178747	20	0	0
T21	0	16	0	0
T61	10502	0	0	0
T169	0	7	0	0
T184	67076	0	0	0
T263	51041	0	0	0
T264	49934	0	0	0
T267	31732	0	0	0
T279	0	8	0	0
T318	66613	0	0	0
T319	40065	0	0	0
T320	73089	0	0	0
T321	107942	0	0	0
T359	0	15	0	0
T360	0	23	0	0
T361	0	28	0	0
T362	0	30	0	0
T363	0	22	0	0
T364	0	16	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89417027	748	0	0
T13	178747	31	0	0
T21	0	21	0	0
T61	10502	0	0	0
T169	0	28	0	0
T184	67076	0	0	0
T263	51041	0	0	0
T264	49934	0	0	0
T267	31732	0	0	0
T279	0	6	0	0
T318	66613	0	0	0
T319	40065	0	0	0
T320	73089	0	0	0
T321	107942	0	0	0
T359	0	27	0	0
T360	0	40	0	0
T361	0	31	0	0
T362	0	12	0	0
T363	0	20	0	0
T364	0	23	0	0