Line Coverage for Instance : tb.dut.u_edn_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 26 | 24 | 92.31 |
| CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 0 | 0 | |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| ALWAYS | 191 | 3 | 3 | 100.00 |
61 logic unused_req_chk;
62 1/1 assign unused_req_chk = req_chk_i;
Tests: T1 T2 T3
63
64 `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
65
66 // this case is basically just a bypass
67 if (N == 1) begin : gen_degenerate_case
68
69 assign valid_o = req_i[0];
70 assign data_o = data_i[0];
71 assign gnt_o[0] = valid_o & ready_i;
72 assign idx_o = '0;
73
74 end else begin : gen_normal_case
75
76 // align to powers of 2 for simplicity
77 // a full binary tree with N levels has 2**N + 2**N-1 nodes
78 logic [2**(IdxW+1)-2:0] req_tree;
79 logic [2**(IdxW+1)-2:0] prio_tree;
80 logic [2**(IdxW+1)-2:0] sel_tree;
81 logic [2**(IdxW+1)-2:0] mask_tree;
82 logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree;
83 logic [2**(IdxW+1)-2:0][DW-1:0] data_tree;
84 logic [N-1:0] prio_mask_d, prio_mask_q;
85
86 for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree
87 //
88 // level+1 C0 C1 <- "Base1" points to the first node on "level+1",
89 // \ / these nodes are the children of the nodes one level below
90 // level Pa <- "Base0", points to the first node on "level",
91 // these nodes are the parents of the nodes one level above
92 //
93 // hence we have the following indices for the Pa, C0, C1 nodes:
94 // Pa = 2**level - 1 + offset = Base0 + offset
95 // C0 = 2**(level+1) - 1 + 2*offset = Base1 + 2*offset
96 // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1
97 //
98 localparam int Base0 = (2**level)-1;
99 localparam int Base1 = (2**(level+1))-1;
100
101 for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level
102 localparam int Pa = Base0 + offset;
103 localparam int C0 = Base1 + 2*offset;
104 localparam int C1 = Base1 + 2*offset + 1;
105
106 // this assigns the gated interrupt source signals, their
107 // corresponding IDs and priorities to the tree leafs
108 if (level == IdxW) begin : gen_leafs
109 if (offset < N) begin : gen_assign
110 // forward path (requests and data)
111 // all requests inputs are assigned to the request tree
112 2/2 assign req_tree[Pa] = req_i[offset];
Tests: T1 T2 T3 | T1 T2 T3
113 // we basically split the incoming request vector into two halves with the following
114 // priority assignment. the prio_mask_q register contains a prefix sum that has been
115 // computed using the last winning index, and hence masks out all requests at offsets
116 // lower or equal the previously granted index. hence, all higher indices are considered
117 // first in the arbitration tree nodes below, before considering the lower indices.
118 2/2 assign prio_tree[Pa] = req_i[offset] & prio_mask_q[offset];
Tests: T1 T2 T3 | T1 T2 T3
119 // input for the index muxes (used to compute the winner index)
120 assign idx_tree[Pa] = offset;
121 // input for the data muxes
122 0/2 ==> assign data_tree[Pa] = data_i[offset];
123
124 // backward path (grants and prefix sum)
125 // grant if selected, ready and request asserted
126 2/2 assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i;
Tests: T1 T2 T3 | T1 T2 T3
127 // only update mask if there is a valid request
128 2/2 assign prio_mask_d[offset] = (|req_i) ?
Tests: T1 T2 T3 | T1 T2 T3
129 mask_tree[Pa] | sel_tree[Pa] & ~ready_i :
130 prio_mask_q[offset];
131 end else begin : gen_tie_off
132 // forward path
133 assign req_tree[Pa] = '0;
134 assign prio_tree[Pa] = '0;
135 assign idx_tree[Pa] = '0;
136 assign data_tree[Pa] = '0;
137 logic unused_sigs;
138 assign unused_sigs = ^{mask_tree[Pa],
139 sel_tree[Pa]};
140 end
141 // this creates the node assignments
142 end else begin : gen_nodes
143 // local helper variable
144 logic sel;
145
146 // forward path (requests and data)
147 // each node looks at its two children, and selects the one with higher priority
148 1/1 assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1];
Tests: T1 T2 T3
149 // propagate requests
150 1/1 assign req_tree[Pa] = req_tree[C0] | req_tree[C1];
Tests: T1 T2 T3
151 1/1 assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0];
Tests: T1 T2 T3
152 // data and index muxes
153 // Note: these ternaries have triggered a synthesis bug in Vivado versions older
154 // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
155 1/1 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
Tests: T1 T2 T3
156 1/1 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
Tests: T1 T2 T3
157
158 // backward path (grants and prefix sum)
159 // this propagates the selction index back and computes a hot one mask
160 1/1 assign sel_tree[C0] = sel_tree[Pa] & ~sel;
Tests: T1 T2 T3
161 1/1 assign sel_tree[C1] = sel_tree[Pa] & sel;
Tests: T1 T2 T3
162 // this performs a prefix sum for masking the input requests in the next cycle
163 unreachable assign mask_tree[C0] = mask_tree[Pa];
164 1/1 assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0];
Tests: T1 T2 T3
165 end
166 end : gen_level
167 end : gen_tree
168
169 // the results can be found at the tree root
170 if (EnDataPort) begin : gen_data_port
171 assign data_o = data_tree[0];
172 end else begin : gen_no_dataport
173 logic [DW-1:0] unused_data;
174 1/1 assign unused_data = data_tree[0];
Tests: T1 T2 T3
175 assign data_o = '1;
176 end
177
178 // This index is unused.
179 logic unused_prio_tree;
180 1/1 assign unused_prio_tree = prio_tree[0];
Tests: T1 T2 T3
181
182 1/1 assign idx_o = idx_tree[0];
Tests: T1 T2 T3
183 1/1 assign valid_o = req_tree[0];
Tests: T1 T2 T3
184
185 // the select tree computes a hot one signal that indicates which request is currently selected
186 assign sel_tree[0] = 1'b1;
187 // the mask tree is basically a prefix sum of the hot one select signal computed above
188 assign mask_tree[0] = 1'b0;
189
190 always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg
191 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
192 1/1 prio_mask_q <= '0;
Tests: T1 T2 T3
193 end else begin
194 1/1 prio_mask_q <= prio_mask_d;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_edn_arb
| Total | Covered | Percent |
|---|
| Conditions | 49 | 45 | 91.84 |
| Logical | 49 | 45 | 91.84 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T16 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | 1 | Covered | T16 |
| 1 | 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Covered | T16 |
| 1 | 1 | 1 | Covered | T16 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T6 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T6 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16 |
| 0 | 1 | Covered | T16 |
| 1 | 0 | Covered | T4,T5,T6 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T16 |
| 1 | 1 | Covered | T16 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T16 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T16 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T16 |
| 1 | 0 | Covered | T4,T5,T6 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T16 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_edn_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
10 |
10 |
100.00 |
| TERNARY |
155 |
2 |
2 |
100.00 |
| TERNARY |
156 |
2 |
2 |
100.00 |
| TERNARY |
128 |
2 |
2 |
100.00 |
| TERNARY |
128 |
2 |
2 |
100.00 |
| IF |
191 |
2 |
2 |
100.00 |
155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T4,T5,T6 |
156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T4,T5,T6 |
128 assign prio_mask_d[offset] = (|req_i) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T1,T2,T3 |
128 assign prio_mask_d[offset] = (|req_i) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T1,T2,T3 |
191 if (!rst_ni) begin
-1-
192 prio_mask_q <= '0;
==>
193 end else begin
194 prio_mask_q <= prio_mask_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_arb
Assertion Details
CheckHotOne_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
CheckNGreaterZero_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1125 |
1125 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
208427 |
0 |
0 |
| T4 |
52297 |
185 |
0 |
0 |
| T5 |
25244 |
47 |
0 |
0 |
| T6 |
13766 |
48 |
0 |
0 |
| T10 |
23744 |
95 |
0 |
0 |
| T11 |
43902 |
0 |
0 |
0 |
| T12 |
34978 |
92 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T23 |
20929 |
46 |
0 |
0 |
| T24 |
0 |
230 |
0 |
0 |
| T90 |
77418 |
199 |
0 |
0 |
| T93 |
0 |
534 |
0 |
0 |
| T95 |
12284 |
0 |
0 |
0 |
| T124 |
0 |
46 |
0 |
0 |
GntImpliesValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
208427 |
0 |
0 |
| T4 |
52297 |
185 |
0 |
0 |
| T5 |
25244 |
47 |
0 |
0 |
| T6 |
13766 |
48 |
0 |
0 |
| T10 |
23744 |
95 |
0 |
0 |
| T11 |
43902 |
0 |
0 |
0 |
| T12 |
34978 |
92 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T23 |
20929 |
46 |
0 |
0 |
| T24 |
0 |
230 |
0 |
0 |
| T90 |
77418 |
199 |
0 |
0 |
| T93 |
0 |
534 |
0 |
0 |
| T95 |
12284 |
0 |
0 |
0 |
| T124 |
0 |
46 |
0 |
0 |
GrantKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
IdxKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
IndexIsCorrect_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
208427 |
0 |
0 |
| T4 |
52297 |
185 |
0 |
0 |
| T5 |
25244 |
47 |
0 |
0 |
| T6 |
13766 |
48 |
0 |
0 |
| T10 |
23744 |
95 |
0 |
0 |
| T11 |
43902 |
0 |
0 |
0 |
| T12 |
34978 |
92 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T23 |
20929 |
46 |
0 |
0 |
| T24 |
0 |
230 |
0 |
0 |
| T90 |
77418 |
199 |
0 |
0 |
| T93 |
0 |
534 |
0 |
0 |
| T95 |
12284 |
0 |
0 |
0 |
| T124 |
0 |
46 |
0 |
0 |
LockArbDecision_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
14409906 |
0 |
0 |
| T4 |
52297 |
4928 |
0 |
0 |
| T5 |
25244 |
2315 |
0 |
0 |
| T6 |
13766 |
765 |
0 |
0 |
| T10 |
23744 |
957 |
0 |
0 |
| T11 |
43902 |
0 |
0 |
0 |
| T12 |
34978 |
4168 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T23 |
20929 |
713 |
0 |
0 |
| T24 |
0 |
24412 |
0 |
0 |
| T90 |
77418 |
14091 |
0 |
0 |
| T93 |
0 |
4818 |
0 |
0 |
| T95 |
12284 |
0 |
0 |
0 |
| T124 |
0 |
583 |
0 |
0 |
NoReadyValidNoGrant_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
70863811 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
46395 |
0 |
0 |
| T5 |
25244 |
22601 |
0 |
0 |
| T6 |
13766 |
12786 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
22179 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
30274 |
0 |
0 |
ReadyAndValidImplyGrant_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
208427 |
0 |
0 |
| T4 |
52297 |
185 |
0 |
0 |
| T5 |
25244 |
47 |
0 |
0 |
| T6 |
13766 |
48 |
0 |
0 |
| T10 |
23744 |
95 |
0 |
0 |
| T11 |
43902 |
0 |
0 |
0 |
| T12 |
34978 |
92 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T23 |
20929 |
46 |
0 |
0 |
| T24 |
0 |
230 |
0 |
0 |
| T90 |
77418 |
199 |
0 |
0 |
| T93 |
0 |
534 |
0 |
0 |
| T95 |
12284 |
0 |
0 |
0 |
| T124 |
0 |
46 |
0 |
0 |
ReqAndReadyImplyGrant_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
208427 |
0 |
0 |
| T4 |
52297 |
185 |
0 |
0 |
| T5 |
25244 |
47 |
0 |
0 |
| T6 |
13766 |
48 |
0 |
0 |
| T10 |
23744 |
95 |
0 |
0 |
| T11 |
43902 |
0 |
0 |
0 |
| T12 |
34978 |
92 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T23 |
20929 |
46 |
0 |
0 |
| T24 |
0 |
230 |
0 |
0 |
| T90 |
77418 |
199 |
0 |
0 |
| T93 |
0 |
534 |
0 |
0 |
| T95 |
12284 |
0 |
0 |
0 |
| T124 |
0 |
46 |
0 |
0 |
ReqImpliesValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
14634297 |
0 |
0 |
| T4 |
52297 |
5113 |
0 |
0 |
| T5 |
25244 |
2362 |
0 |
0 |
| T6 |
13766 |
813 |
0 |
0 |
| T10 |
23744 |
1053 |
0 |
0 |
| T11 |
43902 |
0 |
0 |
0 |
| T12 |
34978 |
4260 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T23 |
20929 |
760 |
0 |
0 |
| T24 |
0 |
24652 |
0 |
0 |
| T90 |
77418 |
14290 |
0 |
0 |
| T93 |
0 |
5352 |
0 |
0 |
| T95 |
12284 |
0 |
0 |
0 |
| T124 |
0 |
629 |
0 |
0 |
ReqStaysHighUntilGranted0_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
14409906 |
0 |
0 |
| T4 |
52297 |
4928 |
0 |
0 |
| T5 |
25244 |
2315 |
0 |
0 |
| T6 |
13766 |
765 |
0 |
0 |
| T10 |
23744 |
957 |
0 |
0 |
| T11 |
43902 |
0 |
0 |
0 |
| T12 |
34978 |
4168 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T23 |
20929 |
713 |
0 |
0 |
| T24 |
0 |
24412 |
0 |
0 |
| T90 |
77418 |
14091 |
0 |
0 |
| T93 |
0 |
4818 |
0 |
0 |
| T95 |
12284 |
0 |
0 |
0 |
| T124 |
0 |
583 |
0 |
0 |
RoundRobin_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
0 |
0 |
1112 |
ValidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |