Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 91 | 91 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
| ALWAYS | 164 | 68 | 68 | 100.00 |
| CONT_ASSIGN | 334 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 342 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 350 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 354 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 395 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 454 | 1 | 1 | 100.00 |
| ALWAYS | 461 | 3 | 3 | 100.00 |
| ALWAYS | 464 | 8 | 8 | 100.00 |
137 // Output partition error state.
138 1/1 assign error_o = error_q;
Tests: T1 T2 T3
139
140 // This partition cannot do any write accesses, hence we tie this
141 // constantly off.
142 assign otp_wdata_o = '0;
143 // Depending on the partition configuration, the wrapper is instructed to ignore integrity
144 // calculations and checks. To be on the safe side, the partition filters error responses at this
145 // point and does not report any integrity errors if integrity is disabled.
146 otp_err_e otp_err;
147 if (Info.integrity) begin : gen_integrity
148 assign otp_cmd_o = prim_otp_pkg::Read;
149 1/1 assign otp_err = otp_err_e'(otp_err_i);
Tests: T1 T2 T3
150 end else begin : gen_no_integrity
151 assign otp_cmd_o = prim_otp_pkg::ReadRaw;
152 always_comb begin
153 if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin
154 otp_err = NoError;
155 end else begin
156 otp_err = otp_err_e'(otp_err_i);
157 end
158 end
159 end
160
161 `ASSERT_KNOWN(FsmStateKnown_A, state_q)
162 always_comb begin : p_fsm
163 // Default assignments
164 1/1 state_d = state_q;
Tests: T1 T2 T3
165
166 // Response to init request
167 1/1 init_done_o = 1'b0;
Tests: T1 T2 T3
168
169 // OTP signals
170 1/1 otp_req_o = 1'b0;
Tests: T1 T2 T3
171 1/1 otp_addr_sel = DigestAddrSel;
Tests: T1 T2 T3
172
173 // TL-UL signals
174 1/1 tlul_gnt_o = 1'b0;
Tests: T1 T2 T3
175 1/1 tlul_rvalid_o = 1'b0;
Tests: T1 T2 T3
176 1/1 tlul_rerror_o = '0;
Tests: T1 T2 T3
177
178 // Enable for buffered digest register
179 1/1 digest_reg_en = 1'b0;
Tests: T1 T2 T3
180
181 // Error Register
182 1/1 error_d = error_q;
Tests: T1 T2 T3
183 1/1 pending_tlul_error_d = 1'b0;
Tests: T1 T2 T3
184 1/1 fsm_err_o = 1'b0;
Tests: T1 T2 T3
185
186 1/1 unique case (state_q)
Tests: T1 T2 T3
187 ///////////////////////////////////////////////////////////////////
188 // State right after reset. Wait here until we get a an
189 // initialization request.
190 ResetSt: begin
191 1/1 if (init_req_i) begin
Tests: T1 T2 T3
192 // If the partition does not have a digest, no initialization is necessary.
193 1/1 if (Info.sw_digest) begin
Tests: T1 T2 T3
194 1/1 state_d = InitSt;
Tests: T1 T2 T3
195 end else begin
196 unreachable state_d = IdleSt;
197 end
198 end
MISSING_ELSE
199 end
200 ///////////////////////////////////////////////////////////////////
201 // Initialization reads out the digest only in unbuffered
202 // partitions. Wait here until the OTP request has been granted.
203 // And then wait until the OTP word comes back.
204 InitSt: begin
205 1/1 otp_req_o = 1'b1;
Tests: T1 T2 T3
206 1/1 if (otp_gnt_i) begin
Tests: T1 T2 T3
207 1/1 state_d = InitWaitSt;
Tests: T1 T2 T3
208 end
MISSING_ELSE
209 end
210 ///////////////////////////////////////////////////////////////////
211 // Wait for OTP response and write to digest buffer register. In
212 // case an OTP transaction fails, latch the OTP error code and
213 // jump to a terminal error state.
214 InitWaitSt: begin
215 1/1 if (otp_rvalid_i) begin
Tests: T1 T2 T3
216 1/1 digest_reg_en = 1'b1;
Tests: T1 T2 T3
217 1/1 if (otp_err inside {NoError, MacroEccCorrError}) begin
Tests: T1 T2 T3
218 1/1 state_d = IdleSt;
Tests: T1 T2 T3
219 // At this point the only error that we could have gotten are correctable ECC errors.
220 1/1 if (otp_err != NoError) begin
Tests: T1 T2 T3
221 1/1 error_d = MacroEccCorrError;
Tests: T54 T42 T45
222 end
MISSING_ELSE
223 end else begin
224 1/1 state_d = ErrorSt;
Tests: T182 T187 T188
225 1/1 error_d = otp_err;
Tests: T182 T187 T188
226 end
227 end
MISSING_ELSE
228 end
229 ///////////////////////////////////////////////////////////////////
230 // Wait for TL-UL requests coming in.
231 // Then latch address and go to readout state.
232 IdleSt: begin
233 1/1 init_done_o = 1'b1;
Tests: T1 T2 T3
234 1/1 if (tlul_req_i) begin
Tests: T1 T2 T3
235 1/1 error_d = NoError; // clear recoverable soft errors.
Tests: T2 T7 T4
236 1/1 state_d = ReadSt;
Tests: T2 T7 T4
237 1/1 tlul_gnt_o = 1'b1;
Tests: T2 T7 T4
238 end
MISSING_ELSE
239 end
240 ///////////////////////////////////////////////////////////////////
241 // If the address is out of bounds, or if the partition is
242 // locked, signal back a bus error. Note that such an error does
243 // not cause the partition to go into error state. Otherwise if
244 // these checks pass, an OTP word is requested.
245 ReadSt: begin
246 1/1 init_done_o = 1'b1;
Tests: T2 T7 T4
247 // Double check the address range.
248 1/1 if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
Tests: T2 T7 T4
249 1/1 otp_req_o = 1'b1;
Tests: T2 T7 T4
250 1/1 otp_addr_sel = DataAddrSel;
Tests: T2 T7 T4
251 1/1 if (otp_gnt_i) begin
Tests: T2 T7 T4
252 1/1 state_d = ReadWaitSt;
Tests: T2 T7 T4
253 end
MISSING_ELSE
254 end else begin
255 1/1 state_d = IdleSt;
Tests: T5 T12 T90
256 1/1 error_d = AccessError; // Signal this error, but do not go into terminal error state.
Tests: T5 T12 T90
257 1/1 tlul_rvalid_o = 1'b1;
Tests: T5 T12 T90
258 1/1 tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
Tests: T5 T12 T90
259 end
260 end
261 ///////////////////////////////////////////////////////////////////
262 // Wait for OTP response and release the TL-UL response. In
263 // case an OTP transaction fails, latch the OTP error code,
264 // signal a TL-Ul bus error and jump to a terminal error state.
265 ReadWaitSt: begin
266 1/1 init_done_o = 1'b1;
Tests: T2 T7 T4
267 1/1 if (otp_rvalid_i) begin
Tests: T2 T7 T4
268 1/1 tlul_rvalid_o = 1'b1;
Tests: T2 T7 T4
269 1/1 if (otp_err inside {NoError, MacroEccCorrError}) begin
Tests: T2 T7 T4
270 1/1 state_d = IdleSt;
Tests: T2 T7 T4
271 // At this point the only error that we could have gotten are correctable ECC errors.
272 1/1 if (otp_err != NoError) begin
Tests: T2 T7 T4
273 1/1 error_d = MacroEccCorrError;
Tests: T12 T146 T49
274 end
MISSING_ELSE
275 end else begin
276 1/1 state_d = ErrorSt;
Tests: T193 T192 T194
277 1/1 error_d = otp_err;
Tests: T193 T192 T194
278 // This causes the TL-UL adapter to return a bus error.
279 1/1 tlul_rerror_o = 2'b11;
Tests: T193 T192 T194
280 end
281 end
MISSING_ELSE
282 end
283 ///////////////////////////////////////////////////////////////////
284 // Terminal Error State. This locks access to the partition.
285 // Make sure the partition signals an error state if no error
286 // code has been latched so far.
287 ErrorSt: begin
288 1/1 if (error_q == NoError) begin
Tests: T3 T7 T4
289 1/1 error_d = FsmStateError;
Tests: T26 T27 T28
290 end
MISSING_ELSE
291
292 // Return bus errors if there are pending TL-UL requests.
293 1/1 if (pending_tlul_error_q) begin
Tests: T3 T7 T4
294 1/1 tlul_rerror_o = 2'b11;
Tests: T5 T125 T145
295 1/1 tlul_rvalid_o = 1'b1;
Tests: T5 T125 T145
296 1/1 end else if (tlul_req_i) begin
Tests: T3 T7 T4
297 1/1 tlul_gnt_o = 1'b1;
Tests: T5 T125 T145
298 1/1 pending_tlul_error_d = 1'b1;
Tests: T5 T125 T145
299 end
MISSING_ELSE
300 end
301 ///////////////////////////////////////////////////////////////////
302 // We should never get here. If we do (e.g. via a malicious
303 // glitch), error out immediately.
304 default: begin
305 state_d = ErrorSt;
306 fsm_err_o = 1'b1;
307 end
308 ///////////////////////////////////////////////////////////////////
309 endcase // state_q
310
311 // Unconditionally jump into the terminal error state in case of
312 // an ECC error or escalation, and lock access to the partition down.
313 // SEC_CM: PART.FSM.LOCAL_ESC
314 1/1 if (ecc_err) begin
Tests: T1 T2 T3
315 1/1 state_d = ErrorSt;
Tests: T178 T186
316 1/1 if (state_q != ErrorSt) begin
Tests: T178 T186
317 1/1 error_d = CheckFailError;
Tests: T178 T186
318 end
MISSING_ELSE
319 end
MISSING_ELSE
320 // SEC_CM: PART.FSM.GLOBAL_ESC
321 1/1 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
Tests: T1 T2 T3
322 1/1 state_d = ErrorSt;
Tests: T3 T7 T4
323 1/1 fsm_err_o = 1'b1;
Tests: T3 T7 T4
324 1/1 if (state_q != ErrorSt) begin
Tests: T3 T7 T4
325 1/1 error_d = FsmStateError;
Tests: T3 T7 T4
326 end
MISSING_ELSE
327 end
MISSING_ELSE
328 end
329
330 ///////////////////////////////////
331 // Signals to/from TL-UL Adapter //
332 ///////////////////////////////////
333
334 1/1 assign tlul_addr_d = tlul_addr_i;
Tests: T1 T2 T3
335 // Do not forward data in case of an error.
336 1/1 assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
Tests: T1 T2 T3
337
338 if (Info.offset == 0) begin : gen_zero_offset
339 assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd;
340
341 end else begin : gen_nonzero_offset
342 1/1 assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset &&
Tests: T1 T2 T3
343 {1'b0, tlul_addr_q, 2'b00} < PartEnd;
344 end
345
346 // Note that OTP works on halfword (16bit) addresses, hence need to
347 // shift the addresses appropriately.
348 logic [OtpByteAddrWidth-1:0] addr_calc;
349 1/1 assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
Tests: T1 T2 T3
350 1/1 assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift];
Tests: T1 T2 T3
351
352 if (OtpAddrShift > 0) begin : gen_unused
353 logic unused_bits;
354 1/1 assign unused_bits = ^addr_calc[OtpAddrShift-1:0];
Tests: T1 T2 T3
355 end
356
357 // Request 32bit except in case of the digest.
358 1/1 assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
Tests: T1 T2 T3
359 OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) :
360 OtpSizeWidth'(unsigned'(32 / OtpWidth - 1));
361
362 ////////////////
363 // Digest Reg //
364 ////////////////
365
366 if (Info.sw_digest) begin : gen_ecc_reg
367 // SEC_CM: PART.DATA_REG.INTEGRITY
368 otp_ctrl_ecc_reg #(
369 .Width ( ScrmblBlockWidth ),
370 .Depth ( 1 )
371 ) u_otp_ctrl_ecc_reg (
372 .clk_i,
373 .rst_ni,
374 .wren_i ( digest_reg_en ),
375 .addr_i ( '0 ),
376 .wdata_i ( otp_rdata_i ),
377 .rdata_o ( ),
378 .data_o ( digest_o ),
379 .ecc_err_o ( ecc_err )
380 );
381 end else begin : gen_no_ecc_reg
382 logic unused_digest_reg_en;
383 logic unused_rdata;
384 assign unused_digest_reg_en = digest_reg_en;
385 assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case.
386 assign digest_o = '0;
387 assign ecc_err = 1'b0;
388 end
389
390 ////////////////////////
391 // DAI Access Control //
392 ////////////////////////
393
394 mubi8_t init_locked;
395 1/1 assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
Tests: T1 T2 T3
396
397 // Aggregate all possible DAI write locks. The partition is also locked when uninitialized.
398 // Note that the locks are redundantly encoded values.
399 part_access_t access_pre;
400 prim_mubi8_sender #(
401 .AsyncOn(0)
402 ) u_prim_mubi8_sender_write_lock_pre (
403 .clk_i,
404 .rst_ni,
405 .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)),
406 .mubi_o(access_pre.write_lock)
407 );
408 prim_mubi8_sender #(
409 .AsyncOn(0)
410 ) u_prim_mubi8_sender_read_lock_pre (
411 .clk_i,
412 .rst_ni,
413 .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)),
414 .mubi_o(access_pre.read_lock)
415 );
416
417 // SEC_CM: PART.MEM.SW_UNWRITABLE
418 if (Info.write_lock) begin : gen_digest_write_lock
419 mubi8_t digest_locked;
420 1/1 assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
Tests: T1 T2 T3
421
422 // This prevents the synthesis tool from optimizing the multibit signal.
423 prim_mubi8_sender #(
424 .AsyncOn(0)
425 ) u_prim_mubi8_sender_write_lock (
426 .clk_i,
427 .rst_ni,
428 .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)),
429 .mubi_o(access_o.write_lock)
430 );
431
432 `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock))
433 end else begin : gen_no_digest_write_lock
434 assign access_o.write_lock = access_pre.write_lock;
435 end
436
437 // SEC_CM: PART.MEM.SW_UNREADABLE
438 if (Info.read_lock) begin : gen_digest_read_lock
439 mubi8_t digest_locked;
440 assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
441
442 // This prevents the synthesis tool from optimizing the multibit signal.
443 prim_mubi8_sender #(
444 .AsyncOn(0)
445 ) u_prim_mubi8_sender_read_lock (
446 .clk_i,
447 .rst_ni,
448 .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)),
449 .mubi_o(access_o.read_lock)
450 );
451
452 `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock))
453 end else begin : gen_no_digest_read_lock
454 1/1 assign access_o.read_lock = access_pre.read_lock;
Tests: T1 T2 T3
455 end
456
457 ///////////////
458 // Registers //
459 ///////////////
460
461 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
461.1 `ifdef SIMULATION
461.2 prim_sparse_fsm_flop #(
461.3 .StateEnumT(state_e),
461.4 .Width($bits(state_e)),
461.5 .ResetValue($bits(state_e)'(ResetSt)),
461.6 .EnableAlertTriggerSVA(1),
461.7 .CustomForceName("state_q")
461.8 ) u_state_regs (
461.9 .clk_i ( clk_i ),
461.10 .rst_ni ( rst_ni ),
461.11 .state_i ( state_d ),
461.12 .state_o ( )
461.13 );
461.14 always_ff @(posedge clk_i or negedge rst_ni) begin
461.15 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
461.16 1/1 state_q <= ResetSt;
Tests: T1 T2 T3
461.17 end else begin
461.18 1/1 state_q <= state_d;
Tests: T1 T2 T3
461.19 end
461.20 end
461.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))
461.22 else begin
461.23 `ifdef UVM
461.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
461.25 "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1);
461.26 `else
461.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
461.28 `PRIM_STRINGIFY(u_state_regs_A));
461.29 `endif
461.30 end
461.31 `else
461.32 prim_sparse_fsm_flop #(
461.33 .StateEnumT(state_e),
461.34 .Width($bits(state_e)),
461.35 .ResetValue($bits(state_e)'(ResetSt)),
461.36 .EnableAlertTriggerSVA(1)
461.37 ) u_state_regs (
461.38 .clk_i ( `PRIM_FLOP_CLK ),
461.39 .rst_ni ( `PRIM_FLOP_RST ),
461.40 .state_i ( state_d ),
461.41 .state_o ( state_q )
461.42 );
461.43 `endif462
463 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
464 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
465 1/1 error_q <= NoError;
Tests: T1 T2 T3
466 1/1 tlul_addr_q <= '0;
Tests: T1 T2 T3
467 1/1 pending_tlul_error_q <= 1'b0;
Tests: T1 T2 T3
468 end else begin
469 1/1 error_q <= error_d;
Tests: T1 T2 T3
470 1/1 pending_tlul_error_q <= pending_tlul_error_d;
Tests: T1 T2 T3
471 1/1 if (tlul_gnt_o) begin
Tests: T1 T2 T3
472 1/1 tlul_addr_q <= tlul_addr_d;
Tests: T2 T7 T4
473 end
MISSING_ELSE
Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 220
EXPRESSION (otp_err != NoError)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T54,T42,T45 |
LINE 272
EXPRESSION (otp_err != NoError)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T7,T4 |
| 1 | Covered | T12,T146,T49 |
LINE 288
EXPRESSION (error_q == NoError)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T7,T4 |
| 1 | Covered | T26,T27,T28 |
LINE 316
EXPRESSION (state_q != ErrorSt)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T178,T186 |
| 1 | Covered | T178,T186 |
LINE 324
EXPRESSION (state_q != ErrorSt)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T7,T4 |
| 1 | Covered | T3,T7,T4 |
LINE 336
EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T4 |
LINE 336
SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T5,T12,T90 |
| 1 | 1 | Covered | T2,T7,T4 |
LINE 336
SUB-EXPRESSION (tlul_rerror_o == '0)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 342
EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
--------------------1------------------- ------------------2------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T2,T7,T4 |
LINE 349
EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T7,T4 |
| 1 | Covered | T1,T2,T3 |
LINE 349
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 358
EXPRESSION
Number Term
1 (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T7,T4 |
| 1 | Covered | T1,T2,T3 |
LINE 358
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 395
EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 420
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T4,T6 |
LINE 420
SUB-EXPRESSION (digest_o != '0)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T4,T6 |
FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
7 |
7 |
100.00 |
(Not included in score) |
| Transitions |
13 |
12 |
92.31 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| ErrorSt |
224 |
Covered |
T3,T7,T4 |
| IdleSt |
196 |
Covered |
T1,T2,T3 |
| InitSt |
194 |
Covered |
T1,T2,T3 |
| InitWaitSt |
207 |
Covered |
T1,T2,T3 |
| ReadSt |
236 |
Covered |
T2,T7,T4 |
| ReadWaitSt |
252 |
Covered |
T2,T7,T4 |
| ResetSt |
190 |
Covered |
T1,T2,T3 |
| transitions | Line No. | Covered | Tests | Exclude Annotation |
| IdleSt->ErrorSt |
315 |
Covered |
T3,T7,T4 |
|
| IdleSt->ReadSt |
236 |
Covered |
T2,T7,T4 |
|
| InitSt->ErrorSt |
315 |
Covered |
T96,T110,T183 |
|
| InitSt->InitWaitSt |
207 |
Covered |
T1,T2,T3 |
|
| InitWaitSt->ErrorSt |
224 |
Covered |
T189,T182,T187 |
|
| InitWaitSt->IdleSt |
218 |
Covered |
T1,T2,T3 |
|
| ReadSt->ErrorSt |
315 |
Not Covered |
|
|
| ReadSt->IdleSt |
255 |
Covered |
T5,T12,T90 |
|
| ReadSt->ReadWaitSt |
252 |
Covered |
T2,T7,T4 |
|
| ReadWaitSt->ErrorSt |
276 |
Covered |
T193,T192,T194 |
|
| ReadWaitSt->IdleSt |
270 |
Covered |
T2,T7,T4 |
|
| ResetSt->ErrorSt |
315 |
Covered |
T103,T104,T105 |
|
| ResetSt->IdleSt |
196 |
Excluded |
|
VC_COV_UNR |
| ResetSt->InitSt |
194 |
Covered |
T1,T2,T3 |
|
Summary for FSM :: error_q
| Total | Covered | Percent | |
| States |
5 |
5 |
100.00 |
(Not included in score) |
| Transitions |
11 |
10 |
90.91 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: error_q
| states | Line No. | Covered | Tests |
| AccessError |
256 |
Covered |
T5,T12,T90 |
| CheckFailError |
317 |
Covered |
T178,T186 |
| FsmStateError |
289 |
Covered |
T3,T7,T4 |
| MacroEccCorrError |
221 |
Covered |
T12,T146,T49 |
| NoError |
235 |
Covered |
T1,T2,T3 |
| transitions | Line No. | Covered | Tests | Exclude Annotation |
| AccessError->CheckFailError |
317 |
Excluded |
|
VC_COV_UNR |
| AccessError->FsmStateError |
325 |
Covered |
T5,T125,T8 |
|
| AccessError->MacroEccCorrError |
221 |
Excluded |
|
VC_COV_UNR |
| AccessError->NoError |
235 |
Covered |
T5,T12,T90 |
|
| CheckFailError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
| CheckFailError->FsmStateError |
325 |
Excluded |
|
VC_COV_UNR |
| CheckFailError->MacroEccCorrError |
221 |
Excluded |
|
VC_COV_UNR |
| CheckFailError->NoError |
235 |
Covered |
T178,T186 |
|
| FsmStateError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
| FsmStateError->CheckFailError |
317 |
Excluded |
|
VC_COV_UNR |
| FsmStateError->MacroEccCorrError |
221 |
Excluded |
|
VC_COV_UNR |
| FsmStateError->NoError |
235 |
Covered |
T3,T7,T4 |
|
| MacroEccCorrError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
| MacroEccCorrError->CheckFailError |
317 |
Not Covered |
|
|
| MacroEccCorrError->FsmStateError |
325 |
Covered |
T146,T54,T170 |
|
| MacroEccCorrError->NoError |
235 |
Covered |
T12,T49,T117 |
|
| NoError->AccessError |
256 |
Covered |
T5,T12,T90 |
|
| NoError->CheckFailError |
317 |
Covered |
T178,T186 |
|
| NoError->FsmStateError |
289 |
Covered |
T3,T7,T4 |
|
| NoError->MacroEccCorrError |
221 |
Covered |
T12,T146,T49 |
|
Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf
| Line No. | Total | Covered | Percent |
| Branches |
|
44 |
44 |
100.00 |
| TERNARY |
336 |
2 |
2 |
100.00 |
| TERNARY |
349 |
2 |
2 |
100.00 |
| TERNARY |
358 |
2 |
2 |
100.00 |
| TERNARY |
395 |
2 |
2 |
100.00 |
| TERNARY |
420 |
2 |
2 |
100.00 |
| CASE |
186 |
23 |
23 |
100.00 |
| IF |
314 |
3 |
3 |
100.00 |
| IF |
321 |
3 |
3 |
100.00 |
| IF |
461 |
2 |
2 |
100.00 |
| IF |
464 |
3 |
3 |
100.00 |
336 assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T4 |
| 0 |
Covered |
T1,T2,T3 |
349 assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T2,T7,T4 |
358 assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T2,T7,T4 |
395 assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
420 assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T4,T6 |
| 0 |
Covered |
T1,T2,T3 |
186 unique case (state_q)
-1-
187 ///////////////////////////////////////////////////////////////////
188 // State right after reset. Wait here until we get a an
189 // initialization request.
190 ResetSt: begin
191 if (init_req_i) begin
-2-
192 // If the partition does not have a digest, no initialization is necessary.
193 if (Info.sw_digest) begin
-3-
194 state_d = InitSt;
==>
195 end else begin
196 state_d = IdleSt;
==> (Unreachable)
197 end
198 end
MISSING_ELSE
==>
199 end
200 ///////////////////////////////////////////////////////////////////
201 // Initialization reads out the digest only in unbuffered
202 // partitions. Wait here until the OTP request has been granted.
203 // And then wait until the OTP word comes back.
204 InitSt: begin
205 otp_req_o = 1'b1;
206 if (otp_gnt_i) begin
-4-
207 state_d = InitWaitSt;
==>
208 end
MISSING_ELSE
==>
209 end
210 ///////////////////////////////////////////////////////////////////
211 // Wait for OTP response and write to digest buffer register. In
212 // case an OTP transaction fails, latch the OTP error code and
213 // jump to a terminal error state.
214 InitWaitSt: begin
215 if (otp_rvalid_i) begin
-5-
216 digest_reg_en = 1'b1;
217 if (otp_err inside {NoError, MacroEccCorrError}) begin
-6-
218 state_d = IdleSt;
219 // At this point the only error that we could have gotten are correctable ECC errors.
220 if (otp_err != NoError) begin
-7-
221 error_d = MacroEccCorrError;
==>
222 end
MISSING_ELSE
==>
223 end else begin
224 state_d = ErrorSt;
==>
225 error_d = otp_err;
226 end
227 end
MISSING_ELSE
==>
228 end
229 ///////////////////////////////////////////////////////////////////
230 // Wait for TL-UL requests coming in.
231 // Then latch address and go to readout state.
232 IdleSt: begin
233 init_done_o = 1'b1;
234 if (tlul_req_i) begin
-8-
235 error_d = NoError; // clear recoverable soft errors.
==>
236 state_d = ReadSt;
237 tlul_gnt_o = 1'b1;
238 end
MISSING_ELSE
==>
239 end
240 ///////////////////////////////////////////////////////////////////
241 // If the address is out of bounds, or if the partition is
242 // locked, signal back a bus error. Note that such an error does
243 // not cause the partition to go into error state. Otherwise if
244 // these checks pass, an OTP word is requested.
245 ReadSt: begin
246 init_done_o = 1'b1;
247 // Double check the address range.
248 if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
-9-
249 otp_req_o = 1'b1;
250 otp_addr_sel = DataAddrSel;
251 if (otp_gnt_i) begin
-10-
252 state_d = ReadWaitSt;
==>
253 end
MISSING_ELSE
==>
254 end else begin
255 state_d = IdleSt;
==>
256 error_d = AccessError; // Signal this error, but do not go into terminal error state.
257 tlul_rvalid_o = 1'b1;
258 tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
259 end
260 end
261 ///////////////////////////////////////////////////////////////////
262 // Wait for OTP response and release the TL-UL response. In
263 // case an OTP transaction fails, latch the OTP error code,
264 // signal a TL-Ul bus error and jump to a terminal error state.
265 ReadWaitSt: begin
266 init_done_o = 1'b1;
267 if (otp_rvalid_i) begin
-11-
268 tlul_rvalid_o = 1'b1;
269 if (otp_err inside {NoError, MacroEccCorrError}) begin
-12-
270 state_d = IdleSt;
271 // At this point the only error that we could have gotten are correctable ECC errors.
272 if (otp_err != NoError) begin
-13-
273 error_d = MacroEccCorrError;
==>
274 end
MISSING_ELSE
==>
275 end else begin
276 state_d = ErrorSt;
==>
277 error_d = otp_err;
278 // This causes the TL-UL adapter to return a bus error.
279 tlul_rerror_o = 2'b11;
280 end
281 end
MISSING_ELSE
==>
282 end
283 ///////////////////////////////////////////////////////////////////
284 // Terminal Error State. This locks access to the partition.
285 // Make sure the partition signals an error state if no error
286 // code has been latched so far.
287 ErrorSt: begin
288 if (error_q == NoError) begin
-14-
289 error_d = FsmStateError;
==>
290 end
MISSING_ELSE
==>
291
292 // Return bus errors if there are pending TL-UL requests.
293 if (pending_tlul_error_q) begin
-15-
294 tlul_rerror_o = 2'b11;
==>
295 tlul_rvalid_o = 1'b1;
296 end else if (tlul_req_i) begin
-16-
297 tlul_gnt_o = 1'b1;
==>
298 pending_tlul_error_d = 1'b1;
299 end
MISSING_ELSE
==>
300 end
301 ///////////////////////////////////////////////////////////////////
302 // We should never get here. If we do (e.g. via a malicious
303 // glitch), error out immediately.
304 default: begin
305 state_d = ErrorSt;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | Status | Tests |
| ResetSt |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| ResetSt |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
| ResetSt |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| InitSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| InitSt |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| InitWaitSt |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T54,T42,T45 |
| InitWaitSt |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| InitWaitSt |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T182,T187,T188 |
| InitWaitSt |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| IdleSt |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T7,T4 |
| IdleSt |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| ReadSt |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T7,T4 |
| ReadSt |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T90,T196,T227 |
| ReadSt |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T12,T90 |
| ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
Covered |
T12,T146,T49 |
| ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
Covered |
T2,T7,T4 |
| ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
Covered |
T193,T192,T194 |
| ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T2,T7,T4 |
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T26,T27,T28 |
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T3,T7,T4 |
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T5,T125,T145 |
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
Covered |
T5,T125,T145 |
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
Covered |
T3,T7,T4 |
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T26,T27,T28 |
314 if (ecc_err) begin
-1-
315 state_d = ErrorSt;
316 if (state_q != ErrorSt) begin
-2-
317 error_d = CheckFailError;
==>
318 end
MISSING_ELSE
==>
319 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Covered |
T178,T186 |
| 1 |
0 |
Covered |
T178,T186 |
| 0 |
- |
Covered |
T1,T2,T3 |
321 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
-1-
322 state_d = ErrorSt;
323 fsm_err_o = 1'b1;
324 if (state_q != ErrorSt) begin
-2-
325 error_d = FsmStateError;
==>
326 end
MISSING_ELSE
==>
327 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Covered |
T3,T7,T4 |
| 1 |
0 |
Covered |
T3,T7,T4 |
| 0 |
- |
Covered |
T1,T2,T3 |
461 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
464 if (!rst_ni) begin
-1-
465 error_q <= NoError;
==>
466 tlul_addr_q <= '0;
467 pending_tlul_error_q <= 1'b0;
468 end else begin
469 error_q <= error_d;
470 pending_tlul_error_q <= pending_tlul_error_d;
471 if (tlul_gnt_o) begin
-2-
472 tlul_addr_q <= tlul_addr_d;
==>
473 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T7,T4 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf
Assertion Details
AccessKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
DigestKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
DigestOffsetMustBeRepresentable_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1125 |
1125 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
EccErrorState_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
6219 |
0 |
0 |
| T178 |
10677 |
3206 |
0 |
0 |
| T186 |
0 |
3013 |
0 |
0 |
| T198 |
11467 |
0 |
0 |
0 |
| T199 |
10216 |
0 |
0 |
0 |
| T200 |
14271 |
0 |
0 |
0 |
| T201 |
16828 |
0 |
0 |
0 |
| T202 |
10384 |
0 |
0 |
0 |
| T203 |
14629 |
0 |
0 |
0 |
| T204 |
14433 |
0 |
0 |
0 |
| T205 |
17128 |
0 |
0 |
0 |
| T206 |
14166 |
0 |
0 |
0 |
ErrorKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
FsmStateKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
InitDoneKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
InitReadLocksPartition_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
16465880 |
0 |
0 |
| T1 |
4785 |
120 |
0 |
0 |
| T2 |
13188 |
841 |
0 |
0 |
| T3 |
9679 |
2766 |
0 |
0 |
| T4 |
52297 |
2661 |
0 |
0 |
| T5 |
25244 |
8510 |
0 |
0 |
| T6 |
13766 |
242 |
0 |
0 |
| T7 |
17237 |
4152 |
0 |
0 |
| T10 |
23744 |
1133 |
0 |
0 |
| T11 |
43902 |
99 |
0 |
0 |
| T12 |
34978 |
2676 |
0 |
0 |
InitWriteLocksPartition_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
16465880 |
0 |
0 |
| T1 |
4785 |
120 |
0 |
0 |
| T2 |
13188 |
841 |
0 |
0 |
| T3 |
9679 |
2766 |
0 |
0 |
| T4 |
52297 |
2661 |
0 |
0 |
| T5 |
25244 |
8510 |
0 |
0 |
| T6 |
13766 |
242 |
0 |
0 |
| T7 |
17237 |
4152 |
0 |
0 |
| T10 |
23744 |
1133 |
0 |
0 |
| T11 |
43902 |
99 |
0 |
0 |
| T12 |
34978 |
2676 |
0 |
0 |
OffsetMustBeBlockAligned_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1125 |
1125 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
OtpAddrKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
OtpCmdKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
OtpErrorState_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
40 |
0 |
0 |
| T53 |
11428 |
0 |
0 |
0 |
| T78 |
95044 |
0 |
0 |
0 |
| T182 |
0 |
1 |
0 |
0 |
| T187 |
0 |
1 |
0 |
0 |
| T188 |
0 |
1 |
0 |
0 |
| T192 |
0 |
1 |
0 |
0 |
| T193 |
51087 |
1 |
0 |
0 |
| T194 |
0 |
1 |
0 |
0 |
| T219 |
0 |
1 |
0 |
0 |
| T242 |
0 |
1 |
0 |
0 |
| T243 |
0 |
1 |
0 |
0 |
| T244 |
0 |
1 |
0 |
0 |
| T245 |
66250 |
0 |
0 |
0 |
| T246 |
46742 |
0 |
0 |
0 |
| T247 |
15295 |
0 |
0 |
0 |
| T248 |
12582 |
0 |
0 |
0 |
| T249 |
89353 |
0 |
0 |
0 |
| T250 |
19177 |
0 |
0 |
0 |
| T251 |
16503 |
0 |
0 |
0 |
OtpReqKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
OtpSizeKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
OtpWdataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
ReadLockPropagation_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
15489539 |
0 |
0 |
| T4 |
52297 |
1075 |
0 |
0 |
| T5 |
25244 |
11585 |
0 |
0 |
| T6 |
13766 |
0 |
0 |
0 |
| T10 |
23744 |
0 |
0 |
0 |
| T11 |
43902 |
0 |
0 |
0 |
| T12 |
34978 |
11203 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T18 |
0 |
10944 |
0 |
0 |
| T23 |
20929 |
0 |
0 |
0 |
| T24 |
0 |
11104 |
0 |
0 |
| T90 |
77418 |
5326 |
0 |
0 |
| T93 |
0 |
16234 |
0 |
0 |
| T95 |
12284 |
0 |
0 |
0 |
| T97 |
0 |
2053 |
0 |
0 |
| T125 |
0 |
12444 |
0 |
0 |
| T146 |
0 |
8205 |
0 |
0 |
SizeMustBeBlockAligned_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1125 |
1125 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
TlulGntKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
TlulRdataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
TlulReadOnReadLock_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
6631 |
0 |
0 |
| T5 |
25244 |
8 |
0 |
0 |
| T6 |
13766 |
0 |
0 |
0 |
| T10 |
23744 |
0 |
0 |
0 |
| T11 |
43902 |
0 |
0 |
0 |
| T12 |
34978 |
3 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T18 |
0 |
2 |
0 |
0 |
| T23 |
20929 |
0 |
0 |
0 |
| T49 |
0 |
9 |
0 |
0 |
| T90 |
77418 |
7 |
0 |
0 |
| T93 |
0 |
14 |
0 |
0 |
| T95 |
12284 |
0 |
0 |
0 |
| T123 |
59629 |
0 |
0 |
0 |
| T125 |
0 |
14 |
0 |
0 |
| T145 |
0 |
1 |
0 |
0 |
| T146 |
0 |
14 |
0 |
0 |
| T222 |
0 |
7 |
0 |
0 |
TlulRerrorKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
TlulRvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
WriteLockPropagation_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
2065760 |
0 |
0 |
| T4 |
52297 |
2110 |
0 |
0 |
| T5 |
25244 |
0 |
0 |
0 |
| T6 |
13766 |
0 |
0 |
0 |
| T10 |
23744 |
0 |
0 |
0 |
| T11 |
43902 |
0 |
0 |
0 |
| T12 |
34978 |
0 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T18 |
0 |
12512 |
0 |
0 |
| T19 |
0 |
1439 |
0 |
0 |
| T23 |
20929 |
0 |
0 |
0 |
| T24 |
0 |
4165 |
0 |
0 |
| T49 |
0 |
8790 |
0 |
0 |
| T90 |
77418 |
1299 |
0 |
0 |
| T94 |
0 |
3397 |
0 |
0 |
| T95 |
12284 |
0 |
0 |
0 |
| T119 |
0 |
2754 |
0 |
0 |
| T127 |
0 |
7578 |
0 |
0 |
| T128 |
0 |
5507 |
0 |
0 |
gen_digest_write_lock.DigestWriteLocksPartition_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
26927615 |
0 |
0 |
| T3 |
9679 |
2554 |
0 |
0 |
| T4 |
52297 |
33718 |
0 |
0 |
| T5 |
25244 |
0 |
0 |
0 |
| T6 |
13766 |
3682 |
0 |
0 |
| T7 |
17237 |
0 |
0 |
0 |
| T10 |
23744 |
0 |
0 |
0 |
| T11 |
43902 |
0 |
0 |
0 |
| T12 |
34978 |
18245 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T24 |
0 |
62920 |
0 |
0 |
| T90 |
77418 |
58143 |
0 |
0 |
| T93 |
0 |
76413 |
0 |
0 |
| T97 |
0 |
36530 |
0 |
0 |
| T125 |
0 |
2878 |
0 |
0 |
| T146 |
0 |
19633 |
0 |
0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 88 | 88 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
| ALWAYS | 164 | 65 | 65 | 100.00 |
| CONT_ASSIGN | 334 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 342 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 350 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 354 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 395 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 454 | 1 | 1 | 100.00 |
| ALWAYS | 461 | 3 | 3 | 100.00 |
| ALWAYS | 464 | 8 | 8 | 100.00 |
137 // Output partition error state.
138 1/1 assign error_o = error_q;
Tests: T1 T2 T3
139
140 // This partition cannot do any write accesses, hence we tie this
141 // constantly off.
142 assign otp_wdata_o = '0;
143 // Depending on the partition configuration, the wrapper is instructed to ignore integrity
144 // calculations and checks. To be on the safe side, the partition filters error responses at this
145 // point and does not report any integrity errors if integrity is disabled.
146 otp_err_e otp_err;
147 if (Info.integrity) begin : gen_integrity
148 assign otp_cmd_o = prim_otp_pkg::Read;
149 1/1 assign otp_err = otp_err_e'(otp_err_i);
Tests: T1 T2 T3
150 end else begin : gen_no_integrity
151 assign otp_cmd_o = prim_otp_pkg::ReadRaw;
152 always_comb begin
153 if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin
154 otp_err = NoError;
155 end else begin
156 otp_err = otp_err_e'(otp_err_i);
157 end
158 end
159 end
160
161 `ASSERT_KNOWN(FsmStateKnown_A, state_q)
162 always_comb begin : p_fsm
163 // Default assignments
164 1/1 state_d = state_q;
Tests: T1 T2 T3
165
166 // Response to init request
167 1/1 init_done_o = 1'b0;
Tests: T1 T2 T3
168
169 // OTP signals
170 1/1 otp_req_o = 1'b0;
Tests: T1 T2 T3
171 1/1 otp_addr_sel = DigestAddrSel;
Tests: T1 T2 T3
172
173 // TL-UL signals
174 1/1 tlul_gnt_o = 1'b0;
Tests: T1 T2 T3
175 1/1 tlul_rvalid_o = 1'b0;
Tests: T1 T2 T3
176 1/1 tlul_rerror_o = '0;
Tests: T1 T2 T3
177
178 // Enable for buffered digest register
179 1/1 digest_reg_en = 1'b0;
Tests: T1 T2 T3
180
181 // Error Register
182 1/1 error_d = error_q;
Tests: T1 T2 T3
183 1/1 pending_tlul_error_d = 1'b0;
Tests: T1 T2 T3
184 1/1 fsm_err_o = 1'b0;
Tests: T1 T2 T3
185
186 1/1 unique case (state_q)
Tests: T1 T2 T3
187 ///////////////////////////////////////////////////////////////////
188 // State right after reset. Wait here until we get a an
189 // initialization request.
190 ResetSt: begin
191 1/1 if (init_req_i) begin
Tests: T1 T2 T3
192 // If the partition does not have a digest, no initialization is necessary.
193 1/1 if (Info.sw_digest) begin
Tests: T1 T2 T3
194 1/1 state_d = InitSt;
Tests: T1 T2 T3
195 end else begin
196 unreachable state_d = IdleSt;
197 end
198 end
MISSING_ELSE
199 end
200 ///////////////////////////////////////////////////////////////////
201 // Initialization reads out the digest only in unbuffered
202 // partitions. Wait here until the OTP request has been granted.
203 // And then wait until the OTP word comes back.
204 InitSt: begin
205 1/1 otp_req_o = 1'b1;
Tests: T1 T2 T3
206 1/1 if (otp_gnt_i) begin
Tests: T1 T2 T3
207 1/1 state_d = InitWaitSt;
Tests: T1 T2 T3
208 end
MISSING_ELSE
209 end
210 ///////////////////////////////////////////////////////////////////
211 // Wait for OTP response and write to digest buffer register. In
212 // case an OTP transaction fails, latch the OTP error code and
213 // jump to a terminal error state.
214 InitWaitSt: begin
215 1/1 if (otp_rvalid_i) begin
Tests: T1 T2 T3
216 1/1 digest_reg_en = 1'b1;
Tests: T1 T2 T3
217 1/1 if (otp_err inside {NoError, MacroEccCorrError}) begin
Tests: T1 T2 T3
218 1/1 state_d = IdleSt;
Tests: T1 T2 T3
219 // At this point the only error that we could have gotten are correctable ECC errors.
220 1/1 if (otp_err != NoError) begin
Tests: T1 T2 T3
221 1/1 error_d = MacroEccCorrError;
Tests: T54 T43 T56
222 end
MISSING_ELSE
223 end else begin
224 1/1 state_d = ErrorSt;
Tests: T95 T181 T195
225 1/1 error_d = otp_err;
Tests: T95 T181 T195
226 end
227 end
MISSING_ELSE
228 end
229 ///////////////////////////////////////////////////////////////////
230 // Wait for TL-UL requests coming in.
231 // Then latch address and go to readout state.
232 IdleSt: begin
233 1/1 init_done_o = 1'b1;
Tests: T1 T2 T3
234 1/1 if (tlul_req_i) begin
Tests: T1 T2 T3
235 1/1 error_d = NoError; // clear recoverable soft errors.
Tests: T2 T7 T4
236 1/1 state_d = ReadSt;
Tests: T2 T7 T4
237 1/1 tlul_gnt_o = 1'b1;
Tests: T2 T7 T4
238 end
MISSING_ELSE
239 end
240 ///////////////////////////////////////////////////////////////////
241 // If the address is out of bounds, or if the partition is
242 // locked, signal back a bus error. Note that such an error does
243 // not cause the partition to go into error state. Otherwise if
244 // these checks pass, an OTP word is requested.
245 ReadSt: begin
246 1/1 init_done_o = 1'b1;
Tests: T2 T7 T4
247 // Double check the address range.
248 1/1 if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
Tests: T2 T7 T4
249 1/1 otp_req_o = 1'b1;
Tests: T2 T7 T4
250 1/1 otp_addr_sel = DataAddrSel;
Tests: T2 T7 T4
251 1/1 if (otp_gnt_i) begin
Tests: T2 T7 T4
252 1/1 state_d = ReadWaitSt;
Tests: T2 T7 T4
253 end
MISSING_ELSE
254 end else begin
255 1/1 state_d = IdleSt;
Tests: T5 T12 T90
256 1/1 error_d = AccessError; // Signal this error, but do not go into terminal error state.
Tests: T5 T12 T90
257 1/1 tlul_rvalid_o = 1'b1;
Tests: T5 T12 T90
258 1/1 tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
Tests: T5 T12 T90
259 end
260 end
261 ///////////////////////////////////////////////////////////////////
262 // Wait for OTP response and release the TL-UL response. In
263 // case an OTP transaction fails, latch the OTP error code,
264 // signal a TL-Ul bus error and jump to a terminal error state.
265 ReadWaitSt: begin
266 1/1 init_done_o = 1'b1;
Tests: T2 T7 T4
267 1/1 if (otp_rvalid_i) begin
Tests: T2 T7 T4
268 1/1 tlul_rvalid_o = 1'b1;
Tests: T2 T7 T4
269 1/1 if (otp_err inside {NoError, MacroEccCorrError}) begin
Tests: T2 T7 T4
270 1/1 state_d = IdleSt;
Tests: T2 T7 T4
271 // At this point the only error that we could have gotten are correctable ECC errors.
272 1/1 if (otp_err != NoError) begin
Tests: T2 T7 T4
273 1/1 error_d = MacroEccCorrError;
Tests: T146 T176 T100
274 end
MISSING_ELSE
275 end else begin
276 1/1 state_d = ErrorSt;
Tests: T146 T117 T193
277 1/1 error_d = otp_err;
Tests: T146 T117 T193
278 // This causes the TL-UL adapter to return a bus error.
279 1/1 tlul_rerror_o = 2'b11;
Tests: T146 T117 T193
280 end
281 end
MISSING_ELSE
282 end
283 ///////////////////////////////////////////////////////////////////
284 // Terminal Error State. This locks access to the partition.
285 // Make sure the partition signals an error state if no error
286 // code has been latched so far.
287 ErrorSt: begin
288 1/1 if (error_q == NoError) begin
Tests: T3 T7 T4
289 1/1 error_d = FsmStateError;
Tests: T26 T27 T28
290 end
MISSING_ELSE
291
292 // Return bus errors if there are pending TL-UL requests.
293 1/1 if (pending_tlul_error_q) begin
Tests: T3 T7 T4
294 1/1 tlul_rerror_o = 2'b11;
Tests: T3 T5 T125
295 1/1 tlul_rvalid_o = 1'b1;
Tests: T3 T5 T125
296 1/1 end else if (tlul_req_i) begin
Tests: T3 T7 T4
297 1/1 tlul_gnt_o = 1'b1;
Tests: T3 T5 T125
298 1/1 pending_tlul_error_d = 1'b1;
Tests: T3 T5 T125
299 end
MISSING_ELSE
300 end
301 ///////////////////////////////////////////////////////////////////
302 // We should never get here. If we do (e.g. via a malicious
303 // glitch), error out immediately.
304 default: begin
305 state_d = ErrorSt;
306 fsm_err_o = 1'b1;
307 end
308 ///////////////////////////////////////////////////////////////////
309 endcase // state_q
310
311 // Unconditionally jump into the terminal error state in case of
312 // an ECC error or escalation, and lock access to the partition down.
313 // SEC_CM: PART.FSM.LOCAL_ESC
314 1/1 if (ecc_err) begin
Tests: T1 T2 T3
315 excluded state_d = ErrorSt;
Exclude Annotation: VC_COV_UNR
316 excluded if (state_q != ErrorSt) begin
Exclude Annotation: VC_COV_UNR
317 excluded error_d = CheckFailError;
Exclude Annotation: VC_COV_UNR
318 end
MISSING_ELSE
319 end
MISSING_ELSE
320 // SEC_CM: PART.FSM.GLOBAL_ESC
321 1/1 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
Tests: T1 T2 T3
322 1/1 state_d = ErrorSt;
Tests: T3 T7 T4
323 1/1 fsm_err_o = 1'b1;
Tests: T3 T7 T4
324 1/1 if (state_q != ErrorSt) begin
Tests: T3 T7 T4
325 1/1 error_d = FsmStateError;
Tests: T3 T7 T4
326 end
MISSING_ELSE
327 end
MISSING_ELSE
328 end
329
330 ///////////////////////////////////
331 // Signals to/from TL-UL Adapter //
332 ///////////////////////////////////
333
334 1/1 assign tlul_addr_d = tlul_addr_i;
Tests: T1 T2 T3
335 // Do not forward data in case of an error.
336 1/1 assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
Tests: T1 T2 T3
337
338 if (Info.offset == 0) begin : gen_zero_offset
339 assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd;
340
341 end else begin : gen_nonzero_offset
342 1/1 assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset &&
Tests: T1 T2 T3
343 {1'b0, tlul_addr_q, 2'b00} < PartEnd;
344 end
345
346 // Note that OTP works on halfword (16bit) addresses, hence need to
347 // shift the addresses appropriately.
348 logic [OtpByteAddrWidth-1:0] addr_calc;
349 1/1 assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
Tests: T1 T2 T3
350 1/1 assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift];
Tests: T1 T2 T3
351
352 if (OtpAddrShift > 0) begin : gen_unused
353 logic unused_bits;
354 1/1 assign unused_bits = ^addr_calc[OtpAddrShift-1:0];
Tests: T1 T2 T3
355 end
356
357 // Request 32bit except in case of the digest.
358 1/1 assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
Tests: T1 T2 T3
359 OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) :
360 OtpSizeWidth'(unsigned'(32 / OtpWidth - 1));
361
362 ////////////////
363 // Digest Reg //
364 ////////////////
365
366 if (Info.sw_digest) begin : gen_ecc_reg
367 // SEC_CM: PART.DATA_REG.INTEGRITY
368 otp_ctrl_ecc_reg #(
369 .Width ( ScrmblBlockWidth ),
370 .Depth ( 1 )
371 ) u_otp_ctrl_ecc_reg (
372 .clk_i,
373 .rst_ni,
374 .wren_i ( digest_reg_en ),
375 .addr_i ( '0 ),
376 .wdata_i ( otp_rdata_i ),
377 .rdata_o ( ),
378 .data_o ( digest_o ),
379 .ecc_err_o ( ecc_err )
380 );
381 end else begin : gen_no_ecc_reg
382 logic unused_digest_reg_en;
383 logic unused_rdata;
384 assign unused_digest_reg_en = digest_reg_en;
385 assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case.
386 assign digest_o = '0;
387 assign ecc_err = 1'b0;
388 end
389
390 ////////////////////////
391 // DAI Access Control //
392 ////////////////////////
393
394 mubi8_t init_locked;
395 1/1 assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
Tests: T1 T2 T3
396
397 // Aggregate all possible DAI write locks. The partition is also locked when uninitialized.
398 // Note that the locks are redundantly encoded values.
399 part_access_t access_pre;
400 prim_mubi8_sender #(
401 .AsyncOn(0)
402 ) u_prim_mubi8_sender_write_lock_pre (
403 .clk_i,
404 .rst_ni,
405 .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)),
406 .mubi_o(access_pre.write_lock)
407 );
408 prim_mubi8_sender #(
409 .AsyncOn(0)
410 ) u_prim_mubi8_sender_read_lock_pre (
411 .clk_i,
412 .rst_ni,
413 .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)),
414 .mubi_o(access_pre.read_lock)
415 );
416
417 // SEC_CM: PART.MEM.SW_UNWRITABLE
418 if (Info.write_lock) begin : gen_digest_write_lock
419 mubi8_t digest_locked;
420 1/1 assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
Tests: T1 T2 T3
421
422 // This prevents the synthesis tool from optimizing the multibit signal.
423 prim_mubi8_sender #(
424 .AsyncOn(0)
425 ) u_prim_mubi8_sender_write_lock (
426 .clk_i,
427 .rst_ni,
428 .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)),
429 .mubi_o(access_o.write_lock)
430 );
431
432 `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock))
433 end else begin : gen_no_digest_write_lock
434 assign access_o.write_lock = access_pre.write_lock;
435 end
436
437 // SEC_CM: PART.MEM.SW_UNREADABLE
438 if (Info.read_lock) begin : gen_digest_read_lock
439 mubi8_t digest_locked;
440 assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
441
442 // This prevents the synthesis tool from optimizing the multibit signal.
443 prim_mubi8_sender #(
444 .AsyncOn(0)
445 ) u_prim_mubi8_sender_read_lock (
446 .clk_i,
447 .rst_ni,
448 .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)),
449 .mubi_o(access_o.read_lock)
450 );
451
452 `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock))
453 end else begin : gen_no_digest_read_lock
454 1/1 assign access_o.read_lock = access_pre.read_lock;
Tests: T1 T2 T3
455 end
456
457 ///////////////
458 // Registers //
459 ///////////////
460
461 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
461.1 `ifdef SIMULATION
461.2 prim_sparse_fsm_flop #(
461.3 .StateEnumT(state_e),
461.4 .Width($bits(state_e)),
461.5 .ResetValue($bits(state_e)'(ResetSt)),
461.6 .EnableAlertTriggerSVA(1),
461.7 .CustomForceName("state_q")
461.8 ) u_state_regs (
461.9 .clk_i ( clk_i ),
461.10 .rst_ni ( rst_ni ),
461.11 .state_i ( state_d ),
461.12 .state_o ( )
461.13 );
461.14 always_ff @(posedge clk_i or negedge rst_ni) begin
461.15 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
461.16 1/1 state_q <= ResetSt;
Tests: T1 T2 T3
461.17 end else begin
461.18 1/1 state_q <= state_d;
Tests: T1 T2 T3
461.19 end
461.20 end
461.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))
461.22 else begin
461.23 `ifdef UVM
461.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
461.25 "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1);
461.26 `else
461.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
461.28 `PRIM_STRINGIFY(u_state_regs_A));
461.29 `endif
461.30 end
461.31 `else
461.32 prim_sparse_fsm_flop #(
461.33 .StateEnumT(state_e),
461.34 .Width($bits(state_e)),
461.35 .ResetValue($bits(state_e)'(ResetSt)),
461.36 .EnableAlertTriggerSVA(1)
461.37 ) u_state_regs (
461.38 .clk_i ( `PRIM_FLOP_CLK ),
461.39 .rst_ni ( `PRIM_FLOP_RST ),
461.40 .state_i ( state_d ),
461.41 .state_o ( state_q )
461.42 );
461.43 `endif462
463 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
464 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
465 1/1 error_q <= NoError;
Tests: T1 T2 T3
466 1/1 tlul_addr_q <= '0;
Tests: T1 T2 T3
467 1/1 pending_tlul_error_q <= 1'b0;
Tests: T1 T2 T3
468 end else begin
469 1/1 error_q <= error_d;
Tests: T1 T2 T3
470 1/1 pending_tlul_error_q <= pending_tlul_error_d;
Tests: T1 T2 T3
471 1/1 if (tlul_gnt_o) begin
Tests: T1 T2 T3
472 1/1 tlul_addr_q <= tlul_addr_d;
Tests: T2 T3 T7
473 end
MISSING_ELSE
Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf
| Total | Covered | Percent |
|---|
| Conditions | 31 | 31 | 100.00 |
| Logical | 31 | 31 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 220
EXPRESSION (otp_err != NoError)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T54,T43,T56 |
LINE 272
EXPRESSION (otp_err != NoError)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T7,T4 |
| 1 | Covered | T146,T176,T100 |
LINE 288
EXPRESSION (error_q == NoError)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T7,T4 |
| 1 | Covered | T26,T27,T28 |
LINE 316
EXPRESSION (state_q != ErrorSt)
----------1---------
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | T103,T178,T179 |
VC_COV_UNR |
| 1 | Excluded | T103,T178,T179 |
VC_COV_UNR |
LINE 324
EXPRESSION (state_q != ErrorSt)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T7,T4 |
| 1 | Covered | T3,T7,T4 |
LINE 336
EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T4 |
LINE 336
SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T5,T12 |
| 1 | 1 | Covered | T2,T7,T4 |
LINE 336
SUB-EXPRESSION (tlul_rerror_o == '0)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 342
EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
--------------------1------------------- ------------------2------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 349
EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T7,T4 |
| 1 | Covered | T1,T2,T3 |
LINE 349
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 358
EXPRESSION
Number Term
1 (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T7,T4 |
| 1 | Covered | T1,T2,T3 |
LINE 358
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 395
EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 420
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T12,T90 |
LINE 420
SUB-EXPRESSION (digest_o != '0)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T12,T90 |
FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
7 |
7 |
100.00 |
(Not included in score) |
| Transitions |
13 |
12 |
92.31 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| ErrorSt |
224 |
Covered |
T3,T7,T4 |
| IdleSt |
196 |
Covered |
T1,T2,T3 |
| InitSt |
194 |
Covered |
T1,T2,T3 |
| InitWaitSt |
207 |
Covered |
T1,T2,T3 |
| ReadSt |
236 |
Covered |
T2,T7,T4 |
| ReadWaitSt |
252 |
Covered |
T2,T7,T4 |
| ResetSt |
190 |
Covered |
T1,T2,T3 |
| transitions | Line No. | Covered | Tests | Exclude Annotation |
| IdleSt->ErrorSt |
315 |
Covered |
T3,T7,T4 |
|
| IdleSt->ReadSt |
236 |
Covered |
T2,T7,T4 |
|
| InitSt->ErrorSt |
315 |
Covered |
T96,T110,T183 |
|
| InitSt->InitWaitSt |
207 |
Covered |
T1,T2,T3 |
|
| InitWaitSt->ErrorSt |
224 |
Covered |
T95,T181,T182 |
|
| InitWaitSt->IdleSt |
218 |
Covered |
T1,T2,T3 |
|
| ReadSt->ErrorSt |
315 |
Not Covered |
|
|
| ReadSt->IdleSt |
255 |
Covered |
T5,T12,T90 |
|
| ReadSt->ReadWaitSt |
252 |
Covered |
T2,T7,T4 |
|
| ReadWaitSt->ErrorSt |
276 |
Covered |
T146,T117,T193 |
|
| ReadWaitSt->IdleSt |
270 |
Covered |
T2,T7,T4 |
|
| ResetSt->ErrorSt |
315 |
Covered |
T103,T104,T105 |
|
| ResetSt->IdleSt |
196 |
Excluded |
|
VC_COV_UNR |
| ResetSt->InitSt |
194 |
Covered |
T1,T2,T3 |
|
Summary for FSM :: error_q
| Total | Covered | Percent | |
| States |
4 |
4 |
100.00 |
(Not included in score) |
| Transitions |
8 |
8 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: error_q
| states | Line No. | Covered | Tests | Exclude Annotation |
| AccessError |
256 |
Covered |
T5,T12,T90 |
|
| CheckFailError |
317 |
Excluded |
T103,T178,T179 |
VC_COV_UNR |
| FsmStateError |
289 |
Covered |
T3,T7,T4 |
|
| MacroEccCorrError |
221 |
Covered |
T146,T54,T176 |
|
| NoError |
235 |
Covered |
T1,T2,T3 |
|
| transitions | Line No. | Covered | Tests | Exclude Annotation |
| AccessError->CheckFailError |
317 |
Excluded |
|
|
| AccessError->FsmStateError |
325 |
Covered |
T5,T146,T8 |
|
| AccessError->MacroEccCorrError |
221 |
Excluded |
|
VC_COV_UNR |
| AccessError->NoError |
235 |
Covered |
T5,T12,T90 |
|
| CheckFailError->AccessError |
256 |
Excluded |
|
|
| CheckFailError->FsmStateError |
325 |
Excluded |
|
|
| CheckFailError->MacroEccCorrError |
221 |
Excluded |
|
|
| CheckFailError->NoError |
235 |
Excluded |
T103,T178,T179 |
|
| FsmStateError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
| FsmStateError->CheckFailError |
317 |
Excluded |
|
|
| FsmStateError->MacroEccCorrError |
221 |
Excluded |
|
VC_COV_UNR |
| FsmStateError->NoError |
235 |
Covered |
T3,T7,T4 |
|
| MacroEccCorrError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
| MacroEccCorrError->CheckFailError |
317 |
Excluded |
|
|
| MacroEccCorrError->FsmStateError |
325 |
Covered |
T146,T54,T176 |
|
| MacroEccCorrError->NoError |
235 |
Covered |
T100,T184,T76 |
|
| NoError->AccessError |
256 |
Covered |
T5,T12,T90 |
|
| NoError->CheckFailError |
317 |
Excluded |
T103,T178,T179 |
|
| NoError->FsmStateError |
289 |
Covered |
T3,T7,T4 |
|
| NoError->MacroEccCorrError |
221 |
Covered |
T146,T54,T176 |
|
Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf
| Line No. | Total | Covered | Percent |
| Branches |
|
42 |
42 |
100.00 |
| TERNARY |
336 |
2 |
2 |
100.00 |
| TERNARY |
349 |
2 |
2 |
100.00 |
| TERNARY |
358 |
2 |
2 |
100.00 |
| TERNARY |
395 |
2 |
2 |
100.00 |
| TERNARY |
420 |
2 |
2 |
100.00 |
| CASE |
186 |
23 |
23 |
100.00 |
| IF |
314 |
1 |
1 |
100.00 |
| IF |
321 |
3 |
3 |
100.00 |
| IF |
461 |
2 |
2 |
100.00 |
| IF |
464 |
3 |
3 |
100.00 |
336 assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T4 |
| 0 |
Covered |
T1,T2,T3 |
349 assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T2,T7,T4 |
358 assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T2,T7,T4 |
395 assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
420 assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T12,T90 |
| 0 |
Covered |
T1,T2,T3 |
186 unique case (state_q)
-1-
187 ///////////////////////////////////////////////////////////////////
188 // State right after reset. Wait here until we get a an
189 // initialization request.
190 ResetSt: begin
191 if (init_req_i) begin
-2-
192 // If the partition does not have a digest, no initialization is necessary.
193 if (Info.sw_digest) begin
-3-
194 state_d = InitSt;
==>
195 end else begin
196 state_d = IdleSt;
==> (Unreachable)
197 end
198 end
MISSING_ELSE
==>
199 end
200 ///////////////////////////////////////////////////////////////////
201 // Initialization reads out the digest only in unbuffered
202 // partitions. Wait here until the OTP request has been granted.
203 // And then wait until the OTP word comes back.
204 InitSt: begin
205 otp_req_o = 1'b1;
206 if (otp_gnt_i) begin
-4-
207 state_d = InitWaitSt;
==>
208 end
MISSING_ELSE
==>
209 end
210 ///////////////////////////////////////////////////////////////////
211 // Wait for OTP response and write to digest buffer register. In
212 // case an OTP transaction fails, latch the OTP error code and
213 // jump to a terminal error state.
214 InitWaitSt: begin
215 if (otp_rvalid_i) begin
-5-
216 digest_reg_en = 1'b1;
217 if (otp_err inside {NoError, MacroEccCorrError}) begin
-6-
218 state_d = IdleSt;
219 // At this point the only error that we could have gotten are correctable ECC errors.
220 if (otp_err != NoError) begin
-7-
221 error_d = MacroEccCorrError;
==>
222 end
MISSING_ELSE
==>
223 end else begin
224 state_d = ErrorSt;
==>
225 error_d = otp_err;
226 end
227 end
MISSING_ELSE
==>
228 end
229 ///////////////////////////////////////////////////////////////////
230 // Wait for TL-UL requests coming in.
231 // Then latch address and go to readout state.
232 IdleSt: begin
233 init_done_o = 1'b1;
234 if (tlul_req_i) begin
-8-
235 error_d = NoError; // clear recoverable soft errors.
==>
236 state_d = ReadSt;
237 tlul_gnt_o = 1'b1;
238 end
MISSING_ELSE
==>
239 end
240 ///////////////////////////////////////////////////////////////////
241 // If the address is out of bounds, or if the partition is
242 // locked, signal back a bus error. Note that such an error does
243 // not cause the partition to go into error state. Otherwise if
244 // these checks pass, an OTP word is requested.
245 ReadSt: begin
246 init_done_o = 1'b1;
247 // Double check the address range.
248 if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
-9-
249 otp_req_o = 1'b1;
250 otp_addr_sel = DataAddrSel;
251 if (otp_gnt_i) begin
-10-
252 state_d = ReadWaitSt;
==>
253 end
MISSING_ELSE
==>
254 end else begin
255 state_d = IdleSt;
==>
256 error_d = AccessError; // Signal this error, but do not go into terminal error state.
257 tlul_rvalid_o = 1'b1;
258 tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
259 end
260 end
261 ///////////////////////////////////////////////////////////////////
262 // Wait for OTP response and release the TL-UL response. In
263 // case an OTP transaction fails, latch the OTP error code,
264 // signal a TL-Ul bus error and jump to a terminal error state.
265 ReadWaitSt: begin
266 init_done_o = 1'b1;
267 if (otp_rvalid_i) begin
-11-
268 tlul_rvalid_o = 1'b1;
269 if (otp_err inside {NoError, MacroEccCorrError}) begin
-12-
270 state_d = IdleSt;
271 // At this point the only error that we could have gotten are correctable ECC errors.
272 if (otp_err != NoError) begin
-13-
273 error_d = MacroEccCorrError;
==>
274 end
MISSING_ELSE
==>
275 end else begin
276 state_d = ErrorSt;
==>
277 error_d = otp_err;
278 // This causes the TL-UL adapter to return a bus error.
279 tlul_rerror_o = 2'b11;
280 end
281 end
MISSING_ELSE
==>
282 end
283 ///////////////////////////////////////////////////////////////////
284 // Terminal Error State. This locks access to the partition.
285 // Make sure the partition signals an error state if no error
286 // code has been latched so far.
287 ErrorSt: begin
288 if (error_q == NoError) begin
-14-
289 error_d = FsmStateError;
==>
290 end
MISSING_ELSE
==>
291
292 // Return bus errors if there are pending TL-UL requests.
293 if (pending_tlul_error_q) begin
-15-
294 tlul_rerror_o = 2'b11;
==>
295 tlul_rvalid_o = 1'b1;
296 end else if (tlul_req_i) begin
-16-
297 tlul_gnt_o = 1'b1;
==>
298 pending_tlul_error_d = 1'b1;
299 end
MISSING_ELSE
==>
300 end
301 ///////////////////////////////////////////////////////////////////
302 // We should never get here. If we do (e.g. via a malicious
303 // glitch), error out immediately.
304 default: begin
305 state_d = ErrorSt;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | Status | Tests |
| ResetSt |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| ResetSt |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
| ResetSt |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| InitSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| InitSt |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| InitWaitSt |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T54,T43,T56 |
| InitWaitSt |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| InitWaitSt |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T95,T181,T195 |
| InitWaitSt |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| IdleSt |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T7,T4 |
| IdleSt |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| ReadSt |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T7,T4 |
| ReadSt |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T90,T196,T113 |
| ReadSt |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T12,T90 |
| ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
Covered |
T146,T176,T100 |
| ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
Covered |
T2,T7,T4 |
| ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
Covered |
T146,T117,T193 |
| ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T2,T7,T4 |
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T26,T27,T28 |
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T3,T7,T4 |
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T3,T5,T125 |
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
Covered |
T3,T5,T125 |
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
Covered |
T3,T7,T4 |
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T26,T27,T28 |
314 if (ecc_err) begin
-1-
315 state_d = ErrorSt;
316 if (state_q != ErrorSt) begin
-2-
317 error_d = CheckFailError;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
318 end
MISSING_ELSE
==> (Excluded)
Exclude Annotation: VC_COV_UNR
319 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
1 |
Excluded |
T103,T178,T179 |
VC_COV_UNR |
| 1 |
0 |
Excluded |
T103,T178,T179 |
VC_COV_UNR |
| 0 |
- |
Covered |
T1,T2,T3 |
|
321 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
-1-
322 state_d = ErrorSt;
323 fsm_err_o = 1'b1;
324 if (state_q != ErrorSt) begin
-2-
325 error_d = FsmStateError;
==>
326 end
MISSING_ELSE
==>
327 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Covered |
T3,T7,T4 |
| 1 |
0 |
Covered |
T3,T7,T4 |
| 0 |
- |
Covered |
T1,T2,T3 |
461 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
464 if (!rst_ni) begin
-1-
465 error_q <= NoError;
==>
466 tlul_addr_q <= '0;
467 pending_tlul_error_q <= 1'b0;
468 end else begin
469 error_q <= error_d;
470 pending_tlul_error_q <= pending_tlul_error_d;
471 if (tlul_gnt_o) begin
-2-
472 tlul_addr_q <= tlul_addr_d;
==>
473 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T3,T7 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf
Assertion Details
AccessKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
DigestKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
DigestOffsetMustBeRepresentable_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1125 |
1125 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
EccErrorState_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
11027 |
0 |
0 |
| T103 |
14630 |
2345 |
0 |
0 |
| T178 |
0 |
3206 |
0 |
0 |
| T179 |
0 |
2435 |
0 |
0 |
| T180 |
0 |
3041 |
0 |
0 |
| T193 |
51087 |
0 |
0 |
0 |
| T236 |
16824 |
0 |
0 |
0 |
| T252 |
14831 |
0 |
0 |
0 |
| T253 |
15764 |
0 |
0 |
0 |
| T254 |
77882 |
0 |
0 |
0 |
| T255 |
22956 |
0 |
0 |
0 |
| T256 |
23858 |
0 |
0 |
0 |
| T257 |
72079 |
0 |
0 |
0 |
| T258 |
106412 |
0 |
0 |
0 |
ErrorKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
FsmStateKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
InitDoneKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
InitReadLocksPartition_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
16645202 |
0 |
0 |
| T1 |
4785 |
137 |
0 |
0 |
| T2 |
13188 |
909 |
0 |
0 |
| T3 |
9679 |
2817 |
0 |
0 |
| T4 |
52297 |
2780 |
0 |
0 |
| T5 |
25244 |
8561 |
0 |
0 |
| T6 |
13766 |
276 |
0 |
0 |
| T7 |
17237 |
4203 |
0 |
0 |
| T10 |
23744 |
1235 |
0 |
0 |
| T11 |
43902 |
116 |
0 |
0 |
| T12 |
34978 |
2778 |
0 |
0 |
InitWriteLocksPartition_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
16645202 |
0 |
0 |
| T1 |
4785 |
137 |
0 |
0 |
| T2 |
13188 |
909 |
0 |
0 |
| T3 |
9679 |
2817 |
0 |
0 |
| T4 |
52297 |
2780 |
0 |
0 |
| T5 |
25244 |
8561 |
0 |
0 |
| T6 |
13766 |
276 |
0 |
0 |
| T7 |
17237 |
4203 |
0 |
0 |
| T10 |
23744 |
1235 |
0 |
0 |
| T11 |
43902 |
116 |
0 |
0 |
| T12 |
34978 |
2778 |
0 |
0 |
OffsetMustBeBlockAligned_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1125 |
1125 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
OtpAddrKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
OtpCmdKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
OtpErrorState_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
30 |
0 |
0 |
| T23 |
20929 |
0 |
0 |
0 |
| T24 |
73395 |
0 |
0 |
0 |
| T93 |
84500 |
0 |
0 |
0 |
| T95 |
12284 |
1 |
0 |
0 |
| T97 |
53418 |
0 |
0 |
0 |
| T117 |
0 |
1 |
0 |
0 |
| T123 |
59629 |
0 |
0 |
0 |
| T124 |
30026 |
0 |
0 |
0 |
| T125 |
19761 |
0 |
0 |
0 |
| T126 |
27618 |
0 |
0 |
0 |
| T145 |
38670 |
0 |
0 |
0 |
| T146 |
0 |
1 |
0 |
0 |
| T172 |
0 |
1 |
0 |
0 |
| T181 |
0 |
1 |
0 |
0 |
| T192 |
0 |
1 |
0 |
0 |
| T193 |
0 |
1 |
0 |
0 |
| T195 |
0 |
1 |
0 |
0 |
| T259 |
0 |
1 |
0 |
0 |
| T260 |
0 |
1 |
0 |
0 |
OtpReqKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
OtpSizeKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
OtpWdataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
ReadLockPropagation_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
16092232 |
0 |
0 |
| T4 |
52297 |
1063 |
0 |
0 |
| T5 |
25244 |
11948 |
0 |
0 |
| T6 |
13766 |
0 |
0 |
0 |
| T10 |
23744 |
0 |
0 |
0 |
| T11 |
43902 |
0 |
0 |
0 |
| T12 |
34978 |
11793 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T18 |
0 |
14234 |
0 |
0 |
| T23 |
20929 |
0 |
0 |
0 |
| T24 |
0 |
8383 |
0 |
0 |
| T49 |
0 |
27307 |
0 |
0 |
| T90 |
77418 |
4738 |
0 |
0 |
| T93 |
0 |
17296 |
0 |
0 |
| T95 |
12284 |
0 |
0 |
0 |
| T97 |
0 |
1058 |
0 |
0 |
| T146 |
0 |
8192 |
0 |
0 |
SizeMustBeBlockAligned_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1125 |
1125 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
TlulGntKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
TlulRdataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
TlulReadOnReadLock_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
6297 |
0 |
0 |
| T3 |
9679 |
2 |
0 |
0 |
| T4 |
52297 |
0 |
0 |
0 |
| T5 |
25244 |
8 |
0 |
0 |
| T6 |
13766 |
0 |
0 |
0 |
| T7 |
17237 |
0 |
0 |
0 |
| T10 |
23744 |
0 |
0 |
0 |
| T11 |
43902 |
0 |
0 |
0 |
| T12 |
34978 |
9 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T18 |
0 |
1 |
0 |
0 |
| T24 |
0 |
2 |
0 |
0 |
| T90 |
77418 |
8 |
0 |
0 |
| T93 |
0 |
8 |
0 |
0 |
| T125 |
0 |
8 |
0 |
0 |
| T145 |
0 |
1 |
0 |
0 |
| T146 |
0 |
20 |
0 |
0 |
TlulRerrorKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
TlulRvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
WriteLockPropagation_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
850653 |
0 |
0 |
| T20 |
0 |
7691 |
0 |
0 |
| T23 |
20929 |
0 |
0 |
0 |
| T24 |
73395 |
4455 |
0 |
0 |
| T59 |
0 |
11726 |
0 |
0 |
| T90 |
77418 |
1438 |
0 |
0 |
| T93 |
84500 |
8712 |
0 |
0 |
| T95 |
12284 |
0 |
0 |
0 |
| T97 |
53418 |
0 |
0 |
0 |
| T123 |
59629 |
0 |
0 |
0 |
| T124 |
30026 |
0 |
0 |
0 |
| T125 |
19761 |
0 |
0 |
0 |
| T126 |
27618 |
0 |
0 |
0 |
| T128 |
0 |
2779 |
0 |
0 |
| T261 |
0 |
2190 |
0 |
0 |
| T262 |
0 |
36718 |
0 |
0 |
| T263 |
0 |
21415 |
0 |
0 |
| T264 |
0 |
4120 |
0 |
0 |
gen_digest_write_lock.DigestWriteLocksPartition_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
11287553 |
0 |
0 |
| T4 |
52297 |
43292 |
0 |
0 |
| T5 |
25244 |
0 |
0 |
0 |
| T6 |
13766 |
0 |
0 |
0 |
| T10 |
23744 |
0 |
0 |
0 |
| T11 |
43902 |
0 |
0 |
0 |
| T12 |
34978 |
18177 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T23 |
20929 |
0 |
0 |
0 |
| T24 |
0 |
62631 |
0 |
0 |
| T49 |
0 |
70599 |
0 |
0 |
| T90 |
77418 |
57888 |
0 |
0 |
| T93 |
0 |
76226 |
0 |
0 |
| T95 |
12284 |
2765 |
0 |
0 |
| T97 |
0 |
36360 |
0 |
0 |
| T124 |
0 |
15465 |
0 |
0 |
| T146 |
0 |
5379 |
0 |
0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |