Line Coverage for Module :
prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Line Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T2 T3 T7
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T2 T3 T7
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T2 T3 T7
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Line Coverage for Module :
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T2 T3 T7
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T2 T3 T7
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T2 T3 T7
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Line Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T2 T3 T7
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T2 T3 T7
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Line Coverage for Module :
prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T2 T3
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 11 | 68.75 |
| Logical | 16 | 11 | 68.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T7 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T2,T7,T4 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T7 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 24 | 18 | 75.00 |
| Logical | 24 | 18 | 75.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T4,T11 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T7,T4,T11 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T4,T11 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T7 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 11 | 68.75 |
| Logical | 16 | 11 | 68.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T7 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T2,T7,T4 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T7 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 24 | 18 | 75.00 |
| Logical | 24 | 18 | 75.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
9 |
9 |
100.00 |
| TERNARY |
130 |
2 |
2 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T2,T3,T7 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
881950990 |
63982547 |
0 |
0 |
| T1 |
23925 |
1714 |
0 |
0 |
| T2 |
131880 |
9461 |
0 |
0 |
| T3 |
96790 |
6822 |
0 |
0 |
| T4 |
522970 |
22331 |
0 |
0 |
| T5 |
252440 |
26558 |
0 |
0 |
| T6 |
137660 |
12460 |
0 |
0 |
| T7 |
172370 |
14155 |
0 |
0 |
| T10 |
237440 |
15271 |
0 |
0 |
| T11 |
439020 |
54662 |
0 |
0 |
| T12 |
349780 |
31085 |
0 |
0 |
| T17 |
30150 |
0 |
0 |
0 |
| T90 |
0 |
637 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
881950990 |
872998594 |
0 |
0 |
| T1 |
47850 |
47140 |
0 |
0 |
| T2 |
131880 |
129470 |
0 |
0 |
| T3 |
96790 |
94280 |
0 |
0 |
| T4 |
522970 |
515080 |
0 |
0 |
| T5 |
252440 |
249630 |
0 |
0 |
| T6 |
137660 |
135990 |
0 |
0 |
| T7 |
172370 |
169550 |
0 |
0 |
| T10 |
237440 |
232320 |
0 |
0 |
| T11 |
439020 |
438300 |
0 |
0 |
| T12 |
349780 |
345340 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
881950990 |
872998594 |
0 |
0 |
| T1 |
47850 |
47140 |
0 |
0 |
| T2 |
131880 |
129470 |
0 |
0 |
| T3 |
96790 |
94280 |
0 |
0 |
| T4 |
522970 |
515080 |
0 |
0 |
| T5 |
252440 |
249630 |
0 |
0 |
| T6 |
137660 |
135990 |
0 |
0 |
| T7 |
172370 |
169550 |
0 |
0 |
| T10 |
237440 |
232320 |
0 |
0 |
| T11 |
439020 |
438300 |
0 |
0 |
| T12 |
349780 |
345340 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
881950990 |
872998594 |
0 |
0 |
| T1 |
47850 |
47140 |
0 |
0 |
| T2 |
131880 |
129470 |
0 |
0 |
| T3 |
96790 |
94280 |
0 |
0 |
| T4 |
522970 |
515080 |
0 |
0 |
| T5 |
252440 |
249630 |
0 |
0 |
| T6 |
137660 |
135990 |
0 |
0 |
| T7 |
172370 |
169550 |
0 |
0 |
| T10 |
237440 |
232320 |
0 |
0 |
| T11 |
439020 |
438300 |
0 |
0 |
| T12 |
349780 |
345340 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
881950990 |
872998594 |
0 |
0 |
| T1 |
47850 |
47140 |
0 |
0 |
| T2 |
131880 |
129470 |
0 |
0 |
| T3 |
96790 |
94280 |
0 |
0 |
| T4 |
522970 |
515080 |
0 |
0 |
| T5 |
252440 |
249630 |
0 |
0 |
| T6 |
137660 |
135990 |
0 |
0 |
| T7 |
172370 |
169550 |
0 |
0 |
| T10 |
237440 |
232320 |
0 |
0 |
| T11 |
439020 |
438300 |
0 |
0 |
| T12 |
349780 |
345340 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
345448828 |
18286980 |
0 |
0 |
| T1 |
4785 |
1574 |
0 |
0 |
| T2 |
52752 |
4701 |
0 |
0 |
| T3 |
38716 |
2886 |
0 |
0 |
| T4 |
209188 |
12231 |
0 |
0 |
| T5 |
100976 |
3882 |
0 |
0 |
| T6 |
55064 |
3552 |
0 |
0 |
| T7 |
68948 |
4539 |
0 |
0 |
| T10 |
94976 |
7327 |
0 |
0 |
| T11 |
175608 |
21536 |
0 |
0 |
| T12 |
139912 |
8217 |
0 |
0 |
| T17 |
18090 |
0 |
0 |
0 |
| T90 |
0 |
527 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
7794 |
7794 |
0 |
0 |
| T1 |
6 |
6 |
0 |
0 |
| T2 |
6 |
6 |
0 |
0 |
| T3 |
6 |
6 |
0 |
0 |
| T4 |
6 |
6 |
0 |
0 |
| T5 |
6 |
6 |
0 |
0 |
| T6 |
6 |
6 |
0 |
0 |
| T7 |
6 |
6 |
0 |
0 |
| T10 |
6 |
6 |
0 |
0 |
| T11 |
6 |
6 |
0 |
0 |
| T12 |
6 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
9633057 |
0 |
0 |
| T1 |
4785 |
19 |
0 |
0 |
| T2 |
13188 |
1190 |
0 |
0 |
| T3 |
9679 |
984 |
0 |
0 |
| T4 |
52297 |
2516 |
0 |
0 |
| T5 |
25244 |
5669 |
0 |
0 |
| T6 |
13766 |
2227 |
0 |
0 |
| T7 |
17237 |
891 |
0 |
0 |
| T10 |
23744 |
1986 |
0 |
0 |
| T11 |
43902 |
3936 |
0 |
0 |
| T12 |
34978 |
5717 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1299 |
1299 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
13469721 |
0 |
0 |
| T1 |
4785 |
51 |
0 |
0 |
| T2 |
13188 |
1190 |
0 |
0 |
| T3 |
9679 |
984 |
0 |
0 |
| T4 |
52297 |
2534 |
0 |
0 |
| T5 |
25244 |
5669 |
0 |
0 |
| T6 |
13766 |
2227 |
0 |
0 |
| T7 |
17237 |
3917 |
0 |
0 |
| T10 |
23744 |
1986 |
0 |
0 |
| T11 |
43902 |
12627 |
0 |
0 |
| T12 |
34978 |
5717 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1299 |
1299 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
1278605 |
0 |
0 |
| T2 |
13188 |
9 |
0 |
0 |
| T3 |
9679 |
3 |
0 |
0 |
| T4 |
52297 |
6 |
0 |
0 |
| T5 |
25244 |
46 |
0 |
0 |
| T6 |
13766 |
2 |
0 |
0 |
| T7 |
17237 |
25 |
0 |
0 |
| T10 |
23744 |
4 |
0 |
0 |
| T11 |
43902 |
404 |
0 |
0 |
| T12 |
34978 |
31 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T90 |
0 |
55 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1299 |
1299 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
1180759 |
0 |
0 |
| T2 |
13188 |
9 |
0 |
0 |
| T3 |
9679 |
3 |
0 |
0 |
| T4 |
52297 |
24 |
0 |
0 |
| T5 |
25244 |
46 |
0 |
0 |
| T6 |
13766 |
2 |
0 |
0 |
| T7 |
17237 |
96 |
0 |
0 |
| T10 |
23744 |
4 |
0 |
0 |
| T11 |
43902 |
1720 |
0 |
0 |
| T12 |
34978 |
31 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T90 |
0 |
55 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1299 |
1299 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
7844463 |
0 |
0 |
| T1 |
4785 |
19 |
0 |
0 |
| T2 |
13188 |
1181 |
0 |
0 |
| T3 |
9679 |
981 |
0 |
0 |
| T4 |
52297 |
2510 |
0 |
0 |
| T5 |
25244 |
5623 |
0 |
0 |
| T6 |
13766 |
2225 |
0 |
0 |
| T7 |
17237 |
866 |
0 |
0 |
| T10 |
23744 |
1982 |
0 |
0 |
| T11 |
43902 |
3532 |
0 |
0 |
| T12 |
34978 |
5686 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1299 |
1299 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
12288962 |
0 |
0 |
| T1 |
4785 |
51 |
0 |
0 |
| T2 |
13188 |
1181 |
0 |
0 |
| T3 |
9679 |
981 |
0 |
0 |
| T4 |
52297 |
2510 |
0 |
0 |
| T5 |
25244 |
5623 |
0 |
0 |
| T6 |
13766 |
2225 |
0 |
0 |
| T7 |
17237 |
3821 |
0 |
0 |
| T10 |
23744 |
1982 |
0 |
0 |
| T11 |
43902 |
10907 |
0 |
0 |
| T12 |
34978 |
5686 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
89417027 |
88501027 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1299 |
1299 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T2 T3 T7
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T2 T3 T7
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T2 T3 T7
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
| Total | Covered | Percent |
|---|
| Conditions | 11 | 11 | 100.00 |
| Logical | 11 | 11 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T7 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Covered | T2,T7,T4 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T7 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T2,T3,T7 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
1624744 |
0 |
0 |
| T2 |
13188 |
90 |
0 |
0 |
| T3 |
9679 |
3 |
0 |
0 |
| T4 |
52297 |
78 |
0 |
0 |
| T5 |
25244 |
91 |
0 |
0 |
| T6 |
13766 |
20 |
0 |
0 |
| T7 |
17237 |
321 |
0 |
0 |
| T10 |
23744 |
40 |
0 |
0 |
| T11 |
43902 |
5356 |
0 |
0 |
| T12 |
34978 |
130 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T90 |
0 |
236 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
1624744 |
0 |
0 |
| T2 |
13188 |
90 |
0 |
0 |
| T3 |
9679 |
3 |
0 |
0 |
| T4 |
52297 |
78 |
0 |
0 |
| T5 |
25244 |
91 |
0 |
0 |
| T6 |
13766 |
20 |
0 |
0 |
| T7 |
17237 |
321 |
0 |
0 |
| T10 |
23744 |
40 |
0 |
0 |
| T11 |
43902 |
5356 |
0 |
0 |
| T12 |
34978 |
130 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T90 |
0 |
236 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T2 T3 T7
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T2 T3 T7
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T2 T3 T7
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
| Total | Covered | Percent |
|---|
| Conditions | 11 | 11 | 100.00 |
| Logical | 11 | 11 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T7 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Covered | T2,T7,T4 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T7 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T2,T3,T7 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
551219 |
0 |
0 |
| T2 |
13188 |
90 |
0 |
0 |
| T3 |
9679 |
3 |
0 |
0 |
| T4 |
52297 |
60 |
0 |
0 |
| T5 |
25244 |
91 |
0 |
0 |
| T6 |
13766 |
20 |
0 |
0 |
| T7 |
17237 |
250 |
0 |
0 |
| T10 |
23744 |
40 |
0 |
0 |
| T11 |
43902 |
4040 |
0 |
0 |
| T12 |
34978 |
130 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T90 |
0 |
236 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
551219 |
0 |
0 |
| T2 |
13188 |
90 |
0 |
0 |
| T3 |
9679 |
3 |
0 |
0 |
| T4 |
52297 |
60 |
0 |
0 |
| T5 |
25244 |
91 |
0 |
0 |
| T6 |
13766 |
20 |
0 |
0 |
| T7 |
17237 |
250 |
0 |
0 |
| T10 |
23744 |
40 |
0 |
0 |
| T11 |
43902 |
4040 |
0 |
0 |
| T12 |
34978 |
130 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T90 |
0 |
236 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T2 T3 T7
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T2 T3 T7
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
| Total | Covered | Percent |
|---|
| Conditions | 18 | 18 | 100.00 |
| Logical | 18 | 18 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T4,T11 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Covered | T7,T4,T11 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T4,T11 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T7 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
9 |
9 |
100.00 |
| TERNARY |
130 |
2 |
2 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T2,T3,T7 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
189826 |
0 |
0 |
| T2 |
13188 |
9 |
0 |
0 |
| T3 |
9679 |
3 |
0 |
0 |
| T4 |
52297 |
24 |
0 |
0 |
| T5 |
25244 |
46 |
0 |
0 |
| T6 |
13766 |
2 |
0 |
0 |
| T7 |
17237 |
96 |
0 |
0 |
| T10 |
23744 |
4 |
0 |
0 |
| T11 |
43902 |
1720 |
0 |
0 |
| T12 |
34978 |
31 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T90 |
0 |
55 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
189826 |
0 |
0 |
| T2 |
13188 |
9 |
0 |
0 |
| T3 |
9679 |
3 |
0 |
0 |
| T4 |
52297 |
24 |
0 |
0 |
| T5 |
25244 |
46 |
0 |
0 |
| T6 |
13766 |
2 |
0 |
0 |
| T7 |
17237 |
96 |
0 |
0 |
| T10 |
23744 |
4 |
0 |
0 |
| T11 |
43902 |
1720 |
0 |
0 |
| T12 |
34978 |
31 |
0 |
0 |
| T17 |
6030 |
0 |
0 |
0 |
| T90 |
0 |
55 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_otp_rsp_fifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T2 T3
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp_rsp_fifo
| Total | Covered | Percent |
|---|
| Conditions | 18 | 18 | 100.00 |
| Logical | 18 | 18 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_otp_rsp_fifo
| Line No. | Total | Covered | Percent |
| Branches |
|
9 |
9 |
100.00 |
| TERNARY |
130 |
2 |
2 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_otp_rsp_fifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
15921191 |
0 |
0 |
| T1 |
4785 |
1574 |
0 |
0 |
| T2 |
13188 |
4512 |
0 |
0 |
| T3 |
9679 |
2877 |
0 |
0 |
| T4 |
52297 |
12069 |
0 |
0 |
| T5 |
25244 |
3654 |
0 |
0 |
| T6 |
13766 |
3510 |
0 |
0 |
| T7 |
17237 |
3872 |
0 |
0 |
| T10 |
23744 |
7243 |
0 |
0 |
| T11 |
43902 |
10420 |
0 |
0 |
| T12 |
34978 |
7926 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
85498108 |
0 |
0 |
| T1 |
4785 |
4714 |
0 |
0 |
| T2 |
13188 |
12947 |
0 |
0 |
| T3 |
9679 |
9428 |
0 |
0 |
| T4 |
52297 |
51508 |
0 |
0 |
| T5 |
25244 |
24963 |
0 |
0 |
| T6 |
13766 |
13599 |
0 |
0 |
| T7 |
17237 |
16955 |
0 |
0 |
| T10 |
23744 |
23232 |
0 |
0 |
| T11 |
43902 |
43830 |
0 |
0 |
| T12 |
34978 |
34534 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
86362207 |
15921191 |
0 |
0 |
| T1 |
4785 |
1574 |
0 |
0 |
| T2 |
13188 |
4512 |
0 |
0 |
| T3 |
9679 |
2877 |
0 |
0 |
| T4 |
52297 |
12069 |
0 |
0 |
| T5 |
25244 |
3654 |
0 |
0 |
| T6 |
13766 |
3510 |
0 |
0 |
| T7 |
17237 |
3872 |
0 |
0 |
| T10 |
23744 |
7243 |
0 |
0 |
| T11 |
43902 |
10420 |
0 |
0 |
| T12 |
34978 |
7926 |
0 |
0 |