| T1065 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.2348785245 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:07 PM UTC 24 |
444536989 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.2596905121 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:07 PM UTC 24 |
167517856 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.1410778421 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:07 PM UTC 24 |
182130833 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.2345461783 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:07 PM UTC 24 |
166256804 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_init_fail.1976330542 |
|
|
Oct 09 08:55:01 PM UTC 24 |
Oct 09 08:55:07 PM UTC 24 |
343610419 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.2512350989 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:08 PM UTC 24 |
126943230 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.1842674 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:08 PM UTC 24 |
323207567 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.4110555026 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:08 PM UTC 24 |
403871596 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.2274522729 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:08 PM UTC 24 |
921814843 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.3283008783 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:08 PM UTC 24 |
1863866182 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.464118873 |
|
|
Oct 09 08:55:03 PM UTC 24 |
Oct 09 08:55:08 PM UTC 24 |
264563284 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.814828421 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:08 PM UTC 24 |
192301173 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.2795570510 |
|
|
Oct 09 08:55:03 PM UTC 24 |
Oct 09 08:55:08 PM UTC 24 |
545778167 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.4288518600 |
|
|
Oct 09 08:55:03 PM UTC 24 |
Oct 09 08:55:08 PM UTC 24 |
322888248 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.3569107884 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:08 PM UTC 24 |
1568771809 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.1370232405 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:08 PM UTC 24 |
266298055 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.3750662696 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:10 PM UTC 24 |
2037044265 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_init_fail.4209605714 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:09 PM UTC 24 |
2125120235 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.609614743 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:09 PM UTC 24 |
572442422 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.243144543 |
|
|
Oct 09 08:55:03 PM UTC 24 |
Oct 09 08:55:09 PM UTC 24 |
148965148 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.1888970501 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:09 PM UTC 24 |
146626695 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.3639635595 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:09 PM UTC 24 |
236649758 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.2433088769 |
|
|
Oct 09 08:55:03 PM UTC 24 |
Oct 09 08:55:09 PM UTC 24 |
350241067 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.3434136949 |
|
|
Oct 09 08:55:03 PM UTC 24 |
Oct 09 08:55:09 PM UTC 24 |
211476202 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.3401322595 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:10 PM UTC 24 |
4073213379 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.1628540697 |
|
|
Oct 09 08:55:03 PM UTC 24 |
Oct 09 08:55:10 PM UTC 24 |
654905659 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.2265603405 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:11 PM UTC 24 |
1170911773 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.3376113462 |
|
|
Oct 09 08:55:03 PM UTC 24 |
Oct 09 08:55:11 PM UTC 24 |
2270941406 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.2224316347 |
|
|
Oct 09 08:55:07 PM UTC 24 |
Oct 09 08:55:11 PM UTC 24 |
300344120 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.2956345130 |
|
|
Oct 09 08:55:07 PM UTC 24 |
Oct 09 08:55:11 PM UTC 24 |
306573050 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.1257214888 |
|
|
Oct 09 08:55:07 PM UTC 24 |
Oct 09 08:55:12 PM UTC 24 |
263258924 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.900134050 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:12 PM UTC 24 |
1221605246 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.343094019 |
|
|
Oct 09 08:50:30 PM UTC 24 |
Oct 09 08:55:13 PM UTC 24 |
68441390040 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.1576798031 |
|
|
Oct 09 08:55:07 PM UTC 24 |
Oct 09 08:55:14 PM UTC 24 |
1943333771 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.1146163587 |
|
|
Oct 09 08:54:54 PM UTC 24 |
Oct 09 08:55:14 PM UTC 24 |
9991486467 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.547906333 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:33 PM UTC 24 |
319774914 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.4268478457 |
|
|
Oct 09 08:53:34 PM UTC 24 |
Oct 09 08:55:15 PM UTC 24 |
16816917706 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.3896313560 |
|
|
Oct 09 08:55:13 PM UTC 24 |
Oct 09 08:55:18 PM UTC 24 |
471901665 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.2215737800 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:18 PM UTC 24 |
107678320 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.312474405 |
|
|
Oct 09 08:55:13 PM UTC 24 |
Oct 09 08:55:18 PM UTC 24 |
343316558 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.2730113353 |
|
|
Oct 09 08:55:13 PM UTC 24 |
Oct 09 08:55:18 PM UTC 24 |
477931519 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.2384953826 |
|
|
Oct 09 08:55:13 PM UTC 24 |
Oct 09 08:55:18 PM UTC 24 |
128736412 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.3003940704 |
|
|
Oct 09 08:55:13 PM UTC 24 |
Oct 09 08:55:18 PM UTC 24 |
168126612 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.1548982178 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:18 PM UTC 24 |
126755372 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.3741296540 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:18 PM UTC 24 |
143633748 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.2553199562 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:19 PM UTC 24 |
504784505 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.3099094763 |
|
|
Oct 09 08:55:13 PM UTC 24 |
Oct 09 08:55:19 PM UTC 24 |
115715586 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.1476123902 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:19 PM UTC 24 |
260529787 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.273381915 |
|
|
Oct 09 08:55:13 PM UTC 24 |
Oct 09 08:55:19 PM UTC 24 |
149834722 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.2755275979 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:19 PM UTC 24 |
466770065 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.817043241 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:19 PM UTC 24 |
247310851 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.1803974208 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:19 PM UTC 24 |
397596159 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.2536228948 |
|
|
Oct 09 08:55:13 PM UTC 24 |
Oct 09 08:55:19 PM UTC 24 |
1998110511 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.2148989565 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:19 PM UTC 24 |
340764967 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.2911701809 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:19 PM UTC 24 |
216191746 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.277768429 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:19 PM UTC 24 |
428298963 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.2582756850 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:19 PM UTC 24 |
292319109 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.1513807352 |
|
|
Oct 09 08:55:13 PM UTC 24 |
Oct 09 08:55:19 PM UTC 24 |
2397093142 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.1354864715 |
|
|
Oct 09 08:55:13 PM UTC 24 |
Oct 09 08:55:19 PM UTC 24 |
158168321 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.711492848 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:19 PM UTC 24 |
309001288 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.3203016162 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:20 PM UTC 24 |
163945148 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.2338092137 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:20 PM UTC 24 |
201088513 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.2044442900 |
|
|
Oct 09 08:52:42 PM UTC 24 |
Oct 09 08:55:20 PM UTC 24 |
17628408996 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.119423752 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:20 PM UTC 24 |
140974480 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.1806310718 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:20 PM UTC 24 |
159904265 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.1868856249 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:20 PM UTC 24 |
477923831 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.3179233837 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:20 PM UTC 24 |
2520436542 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.838634783 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:20 PM UTC 24 |
107443467 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.3383820648 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:20 PM UTC 24 |
186675693 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.3580352939 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:20 PM UTC 24 |
631188022 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.2079318789 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:21 PM UTC 24 |
2806005000 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.3205484575 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:21 PM UTC 24 |
1657504698 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.2448900376 |
|
|
Oct 09 08:55:14 PM UTC 24 |
Oct 09 08:55:22 PM UTC 24 |
2174148941 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.1165213894 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:22 PM UTC 24 |
6539277553 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.848822964 |
|
|
Oct 09 08:53:23 PM UTC 24 |
Oct 09 08:55:27 PM UTC 24 |
6211545379 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.3292403325 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:33 PM UTC 24 |
253573400 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.3871816631 |
|
|
Oct 09 08:55:02 PM UTC 24 |
Oct 09 08:55:28 PM UTC 24 |
2419463235 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.1933759418 |
|
|
Oct 09 08:55:01 PM UTC 24 |
Oct 09 08:55:28 PM UTC 24 |
1302200984 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.1157057348 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:31 PM UTC 24 |
152429293 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.4248804248 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:31 PM UTC 24 |
204281541 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.4052854036 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:31 PM UTC 24 |
384678419 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.716005866 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:31 PM UTC 24 |
143801300 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.3841606282 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:31 PM UTC 24 |
163950635 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.3040958615 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:31 PM UTC 24 |
190113229 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.786327518 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:31 PM UTC 24 |
125445215 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.1767271185 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:31 PM UTC 24 |
440980934 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.1579698390 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:31 PM UTC 24 |
491043261 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.4210913928 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:32 PM UTC 24 |
107214762 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.2340058950 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:32 PM UTC 24 |
142836407 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.1045953580 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:32 PM UTC 24 |
176021261 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.3698379811 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:32 PM UTC 24 |
289929577 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.1652971693 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:32 PM UTC 24 |
343107424 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.3790200058 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:32 PM UTC 24 |
243622736 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.745056080 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:32 PM UTC 24 |
170813839 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.2330571660 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:32 PM UTC 24 |
182582480 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.6263522 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:32 PM UTC 24 |
153320321 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.3394113505 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:32 PM UTC 24 |
176474864 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.2036455212 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:32 PM UTC 24 |
2145384459 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.3065950152 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:32 PM UTC 24 |
142840503 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.3750908125 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:32 PM UTC 24 |
158366251 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.1542146303 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:33 PM UTC 24 |
282240865 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.2731801990 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:33 PM UTC 24 |
325305050 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.1209399777 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:33 PM UTC 24 |
598330064 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.945362302 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:33 PM UTC 24 |
297633263 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.2071994432 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:33 PM UTC 24 |
1714907232 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.1059039213 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:33 PM UTC 24 |
433610348 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.2781467485 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:33 PM UTC 24 |
305904448 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.48635604 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:33 PM UTC 24 |
148519461 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.1943027226 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:33 PM UTC 24 |
1735294849 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.51092167 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:33 PM UTC 24 |
659920767 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.80365595 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:33 PM UTC 24 |
467458255 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.1441543610 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:33 PM UTC 24 |
635116297 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.3438416133 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:33 PM UTC 24 |
386172793 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.677247929 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:33 PM UTC 24 |
112449945 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.2810004944 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:34 PM UTC 24 |
324154949 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.3073783247 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:34 PM UTC 24 |
1837909236 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.257632210 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:34 PM UTC 24 |
519856795 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.1442318532 |
|
|
Oct 09 08:55:26 PM UTC 24 |
Oct 09 08:55:34 PM UTC 24 |
1862237630 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.3351762446 |
|
|
Oct 09 08:55:27 PM UTC 24 |
Oct 09 08:55:35 PM UTC 24 |
2032970127 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.3311839241 |
|
|
Oct 09 08:52:42 PM UTC 24 |
Oct 09 08:55:37 PM UTC 24 |
17005128062 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.2502574048 |
|
|
Oct 09 08:55:38 PM UTC 24 |
Oct 09 08:55:42 PM UTC 24 |
239953875 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.2057627614 |
|
|
Oct 09 08:52:15 PM UTC 24 |
Oct 09 08:55:47 PM UTC 24 |
42564123719 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.3687902708 |
|
|
Oct 09 08:53:28 PM UTC 24 |
Oct 09 08:56:01 PM UTC 24 |
3657536214 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.4237066624 |
|
|
Oct 09 08:51:31 PM UTC 24 |
Oct 09 08:56:04 PM UTC 24 |
26428249265 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.536818479 |
|
|
Oct 09 08:52:47 PM UTC 24 |
Oct 09 08:56:12 PM UTC 24 |
11821131934 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2279490430 |
|
|
Oct 09 06:19:10 PM UTC 24 |
Oct 09 06:19:16 PM UTC 24 |
401210189 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.2102476911 |
|
|
Oct 09 06:19:13 PM UTC 24 |
Oct 09 06:19:16 PM UTC 24 |
43870664 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.1780321763 |
|
|
Oct 09 06:19:13 PM UTC 24 |
Oct 09 06:19:17 PM UTC 24 |
545562080 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2148191157 |
|
|
Oct 09 06:19:17 PM UTC 24 |
Oct 09 06:19:20 PM UTC 24 |
538232913 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.3901899826 |
|
|
Oct 09 06:19:18 PM UTC 24 |
Oct 09 06:19:21 PM UTC 24 |
133698498 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2360195095 |
|
|
Oct 09 06:19:18 PM UTC 24 |
Oct 09 06:19:21 PM UTC 24 |
130792850 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1182728505 |
|
|
Oct 09 06:19:11 PM UTC 24 |
Oct 09 06:19:25 PM UTC 24 |
797983496 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.3141314766 |
|
|
Oct 09 06:19:18 PM UTC 24 |
Oct 09 06:19:26 PM UTC 24 |
365046831 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.4282983118 |
|
|
Oct 09 06:19:20 PM UTC 24 |
Oct 09 06:19:26 PM UTC 24 |
450585304 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.3133857416 |
|
|
Oct 09 06:19:23 PM UTC 24 |
Oct 09 06:19:26 PM UTC 24 |
41696512 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.4057874895 |
|
|
Oct 09 06:19:24 PM UTC 24 |
Oct 09 06:19:27 PM UTC 24 |
70248735 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2526757733 |
|
|
Oct 09 06:19:21 PM UTC 24 |
Oct 09 06:19:27 PM UTC 24 |
84305743 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.1056947912 |
|
|
Oct 09 06:19:21 PM UTC 24 |
Oct 09 06:19:28 PM UTC 24 |
267358794 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.931028524 |
|
|
Oct 09 06:19:18 PM UTC 24 |
Oct 09 06:19:28 PM UTC 24 |
307190273 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.3779191608 |
|
|
Oct 09 06:19:26 PM UTC 24 |
Oct 09 06:19:29 PM UTC 24 |
127528666 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1866616463 |
|
|
Oct 09 06:19:26 PM UTC 24 |
Oct 09 06:19:30 PM UTC 24 |
197446399 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2965704026 |
|
|
Oct 09 06:19:27 PM UTC 24 |
Oct 09 06:19:31 PM UTC 24 |
45081347 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.1706506737 |
|
|
Oct 09 06:19:28 PM UTC 24 |
Oct 09 06:19:32 PM UTC 24 |
36130013 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1961504943 |
|
|
Oct 09 06:19:30 PM UTC 24 |
Oct 09 06:19:33 PM UTC 24 |
143897980 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2082305579 |
|
|
Oct 09 06:19:30 PM UTC 24 |
Oct 09 06:19:33 PM UTC 24 |
71794342 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.394560011 |
|
|
Oct 09 06:19:27 PM UTC 24 |
Oct 09 06:19:33 PM UTC 24 |
157373038 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1924724502 |
|
|
Oct 09 06:19:30 PM UTC 24 |
Oct 09 06:19:33 PM UTC 24 |
51385026 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3114871516 |
|
|
Oct 09 06:19:28 PM UTC 24 |
Oct 09 06:19:34 PM UTC 24 |
1023994682 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2387064635 |
|
|
Oct 09 06:19:27 PM UTC 24 |
Oct 09 06:19:35 PM UTC 24 |
300585750 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2516427203 |
|
|
Oct 09 06:19:27 PM UTC 24 |
Oct 09 06:19:35 PM UTC 24 |
1279375281 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2033274081 |
|
|
Oct 09 06:19:28 PM UTC 24 |
Oct 09 06:19:36 PM UTC 24 |
124427719 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.4280954128 |
|
|
Oct 09 06:19:30 PM UTC 24 |
Oct 09 06:19:36 PM UTC 24 |
1605655133 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2684061615 |
|
|
Oct 09 06:19:34 PM UTC 24 |
Oct 09 06:19:38 PM UTC 24 |
208338554 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.1290873354 |
|
|
Oct 09 06:19:54 PM UTC 24 |
Oct 09 06:19:58 PM UTC 24 |
43755501 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2284685975 |
|
|
Oct 09 06:19:35 PM UTC 24 |
Oct 09 06:19:38 PM UTC 24 |
39867196 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.2164289122 |
|
|
Oct 09 06:19:34 PM UTC 24 |
Oct 09 06:19:38 PM UTC 24 |
140861373 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.2994038716 |
|
|
Oct 09 06:19:35 PM UTC 24 |
Oct 09 06:19:38 PM UTC 24 |
43084068 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.3979686385 |
|
|
Oct 09 06:19:35 PM UTC 24 |
Oct 09 06:19:39 PM UTC 24 |
537463058 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.3375450530 |
|
|
Oct 09 06:19:36 PM UTC 24 |
Oct 09 06:19:40 PM UTC 24 |
74000287 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.966097197 |
|
|
Oct 09 06:19:36 PM UTC 24 |
Oct 09 06:19:40 PM UTC 24 |
1091490345 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2599145353 |
|
|
Oct 09 06:19:31 PM UTC 24 |
Oct 09 06:19:41 PM UTC 24 |
3761613382 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1669108230 |
|
|
Oct 09 06:19:38 PM UTC 24 |
Oct 09 06:19:42 PM UTC 24 |
79469010 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1443633887 |
|
|
Oct 09 06:19:35 PM UTC 24 |
Oct 09 06:19:42 PM UTC 24 |
66809520 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.4160146919 |
|
|
Oct 09 06:19:40 PM UTC 24 |
Oct 09 06:19:43 PM UTC 24 |
70433317 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.3564540427 |
|
|
Oct 09 06:19:40 PM UTC 24 |
Oct 09 06:19:43 PM UTC 24 |
80818998 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.1278171908 |
|
|
Oct 09 06:19:34 PM UTC 24 |
Oct 09 06:19:43 PM UTC 24 |
318404480 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.4191206169 |
|
|
Oct 09 06:19:37 PM UTC 24 |
Oct 09 06:19:44 PM UTC 24 |
144237782 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.671126843 |
|
|
Oct 09 06:19:41 PM UTC 24 |
Oct 09 06:19:44 PM UTC 24 |
71355853 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.2988451444 |
|
|
Oct 09 06:19:41 PM UTC 24 |
Oct 09 06:19:45 PM UTC 24 |
189337822 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3818557229 |
|
|
Oct 09 06:19:37 PM UTC 24 |
Oct 09 06:19:45 PM UTC 24 |
891190318 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.1448325146 |
|
|
Oct 09 06:19:42 PM UTC 24 |
Oct 09 06:19:46 PM UTC 24 |
75669814 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1912750346 |
|
|
Oct 09 06:19:36 PM UTC 24 |
Oct 09 06:19:46 PM UTC 24 |
129393945 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3195928485 |
|
|
Oct 09 06:19:39 PM UTC 24 |
Oct 09 06:19:48 PM UTC 24 |
90226957 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2586233876 |
|
|
Oct 09 06:19:28 PM UTC 24 |
Oct 09 06:19:48 PM UTC 24 |
2457246797 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.329519208 |
|
|
Oct 09 06:19:46 PM UTC 24 |
Oct 09 06:19:49 PM UTC 24 |
52240328 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3332724885 |
|
|
Oct 09 06:19:46 PM UTC 24 |
Oct 09 06:19:50 PM UTC 24 |
50998586 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3265657858 |
|
|
Oct 09 06:19:44 PM UTC 24 |
Oct 09 06:19:50 PM UTC 24 |
111950058 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.2934673364 |
|
|
Oct 09 06:19:44 PM UTC 24 |
Oct 09 06:19:50 PM UTC 24 |
1720458285 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1535519089 |
|
|
Oct 09 06:19:47 PM UTC 24 |
Oct 09 06:19:51 PM UTC 24 |
89897294 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.3292024251 |
|
|
Oct 09 06:19:48 PM UTC 24 |
Oct 09 06:19:52 PM UTC 24 |
153484608 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.4083957603 |
|
|
Oct 09 06:19:21 PM UTC 24 |
Oct 09 06:19:52 PM UTC 24 |
3749030560 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.788517481 |
|
|
Oct 09 06:19:47 PM UTC 24 |
Oct 09 06:19:53 PM UTC 24 |
105659431 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.97367269 |
|
|
Oct 09 06:19:43 PM UTC 24 |
Oct 09 06:19:53 PM UTC 24 |
158814179 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.1764199683 |
|
|
Oct 09 06:19:44 PM UTC 24 |
Oct 09 06:19:53 PM UTC 24 |
505459734 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.3066059831 |
|
|
Oct 09 06:19:43 PM UTC 24 |
Oct 09 06:19:53 PM UTC 24 |
130882570 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2284681362 |
|
|
Oct 09 06:19:49 PM UTC 24 |
Oct 09 06:19:53 PM UTC 24 |
71361143 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3659466467 |
|
|
Oct 09 06:19:50 PM UTC 24 |
Oct 09 06:19:53 PM UTC 24 |
58956238 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1781208435 |
|
|
Oct 09 06:19:47 PM UTC 24 |
Oct 09 06:19:54 PM UTC 24 |
369959451 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.2272908380 |
|
|
Oct 09 06:19:52 PM UTC 24 |
Oct 09 06:19:55 PM UTC 24 |
143227124 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.3895704199 |
|
|
Oct 09 06:19:51 PM UTC 24 |
Oct 09 06:19:55 PM UTC 24 |
72604031 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.900532989 |
|
|
Oct 09 06:19:53 PM UTC 24 |
Oct 09 06:19:56 PM UTC 24 |
117046000 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.4120323533 |
|
|
Oct 09 06:19:35 PM UTC 24 |
Oct 09 06:19:57 PM UTC 24 |
20272558069 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.1416374107 |
|
|
Oct 09 06:19:51 PM UTC 24 |
Oct 09 06:19:58 PM UTC 24 |
156581233 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.1880399587 |
|
|
Oct 09 06:19:54 PM UTC 24 |
Oct 09 06:19:58 PM UTC 24 |
154797015 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.2549648906 |
|
|
Oct 09 06:19:53 PM UTC 24 |
Oct 09 06:19:58 PM UTC 24 |
323513864 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3857619760 |
|
|
Oct 09 06:19:55 PM UTC 24 |
Oct 09 06:19:58 PM UTC 24 |
73246558 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.211741586 |
|
|
Oct 09 06:19:55 PM UTC 24 |
Oct 09 06:19:59 PM UTC 24 |
91430794 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.1366799815 |
|
|
Oct 09 06:19:57 PM UTC 24 |
Oct 09 06:20:00 PM UTC 24 |
146488177 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1191028561 |
|
|
Oct 09 06:19:54 PM UTC 24 |
Oct 09 06:20:01 PM UTC 24 |
284336496 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1326272324 |
|
|
Oct 09 06:19:58 PM UTC 24 |
Oct 09 06:20:01 PM UTC 24 |
90302297 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1348790035 |
|
|
Oct 09 06:19:56 PM UTC 24 |
Oct 09 06:20:01 PM UTC 24 |
51913258 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.1254663856 |
|
|
Oct 09 06:19:45 PM UTC 24 |
Oct 09 06:20:02 PM UTC 24 |
2469596839 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.2966802105 |
|
|
Oct 09 06:19:59 PM UTC 24 |
Oct 09 06:20:03 PM UTC 24 |
592555480 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2147890964 |
|
|
Oct 09 06:19:54 PM UTC 24 |
Oct 09 06:20:03 PM UTC 24 |
90791450 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.4004695034 |
|
|
Oct 09 06:19:59 PM UTC 24 |
Oct 09 06:20:03 PM UTC 24 |
134214529 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2830839574 |
|
|
Oct 09 06:19:47 PM UTC 24 |
Oct 09 06:20:04 PM UTC 24 |
2456127416 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.130439804 |
|
|
Oct 09 06:20:00 PM UTC 24 |
Oct 09 06:20:04 PM UTC 24 |
44036716 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.3890945296 |
|
|
Oct 09 06:20:01 PM UTC 24 |
Oct 09 06:20:05 PM UTC 24 |
159864425 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3000551538 |
|
|
Oct 09 06:19:59 PM UTC 24 |
Oct 09 06:20:06 PM UTC 24 |
146429564 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.470953778 |
|
|
Oct 09 06:20:36 PM UTC 24 |
Oct 09 06:20:39 PM UTC 24 |
40664773 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.3176607482 |
|
|
Oct 09 06:20:03 PM UTC 24 |
Oct 09 06:20:06 PM UTC 24 |
81091249 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1142214559 |
|
|
Oct 09 06:19:40 PM UTC 24 |
Oct 09 06:20:08 PM UTC 24 |
4778695896 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.563702343 |
|
|
Oct 09 06:19:57 PM UTC 24 |
Oct 09 06:20:08 PM UTC 24 |
2378925256 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.3444763424 |
|
|
Oct 09 06:20:05 PM UTC 24 |
Oct 09 06:20:09 PM UTC 24 |
142997536 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.133930009 |
|
|
Oct 09 06:20:05 PM UTC 24 |
Oct 09 06:20:09 PM UTC 24 |
84915742 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1576332888 |
|
|
Oct 09 06:20:05 PM UTC 24 |
Oct 09 06:20:10 PM UTC 24 |
77638925 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2377924396 |
|
|
Oct 09 06:20:05 PM UTC 24 |
Oct 09 06:20:10 PM UTC 24 |
112314602 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.2979572941 |
|
|
Oct 09 06:20:07 PM UTC 24 |
Oct 09 06:20:10 PM UTC 24 |
88388195 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3070326342 |
|
|
Oct 09 06:19:59 PM UTC 24 |
Oct 09 06:20:11 PM UTC 24 |
200051908 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2877442131 |
|
|
Oct 09 06:20:03 PM UTC 24 |
Oct 09 06:20:11 PM UTC 24 |
271803409 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.936942792 |
|
|
Oct 09 06:20:07 PM UTC 24 |
Oct 09 06:20:11 PM UTC 24 |
155685658 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1752255374 |
|
|
Oct 09 06:20:07 PM UTC 24 |
Oct 09 06:20:11 PM UTC 24 |
237201061 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1217284258 |
|
|
Oct 09 06:20:07 PM UTC 24 |
Oct 09 06:20:12 PM UTC 24 |
50242762 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.157830450 |
|
|
Oct 09 06:20:09 PM UTC 24 |
Oct 09 06:20:12 PM UTC 24 |
91906378 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.700787053 |
|
|
Oct 09 06:20:17 PM UTC 24 |
Oct 09 06:20:40 PM UTC 24 |
1347853480 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.687542413 |
|
|
Oct 09 06:20:10 PM UTC 24 |
Oct 09 06:20:13 PM UTC 24 |
579388684 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3908013255 |
|
|
Oct 09 06:20:10 PM UTC 24 |
Oct 09 06:20:14 PM UTC 24 |
70521236 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2029819326 |
|
|
Oct 09 06:20:05 PM UTC 24 |
Oct 09 06:20:14 PM UTC 24 |
147599197 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.1087356889 |
|
|
Oct 09 06:20:11 PM UTC 24 |
Oct 09 06:20:15 PM UTC 24 |
81823778 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1390160252 |
|
|
Oct 09 06:20:11 PM UTC 24 |
Oct 09 06:20:15 PM UTC 24 |
563980714 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1564784032 |
|
|
Oct 09 06:20:13 PM UTC 24 |
Oct 09 06:20:16 PM UTC 24 |
99007862 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3754852788 |
|
|
Oct 09 06:19:54 PM UTC 24 |
Oct 09 06:20:17 PM UTC 24 |
10319715105 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.185417588 |
|
|
Oct 09 06:20:13 PM UTC 24 |
Oct 09 06:20:18 PM UTC 24 |
68416358 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.1844234099 |
|
|
Oct 09 06:20:15 PM UTC 24 |
Oct 09 06:20:18 PM UTC 24 |
42796278 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3225980926 |
|
|
Oct 09 06:20:11 PM UTC 24 |
Oct 09 06:20:18 PM UTC 24 |
107473159 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1632550848 |
|
|
Oct 09 06:20:13 PM UTC 24 |
Oct 09 06:20:19 PM UTC 24 |
103728123 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1142767364 |
|
|
Oct 09 06:20:15 PM UTC 24 |
Oct 09 06:20:19 PM UTC 24 |
98073198 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2234326179 |
|
|
Oct 09 06:20:15 PM UTC 24 |
Oct 09 06:20:20 PM UTC 24 |
133893158 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3939148492 |
|
|
Oct 09 06:20:11 PM UTC 24 |
Oct 09 06:20:20 PM UTC 24 |
130432848 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3742733285 |
|
|
Oct 09 06:19:52 PM UTC 24 |
Oct 09 06:20:20 PM UTC 24 |
1461016738 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.1144385000 |
|
|
Oct 09 06:20:18 PM UTC 24 |
Oct 09 06:20:22 PM UTC 24 |
47172518 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1091111085 |
|
|
Oct 09 06:20:16 PM UTC 24 |
Oct 09 06:20:22 PM UTC 24 |
223391028 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.4294734445 |
|
|
Oct 09 06:20:16 PM UTC 24 |
Oct 09 06:20:24 PM UTC 24 |
156260464 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.2497491212 |
|
|
Oct 09 06:20:18 PM UTC 24 |
Oct 09 06:20:24 PM UTC 24 |
682370212 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.935000832 |
|
|
Oct 09 06:20:20 PM UTC 24 |
Oct 09 06:20:24 PM UTC 24 |
177253920 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.495958494 |
|
|
Oct 09 06:20:21 PM UTC 24 |
Oct 09 06:20:25 PM UTC 24 |
513496841 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.471153915 |
|
|
Oct 09 06:20:21 PM UTC 24 |
Oct 09 06:20:25 PM UTC 24 |
574101512 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.1458046458 |
|
|
Oct 09 06:20:36 PM UTC 24 |
Oct 09 06:20:40 PM UTC 24 |
41476200 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1105559895 |
|
|
Oct 09 06:20:20 PM UTC 24 |
Oct 09 06:20:25 PM UTC 24 |
103858843 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.2321602291 |
|
|
Oct 09 06:20:21 PM UTC 24 |
Oct 09 06:20:27 PM UTC 24 |
87887050 ps |