| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 95.20 | 93.73 | 97.18 | 95.91 | 92.53 | 97.45 | 96.37 | 93.21 |
| T397 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.3232364193 | Oct 09 06:19:59 PM UTC 24 | Oct 09 06:20:27 PM UTC 24 | 2473908718 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3551578483 | Oct 09 06:20:03 PM UTC 24 | Oct 09 06:20:28 PM UTC 24 | 1481193722 ps | ||
| T1258 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3490639326 | Oct 09 06:20:23 PM UTC 24 | Oct 09 06:20:29 PM UTC 24 | 417388621 ps | ||
| T1259 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.3483584108 | Oct 09 06:20:25 PM UTC 24 | Oct 09 06:20:29 PM UTC 24 | 40249252 ps | ||
| T1260 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3758750991 | Oct 09 06:20:25 PM UTC 24 | Oct 09 06:20:29 PM UTC 24 | 164170138 ps | ||
| T1261 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1786981614 | Oct 09 06:20:20 PM UTC 24 | Oct 09 06:20:29 PM UTC 24 | 1504693439 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1443688823 | Oct 09 06:20:11 PM UTC 24 | Oct 09 06:20:30 PM UTC 24 | 1836997250 ps | ||
| T1262 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.1825332837 | Oct 09 06:20:28 PM UTC 24 | Oct 09 06:20:31 PM UTC 24 | 46622542 ps | ||
| T1263 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.713373766 | Oct 09 06:20:26 PM UTC 24 | Oct 09 06:20:32 PM UTC 24 | 359020590 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2361287253 | Oct 09 06:20:05 PM UTC 24 | Oct 09 06:20:32 PM UTC 24 | 1785380336 ps | ||
| T1264 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3461384104 | Oct 09 06:20:25 PM UTC 24 | Oct 09 06:20:33 PM UTC 24 | 822642630 ps | ||
| T1265 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3430776094 | Oct 09 06:20:29 PM UTC 24 | Oct 09 06:20:33 PM UTC 24 | 137995612 ps | ||
| T1266 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1619277132 | Oct 09 06:20:29 PM UTC 24 | Oct 09 06:20:33 PM UTC 24 | 182131497 ps | ||
| T1267 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.1388138363 | Oct 09 06:20:30 PM UTC 24 | Oct 09 06:20:34 PM UTC 24 | 527205168 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.473516969 | Oct 09 06:20:14 PM UTC 24 | Oct 09 06:20:34 PM UTC 24 | 9750360148 ps | ||
| T1268 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.1245742161 | Oct 09 06:20:30 PM UTC 24 | Oct 09 06:20:35 PM UTC 24 | 571946808 ps | ||
| T1269 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2680749759 | Oct 09 06:20:23 PM UTC 24 | Oct 09 06:20:35 PM UTC 24 | 2402779057 ps | ||
| T1270 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.775692408 | Oct 09 06:20:31 PM UTC 24 | Oct 09 06:20:36 PM UTC 24 | 44796260 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.3480085648 | Oct 09 06:20:32 PM UTC 24 | Oct 09 06:20:36 PM UTC 24 | 141054231 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2229968262 | Oct 09 06:20:30 PM UTC 24 | Oct 09 06:20:37 PM UTC 24 | 208436514 ps | ||
| T1273 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.1704795136 | Oct 09 06:20:34 PM UTC 24 | Oct 09 06:20:37 PM UTC 24 | 37998258 ps | ||
| T1274 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.3341573380 | Oct 09 06:20:34 PM UTC 24 | Oct 09 06:20:37 PM UTC 24 | 79711071 ps | ||
| T1275 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.1317065348 | Oct 09 06:20:34 PM UTC 24 | Oct 09 06:20:38 PM UTC 24 | 510055675 ps | ||
| T1276 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.3136778596 | Oct 09 06:20:34 PM UTC 24 | Oct 09 06:20:38 PM UTC 24 | 81653394 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2680288099 | Oct 09 06:20:20 PM UTC 24 | Oct 09 06:20:38 PM UTC 24 | 10619921543 ps | ||
| T1277 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.2003788095 | Oct 09 06:20:37 PM UTC 24 | Oct 09 06:20:40 PM UTC 24 | 72027613 ps | ||
| T1278 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.3933257608 | Oct 09 06:20:35 PM UTC 24 | Oct 09 06:20:38 PM UTC 24 | 83091090 ps | ||
| T1279 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.1164114867 | Oct 09 06:20:35 PM UTC 24 | Oct 09 06:20:38 PM UTC 24 | 585217895 ps | ||
| T1280 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.2537759932 | Oct 09 06:20:37 PM UTC 24 | Oct 09 06:20:41 PM UTC 24 | 642952353 ps | ||
| T1281 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.56149929 | Oct 09 06:20:27 PM UTC 24 | Oct 09 06:20:38 PM UTC 24 | 2781502597 ps | ||
| T1282 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.472273107 | Oct 09 06:20:36 PM UTC 24 | Oct 09 06:20:39 PM UTC 24 | 42542376 ps | ||
| T1283 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.1150962131 | Oct 09 06:20:36 PM UTC 24 | Oct 09 06:20:39 PM UTC 24 | 75574694 ps | ||
| T1284 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.1872626416 | Oct 09 06:20:39 PM UTC 24 | Oct 09 06:20:42 PM UTC 24 | 145020700 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.4209081275 | Oct 09 06:20:09 PM UTC 24 | Oct 09 06:20:42 PM UTC 24 | 2658871575 ps | ||
| T1285 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.306184751 | Oct 09 06:20:38 PM UTC 24 | Oct 09 06:20:42 PM UTC 24 | 39982642 ps | ||
| T1286 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.3367475203 | Oct 09 06:20:39 PM UTC 24 | Oct 09 06:20:42 PM UTC 24 | 38081349 ps | ||
| T1287 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.3268522579 | Oct 09 06:20:39 PM UTC 24 | Oct 09 06:20:42 PM UTC 24 | 74003525 ps | ||
| T1288 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.144496019 | Oct 09 06:20:39 PM UTC 24 | Oct 09 06:20:42 PM UTC 24 | 36653771 ps | ||
| T1289 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.4262541426 | Oct 09 06:20:40 PM UTC 24 | Oct 09 06:20:43 PM UTC 24 | 83678766 ps | ||
| T1290 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.1331916980 | Oct 09 06:20:40 PM UTC 24 | Oct 09 06:20:43 PM UTC 24 | 39028485 ps | ||
| T1291 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.3623066323 | Oct 09 06:20:40 PM UTC 24 | Oct 09 06:20:43 PM UTC 24 | 39215398 ps | ||
| T1292 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.39729566 | Oct 09 06:20:40 PM UTC 24 | Oct 09 06:20:43 PM UTC 24 | 146275401 ps | ||
| T1293 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.3395731779 | Oct 09 06:20:40 PM UTC 24 | Oct 09 06:20:43 PM UTC 24 | 38778807 ps | ||
| T1294 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.472249158 | Oct 09 06:20:40 PM UTC 24 | Oct 09 06:20:44 PM UTC 24 | 53176675 ps | ||
| T1295 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.3425635072 | Oct 09 06:20:41 PM UTC 24 | Oct 09 06:20:44 PM UTC 24 | 541416958 ps | ||
| T1296 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.95188886 | Oct 09 06:20:41 PM UTC 24 | Oct 09 06:20:45 PM UTC 24 | 39766431 ps | ||
| T1297 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.3144411479 | Oct 09 06:20:41 PM UTC 24 | Oct 09 06:20:45 PM UTC 24 | 44477847 ps | ||
| T1298 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.956885973 | Oct 09 06:20:24 PM UTC 24 | Oct 09 06:20:52 PM UTC 24 | 2746977638 ps | ||
| T1299 | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2341931952 | Oct 09 06:20:28 PM UTC 24 | Oct 09 06:21:00 PM UTC 24 | 1810614313 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_background_chks.2853955487 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 539150180 ps |
| CPU time | 10.21 seconds |
| Started | Oct 09 08:43:35 PM UTC 24 |
| Finished | Oct 09 08:43:46 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853955487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.2853955487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_check_fail.969518743 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1010012665 ps |
| CPU time | 24.32 seconds |
| Started | Oct 09 08:44:01 PM UTC 24 |
| Finished | Oct 09 08:44:27 PM UTC 24 |
| Peak memory | 254596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969518743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.969518743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.3066768343 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11123132429 ps |
| CPU time | 55.46 seconds |
| Started | Oct 09 08:45:04 PM UTC 24 |
| Finished | Oct 09 08:46:01 PM UTC 24 |
| Peak memory | 258916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3066768343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.otp_ctrl_stress_all_with_rand_reset.3066768343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all.932833523 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 7916523182 ps |
| CPU time | 150.58 seconds |
| Started | Oct 09 08:44:44 PM UTC 24 |
| Finished | Oct 09 08:47:18 PM UTC 24 |
| Peak memory | 272972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932833523 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.932833523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_test_access.3185555721 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 1034262674 ps |
| CPU time | 24.45 seconds |
| Started | Oct 09 08:44:28 PM UTC 24 |
| Finished | Oct 09 08:44:54 PM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185555721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.3185555721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_req.29296527 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1612874536 ps |
| CPU time | 22.91 seconds |
| Started | Oct 09 08:43:35 PM UTC 24 |
| Finished | Oct 09 08:43:59 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29296527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.29296527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_macro_errs.405163352 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 6021066464 ps |
| CPU time | 40.9 seconds |
| Started | Oct 09 08:43:37 PM UTC 24 |
| Finished | Oct 09 08:44:20 PM UTC 24 |
| Peak memory | 269068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405163352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.405163352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_sec_cm.1914142876 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10491310733 ps |
| CPU time | 160.89 seconds |
| Started | Oct 09 08:45:06 PM UTC 24 |
| Finished | Oct 09 08:47:50 PM UTC 24 |
| Peak memory | 296952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914142876 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.1914142876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all.1116155582 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 25844001468 ps |
| CPU time | 230.68 seconds |
| Started | Oct 09 08:43:47 PM UTC 24 |
| Finished | Oct 09 08:47:42 PM UTC 24 |
| Peak memory | 275108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116155582 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.1116155582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_key_req.1932968607 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 2738725032 ps |
| CPU time | 40.71 seconds |
| Started | Oct 09 08:44:03 PM UTC 24 |
| Finished | Oct 09 08:44:46 PM UTC 24 |
| Peak memory | 252484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932968607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.1932968607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_init_fail.3577075668 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 111252463 ps |
| CPU time | 3.07 seconds |
| Started | Oct 09 08:54:08 PM UTC 24 |
| Finished | Oct 09 08:54:12 PM UTC 24 |
| Peak memory | 252492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577075668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.3577075668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/117.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.269504538 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 8821939374 ps |
| CPU time | 165.97 seconds |
| Started | Oct 09 08:46:45 PM UTC 24 |
| Finished | Oct 09 08:49:34 PM UTC 24 |
| Peak memory | 271048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=269504538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.269504538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_check_fail.87882697 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 3484267793 ps |
| CPU time | 54.14 seconds |
| Started | Oct 09 08:44:42 PM UTC 24 |
| Finished | Oct 09 08:45:38 PM UTC 24 |
| Peak memory | 254628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87882697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.87882697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_init_fail.1445337771 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 2730886768 ps |
| CPU time | 11.89 seconds |
| Started | Oct 09 08:44:50 PM UTC 24 |
| Finished | Oct 09 08:45:03 PM UTC 24 |
| Peak memory | 252412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445337771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.1445337771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_regwen.2832111957 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 255467818 ps |
| CPU time | 13.06 seconds |
| Started | Oct 09 08:44:26 PM UTC 24 |
| Finished | Oct 09 08:44:41 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832111957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.2832111957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.3660715768 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 37441061808 ps |
| CPU time | 215.27 seconds |
| Started | Oct 09 08:47:09 PM UTC 24 |
| Finished | Oct 09 08:50:48 PM UTC 24 |
| Peak memory | 269060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3660715768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.otp_ctrl_stress_all_with_rand_reset.3660715768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.4083957603 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3749030560 ps |
| CPU time | 29.19 seconds |
| Started | Oct 09 06:19:21 PM UTC 24 |
| Finished | Oct 09 06:19:52 PM UTC 24 |
| Peak memory | 251624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083957603 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_intg_err.4083957603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all.959436079 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 26893986963 ps |
| CPU time | 181.84 seconds |
| Started | Oct 09 08:45:06 PM UTC 24 |
| Finished | Oct 09 08:48:11 PM UTC 24 |
| Peak memory | 258628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959436079 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.959436079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_test_access.2427273281 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 7481681843 ps |
| CPU time | 40.72 seconds |
| Started | Oct 09 08:44:43 PM UTC 24 |
| Finished | Oct 09 08:45:26 PM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427273281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.2427273281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_init_fail.2636447777 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 140556689 ps |
| CPU time | 5.5 seconds |
| Started | Oct 09 08:46:38 PM UTC 24 |
| Finished | Oct 09 08:46:44 PM UTC 24 |
| Peak memory | 252392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636447777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.2636447777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_check_fail.206630046 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 767241862 ps |
| CPU time | 24.91 seconds |
| Started | Oct 09 08:45:16 PM UTC 24 |
| Finished | Oct 09 08:45:43 PM UTC 24 |
| Peak memory | 254700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206630046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.206630046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_init_fail.2108445075 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 244082576 ps |
| CPU time | 3.35 seconds |
| Started | Oct 09 08:54:40 PM UTC 24 |
| Finished | Oct 09 08:54:45 PM UTC 24 |
| Peak memory | 252308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108445075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.2108445075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/168.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_macro_errs.47063129 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1521072495 ps |
| CPU time | 14.8 seconds |
| Started | Oct 09 08:45:29 PM UTC 24 |
| Finished | Oct 09 08:45:45 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47063129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.47063129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_init_fail.4186677611 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 2873204481 ps |
| CPU time | 13.43 seconds |
| Started | Oct 09 08:43:31 PM UTC 24 |
| Finished | Oct 09 08:43:46 PM UTC 24 |
| Peak memory | 252416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186677611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.4186677611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_init_fail.1901944727 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 166938199 ps |
| CPU time | 4.21 seconds |
| Started | Oct 09 08:53:48 PM UTC 24 |
| Finished | Oct 09 08:53:54 PM UTC 24 |
| Peak memory | 252556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901944727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.1901944727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/105.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_errs.364034286 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 301411493 ps |
| CPU time | 18.9 seconds |
| Started | Oct 09 08:45:15 PM UTC 24 |
| Finished | Oct 09 08:45:35 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364034286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.364034286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_check_fail.3953647855 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 22892235031 ps |
| CPU time | 48.34 seconds |
| Started | Oct 09 08:45:41 PM UTC 24 |
| Finished | Oct 09 08:46:31 PM UTC 24 |
| Peak memory | 254684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953647855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.3953647855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.931028524 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 307190273 ps |
| CPU time | 8.88 seconds |
| Started | Oct 09 06:19:18 PM UTC 24 |
| Finished | Oct 09 06:19:28 PM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931028524 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_aliasing.931028524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_alert_test.2177721106 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 696160720 ps |
| CPU time | 3.97 seconds |
| Started | Oct 09 08:44:35 PM UTC 24 |
| Finished | Oct 09 08:44:40 PM UTC 24 |
| Peak memory | 252320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177721106 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.2177721106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all.2282094155 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 9939012823 ps |
| CPU time | 155.58 seconds |
| Started | Oct 09 08:48:50 PM UTC 24 |
| Finished | Oct 09 08:51:29 PM UTC 24 |
| Peak memory | 258768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282094155 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.2282094155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_init_fail.4066430093 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 492563849 ps |
| CPU time | 4.99 seconds |
| Started | Oct 09 08:47:28 PM UTC 24 |
| Finished | Oct 09 08:47:34 PM UTC 24 |
| Peak memory | 252496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066430093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.4066430093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/20.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.4052854036 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 384678419 ps |
| CPU time | 3.35 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:31 PM UTC 24 |
| Peak memory | 252328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052854036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.4052854036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/260.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all.1029037244 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 80979170878 ps |
| CPU time | 188.59 seconds |
| Started | Oct 09 08:46:17 PM UTC 24 |
| Finished | Oct 09 08:49:29 PM UTC 24 |
| Peak memory | 272992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029037244 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.1029037244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.51092167 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 659920767 ps |
| CPU time | 4.18 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:33 PM UTC 24 |
| Peak memory | 252280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51092167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.51092167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/292.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_init_fail.3685073804 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 654475614 ps |
| CPU time | 6.94 seconds |
| Started | Oct 09 08:45:23 PM UTC 24 |
| Finished | Oct 09 08:45:32 PM UTC 24 |
| Peak memory | 252416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685073804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.3685073804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_regwen.229489832 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1085625105 ps |
| CPU time | 14.08 seconds |
| Started | Oct 09 08:45:43 PM UTC 24 |
| Finished | Oct 09 08:45:58 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229489832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.229489832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.3820388139 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 9484387120 ps |
| CPU time | 139.04 seconds |
| Started | Oct 09 08:51:22 PM UTC 24 |
| Finished | Oct 09 08:53:43 PM UTC 24 |
| Peak memory | 269060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3820388139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 44.otp_ctrl_stress_all_with_rand_reset.3820388139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_macro_errs.2735387058 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 3394242419 ps |
| CPU time | 40.8 seconds |
| Started | Oct 09 08:45:51 PM UTC 24 |
| Finished | Oct 09 08:46:33 PM UTC 24 |
| Peak memory | 258724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735387058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.2735387058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_init_fail.3679852597 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 171173845 ps |
| CPU time | 5.59 seconds |
| Started | Oct 09 08:52:09 PM UTC 24 |
| Finished | Oct 09 08:52:16 PM UTC 24 |
| Peak memory | 252432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679852597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.3679852597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/53.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_lock.1197811575 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 975550057 ps |
| CPU time | 33.57 seconds |
| Started | Oct 09 08:46:49 PM UTC 24 |
| Finished | Oct 09 08:47:24 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197811575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.1197811575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.291980055 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2356282493 ps |
| CPU time | 57.31 seconds |
| Started | Oct 09 08:52:53 PM UTC 24 |
| Finished | Oct 09 08:53:52 PM UTC 24 |
| Peak memory | 258792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=291980055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.291980055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/82.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.2956345130 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 306573050 ps |
| CPU time | 3.63 seconds |
| Started | Oct 09 08:55:07 PM UTC 24 |
| Finished | Oct 09 08:55:11 PM UTC 24 |
| Peak memory | 252408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956345130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.2956345130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/215.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_init_fail.3977010846 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 99001541 ps |
| CPU time | 5.58 seconds |
| Started | Oct 09 08:44:17 PM UTC 24 |
| Finished | Oct 09 08:44:24 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977010846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.3977010846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_key_req.2799310737 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 882374904 ps |
| CPU time | 19.72 seconds |
| Started | Oct 09 08:44:42 PM UTC 24 |
| Finished | Oct 09 08:45:03 PM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799310737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.2799310737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_check_fail.1318260090 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10346395284 ps |
| CPU time | 29.61 seconds |
| Started | Oct 09 08:46:28 PM UTC 24 |
| Finished | Oct 09 08:47:00 PM UTC 24 |
| Peak memory | 252500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318260090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.1318260090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_parallel_lc_esc.3306189982 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1733359858 ps |
| CPU time | 5.3 seconds |
| Started | Oct 09 08:52:35 PM UTC 24 |
| Finished | Oct 09 08:52:41 PM UTC 24 |
| Peak memory | 252356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306189982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.3306189982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/70.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.2582756850 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 292319109 ps |
| CPU time | 4.25 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:19 PM UTC 24 |
| Peak memory | 252224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582756850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.2582756850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/236.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_parallel_lc_esc.3401520678 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 294162616 ps |
| CPU time | 7.81 seconds |
| Started | Oct 09 08:52:25 PM UTC 24 |
| Finished | Oct 09 08:52:34 PM UTC 24 |
| Peak memory | 252308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401520678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.3401520678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/64.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2830839574 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 2456127416 ps |
| CPU time | 15.44 seconds |
| Started | Oct 09 06:19:47 PM UTC 24 |
| Finished | Oct 09 06:20:04 PM UTC 24 |
| Peak memory | 255668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830839574 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg_err.2830839574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all.3774165532 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 7190655041 ps |
| CPU time | 116.21 seconds |
| Started | Oct 09 08:47:34 PM UTC 24 |
| Finished | Oct 09 08:49:33 PM UTC 24 |
| Peak memory | 256648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774165532 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.3774165532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_lock.3219013254 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 14083787567 ps |
| CPU time | 37.03 seconds |
| Started | Oct 09 08:43:36 PM UTC 24 |
| Finished | Oct 09 08:44:15 PM UTC 24 |
| Peak memory | 252656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219013254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.3219013254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_check_fail.2871565691 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2213016578 ps |
| CPU time | 25.29 seconds |
| Started | Oct 09 08:47:17 PM UTC 24 |
| Finished | Oct 09 08:47:44 PM UTC 24 |
| Peak memory | 256624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871565691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.2871565691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_regwen.1246427560 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 452326750 ps |
| CPU time | 10.73 seconds |
| Started | Oct 09 08:46:43 PM UTC 24 |
| Finished | Oct 09 08:46:55 PM UTC 24 |
| Peak memory | 252328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246427560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.1246427560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_init_fail.3563043428 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 394269948 ps |
| CPU time | 6.39 seconds |
| Started | Oct 09 08:53:43 PM UTC 24 |
| Finished | Oct 09 08:53:52 PM UTC 24 |
| Peak memory | 252276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563043428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.3563043428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/100.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_init_fail.1054120593 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 117620368 ps |
| CPU time | 3.99 seconds |
| Started | Oct 09 08:54:35 PM UTC 24 |
| Finished | Oct 09 08:54:41 PM UTC 24 |
| Peak memory | 252484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054120593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.1054120593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/155.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.69523954 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 18298292785 ps |
| CPU time | 186.47 seconds |
| Started | Oct 09 08:47:48 PM UTC 24 |
| Finished | Oct 09 08:50:58 PM UTC 24 |
| Peak memory | 268992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=69523954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.69523954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all.3005087914 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1841403391 ps |
| CPU time | 51.8 seconds |
| Started | Oct 09 08:46:25 PM UTC 24 |
| Finished | Oct 09 08:47:20 PM UTC 24 |
| Peak memory | 254476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005087914 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.3005087914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_esc.1464066459 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 100591778 ps |
| CPU time | 3.68 seconds |
| Started | Oct 09 08:46:33 PM UTC 24 |
| Finished | Oct 09 08:46:38 PM UTC 24 |
| Peak memory | 252356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464066459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.1464066459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.1478852946 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 16121087339 ps |
| CPU time | 35.03 seconds |
| Started | Oct 09 08:52:02 PM UTC 24 |
| Finished | Oct 09 08:52:39 PM UTC 24 |
| Peak memory | 268944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1478852946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 50.otp_ctrl_stress_all_with_rand_reset.1478852946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_check_fail.2594555299 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1609848625 ps |
| CPU time | 18.31 seconds |
| Started | Oct 09 08:47:03 PM UTC 24 |
| Finished | Oct 09 08:47:22 PM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594555299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.2594555299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all.4106768154 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 7389544677 ps |
| CPU time | 136.66 seconds |
| Started | Oct 09 08:48:02 PM UTC 24 |
| Finished | Oct 09 08:50:22 PM UTC 24 |
| Peak memory | 258700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106768154 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.4106768154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_parallel_lc_esc.3842817634 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 513824015 ps |
| CPU time | 8.68 seconds |
| Started | Oct 09 08:54:08 PM UTC 24 |
| Finished | Oct 09 08:54:19 PM UTC 24 |
| Peak memory | 252352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842817634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.3842817634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/120.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_parallel_lc_esc.1156802426 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2220759716 ps |
| CPU time | 9.35 seconds |
| Started | Oct 09 08:54:17 PM UTC 24 |
| Finished | Oct 09 08:54:28 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156802426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.1156802426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/133.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_esc.2761914564 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 409429563 ps |
| CPU time | 5.39 seconds |
| Started | Oct 09 08:48:45 PM UTC 24 |
| Finished | Oct 09 08:48:51 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761914564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.2761914564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_esc.2658104536 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 161032770 ps |
| CPU time | 7.35 seconds |
| Started | Oct 09 08:51:58 PM UTC 24 |
| Finished | Oct 09 08:52:06 PM UTC 24 |
| Peak memory | 252292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658104536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.2658104536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_parallel_lc_esc.2427062214 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 721601646 ps |
| CPU time | 9.92 seconds |
| Started | Oct 09 08:52:14 PM UTC 24 |
| Finished | Oct 09 08:52:26 PM UTC 24 |
| Peak memory | 252344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427062214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.2427062214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/56.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_init_fail.3580958112 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 706437632 ps |
| CPU time | 5.69 seconds |
| Started | Oct 09 08:52:28 PM UTC 24 |
| Finished | Oct 09 08:52:35 PM UTC 24 |
| Peak memory | 252416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580958112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.3580958112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/67.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_regwen.50134271 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 5288789953 ps |
| CPU time | 12.84 seconds |
| Started | Oct 09 08:45:53 PM UTC 24 |
| Finished | Oct 09 08:46:07 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50134271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ot p_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.50134271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_key_req.2874784436 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 733978009 ps |
| CPU time | 24.91 seconds |
| Started | Oct 09 08:43:39 PM UTC 24 |
| Finished | Oct 09 08:44:06 PM UTC 24 |
| Peak memory | 258520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874784436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.2874784436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.8336253 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 8953939891 ps |
| CPU time | 110.91 seconds |
| Started | Oct 09 08:45:45 PM UTC 24 |
| Finished | Oct 09 08:47:38 PM UTC 24 |
| Peak memory | 258780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=8336253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7 .otp_ctrl_stress_all_with_rand_reset.8336253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_esc.3687823453 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 205884828 ps |
| CPU time | 15.53 seconds |
| Started | Oct 09 08:43:58 PM UTC 24 |
| Finished | Oct 09 08:44:14 PM UTC 24 |
| Peak memory | 252308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687823453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.3687823453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.3375450530 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 74000287 ps |
| CPU time | 2.33 seconds |
| Started | Oct 09 06:19:36 PM UTC 24 |
| Finished | Oct 09 06:19:40 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375450530 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.3375450530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_init_fail.3082033154 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 303176383 ps |
| CPU time | 4.09 seconds |
| Started | Oct 09 08:54:48 PM UTC 24 |
| Finished | Oct 09 08:54:54 PM UTC 24 |
| Peak memory | 252476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082033154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.3082033154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/169.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_check_fail.2390488627 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 349811077 ps |
| CPU time | 17.31 seconds |
| Started | Oct 09 08:43:37 PM UTC 24 |
| Finished | Oct 09 08:43:56 PM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390488627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.2390488627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_check_fail.212213823 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 7141635628 ps |
| CPU time | 25.66 seconds |
| Started | Oct 09 08:46:33 PM UTC 24 |
| Finished | Oct 09 08:47:00 PM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212213823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.212213823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_check_fail.1821851696 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1628959609 ps |
| CPU time | 14.72 seconds |
| Started | Oct 09 08:48:08 PM UTC 24 |
| Finished | Oct 09 08:48:24 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821851696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.1821851696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/24.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_check_fail.2023083277 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 2066191866 ps |
| CPU time | 20.93 seconds |
| Started | Oct 09 08:46:04 PM UTC 24 |
| Finished | Oct 09 08:46:26 PM UTC 24 |
| Peak memory | 254312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023083277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.2023083277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2361287253 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1785380336 ps |
| CPU time | 25.36 seconds |
| Started | Oct 09 06:20:05 PM UTC 24 |
| Finished | Oct 09 06:20:32 PM UTC 24 |
| Peak memory | 255648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361287253 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_intg_err.2361287253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_errs.2407828889 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2448399378 ps |
| CPU time | 16.86 seconds |
| Started | Oct 09 08:47:30 PM UTC 24 |
| Finished | Oct 09 08:47:48 PM UTC 24 |
| Peak memory | 252464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407828889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.2407828889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/20.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_req.779272477 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 990144753 ps |
| CPU time | 19.08 seconds |
| Started | Oct 09 08:45:28 PM UTC 24 |
| Finished | Oct 09 08:45:48 PM UTC 24 |
| Peak memory | 252356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779272477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.779272477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_regwen.4077432853 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4795871983 ps |
| CPU time | 14.95 seconds |
| Started | Oct 09 08:45:04 PM UTC 24 |
| Finished | Oct 09 08:45:20 PM UTC 24 |
| Peak memory | 254528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077432853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.4077432853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.1091498376 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 13742508842 ps |
| CPU time | 128.82 seconds |
| Started | Oct 09 08:46:35 PM UTC 24 |
| Finished | Oct 09 08:48:47 PM UTC 24 |
| Peak memory | 269220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1091498376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.otp_ctrl_stress_all_with_rand_reset.1091498376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.3283502536 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 4302996750 ps |
| CPU time | 61.8 seconds |
| Started | Oct 09 08:50:30 PM UTC 24 |
| Finished | Oct 09 08:51:34 PM UTC 24 |
| Peak memory | 258820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3283502536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 37.otp_ctrl_stress_all_with_rand_reset.3283502536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_init_fail.2824157513 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 255923594 ps |
| CPU time | 4.41 seconds |
| Started | Oct 09 08:43:56 PM UTC 24 |
| Finished | Oct 09 08:44:02 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824157513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.2824157513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_init_fail.92030674 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 105928214 ps |
| CPU time | 3.74 seconds |
| Started | Oct 09 08:46:25 PM UTC 24 |
| Finished | Oct 09 08:46:31 PM UTC 24 |
| Peak memory | 252532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92030674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.92030674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_init_fail.718923909 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 442234093 ps |
| CPU time | 3.3 seconds |
| Started | Oct 09 08:54:17 PM UTC 24 |
| Finished | Oct 09 08:54:21 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718923909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.718923909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/134.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_regwen.2110392557 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 679037432 ps |
| CPU time | 13.36 seconds |
| Started | Oct 09 08:47:25 PM UTC 24 |
| Finished | Oct 09 08:47:40 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110392557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.2110392557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_wake_up.2780935016 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 797918118 ps |
| CPU time | 3.77 seconds |
| Started | Oct 09 08:43:28 PM UTC 24 |
| Finished | Oct 09 08:43:33 PM UTC 24 |
| Peak memory | 252312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780935016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes t +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.2780935016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.1056947912 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 267358794 ps |
| CPU time | 5.05 seconds |
| Started | Oct 09 06:19:21 PM UTC 24 |
| Finished | Oct 09 06:19:28 PM UTC 24 |
| Peak memory | 257680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1056947912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_cs r_mem_rw_with_rand_reset.1056947912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.4209081275 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2658871575 ps |
| CPU time | 31.45 seconds |
| Started | Oct 09 06:20:09 PM UTC 24 |
| Finished | Oct 09 06:20:42 PM UTC 24 |
| Peak memory | 257908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209081275 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_intg_err.4209081275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.4120323533 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 20272558069 ps |
| CPU time | 20.78 seconds |
| Started | Oct 09 06:19:35 PM UTC 24 |
| Finished | Oct 09 06:19:57 PM UTC 24 |
| Peak memory | 257420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120323533 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_intg_err.4120323533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_errs.3781716475 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1567713400 ps |
| CPU time | 28.28 seconds |
| Started | Oct 09 08:46:21 PM UTC 24 |
| Finished | Oct 09 08:46:50 PM UTC 24 |
| Peak memory | 252524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781716475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.3781716475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_init_fail.579118784 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 516135484 ps |
| CPU time | 3.66 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:31 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579118784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.579118784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/140.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_test_access.2191100417 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 143429838 ps |
| CPU time | 8.35 seconds |
| Started | Oct 09 08:43:44 PM UTC 24 |
| Finished | Oct 09 08:43:53 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191100417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.2191100417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_init_fail.1323975478 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 163437171 ps |
| CPU time | 4.54 seconds |
| Started | Oct 09 08:54:17 PM UTC 24 |
| Finished | Oct 09 08:54:23 PM UTC 24 |
| Peak memory | 252412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323975478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.1323975478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/131.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.1870720556 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 19885636902 ps |
| CPU time | 41.31 seconds |
| Started | Oct 09 08:52:34 PM UTC 24 |
| Finished | Oct 09 08:53:17 PM UTC 24 |
| Peak memory | 273092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1870720556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 68.otp_ctrl_stress_all_with_rand_reset.1870720556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_init_fail.2934721441 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 154259747 ps |
| CPU time | 5.37 seconds |
| Started | Oct 09 08:52:34 PM UTC 24 |
| Finished | Oct 09 08:52:41 PM UTC 24 |
| Peak memory | 252336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934721441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.2934721441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/70.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_req.2055180446 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 11068090537 ps |
| CPU time | 24.51 seconds |
| Started | Oct 09 08:44:40 PM UTC 24 |
| Finished | Oct 09 08:45:06 PM UTC 24 |
| Peak memory | 252484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055180446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.2055180446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_test_access.1015084784 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1441622268 ps |
| CPU time | 28.37 seconds |
| Started | Oct 09 08:45:53 PM UTC 24 |
| Finished | Oct 09 08:46:23 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015084784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.1015084784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all.2613726736 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 8662634935 ps |
| CPU time | 24.88 seconds |
| Started | Oct 09 08:44:13 PM UTC 24 |
| Finished | Oct 09 08:44:39 PM UTC 24 |
| Peak memory | 254552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613726736 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.2613726736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_init_fail.1681452454 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2266410590 ps |
| CPU time | 5.87 seconds |
| Started | Oct 09 08:47:09 PM UTC 24 |
| Finished | Oct 09 08:47:16 PM UTC 24 |
| Peak memory | 252416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681452454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.1681452454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_init_fail.1524895282 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 443859861 ps |
| CPU time | 5.06 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:55 PM UTC 24 |
| Peak memory | 252340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524895282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.1524895282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/179.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_req.3649906528 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 467622979 ps |
| CPU time | 7.7 seconds |
| Started | Oct 09 08:45:39 PM UTC 24 |
| Finished | Oct 09 08:45:48 PM UTC 24 |
| Peak memory | 252264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649906528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.3649906528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_test_access.1434065568 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 7902743277 ps |
| CPU time | 19.43 seconds |
| Started | Oct 09 08:46:22 PM UTC 24 |
| Finished | Oct 09 08:46:43 PM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434065568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.1434065568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_parallel_lc_esc.1837025200 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 140911843 ps |
| CPU time | 6.19 seconds |
| Started | Oct 09 08:53:43 PM UTC 24 |
| Finished | Oct 09 08:53:51 PM UTC 24 |
| Peak memory | 252224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837025200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.1837025200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/100.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.3141314766 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 365046831 ps |
| CPU time | 7.26 seconds |
| Started | Oct 09 06:19:18 PM UTC 24 |
| Finished | Oct 09 06:19:26 PM UTC 24 |
| Peak memory | 251576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141314766 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_bash.3141314766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.3901899826 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 133698498 ps |
| CPU time | 2.01 seconds |
| Started | Oct 09 06:19:18 PM UTC 24 |
| Finished | Oct 09 06:19:21 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901899826 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_reset.3901899826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2360195095 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 130792850 ps |
| CPU time | 2.23 seconds |
| Started | Oct 09 06:19:18 PM UTC 24 |
| Finished | Oct 09 06:19:21 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360195095 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.2360195095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.2102476911 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 43870664 ps |
| CPU time | 2.2 seconds |
| Started | Oct 09 06:19:13 PM UTC 24 |
| Finished | Oct 09 06:19:16 PM UTC 24 |
| Peak memory | 240504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102476911 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.2102476911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2148191157 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 538232913 ps |
| CPU time | 2.28 seconds |
| Started | Oct 09 06:19:17 PM UTC 24 |
| Finished | Oct 09 06:19:20 PM UTC 24 |
| Peak memory | 240184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148191157 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_partial_access.2148191157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.1780321763 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 545562080 ps |
| CPU time | 2.4 seconds |
| Started | Oct 09 06:19:13 PM UTC 24 |
| Finished | Oct 09 06:19:17 PM UTC 24 |
| Peak memory | 240628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780321763 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.1780321763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.4282983118 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 450585304 ps |
| CPU time | 4.98 seconds |
| Started | Oct 09 06:19:20 PM UTC 24 |
| Finished | Oct 09 06:19:26 PM UTC 24 |
| Peak memory | 251560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282983118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_same_csr_outstanding.4282983118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2279490430 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 401210189 ps |
| CPU time | 5.03 seconds |
| Started | Oct 09 06:19:10 PM UTC 24 |
| Finished | Oct 09 06:19:16 PM UTC 24 |
| Peak memory | 257764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279490430 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.2279490430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1182728505 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 797983496 ps |
| CPU time | 12.66 seconds |
| Started | Oct 09 06:19:11 PM UTC 24 |
| Finished | Oct 09 06:19:25 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182728505 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_intg_err.1182728505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2387064635 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 300585750 ps |
| CPU time | 6.08 seconds |
| Started | Oct 09 06:19:27 PM UTC 24 |
| Finished | Oct 09 06:19:35 PM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387064635 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_aliasing.2387064635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2516427203 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 1279375281 ps |
| CPU time | 6.97 seconds |
| Started | Oct 09 06:19:27 PM UTC 24 |
| Finished | Oct 09 06:19:35 PM UTC 24 |
| Peak memory | 251600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516427203 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_bash.2516427203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1866616463 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 197446399 ps |
| CPU time | 2.82 seconds |
| Started | Oct 09 06:19:26 PM UTC 24 |
| Finished | Oct 09 06:19:30 PM UTC 24 |
| Peak memory | 253528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866616463 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_reset.1866616463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3114871516 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1023994682 ps |
| CPU time | 5 seconds |
| Started | Oct 09 06:19:28 PM UTC 24 |
| Finished | Oct 09 06:19:34 PM UTC 24 |
| Peak memory | 257708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3114871516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_cs r_mem_rw_with_rand_reset.3114871516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2965704026 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 45081347 ps |
| CPU time | 2.34 seconds |
| Started | Oct 09 06:19:27 PM UTC 24 |
| Finished | Oct 09 06:19:31 PM UTC 24 |
| Peak memory | 253808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965704026 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.2965704026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.3133857416 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 41696512 ps |
| CPU time | 2.44 seconds |
| Started | Oct 09 06:19:23 PM UTC 24 |
| Finished | Oct 09 06:19:26 PM UTC 24 |
| Peak memory | 240412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133857416 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.3133857416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.3779191608 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 127528666 ps |
| CPU time | 2.14 seconds |
| Started | Oct 09 06:19:26 PM UTC 24 |
| Finished | Oct 09 06:19:29 PM UTC 24 |
| Peak memory | 240160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779191608 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_partial_access.3779191608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.4057874895 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 70248735 ps |
| CPU time | 2.27 seconds |
| Started | Oct 09 06:19:24 PM UTC 24 |
| Finished | Oct 09 06:19:27 PM UTC 24 |
| Peak memory | 240276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057874895 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.4057874895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.394560011 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 157373038 ps |
| CPU time | 4.71 seconds |
| Started | Oct 09 06:19:27 PM UTC 24 |
| Finished | Oct 09 06:19:33 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394560011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_same_csr_outstanding.394560011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2526757733 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 84305743 ps |
| CPU time | 4.71 seconds |
| Started | Oct 09 06:19:21 PM UTC 24 |
| Finished | Oct 09 06:19:27 PM UTC 24 |
| Peak memory | 251560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526757733 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.2526757733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.130439804 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 44036716 ps |
| CPU time | 2.68 seconds |
| Started | Oct 09 06:20:00 PM UTC 24 |
| Finished | Oct 09 06:20:04 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130439804 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.130439804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.2966802105 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 592555480 ps |
| CPU time | 2.64 seconds |
| Started | Oct 09 06:19:59 PM UTC 24 |
| Finished | Oct 09 06:20:03 PM UTC 24 |
| Peak memory | 240524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966802105 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.2966802105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.3890945296 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 159864425 ps |
| CPU time | 2.9 seconds |
| Started | Oct 09 06:20:01 PM UTC 24 |
| Finished | Oct 09 06:20:05 PM UTC 24 |
| Peak memory | 251672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890945296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_same_csr_outstanding.3890945296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3070326342 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 200051908 ps |
| CPU time | 10.16 seconds |
| Started | Oct 09 06:19:59 PM UTC 24 |
| Finished | Oct 09 06:20:11 PM UTC 24 |
| Peak memory | 257556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070326342 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.3070326342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.3232364193 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2473908718 ps |
| CPU time | 26.43 seconds |
| Started | Oct 09 06:19:59 PM UTC 24 |
| Finished | Oct 09 06:20:27 PM UTC 24 |
| Peak memory | 251620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232364193 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_intg_err.3232364193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1576332888 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 77638925 ps |
| CPU time | 3.33 seconds |
| Started | Oct 09 06:20:05 PM UTC 24 |
| Finished | Oct 09 06:20:10 PM UTC 24 |
| Peak memory | 255724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1576332888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_c sr_mem_rw_with_rand_reset.1576332888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.133930009 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 84915742 ps |
| CPU time | 2.7 seconds |
| Started | Oct 09 06:20:05 PM UTC 24 |
| Finished | Oct 09 06:20:09 PM UTC 24 |
| Peak memory | 253544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133930009 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.133930009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.3176607482 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 81091249 ps |
| CPU time | 2.28 seconds |
| Started | Oct 09 06:20:03 PM UTC 24 |
| Finished | Oct 09 06:20:06 PM UTC 24 |
| Peak memory | 240748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176607482 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.3176607482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2377924396 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 112314602 ps |
| CPU time | 3.87 seconds |
| Started | Oct 09 06:20:05 PM UTC 24 |
| Finished | Oct 09 06:20:10 PM UTC 24 |
| Peak memory | 251628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377924396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_same_csr_outstanding.2377924396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2877442131 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 271803409 ps |
| CPU time | 6.95 seconds |
| Started | Oct 09 06:20:03 PM UTC 24 |
| Finished | Oct 09 06:20:11 PM UTC 24 |
| Peak memory | 257624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877442131 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.2877442131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3551578483 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 1481193722 ps |
| CPU time | 23.75 seconds |
| Started | Oct 09 06:20:03 PM UTC 24 |
| Finished | Oct 09 06:20:28 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551578483 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_intg_err.3551578483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1752255374 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 237201061 ps |
| CPU time | 3.78 seconds |
| Started | Oct 09 06:20:07 PM UTC 24 |
| Finished | Oct 09 06:20:11 PM UTC 24 |
| Peak memory | 257768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1752255374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_c sr_mem_rw_with_rand_reset.1752255374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.2979572941 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 88388195 ps |
| CPU time | 2.66 seconds |
| Started | Oct 09 06:20:07 PM UTC 24 |
| Finished | Oct 09 06:20:10 PM UTC 24 |
| Peak memory | 253536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979572941 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.2979572941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.3444763424 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 142997536 ps |
| CPU time | 2.25 seconds |
| Started | Oct 09 06:20:05 PM UTC 24 |
| Finished | Oct 09 06:20:09 PM UTC 24 |
| Peak memory | 241204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444763424 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.3444763424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.936942792 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 155685658 ps |
| CPU time | 3.7 seconds |
| Started | Oct 09 06:20:07 PM UTC 24 |
| Finished | Oct 09 06:20:11 PM UTC 24 |
| Peak memory | 251432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936942792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_same_csr_outstanding.936942792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2029819326 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 147599197 ps |
| CPU time | 7.81 seconds |
| Started | Oct 09 06:20:05 PM UTC 24 |
| Finished | Oct 09 06:20:14 PM UTC 24 |
| Peak memory | 257828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029819326 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.2029819326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3225980926 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 107473159 ps |
| CPU time | 6.1 seconds |
| Started | Oct 09 06:20:11 PM UTC 24 |
| Finished | Oct 09 06:20:18 PM UTC 24 |
| Peak memory | 257536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3225980926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_c sr_mem_rw_with_rand_reset.3225980926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.687542413 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 579388684 ps |
| CPU time | 2.39 seconds |
| Started | Oct 09 06:20:10 PM UTC 24 |
| Finished | Oct 09 06:20:13 PM UTC 24 |
| Peak memory | 253596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687542413 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.687542413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.157830450 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 91906378 ps |
| CPU time | 2.31 seconds |
| Started | Oct 09 06:20:09 PM UTC 24 |
| Finished | Oct 09 06:20:12 PM UTC 24 |
| Peak memory | 240492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157830450 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.157830450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3908013255 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 70521236 ps |
| CPU time | 2.8 seconds |
| Started | Oct 09 06:20:10 PM UTC 24 |
| Finished | Oct 09 06:20:14 PM UTC 24 |
| Peak memory | 253576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908013255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_same_csr_outstanding.3908013255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1217284258 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 50242762 ps |
| CPU time | 4.04 seconds |
| Started | Oct 09 06:20:07 PM UTC 24 |
| Finished | Oct 09 06:20:12 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217284258 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.1217284258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1632550848 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 103728123 ps |
| CPU time | 4.87 seconds |
| Started | Oct 09 06:20:13 PM UTC 24 |
| Finished | Oct 09 06:20:19 PM UTC 24 |
| Peak memory | 257768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1632550848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_c sr_mem_rw_with_rand_reset.1632550848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1390160252 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 563980714 ps |
| CPU time | 2.66 seconds |
| Started | Oct 09 06:20:11 PM UTC 24 |
| Finished | Oct 09 06:20:15 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390160252 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.1390160252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.1087356889 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 81823778 ps |
| CPU time | 2.46 seconds |
| Started | Oct 09 06:20:11 PM UTC 24 |
| Finished | Oct 09 06:20:15 PM UTC 24 |
| Peak memory | 241336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087356889 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.1087356889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1564784032 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 99007862 ps |
| CPU time | 2.75 seconds |
| Started | Oct 09 06:20:13 PM UTC 24 |
| Finished | Oct 09 06:20:16 PM UTC 24 |
| Peak memory | 251564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564784032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_same_csr_outstanding.1564784032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3939148492 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 130432848 ps |
| CPU time | 7.35 seconds |
| Started | Oct 09 06:20:11 PM UTC 24 |
| Finished | Oct 09 06:20:20 PM UTC 24 |
| Peak memory | 257312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939148492 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.3939148492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1443688823 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 1836997250 ps |
| CPU time | 17.79 seconds |
| Started | Oct 09 06:20:11 PM UTC 24 |
| Finished | Oct 09 06:20:30 PM UTC 24 |
| Peak memory | 255604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443688823 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_intg_err.1443688823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1091111085 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 223391028 ps |
| CPU time | 4.93 seconds |
| Started | Oct 09 06:20:16 PM UTC 24 |
| Finished | Oct 09 06:20:22 PM UTC 24 |
| Peak memory | 257868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1091111085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_c sr_mem_rw_with_rand_reset.1091111085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1142767364 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 98073198 ps |
| CPU time | 2.62 seconds |
| Started | Oct 09 06:20:15 PM UTC 24 |
| Finished | Oct 09 06:20:19 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142767364 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.1142767364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.1844234099 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 42796278 ps |
| CPU time | 2.33 seconds |
| Started | Oct 09 06:20:15 PM UTC 24 |
| Finished | Oct 09 06:20:18 PM UTC 24 |
| Peak memory | 240464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844234099 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.1844234099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2234326179 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 133893158 ps |
| CPU time | 3.58 seconds |
| Started | Oct 09 06:20:15 PM UTC 24 |
| Finished | Oct 09 06:20:20 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234326179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_same_csr_outstanding.2234326179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.185417588 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 68416358 ps |
| CPU time | 3.97 seconds |
| Started | Oct 09 06:20:13 PM UTC 24 |
| Finished | Oct 09 06:20:18 PM UTC 24 |
| Peak memory | 257632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185417588 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.185417588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.473516969 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 9750360148 ps |
| CPU time | 19.39 seconds |
| Started | Oct 09 06:20:14 PM UTC 24 |
| Finished | Oct 09 06:20:34 PM UTC 24 |
| Peak memory | 255604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473516969 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_intg_err.473516969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1105559895 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 103858843 ps |
| CPU time | 4.39 seconds |
| Started | Oct 09 06:20:20 PM UTC 24 |
| Finished | Oct 09 06:20:25 PM UTC 24 |
| Peak memory | 257628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1105559895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_c sr_mem_rw_with_rand_reset.1105559895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.2497491212 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 682370212 ps |
| CPU time | 4.69 seconds |
| Started | Oct 09 06:20:18 PM UTC 24 |
| Finished | Oct 09 06:20:24 PM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497491212 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.2497491212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.1144385000 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 47172518 ps |
| CPU time | 2.43 seconds |
| Started | Oct 09 06:20:18 PM UTC 24 |
| Finished | Oct 09 06:20:22 PM UTC 24 |
| Peak memory | 240716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144385000 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.1144385000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.935000832 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 177253920 ps |
| CPU time | 3.53 seconds |
| Started | Oct 09 06:20:20 PM UTC 24 |
| Finished | Oct 09 06:20:24 PM UTC 24 |
| Peak memory | 253532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935000832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_same_csr_outstanding.935000832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.4294734445 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 156260464 ps |
| CPU time | 6.42 seconds |
| Started | Oct 09 06:20:16 PM UTC 24 |
| Finished | Oct 09 06:20:24 PM UTC 24 |
| Peak memory | 257628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294734445 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.4294734445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.700787053 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 1347853480 ps |
| CPU time | 21.25 seconds |
| Started | Oct 09 06:20:17 PM UTC 24 |
| Finished | Oct 09 06:20:40 PM UTC 24 |
| Peak memory | 251620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700787053 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_intg_err.700787053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3490639326 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 417388621 ps |
| CPU time | 4.28 seconds |
| Started | Oct 09 06:20:23 PM UTC 24 |
| Finished | Oct 09 06:20:29 PM UTC 24 |
| Peak memory | 257928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3490639326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_c sr_mem_rw_with_rand_reset.3490639326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.471153915 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 574101512 ps |
| CPU time | 2.69 seconds |
| Started | Oct 09 06:20:21 PM UTC 24 |
| Finished | Oct 09 06:20:25 PM UTC 24 |
| Peak memory | 253552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471153915 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.471153915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.495958494 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 513496841 ps |
| CPU time | 2.64 seconds |
| Started | Oct 09 06:20:21 PM UTC 24 |
| Finished | Oct 09 06:20:25 PM UTC 24 |
| Peak memory | 240964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495958494 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.495958494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.2321602291 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 87887050 ps |
| CPU time | 4.53 seconds |
| Started | Oct 09 06:20:21 PM UTC 24 |
| Finished | Oct 09 06:20:27 PM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321602291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_same_csr_outstanding.2321602291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1786981614 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 1504693439 ps |
| CPU time | 8.43 seconds |
| Started | Oct 09 06:20:20 PM UTC 24 |
| Finished | Oct 09 06:20:29 PM UTC 24 |
| Peak memory | 257900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786981614 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1786981614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2680288099 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 10619921543 ps |
| CPU time | 16.81 seconds |
| Started | Oct 09 06:20:20 PM UTC 24 |
| Finished | Oct 09 06:20:38 PM UTC 24 |
| Peak memory | 255600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680288099 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_intg_err.2680288099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.713373766 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 359020590 ps |
| CPU time | 5.24 seconds |
| Started | Oct 09 06:20:26 PM UTC 24 |
| Finished | Oct 09 06:20:32 PM UTC 24 |
| Peak memory | 251632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=713373766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_cs r_mem_rw_with_rand_reset.713373766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3758750991 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 164170138 ps |
| CPU time | 2.64 seconds |
| Started | Oct 09 06:20:25 PM UTC 24 |
| Finished | Oct 09 06:20:29 PM UTC 24 |
| Peak memory | 253752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758750991 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.3758750991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.3483584108 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 40249252 ps |
| CPU time | 2.28 seconds |
| Started | Oct 09 06:20:25 PM UTC 24 |
| Finished | Oct 09 06:20:29 PM UTC 24 |
| Peak memory | 240772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483584108 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.3483584108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3461384104 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 822642630 ps |
| CPU time | 5.88 seconds |
| Started | Oct 09 06:20:25 PM UTC 24 |
| Finished | Oct 09 06:20:33 PM UTC 24 |
| Peak memory | 251528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461384104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_same_csr_outstanding.3461384104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2680749759 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 2402779057 ps |
| CPU time | 10.94 seconds |
| Started | Oct 09 06:20:23 PM UTC 24 |
| Finished | Oct 09 06:20:35 PM UTC 24 |
| Peak memory | 257836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680749759 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.2680749759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.956885973 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 2746977638 ps |
| CPU time | 26.61 seconds |
| Started | Oct 09 06:20:24 PM UTC 24 |
| Finished | Oct 09 06:20:52 PM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956885973 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_intg_err.956885973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2229968262 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 208436514 ps |
| CPU time | 5.04 seconds |
| Started | Oct 09 06:20:30 PM UTC 24 |
| Finished | Oct 09 06:20:37 PM UTC 24 |
| Peak memory | 257648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2229968262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_c sr_mem_rw_with_rand_reset.2229968262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3430776094 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 137995612 ps |
| CPU time | 3.06 seconds |
| Started | Oct 09 06:20:29 PM UTC 24 |
| Finished | Oct 09 06:20:33 PM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430776094 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.3430776094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.1825332837 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 46622542 ps |
| CPU time | 2.43 seconds |
| Started | Oct 09 06:20:28 PM UTC 24 |
| Finished | Oct 09 06:20:31 PM UTC 24 |
| Peak memory | 240660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825332837 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.1825332837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1619277132 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 182131497 ps |
| CPU time | 3.38 seconds |
| Started | Oct 09 06:20:29 PM UTC 24 |
| Finished | Oct 09 06:20:33 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619277132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_same_csr_outstanding.1619277132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.56149929 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 2781502597 ps |
| CPU time | 10.09 seconds |
| Started | Oct 09 06:20:27 PM UTC 24 |
| Finished | Oct 09 06:20:38 PM UTC 24 |
| Peak memory | 257692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56149929 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.56149929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2341931952 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 1810614313 ps |
| CPU time | 30.57 seconds |
| Started | Oct 09 06:20:28 PM UTC 24 |
| Finished | Oct 09 06:21:00 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341931952 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_intg_err.2341931952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.1278171908 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 318404480 ps |
| CPU time | 8.71 seconds |
| Started | Oct 09 06:19:34 PM UTC 24 |
| Finished | Oct 09 06:19:43 PM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278171908 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_aliasing.1278171908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2599145353 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 3761613382 ps |
| CPU time | 8.77 seconds |
| Started | Oct 09 06:19:31 PM UTC 24 |
| Finished | Oct 09 06:19:41 PM UTC 24 |
| Peak memory | 241332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599145353 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_bash.2599145353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.4280954128 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 1605655133 ps |
| CPU time | 4.88 seconds |
| Started | Oct 09 06:19:30 PM UTC 24 |
| Finished | Oct 09 06:19:36 PM UTC 24 |
| Peak memory | 251632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280954128 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_reset.4280954128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.2164289122 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 140861373 ps |
| CPU time | 3.51 seconds |
| Started | Oct 09 06:19:34 PM UTC 24 |
| Finished | Oct 09 06:19:38 PM UTC 24 |
| Peak memory | 255584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2164289122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_cs r_mem_rw_with_rand_reset.2164289122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1924724502 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 51385026 ps |
| CPU time | 2.54 seconds |
| Started | Oct 09 06:19:30 PM UTC 24 |
| Finished | Oct 09 06:19:33 PM UTC 24 |
| Peak memory | 253552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924724502 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.1924724502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.1706506737 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 36130013 ps |
| CPU time | 2.13 seconds |
| Started | Oct 09 06:19:28 PM UTC 24 |
| Finished | Oct 09 06:19:32 PM UTC 24 |
| Peak memory | 240996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706506737 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.1706506737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1961504943 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 143897980 ps |
| CPU time | 2.22 seconds |
| Started | Oct 09 06:19:30 PM UTC 24 |
| Finished | Oct 09 06:19:33 PM UTC 24 |
| Peak memory | 240444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961504943 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_partial_access.1961504943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2082305579 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 71794342 ps |
| CPU time | 2.4 seconds |
| Started | Oct 09 06:19:30 PM UTC 24 |
| Finished | Oct 09 06:19:33 PM UTC 24 |
| Peak memory | 241196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082305579 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.2082305579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2684061615 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 208338554 ps |
| CPU time | 3.37 seconds |
| Started | Oct 09 06:19:34 PM UTC 24 |
| Finished | Oct 09 06:19:38 PM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684061615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_same_csr_outstanding.2684061615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2033274081 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 124427719 ps |
| CPU time | 6.28 seconds |
| Started | Oct 09 06:19:28 PM UTC 24 |
| Finished | Oct 09 06:19:36 PM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033274081 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.2033274081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2586233876 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2457246797 ps |
| CPU time | 18.66 seconds |
| Started | Oct 09 06:19:28 PM UTC 24 |
| Finished | Oct 09 06:19:48 PM UTC 24 |
| Peak memory | 255968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586233876 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_intg_err.2586233876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.1388138363 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 527205168 ps |
| CPU time | 2.3 seconds |
| Started | Oct 09 06:20:30 PM UTC 24 |
| Finished | Oct 09 06:20:34 PM UTC 24 |
| Peak memory | 240532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388138363 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.1388138363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/20.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.1245742161 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 571946808 ps |
| CPU time | 3.49 seconds |
| Started | Oct 09 06:20:30 PM UTC 24 |
| Finished | Oct 09 06:20:35 PM UTC 24 |
| Peak memory | 240548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245742161 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.1245742161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/21.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.775692408 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 44796260 ps |
| CPU time | 2.41 seconds |
| Started | Oct 09 06:20:31 PM UTC 24 |
| Finished | Oct 09 06:20:36 PM UTC 24 |
| Peak memory | 240664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775692408 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.775692408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/22.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.3480085648 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 141054231 ps |
| CPU time | 2.22 seconds |
| Started | Oct 09 06:20:32 PM UTC 24 |
| Finished | Oct 09 06:20:36 PM UTC 24 |
| Peak memory | 240420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480085648 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.3480085648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/23.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.3341573380 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 79711071 ps |
| CPU time | 2.19 seconds |
| Started | Oct 09 06:20:34 PM UTC 24 |
| Finished | Oct 09 06:20:37 PM UTC 24 |
| Peak memory | 241208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341573380 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.3341573380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/24.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.1704795136 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 37998258 ps |
| CPU time | 2.15 seconds |
| Started | Oct 09 06:20:34 PM UTC 24 |
| Finished | Oct 09 06:20:37 PM UTC 24 |
| Peak memory | 240656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704795136 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.1704795136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/25.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.1317065348 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 510055675 ps |
| CPU time | 2.31 seconds |
| Started | Oct 09 06:20:34 PM UTC 24 |
| Finished | Oct 09 06:20:38 PM UTC 24 |
| Peak memory | 240752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317065348 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.1317065348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/26.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.3136778596 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 81653394 ps |
| CPU time | 2.49 seconds |
| Started | Oct 09 06:20:34 PM UTC 24 |
| Finished | Oct 09 06:20:38 PM UTC 24 |
| Peak memory | 240428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136778596 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.3136778596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/27.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.1164114867 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 585217895 ps |
| CPU time | 2.11 seconds |
| Started | Oct 09 06:20:35 PM UTC 24 |
| Finished | Oct 09 06:20:38 PM UTC 24 |
| Peak memory | 241104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164114867 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.1164114867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/28.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.3933257608 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 83091090 ps |
| CPU time | 2.04 seconds |
| Started | Oct 09 06:20:35 PM UTC 24 |
| Finished | Oct 09 06:20:38 PM UTC 24 |
| Peak memory | 240996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933257608 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.3933257608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/29.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3818557229 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 891190318 ps |
| CPU time | 6.9 seconds |
| Started | Oct 09 06:19:37 PM UTC 24 |
| Finished | Oct 09 06:19:45 PM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818557229 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_aliasing.3818557229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1912750346 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 129393945 ps |
| CPU time | 8.34 seconds |
| Started | Oct 09 06:19:36 PM UTC 24 |
| Finished | Oct 09 06:19:46 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912750346 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_bash.1912750346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.966097197 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 1091490345 ps |
| CPU time | 3.16 seconds |
| Started | Oct 09 06:19:36 PM UTC 24 |
| Finished | Oct 09 06:19:40 PM UTC 24 |
| Peak memory | 251616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966097197 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_reset.966097197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1669108230 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 79469010 ps |
| CPU time | 2.46 seconds |
| Started | Oct 09 06:19:38 PM UTC 24 |
| Finished | Oct 09 06:19:42 PM UTC 24 |
| Peak memory | 257772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1669108230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_cs r_mem_rw_with_rand_reset.1669108230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.2994038716 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 43084068 ps |
| CPU time | 2.31 seconds |
| Started | Oct 09 06:19:35 PM UTC 24 |
| Finished | Oct 09 06:19:38 PM UTC 24 |
| Peak memory | 240508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994038716 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.2994038716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.3979686385 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 537463058 ps |
| CPU time | 2.84 seconds |
| Started | Oct 09 06:19:35 PM UTC 24 |
| Finished | Oct 09 06:19:39 PM UTC 24 |
| Peak memory | 240444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979686385 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_partial_access.3979686385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2284685975 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 39867196 ps |
| CPU time | 2.02 seconds |
| Started | Oct 09 06:19:35 PM UTC 24 |
| Finished | Oct 09 06:19:38 PM UTC 24 |
| Peak memory | 241260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284685975 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.2284685975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.4191206169 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 144237782 ps |
| CPU time | 5.44 seconds |
| Started | Oct 09 06:19:37 PM UTC 24 |
| Finished | Oct 09 06:19:44 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191206169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_same_csr_outstanding.4191206169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1443633887 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 66809520 ps |
| CPU time | 6.31 seconds |
| Started | Oct 09 06:19:35 PM UTC 24 |
| Finished | Oct 09 06:19:42 PM UTC 24 |
| Peak memory | 257380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443633887 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.1443633887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.472273107 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 42542376 ps |
| CPU time | 1.82 seconds |
| Started | Oct 09 06:20:36 PM UTC 24 |
| Finished | Oct 09 06:20:39 PM UTC 24 |
| Peak memory | 239996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472273107 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.472273107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/30.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.470953778 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 40664773 ps |
| CPU time | 2.28 seconds |
| Started | Oct 09 06:20:36 PM UTC 24 |
| Finished | Oct 09 06:20:39 PM UTC 24 |
| Peak memory | 240496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470953778 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.470953778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/31.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.1458046458 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 41476200 ps |
| CPU time | 2.3 seconds |
| Started | Oct 09 06:20:36 PM UTC 24 |
| Finished | Oct 09 06:20:40 PM UTC 24 |
| Peak memory | 240768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458046458 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.1458046458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/32.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.1150962131 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 75574694 ps |
| CPU time | 1.77 seconds |
| Started | Oct 09 06:20:36 PM UTC 24 |
| Finished | Oct 09 06:20:39 PM UTC 24 |
| Peak memory | 240312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150962131 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.1150962131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/33.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.2537759932 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 642952353 ps |
| CPU time | 2.41 seconds |
| Started | Oct 09 06:20:37 PM UTC 24 |
| Finished | Oct 09 06:20:41 PM UTC 24 |
| Peak memory | 240748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537759932 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.2537759932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/34.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.2003788095 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 72027613 ps |
| CPU time | 1.62 seconds |
| Started | Oct 09 06:20:37 PM UTC 24 |
| Finished | Oct 09 06:20:40 PM UTC 24 |
| Peak memory | 240048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003788095 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.2003788095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/35.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.306184751 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 39982642 ps |
| CPU time | 2.12 seconds |
| Started | Oct 09 06:20:38 PM UTC 24 |
| Finished | Oct 09 06:20:42 PM UTC 24 |
| Peak memory | 240644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306184751 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.306184751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/36.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.3268522579 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 74003525 ps |
| CPU time | 2.48 seconds |
| Started | Oct 09 06:20:39 PM UTC 24 |
| Finished | Oct 09 06:20:42 PM UTC 24 |
| Peak memory | 240484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268522579 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.3268522579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/37.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.3367475203 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 38081349 ps |
| CPU time | 2.29 seconds |
| Started | Oct 09 06:20:39 PM UTC 24 |
| Finished | Oct 09 06:20:42 PM UTC 24 |
| Peak memory | 240708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367475203 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.3367475203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/38.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.1872626416 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 145020700 ps |
| CPU time | 1.85 seconds |
| Started | Oct 09 06:20:39 PM UTC 24 |
| Finished | Oct 09 06:20:42 PM UTC 24 |
| Peak memory | 240048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872626416 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.1872626416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/39.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.97367269 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 158814179 ps |
| CPU time | 8.76 seconds |
| Started | Oct 09 06:19:43 PM UTC 24 |
| Finished | Oct 09 06:19:53 PM UTC 24 |
| Peak memory | 251524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97367269 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_aliasing.97367269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.3066059831 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 130882570 ps |
| CPU time | 8.93 seconds |
| Started | Oct 09 06:19:43 PM UTC 24 |
| Finished | Oct 09 06:19:53 PM UTC 24 |
| Peak memory | 241372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066059831 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_bash.3066059831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.2988451444 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 189337822 ps |
| CPU time | 3.18 seconds |
| Started | Oct 09 06:19:41 PM UTC 24 |
| Finished | Oct 09 06:19:45 PM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988451444 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_reset.2988451444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3265657858 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 111950058 ps |
| CPU time | 4.81 seconds |
| Started | Oct 09 06:19:44 PM UTC 24 |
| Finished | Oct 09 06:19:50 PM UTC 24 |
| Peak memory | 257708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3265657858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_cs r_mem_rw_with_rand_reset.3265657858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.1448325146 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 75669814 ps |
| CPU time | 2.54 seconds |
| Started | Oct 09 06:19:42 PM UTC 24 |
| Finished | Oct 09 06:19:46 PM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448325146 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.1448325146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.4160146919 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 70433317 ps |
| CPU time | 2.14 seconds |
| Started | Oct 09 06:19:40 PM UTC 24 |
| Finished | Oct 09 06:19:43 PM UTC 24 |
| Peak memory | 240660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160146919 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.4160146919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.671126843 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 71355853 ps |
| CPU time | 2.35 seconds |
| Started | Oct 09 06:19:41 PM UTC 24 |
| Finished | Oct 09 06:19:44 PM UTC 24 |
| Peak memory | 240212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671126843 -assert nopostproc +U VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_partial_access.671126843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.3564540427 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 80818998 ps |
| CPU time | 2.19 seconds |
| Started | Oct 09 06:19:40 PM UTC 24 |
| Finished | Oct 09 06:19:43 PM UTC 24 |
| Peak memory | 241280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564540427 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.3564540427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.2934673364 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 1720458285 ps |
| CPU time | 4.96 seconds |
| Started | Oct 09 06:19:44 PM UTC 24 |
| Finished | Oct 09 06:19:50 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934673364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_same_csr_outstanding.2934673364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3195928485 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 90226957 ps |
| CPU time | 7.91 seconds |
| Started | Oct 09 06:19:39 PM UTC 24 |
| Finished | Oct 09 06:19:48 PM UTC 24 |
| Peak memory | 257624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195928485 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.3195928485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1142214559 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 4778695896 ps |
| CPU time | 26.83 seconds |
| Started | Oct 09 06:19:40 PM UTC 24 |
| Finished | Oct 09 06:20:08 PM UTC 24 |
| Peak memory | 255772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142214559 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg_err.1142214559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.144496019 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 36653771 ps |
| CPU time | 2.35 seconds |
| Started | Oct 09 06:20:39 PM UTC 24 |
| Finished | Oct 09 06:20:42 PM UTC 24 |
| Peak memory | 241204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144496019 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.144496019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/40.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.3623066323 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 39215398 ps |
| CPU time | 2.41 seconds |
| Started | Oct 09 06:20:40 PM UTC 24 |
| Finished | Oct 09 06:20:43 PM UTC 24 |
| Peak memory | 241400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623066323 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.3623066323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/41.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.4262541426 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 83678766 ps |
| CPU time | 2.17 seconds |
| Started | Oct 09 06:20:40 PM UTC 24 |
| Finished | Oct 09 06:20:43 PM UTC 24 |
| Peak memory | 240472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262541426 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.4262541426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/42.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.1331916980 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 39028485 ps |
| CPU time | 2.19 seconds |
| Started | Oct 09 06:20:40 PM UTC 24 |
| Finished | Oct 09 06:20:43 PM UTC 24 |
| Peak memory | 241400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331916980 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.1331916980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/43.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.3395731779 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 38778807 ps |
| CPU time | 2.38 seconds |
| Started | Oct 09 06:20:40 PM UTC 24 |
| Finished | Oct 09 06:20:43 PM UTC 24 |
| Peak memory | 241408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395731779 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.3395731779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/44.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.472249158 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 53176675 ps |
| CPU time | 2.48 seconds |
| Started | Oct 09 06:20:40 PM UTC 24 |
| Finished | Oct 09 06:20:44 PM UTC 24 |
| Peak memory | 240436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472249158 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.472249158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/45.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.39729566 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 146275401 ps |
| CPU time | 2.13 seconds |
| Started | Oct 09 06:20:40 PM UTC 24 |
| Finished | Oct 09 06:20:43 PM UTC 24 |
| Peak memory | 240476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39729566 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.39729566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/46.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.95188886 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 39766431 ps |
| CPU time | 2.49 seconds |
| Started | Oct 09 06:20:41 PM UTC 24 |
| Finished | Oct 09 06:20:45 PM UTC 24 |
| Peak memory | 240508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95188886 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.95188886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/47.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.3425635072 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 541416958 ps |
| CPU time | 1.98 seconds |
| Started | Oct 09 06:20:41 PM UTC 24 |
| Finished | Oct 09 06:20:44 PM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425635072 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.3425635072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/48.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.3144411479 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 44477847 ps |
| CPU time | 2.43 seconds |
| Started | Oct 09 06:20:41 PM UTC 24 |
| Finished | Oct 09 06:20:45 PM UTC 24 |
| Peak memory | 240508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144411479 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3144411479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/49.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.788517481 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 105659431 ps |
| CPU time | 4.76 seconds |
| Started | Oct 09 06:19:47 PM UTC 24 |
| Finished | Oct 09 06:19:53 PM UTC 24 |
| Peak memory | 257680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=788517481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr _mem_rw_with_rand_reset.788517481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3332724885 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 50998586 ps |
| CPU time | 2.83 seconds |
| Started | Oct 09 06:19:46 PM UTC 24 |
| Finished | Oct 09 06:19:50 PM UTC 24 |
| Peak memory | 257588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332724885 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.3332724885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.329519208 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 52240328 ps |
| CPU time | 2.37 seconds |
| Started | Oct 09 06:19:46 PM UTC 24 |
| Finished | Oct 09 06:19:49 PM UTC 24 |
| Peak memory | 240488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329519208 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.329519208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1535519089 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 89897294 ps |
| CPU time | 2.87 seconds |
| Started | Oct 09 06:19:47 PM UTC 24 |
| Finished | Oct 09 06:19:51 PM UTC 24 |
| Peak memory | 251520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535519089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_same_csr_outstanding.1535519089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.1764199683 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 505459734 ps |
| CPU time | 7.66 seconds |
| Started | Oct 09 06:19:44 PM UTC 24 |
| Finished | Oct 09 06:19:53 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764199683 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.1764199683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.1254663856 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2469596839 ps |
| CPU time | 14.81 seconds |
| Started | Oct 09 06:19:45 PM UTC 24 |
| Finished | Oct 09 06:20:02 PM UTC 24 |
| Peak memory | 255708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254663856 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_intg_err.1254663856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.3895704199 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 72604031 ps |
| CPU time | 3.69 seconds |
| Started | Oct 09 06:19:51 PM UTC 24 |
| Finished | Oct 09 06:19:55 PM UTC 24 |
| Peak memory | 257772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3895704199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_cs r_mem_rw_with_rand_reset.3895704199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2284681362 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 71361143 ps |
| CPU time | 2.72 seconds |
| Started | Oct 09 06:19:49 PM UTC 24 |
| Finished | Oct 09 06:19:53 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284681362 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.2284681362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.3292024251 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 153484608 ps |
| CPU time | 2.1 seconds |
| Started | Oct 09 06:19:48 PM UTC 24 |
| Finished | Oct 09 06:19:52 PM UTC 24 |
| Peak memory | 241408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292024251 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.3292024251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3659466467 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 58956238 ps |
| CPU time | 2.89 seconds |
| Started | Oct 09 06:19:50 PM UTC 24 |
| Finished | Oct 09 06:19:53 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659466467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_same_csr_outstanding.3659466467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1781208435 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 369959451 ps |
| CPU time | 5.33 seconds |
| Started | Oct 09 06:19:47 PM UTC 24 |
| Finished | Oct 09 06:19:54 PM UTC 24 |
| Peak memory | 257624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781208435 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.1781208435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1191028561 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 284336496 ps |
| CPU time | 5.64 seconds |
| Started | Oct 09 06:19:54 PM UTC 24 |
| Finished | Oct 09 06:20:01 PM UTC 24 |
| Peak memory | 257964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1191028561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_cs r_mem_rw_with_rand_reset.1191028561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.900532989 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 117046000 ps |
| CPU time | 1.98 seconds |
| Started | Oct 09 06:19:53 PM UTC 24 |
| Finished | Oct 09 06:19:56 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900532989 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.900532989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.2272908380 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 143227124 ps |
| CPU time | 1.66 seconds |
| Started | Oct 09 06:19:52 PM UTC 24 |
| Finished | Oct 09 06:19:55 PM UTC 24 |
| Peak memory | 241076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272908380 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.2272908380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.2549648906 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 323513864 ps |
| CPU time | 4.2 seconds |
| Started | Oct 09 06:19:53 PM UTC 24 |
| Finished | Oct 09 06:19:58 PM UTC 24 |
| Peak memory | 251704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549648906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_same_csr_outstanding.2549648906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.1416374107 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 156581233 ps |
| CPU time | 5.78 seconds |
| Started | Oct 09 06:19:51 PM UTC 24 |
| Finished | Oct 09 06:19:58 PM UTC 24 |
| Peak memory | 251564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416374107 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.1416374107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3742733285 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 1461016738 ps |
| CPU time | 26.56 seconds |
| Started | Oct 09 06:19:52 PM UTC 24 |
| Finished | Oct 09 06:20:20 PM UTC 24 |
| Peak memory | 255868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742733285 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_intg_err.3742733285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3857619760 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 73246558 ps |
| CPU time | 2.5 seconds |
| Started | Oct 09 06:19:55 PM UTC 24 |
| Finished | Oct 09 06:19:58 PM UTC 24 |
| Peak memory | 255632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3857619760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_cs r_mem_rw_with_rand_reset.3857619760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.1880399587 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 154797015 ps |
| CPU time | 2.56 seconds |
| Started | Oct 09 06:19:54 PM UTC 24 |
| Finished | Oct 09 06:19:58 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880399587 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.1880399587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.1290873354 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 43755501 ps |
| CPU time | 2.2 seconds |
| Started | Oct 09 06:19:54 PM UTC 24 |
| Finished | Oct 09 06:19:58 PM UTC 24 |
| Peak memory | 240432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290873354 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.1290873354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.211741586 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 91430794 ps |
| CPU time | 3.14 seconds |
| Started | Oct 09 06:19:55 PM UTC 24 |
| Finished | Oct 09 06:19:59 PM UTC 24 |
| Peak memory | 251564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211741586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_same_csr_outstanding.211741586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2147890964 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 90791450 ps |
| CPU time | 7.66 seconds |
| Started | Oct 09 06:19:54 PM UTC 24 |
| Finished | Oct 09 06:20:03 PM UTC 24 |
| Peak memory | 257668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147890964 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.2147890964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3754852788 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 10319715105 ps |
| CPU time | 21.12 seconds |
| Started | Oct 09 06:19:54 PM UTC 24 |
| Finished | Oct 09 06:20:17 PM UTC 24 |
| Peak memory | 255664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754852788 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_intg_err.3754852788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.4004695034 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 134214529 ps |
| CPU time | 3.26 seconds |
| Started | Oct 09 06:19:59 PM UTC 24 |
| Finished | Oct 09 06:20:03 PM UTC 24 |
| Peak memory | 255724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4004695034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_cs r_mem_rw_with_rand_reset.4004695034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1326272324 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 90302297 ps |
| CPU time | 2.32 seconds |
| Started | Oct 09 06:19:58 PM UTC 24 |
| Finished | Oct 09 06:20:01 PM UTC 24 |
| Peak memory | 251568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326272324 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.1326272324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.1366799815 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 146488177 ps |
| CPU time | 2.62 seconds |
| Started | Oct 09 06:19:57 PM UTC 24 |
| Finished | Oct 09 06:20:00 PM UTC 24 |
| Peak memory | 241216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366799815 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.1366799815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3000551538 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 146429564 ps |
| CPU time | 5.57 seconds |
| Started | Oct 09 06:19:59 PM UTC 24 |
| Finished | Oct 09 06:20:06 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000551538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_same_csr_outstanding.3000551538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1348790035 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 51913258 ps |
| CPU time | 4.72 seconds |
| Started | Oct 09 06:19:56 PM UTC 24 |
| Finished | Oct 09 06:20:01 PM UTC 24 |
| Peak memory | 257772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348790035 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.1348790035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.563702343 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 2378925256 ps |
| CPU time | 10.12 seconds |
| Started | Oct 09 06:19:57 PM UTC 24 |
| Finished | Oct 09 06:20:08 PM UTC 24 |
| Peak memory | 251624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563702343 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_intg_err.563702343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_alert_test.2877189475 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 61554912 ps |
| CPU time | 2.87 seconds |
| Started | Oct 09 08:43:54 PM UTC 24 |
| Finished | Oct 09 08:43:58 PM UTC 24 |
| Peak memory | 252300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877189475 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.2877189475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_errs.755403113 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 257604770 ps |
| CPU time | 10.29 seconds |
| Started | Oct 09 08:43:36 PM UTC 24 |
| Finished | Oct 09 08:43:48 PM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755403113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.755403113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_low_freq_read.3456670722 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7298333970 ps |
| CPU time | 23.52 seconds |
| Started | Oct 09 08:43:30 PM UTC 24 |
| Finished | Oct 09 08:43:55 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456670722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.3456670722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_esc.3369318731 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 312252528 ps |
| CPU time | 5.69 seconds |
| Started | Oct 09 08:43:35 PM UTC 24 |
| Finished | Oct 09 08:43:42 PM UTC 24 |
| Peak memory | 252288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369318731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.3369318731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_partition_walk.875256986 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 9938418001 ps |
| CPU time | 33.91 seconds |
| Started | Oct 09 08:43:29 PM UTC 24 |
| Finished | Oct 09 08:44:04 PM UTC 24 |
| Peak memory | 252316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875256986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.875256986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_regwen.1134182234 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 949809027 ps |
| CPU time | 10.92 seconds |
| Started | Oct 09 08:43:43 PM UTC 24 |
| Finished | Oct 09 08:43:55 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134182234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.1134182234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_sec_cm.4005091011 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 172925926060 ps |
| CPU time | 263.15 seconds |
| Started | Oct 09 08:43:48 PM UTC 24 |
| Finished | Oct 09 08:48:16 PM UTC 24 |
| Peak memory | 289000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005091011 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.4005091011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_smoke.570029846 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 133232487 ps |
| CPU time | 6.3 seconds |
| Started | Oct 09 08:43:28 PM UTC 24 |
| Finished | Oct 09 08:43:35 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570029846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.570029846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_alert_test.1756445171 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 387983255 ps |
| CPU time | 7.93 seconds |
| Started | Oct 09 08:44:15 PM UTC 24 |
| Finished | Oct 09 08:44:25 PM UTC 24 |
| Peak memory | 252272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756445171 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.1756445171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_background_chks.3330222710 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1112887419 ps |
| CPU time | 19.96 seconds |
| Started | Oct 09 08:43:56 PM UTC 24 |
| Finished | Oct 09 08:44:17 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330222710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.3330222710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_errs.1823922299 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 2117458736 ps |
| CPU time | 26.42 seconds |
| Started | Oct 09 08:44:00 PM UTC 24 |
| Finished | Oct 09 08:44:28 PM UTC 24 |
| Peak memory | 252596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823922299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.1823922299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_lock.726834850 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 3430027460 ps |
| CPU time | 29.18 seconds |
| Started | Oct 09 08:43:59 PM UTC 24 |
| Finished | Oct 09 08:44:29 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726834850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.726834850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_macro_errs.2641145340 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 920780808 ps |
| CPU time | 14.59 seconds |
| Started | Oct 09 08:44:02 PM UTC 24 |
| Finished | Oct 09 08:44:18 PM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641145340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.2641145340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_req.3640672499 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 577472807 ps |
| CPU time | 15.53 seconds |
| Started | Oct 09 08:43:56 PM UTC 24 |
| Finished | Oct 09 08:44:13 PM UTC 24 |
| Peak memory | 252352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640672499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.3640672499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_regwen.2948598471 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 563639887 ps |
| CPU time | 10.64 seconds |
| Started | Oct 09 08:44:06 PM UTC 24 |
| Finished | Oct 09 08:44:18 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948598471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.2948598471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_sec_cm.4034521497 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 20245131806 ps |
| CPU time | 183.7 seconds |
| Started | Oct 09 08:44:14 PM UTC 24 |
| Finished | Oct 09 08:47:21 PM UTC 24 |
| Peak memory | 286712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034521497 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.4034521497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_smoke.1340738164 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 218050735 ps |
| CPU time | 7.39 seconds |
| Started | Oct 09 08:43:54 PM UTC 24 |
| Finished | Oct 09 08:44:02 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340738164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.1340738164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_test_access.3216603487 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 875452246 ps |
| CPU time | 13.72 seconds |
| Started | Oct 09 08:44:06 PM UTC 24 |
| Finished | Oct 09 08:44:21 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216603487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.3216603487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_alert_test.4158306555 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 154513486 ps |
| CPU time | 3.91 seconds |
| Started | Oct 09 08:46:20 PM UTC 24 |
| Finished | Oct 09 08:46:25 PM UTC 24 |
| Peak memory | 252240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158306555 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.4158306555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_check_fail.614257440 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 1787105047 ps |
| CPU time | 16.67 seconds |
| Started | Oct 09 08:46:09 PM UTC 24 |
| Finished | Oct 09 08:46:27 PM UTC 24 |
| Peak memory | 254560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614257440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.614257440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_errs.3758950310 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 3196572626 ps |
| CPU time | 16.76 seconds |
| Started | Oct 09 08:46:08 PM UTC 24 |
| Finished | Oct 09 08:46:27 PM UTC 24 |
| Peak memory | 252468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758950310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.3758950310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_lock.3726093612 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 936674360 ps |
| CPU time | 22.63 seconds |
| Started | Oct 09 08:46:08 PM UTC 24 |
| Finished | Oct 09 08:46:33 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726093612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.3726093612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_init_fail.3334945701 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 304797606 ps |
| CPU time | 5.07 seconds |
| Started | Oct 09 08:46:06 PM UTC 24 |
| Finished | Oct 09 08:46:13 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334945701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.3334945701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_macro_errs.3544762325 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 1652380032 ps |
| CPU time | 19.99 seconds |
| Started | Oct 09 08:46:09 PM UTC 24 |
| Finished | Oct 09 08:46:30 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544762325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.3544762325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_key_req.1330623427 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 651608511 ps |
| CPU time | 30.36 seconds |
| Started | Oct 09 08:46:09 PM UTC 24 |
| Finished | Oct 09 08:46:41 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330623427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.1330623427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_esc.1700285979 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 175289427 ps |
| CPU time | 10.43 seconds |
| Started | Oct 09 08:46:06 PM UTC 24 |
| Finished | Oct 09 08:46:18 PM UTC 24 |
| Peak memory | 252344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700285979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.1700285979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_req.381086782 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 3826432148 ps |
| CPU time | 9.24 seconds |
| Started | Oct 09 08:46:06 PM UTC 24 |
| Finished | Oct 09 08:46:17 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381086782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.381086782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_regwen.2271644190 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 375381269 ps |
| CPU time | 6.07 seconds |
| Started | Oct 09 08:46:09 PM UTC 24 |
| Finished | Oct 09 08:46:16 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271644190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.2271644190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_smoke.1886302819 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 7790632151 ps |
| CPU time | 18.59 seconds |
| Started | Oct 09 08:46:04 PM UTC 24 |
| Finished | Oct 09 08:46:24 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886302819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.1886302819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.3402065031 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2012656311 ps |
| CPU time | 48.83 seconds |
| Started | Oct 09 08:46:17 PM UTC 24 |
| Finished | Oct 09 08:47:07 PM UTC 24 |
| Peak memory | 269028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3402065031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.otp_ctrl_stress_all_with_rand_reset.3402065031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_test_access.1710443901 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1183047269 ps |
| CPU time | 12.88 seconds |
| Started | Oct 09 08:46:10 PM UTC 24 |
| Finished | Oct 09 08:46:24 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710443901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.1710443901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_init_fail.3737629924 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 247104694 ps |
| CPU time | 4.27 seconds |
| Started | Oct 09 08:53:43 PM UTC 24 |
| Finished | Oct 09 08:53:49 PM UTC 24 |
| Peak memory | 252552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737629924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.3737629924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/101.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_parallel_lc_esc.3498692735 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 201655102 ps |
| CPU time | 9.86 seconds |
| Started | Oct 09 08:53:43 PM UTC 24 |
| Finished | Oct 09 08:53:55 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498692735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.3498692735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/101.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_init_fail.1430445115 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 108855336 ps |
| CPU time | 5.77 seconds |
| Started | Oct 09 08:53:44 PM UTC 24 |
| Finished | Oct 09 08:53:51 PM UTC 24 |
| Peak memory | 252472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430445115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.1430445115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/102.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_parallel_lc_esc.1553304183 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 758100109 ps |
| CPU time | 22.07 seconds |
| Started | Oct 09 08:53:44 PM UTC 24 |
| Finished | Oct 09 08:54:08 PM UTC 24 |
| Peak memory | 252392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553304183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.1553304183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/102.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_init_fail.3366763052 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 313903661 ps |
| CPU time | 5.55 seconds |
| Started | Oct 09 08:53:44 PM UTC 24 |
| Finished | Oct 09 08:53:51 PM UTC 24 |
| Peak memory | 252348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366763052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.3366763052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/103.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_parallel_lc_esc.1896922298 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 212737733 ps |
| CPU time | 5.6 seconds |
| Started | Oct 09 08:53:48 PM UTC 24 |
| Finished | Oct 09 08:53:55 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896922298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.1896922298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/103.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_init_fail.1395788969 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 150388173 ps |
| CPU time | 5.18 seconds |
| Started | Oct 09 08:53:48 PM UTC 24 |
| Finished | Oct 09 08:53:55 PM UTC 24 |
| Peak memory | 252436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395788969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.1395788969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/104.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_parallel_lc_esc.2824717501 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 841102488 ps |
| CPU time | 7.97 seconds |
| Started | Oct 09 08:53:48 PM UTC 24 |
| Finished | Oct 09 08:53:58 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824717501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.2824717501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/104.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_parallel_lc_esc.921548365 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 2127258797 ps |
| CPU time | 8.64 seconds |
| Started | Oct 09 08:53:49 PM UTC 24 |
| Finished | Oct 09 08:53:59 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921548365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.921548365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/105.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_init_fail.1204290450 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 110387699 ps |
| CPU time | 5.56 seconds |
| Started | Oct 09 08:53:58 PM UTC 24 |
| Finished | Oct 09 08:54:04 PM UTC 24 |
| Peak memory | 252484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204290450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.1204290450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/106.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_parallel_lc_esc.9353714 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 271189392 ps |
| CPU time | 7.49 seconds |
| Started | Oct 09 08:53:58 PM UTC 24 |
| Finished | Oct 09 08:54:07 PM UTC 24 |
| Peak memory | 252352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9353714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.9353714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/106.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_init_fail.539777971 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 348429849 ps |
| CPU time | 4.61 seconds |
| Started | Oct 09 08:53:58 PM UTC 24 |
| Finished | Oct 09 08:54:04 PM UTC 24 |
| Peak memory | 252332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539777971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.539777971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/107.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_parallel_lc_esc.3837864686 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 208321120 ps |
| CPU time | 5.3 seconds |
| Started | Oct 09 08:53:58 PM UTC 24 |
| Finished | Oct 09 08:54:04 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837864686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.3837864686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/107.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_init_fail.700215412 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 608012324 ps |
| CPU time | 4.77 seconds |
| Started | Oct 09 08:53:58 PM UTC 24 |
| Finished | Oct 09 08:54:04 PM UTC 24 |
| Peak memory | 252396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700215412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.700215412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/108.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_parallel_lc_esc.595696469 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 822135198 ps |
| CPU time | 16.34 seconds |
| Started | Oct 09 08:53:58 PM UTC 24 |
| Finished | Oct 09 08:54:16 PM UTC 24 |
| Peak memory | 252320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595696469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.595696469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/108.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_init_fail.4207896806 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 2404171663 ps |
| CPU time | 9.26 seconds |
| Started | Oct 09 08:53:58 PM UTC 24 |
| Finished | Oct 09 08:54:08 PM UTC 24 |
| Peak memory | 252404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207896806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.4207896806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/109.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_parallel_lc_esc.2386213126 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 345979339 ps |
| CPU time | 6.71 seconds |
| Started | Oct 09 08:53:58 PM UTC 24 |
| Finished | Oct 09 08:54:06 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386213126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.2386213126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/109.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_alert_test.1133236441 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 161957530 ps |
| CPU time | 3.47 seconds |
| Started | Oct 09 08:46:25 PM UTC 24 |
| Finished | Oct 09 08:46:31 PM UTC 24 |
| Peak memory | 252300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133236441 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.1133236441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_check_fail.2881337145 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 242418177 ps |
| CPU time | 6.54 seconds |
| Started | Oct 09 08:46:21 PM UTC 24 |
| Finished | Oct 09 08:46:28 PM UTC 24 |
| Peak memory | 258588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881337145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.2881337145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_lock.148689346 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 4380591894 ps |
| CPU time | 12.24 seconds |
| Started | Oct 09 08:46:21 PM UTC 24 |
| Finished | Oct 09 08:46:34 PM UTC 24 |
| Peak memory | 252592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148689346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.148689346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_init_fail.3188004951 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 129896724 ps |
| CPU time | 5.02 seconds |
| Started | Oct 09 08:46:20 PM UTC 24 |
| Finished | Oct 09 08:46:27 PM UTC 24 |
| Peak memory | 252248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188004951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.3188004951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_macro_errs.4245612878 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 1018424163 ps |
| CPU time | 22.39 seconds |
| Started | Oct 09 08:46:21 PM UTC 24 |
| Finished | Oct 09 08:46:45 PM UTC 24 |
| Peak memory | 254500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245612878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.4245612878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_key_req.1663170400 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 355795061 ps |
| CPU time | 12.93 seconds |
| Started | Oct 09 08:46:21 PM UTC 24 |
| Finished | Oct 09 08:46:35 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663170400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.1663170400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_esc.3228667605 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 1851913365 ps |
| CPU time | 7.42 seconds |
| Started | Oct 09 08:46:20 PM UTC 24 |
| Finished | Oct 09 08:46:29 PM UTC 24 |
| Peak memory | 252356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228667605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.3228667605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_req.898390342 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 336806568 ps |
| CPU time | 5.38 seconds |
| Started | Oct 09 08:46:20 PM UTC 24 |
| Finished | Oct 09 08:46:27 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898390342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.898390342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_regwen.1201004244 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 489711187 ps |
| CPU time | 8.2 seconds |
| Started | Oct 09 08:46:21 PM UTC 24 |
| Finished | Oct 09 08:46:30 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201004244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.1201004244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_smoke.3503585163 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 128409215 ps |
| CPU time | 4.58 seconds |
| Started | Oct 09 08:46:20 PM UTC 24 |
| Finished | Oct 09 08:46:26 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503585163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.3503585163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.1579969182 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 15375677527 ps |
| CPU time | 99.41 seconds |
| Started | Oct 09 08:46:22 PM UTC 24 |
| Finished | Oct 09 08:48:04 PM UTC 24 |
| Peak memory | 268996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1579969182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.otp_ctrl_stress_all_with_rand_reset.1579969182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_init_fail.1980778921 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 270933759 ps |
| CPU time | 4.16 seconds |
| Started | Oct 09 08:53:58 PM UTC 24 |
| Finished | Oct 09 08:54:03 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980778921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.1980778921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/110.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_parallel_lc_esc.2839904970 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 227779274 ps |
| CPU time | 5.26 seconds |
| Started | Oct 09 08:53:58 PM UTC 24 |
| Finished | Oct 09 08:54:05 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839904970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.2839904970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/110.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_init_fail.2202245979 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 103739840 ps |
| CPU time | 5.3 seconds |
| Started | Oct 09 08:53:58 PM UTC 24 |
| Finished | Oct 09 08:54:05 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202245979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.2202245979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/111.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_parallel_lc_esc.480127620 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 269596441 ps |
| CPU time | 6.97 seconds |
| Started | Oct 09 08:53:58 PM UTC 24 |
| Finished | Oct 09 08:54:06 PM UTC 24 |
| Peak memory | 252296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480127620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.480127620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/111.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_init_fail.3769585887 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 180604435 ps |
| CPU time | 5.2 seconds |
| Started | Oct 09 08:53:58 PM UTC 24 |
| Finished | Oct 09 08:54:05 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769585887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.3769585887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/112.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_parallel_lc_esc.1546793295 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 376444686 ps |
| CPU time | 8.76 seconds |
| Started | Oct 09 08:53:58 PM UTC 24 |
| Finished | Oct 09 08:54:08 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546793295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.1546793295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/112.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_init_fail.595878786 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 443785139 ps |
| CPU time | 3.02 seconds |
| Started | Oct 09 08:53:58 PM UTC 24 |
| Finished | Oct 09 08:54:03 PM UTC 24 |
| Peak memory | 252392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595878786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.595878786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/113.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_parallel_lc_esc.447983490 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 80533238 ps |
| CPU time | 4.18 seconds |
| Started | Oct 09 08:53:58 PM UTC 24 |
| Finished | Oct 09 08:54:04 PM UTC 24 |
| Peak memory | 252232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447983490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.447983490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/113.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_init_fail.1729502178 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 237596660 ps |
| CPU time | 4.67 seconds |
| Started | Oct 09 08:54:01 PM UTC 24 |
| Finished | Oct 09 08:54:07 PM UTC 24 |
| Peak memory | 252476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729502178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.1729502178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/114.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_parallel_lc_esc.922126272 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 387162705 ps |
| CPU time | 3.32 seconds |
| Started | Oct 09 08:54:01 PM UTC 24 |
| Finished | Oct 09 08:54:05 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922126272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.922126272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/114.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_init_fail.927836061 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 1566243411 ps |
| CPU time | 4.64 seconds |
| Started | Oct 09 08:54:01 PM UTC 24 |
| Finished | Oct 09 08:54:07 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927836061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.927836061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/115.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_parallel_lc_esc.1883850917 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 467011205 ps |
| CPU time | 13.94 seconds |
| Started | Oct 09 08:54:01 PM UTC 24 |
| Finished | Oct 09 08:54:16 PM UTC 24 |
| Peak memory | 252312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883850917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.1883850917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/115.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_init_fail.4202824566 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 108356466 ps |
| CPU time | 4.52 seconds |
| Started | Oct 09 08:54:01 PM UTC 24 |
| Finished | Oct 09 08:54:07 PM UTC 24 |
| Peak memory | 252484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202824566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.4202824566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/116.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_parallel_lc_esc.3020340626 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 1178065156 ps |
| CPU time | 9.51 seconds |
| Started | Oct 09 08:54:04 PM UTC 24 |
| Finished | Oct 09 08:54:15 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020340626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.3020340626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/116.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_parallel_lc_esc.3584359235 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 304775763 ps |
| CPU time | 4.42 seconds |
| Started | Oct 09 08:54:08 PM UTC 24 |
| Finished | Oct 09 08:54:14 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584359235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.3584359235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/117.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_init_fail.786246217 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 108695415 ps |
| CPU time | 3.88 seconds |
| Started | Oct 09 08:54:08 PM UTC 24 |
| Finished | Oct 09 08:54:13 PM UTC 24 |
| Peak memory | 252460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786246217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.786246217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/118.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_parallel_lc_esc.2692486279 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 342592866 ps |
| CPU time | 5.11 seconds |
| Started | Oct 09 08:54:08 PM UTC 24 |
| Finished | Oct 09 08:54:15 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692486279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.2692486279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/118.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_init_fail.3198784939 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 358095349 ps |
| CPU time | 4 seconds |
| Started | Oct 09 08:54:08 PM UTC 24 |
| Finished | Oct 09 08:54:14 PM UTC 24 |
| Peak memory | 252224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198784939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.3198784939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/119.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_parallel_lc_esc.2604904066 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 780966240 ps |
| CPU time | 10.19 seconds |
| Started | Oct 09 08:54:08 PM UTC 24 |
| Finished | Oct 09 08:54:20 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604904066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.2604904066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/119.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_alert_test.2347358093 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 709859102 ps |
| CPU time | 2.72 seconds |
| Started | Oct 09 08:46:31 PM UTC 24 |
| Finished | Oct 09 08:46:35 PM UTC 24 |
| Peak memory | 252244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347358093 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.2347358093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_errs.2600757697 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 980168008 ps |
| CPU time | 35.01 seconds |
| Started | Oct 09 08:46:28 PM UTC 24 |
| Finished | Oct 09 08:47:05 PM UTC 24 |
| Peak memory | 256564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600757697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.2600757697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_lock.320265964 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 803937772 ps |
| CPU time | 26.5 seconds |
| Started | Oct 09 08:46:27 PM UTC 24 |
| Finished | Oct 09 08:46:55 PM UTC 24 |
| Peak memory | 252592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320265964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.320265964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_macro_errs.2049873381 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2370130244 ps |
| CPU time | 39.14 seconds |
| Started | Oct 09 08:46:28 PM UTC 24 |
| Finished | Oct 09 08:47:10 PM UTC 24 |
| Peak memory | 254560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049873381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.2049873381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_key_req.765377532 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1007405184 ps |
| CPU time | 22.14 seconds |
| Started | Oct 09 08:46:28 PM UTC 24 |
| Finished | Oct 09 08:46:52 PM UTC 24 |
| Peak memory | 252436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765377532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.765377532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_esc.3865821496 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 120497420 ps |
| CPU time | 6.04 seconds |
| Started | Oct 09 08:46:26 PM UTC 24 |
| Finished | Oct 09 08:46:34 PM UTC 24 |
| Peak memory | 252288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865821496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.3865821496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_req.4189590999 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 370242240 ps |
| CPU time | 12.45 seconds |
| Started | Oct 09 08:46:25 PM UTC 24 |
| Finished | Oct 09 08:46:40 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189590999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.4189590999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_regwen.2359929958 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 257699496 ps |
| CPU time | 6 seconds |
| Started | Oct 09 08:46:28 PM UTC 24 |
| Finished | Oct 09 08:46:36 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359929958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2359929958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_smoke.3283156579 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 436564328 ps |
| CPU time | 4.06 seconds |
| Started | Oct 09 08:46:25 PM UTC 24 |
| Finished | Oct 09 08:46:31 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283156579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.3283156579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all.1117139002 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 12391127211 ps |
| CPU time | 110.67 seconds |
| Started | Oct 09 08:46:30 PM UTC 24 |
| Finished | Oct 09 08:48:24 PM UTC 24 |
| Peak memory | 258788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117139002 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.1117139002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_test_access.1610971489 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 340905949 ps |
| CPU time | 6.78 seconds |
| Started | Oct 09 08:46:28 PM UTC 24 |
| Finished | Oct 09 08:46:37 PM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610971489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.1610971489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/12.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_init_fail.3530378731 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 1731094706 ps |
| CPU time | 3.91 seconds |
| Started | Oct 09 08:54:08 PM UTC 24 |
| Finished | Oct 09 08:54:14 PM UTC 24 |
| Peak memory | 252412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530378731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.3530378731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/120.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_init_fail.2330051675 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 147595831 ps |
| CPU time | 5.02 seconds |
| Started | Oct 09 08:54:09 PM UTC 24 |
| Finished | Oct 09 08:54:15 PM UTC 24 |
| Peak memory | 252316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330051675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.2330051675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/121.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_parallel_lc_esc.3687572761 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 216614149 ps |
| CPU time | 4.99 seconds |
| Started | Oct 09 08:54:09 PM UTC 24 |
| Finished | Oct 09 08:54:15 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687572761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.3687572761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/121.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_init_fail.756401714 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 145639724 ps |
| CPU time | 3.41 seconds |
| Started | Oct 09 08:54:09 PM UTC 24 |
| Finished | Oct 09 08:54:13 PM UTC 24 |
| Peak memory | 252328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756401714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.756401714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/122.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_parallel_lc_esc.1596316751 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 596217101 ps |
| CPU time | 13.19 seconds |
| Started | Oct 09 08:54:09 PM UTC 24 |
| Finished | Oct 09 08:54:23 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596316751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.1596316751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/122.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_init_fail.829995984 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 229379064 ps |
| CPU time | 3.26 seconds |
| Started | Oct 09 08:54:09 PM UTC 24 |
| Finished | Oct 09 08:54:13 PM UTC 24 |
| Peak memory | 252200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829995984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.829995984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/123.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_parallel_lc_esc.1747650305 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 300105956 ps |
| CPU time | 6.61 seconds |
| Started | Oct 09 08:54:09 PM UTC 24 |
| Finished | Oct 09 08:54:17 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747650305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.1747650305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/123.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_init_fail.3249344816 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 294576396 ps |
| CPU time | 4.02 seconds |
| Started | Oct 09 08:54:09 PM UTC 24 |
| Finished | Oct 09 08:54:14 PM UTC 24 |
| Peak memory | 252476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249344816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.3249344816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/124.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_parallel_lc_esc.3842504527 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 460033573 ps |
| CPU time | 9.68 seconds |
| Started | Oct 09 08:54:16 PM UTC 24 |
| Finished | Oct 09 08:54:27 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842504527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.3842504527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/124.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_init_fail.673262912 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 283518190 ps |
| CPU time | 5.05 seconds |
| Started | Oct 09 08:54:16 PM UTC 24 |
| Finished | Oct 09 08:54:22 PM UTC 24 |
| Peak memory | 252392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673262912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.673262912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/125.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_parallel_lc_esc.1859602517 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 125624945 ps |
| CPU time | 5.07 seconds |
| Started | Oct 09 08:54:16 PM UTC 24 |
| Finished | Oct 09 08:54:23 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859602517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.1859602517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/125.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_init_fail.2200009848 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 445719578 ps |
| CPU time | 4.23 seconds |
| Started | Oct 09 08:54:16 PM UTC 24 |
| Finished | Oct 09 08:54:22 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200009848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.2200009848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/126.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_parallel_lc_esc.819020682 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 2761207678 ps |
| CPU time | 21.52 seconds |
| Started | Oct 09 08:54:16 PM UTC 24 |
| Finished | Oct 09 08:54:39 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819020682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.819020682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/126.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_init_fail.3644318406 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 167686224 ps |
| CPU time | 4.92 seconds |
| Started | Oct 09 08:54:16 PM UTC 24 |
| Finished | Oct 09 08:54:23 PM UTC 24 |
| Peak memory | 252344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644318406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.3644318406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/127.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_parallel_lc_esc.4135685601 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 612432840 ps |
| CPU time | 17.66 seconds |
| Started | Oct 09 08:54:16 PM UTC 24 |
| Finished | Oct 09 08:54:36 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135685601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.4135685601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/127.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_init_fail.525106764 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 123806538 ps |
| CPU time | 4.08 seconds |
| Started | Oct 09 08:54:16 PM UTC 24 |
| Finished | Oct 09 08:54:22 PM UTC 24 |
| Peak memory | 252252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525106764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.525106764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/128.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_parallel_lc_esc.2409068662 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 137953932 ps |
| CPU time | 4.86 seconds |
| Started | Oct 09 08:54:16 PM UTC 24 |
| Finished | Oct 09 08:54:23 PM UTC 24 |
| Peak memory | 252316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409068662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.2409068662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/128.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_init_fail.2600392864 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 2080830749 ps |
| CPU time | 5.02 seconds |
| Started | Oct 09 08:54:16 PM UTC 24 |
| Finished | Oct 09 08:54:23 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600392864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.2600392864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/129.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_parallel_lc_esc.3495080834 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 630856411 ps |
| CPU time | 5.23 seconds |
| Started | Oct 09 08:54:17 PM UTC 24 |
| Finished | Oct 09 08:54:23 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495080834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.3495080834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/129.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_alert_test.905626742 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 97980126 ps |
| CPU time | 1.93 seconds |
| Started | Oct 09 08:46:35 PM UTC 24 |
| Finished | Oct 09 08:46:39 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905626742 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.905626742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_errs.3013937289 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 932637258 ps |
| CPU time | 19.68 seconds |
| Started | Oct 09 08:46:33 PM UTC 24 |
| Finished | Oct 09 08:46:54 PM UTC 24 |
| Peak memory | 252268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013937289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.3013937289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_lock.3641895957 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 12335829508 ps |
| CPU time | 34.62 seconds |
| Started | Oct 09 08:46:33 PM UTC 24 |
| Finished | Oct 09 08:47:09 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641895957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.3641895957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_init_fail.4159297095 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 1577022447 ps |
| CPU time | 5.62 seconds |
| Started | Oct 09 08:46:33 PM UTC 24 |
| Finished | Oct 09 08:46:39 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159297095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.4159297095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_macro_errs.192551239 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1995246336 ps |
| CPU time | 12.55 seconds |
| Started | Oct 09 08:46:33 PM UTC 24 |
| Finished | Oct 09 08:46:47 PM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192551239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.192551239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_key_req.1177348614 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 710876034 ps |
| CPU time | 26.07 seconds |
| Started | Oct 09 08:46:33 PM UTC 24 |
| Finished | Oct 09 08:47:01 PM UTC 24 |
| Peak memory | 252460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177348614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.1177348614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_req.318202660 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 859491643 ps |
| CPU time | 11.87 seconds |
| Started | Oct 09 08:46:33 PM UTC 24 |
| Finished | Oct 09 08:46:46 PM UTC 24 |
| Peak memory | 252168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318202660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.318202660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_regwen.2958819751 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 158618623 ps |
| CPU time | 6.94 seconds |
| Started | Oct 09 08:46:35 PM UTC 24 |
| Finished | Oct 09 08:46:44 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958819751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.2958819751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_smoke.4249997800 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 1895266707 ps |
| CPU time | 12.84 seconds |
| Started | Oct 09 08:46:31 PM UTC 24 |
| Finished | Oct 09 08:46:45 PM UTC 24 |
| Peak memory | 252524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249997800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.4249997800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all.4059813294 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 28919782286 ps |
| CPU time | 322.22 seconds |
| Started | Oct 09 08:46:35 PM UTC 24 |
| Finished | Oct 09 08:52:02 PM UTC 24 |
| Peak memory | 282068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059813294 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.4059813294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_test_access.2294586450 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1680231592 ps |
| CPU time | 10.04 seconds |
| Started | Oct 09 08:46:35 PM UTC 24 |
| Finished | Oct 09 08:46:47 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294586450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.2294586450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/13.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_init_fail.2548863205 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 101672738 ps |
| CPU time | 3.71 seconds |
| Started | Oct 09 08:54:17 PM UTC 24 |
| Finished | Oct 09 08:54:22 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548863205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.2548863205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/130.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_parallel_lc_esc.155108739 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 315952944 ps |
| CPU time | 12.3 seconds |
| Started | Oct 09 08:54:17 PM UTC 24 |
| Finished | Oct 09 08:54:30 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155108739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.155108739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/130.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_parallel_lc_esc.3383733830 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 127825682 ps |
| CPU time | 5.08 seconds |
| Started | Oct 09 08:54:17 PM UTC 24 |
| Finished | Oct 09 08:54:23 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383733830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.3383733830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/131.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_init_fail.2976980142 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 511725630 ps |
| CPU time | 3.72 seconds |
| Started | Oct 09 08:54:17 PM UTC 24 |
| Finished | Oct 09 08:54:22 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976980142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.2976980142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/132.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_parallel_lc_esc.232828077 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 1619864191 ps |
| CPU time | 12.05 seconds |
| Started | Oct 09 08:54:17 PM UTC 24 |
| Finished | Oct 09 08:54:30 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232828077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.232828077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/132.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_init_fail.2185693681 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 121767154 ps |
| CPU time | 4.17 seconds |
| Started | Oct 09 08:54:17 PM UTC 24 |
| Finished | Oct 09 08:54:22 PM UTC 24 |
| Peak memory | 252344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185693681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.2185693681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/133.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_parallel_lc_esc.30556472 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 566085590 ps |
| CPU time | 6.68 seconds |
| Started | Oct 09 08:54:17 PM UTC 24 |
| Finished | Oct 09 08:54:25 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30556472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.30556472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/134.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_init_fail.4169709857 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 2440658372 ps |
| CPU time | 6.59 seconds |
| Started | Oct 09 08:54:17 PM UTC 24 |
| Finished | Oct 09 08:54:25 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169709857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.4169709857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/135.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_parallel_lc_esc.2032352641 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 780446704 ps |
| CPU time | 12.53 seconds |
| Started | Oct 09 08:54:17 PM UTC 24 |
| Finished | Oct 09 08:54:31 PM UTC 24 |
| Peak memory | 252316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032352641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.2032352641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/135.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_init_fail.1029832380 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 111455940 ps |
| CPU time | 4.62 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:32 PM UTC 24 |
| Peak memory | 252412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029832380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.1029832380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/136.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_parallel_lc_esc.1449705987 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 1602551865 ps |
| CPU time | 23.33 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:51 PM UTC 24 |
| Peak memory | 252328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449705987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.1449705987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/136.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_init_fail.2234348169 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 626567944 ps |
| CPU time | 4.62 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:32 PM UTC 24 |
| Peak memory | 252344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234348169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.2234348169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/137.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_parallel_lc_esc.3731702503 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 442665026 ps |
| CPU time | 7.63 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:35 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731702503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.3731702503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/137.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_init_fail.693905705 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 306961008 ps |
| CPU time | 4.24 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:31 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693905705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.693905705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/138.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_parallel_lc_esc.2076949784 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 619938199 ps |
| CPU time | 15.38 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:43 PM UTC 24 |
| Peak memory | 252320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076949784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.2076949784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/138.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_init_fail.2228278300 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 323008441 ps |
| CPU time | 5.12 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:32 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228278300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2228278300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/139.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_parallel_lc_esc.1527730216 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 79096860 ps |
| CPU time | 2.47 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:30 PM UTC 24 |
| Peak memory | 252232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527730216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.1527730216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/139.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_alert_test.873565997 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 131653258 ps |
| CPU time | 2.81 seconds |
| Started | Oct 09 08:46:47 PM UTC 24 |
| Finished | Oct 09 08:46:51 PM UTC 24 |
| Peak memory | 252320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873565997 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.873565997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_check_fail.953308201 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 4242154737 ps |
| CPU time | 26.16 seconds |
| Started | Oct 09 08:46:40 PM UTC 24 |
| Finished | Oct 09 08:47:08 PM UTC 24 |
| Peak memory | 256668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953308201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.953308201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_errs.4061552275 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 2133954454 ps |
| CPU time | 17.96 seconds |
| Started | Oct 09 08:46:39 PM UTC 24 |
| Finished | Oct 09 08:46:58 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061552275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.4061552275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_lock.279863255 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 760537121 ps |
| CPU time | 23.64 seconds |
| Started | Oct 09 08:46:39 PM UTC 24 |
| Finished | Oct 09 08:47:04 PM UTC 24 |
| Peak memory | 252528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279863255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.279863255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_macro_errs.4263056093 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1756762278 ps |
| CPU time | 21.28 seconds |
| Started | Oct 09 08:46:40 PM UTC 24 |
| Finished | Oct 09 08:47:03 PM UTC 24 |
| Peak memory | 252592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263056093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.4263056093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_key_req.784314497 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 2343821598 ps |
| CPU time | 22.03 seconds |
| Started | Oct 09 08:46:42 PM UTC 24 |
| Finished | Oct 09 08:47:05 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784314497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.784314497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_esc.2275367380 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 756722577 ps |
| CPU time | 7.34 seconds |
| Started | Oct 09 08:46:38 PM UTC 24 |
| Finished | Oct 09 08:46:46 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275367380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.2275367380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_req.3445478841 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 872518098 ps |
| CPU time | 24 seconds |
| Started | Oct 09 08:46:38 PM UTC 24 |
| Finished | Oct 09 08:47:03 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445478841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.3445478841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_smoke.4139802485 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 807186215 ps |
| CPU time | 5.89 seconds |
| Started | Oct 09 08:46:37 PM UTC 24 |
| Finished | Oct 09 08:46:44 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139802485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.4139802485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all.3525360548 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 39913033356 ps |
| CPU time | 198.63 seconds |
| Started | Oct 09 08:46:45 PM UTC 24 |
| Finished | Oct 09 08:50:07 PM UTC 24 |
| Peak memory | 256652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525360548 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.3525360548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_test_access.2241071615 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 517893661 ps |
| CPU time | 13.88 seconds |
| Started | Oct 09 08:46:43 PM UTC 24 |
| Finished | Oct 09 08:46:58 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241071615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.2241071615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/14.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_parallel_lc_esc.248302460 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 135975316 ps |
| CPU time | 5.28 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:33 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248302460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.248302460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/140.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_init_fail.3187073500 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 371965153 ps |
| CPU time | 3.24 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:31 PM UTC 24 |
| Peak memory | 252552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187073500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.3187073500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/141.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_parallel_lc_esc.528938042 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 600493920 ps |
| CPU time | 6.8 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:34 PM UTC 24 |
| Peak memory | 252296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528938042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.528938042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/141.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_init_fail.400215857 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 274029776 ps |
| CPU time | 3.64 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:31 PM UTC 24 |
| Peak memory | 252308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400215857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.400215857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/142.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_parallel_lc_esc.1040252338 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 677994877 ps |
| CPU time | 6.47 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:34 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040252338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.1040252338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/142.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_init_fail.3478243352 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 257360803 ps |
| CPU time | 3.9 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:32 PM UTC 24 |
| Peak memory | 252332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478243352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.3478243352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/143.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_parallel_lc_esc.4045720190 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 184455317 ps |
| CPU time | 3.77 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:31 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045720190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.4045720190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/143.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_init_fail.2651872089 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 137460733 ps |
| CPU time | 4.76 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:33 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651872089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.2651872089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/144.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_parallel_lc_esc.10528044 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 2546725821 ps |
| CPU time | 5.38 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:33 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10528044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.10528044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/144.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_init_fail.2459139199 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 279676332 ps |
| CPU time | 4.46 seconds |
| Started | Oct 09 08:54:26 PM UTC 24 |
| Finished | Oct 09 08:54:32 PM UTC 24 |
| Peak memory | 252408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459139199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.2459139199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/145.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_parallel_lc_esc.3218038258 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 3708166040 ps |
| CPU time | 8.99 seconds |
| Started | Oct 09 08:54:27 PM UTC 24 |
| Finished | Oct 09 08:54:37 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218038258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.3218038258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/145.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_init_fail.3882819258 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 1840017875 ps |
| CPU time | 3.94 seconds |
| Started | Oct 09 08:54:27 PM UTC 24 |
| Finished | Oct 09 08:54:32 PM UTC 24 |
| Peak memory | 252480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882819258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.3882819258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/146.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_parallel_lc_esc.2612266696 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 157799207 ps |
| CPU time | 4.01 seconds |
| Started | Oct 09 08:54:27 PM UTC 24 |
| Finished | Oct 09 08:54:32 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612266696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.2612266696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/146.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_init_fail.1890010924 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 3052311384 ps |
| CPU time | 4.97 seconds |
| Started | Oct 09 08:54:27 PM UTC 24 |
| Finished | Oct 09 08:54:33 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890010924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.1890010924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/147.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_parallel_lc_esc.1709317932 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 1235705144 ps |
| CPU time | 4.95 seconds |
| Started | Oct 09 08:54:27 PM UTC 24 |
| Finished | Oct 09 08:54:33 PM UTC 24 |
| Peak memory | 252356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709317932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.1709317932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/147.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_init_fail.2230664308 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 1633854136 ps |
| CPU time | 6.77 seconds |
| Started | Oct 09 08:54:27 PM UTC 24 |
| Finished | Oct 09 08:54:35 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230664308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.2230664308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/148.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_parallel_lc_esc.1829986500 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 1115125631 ps |
| CPU time | 8.5 seconds |
| Started | Oct 09 08:54:27 PM UTC 24 |
| Finished | Oct 09 08:54:37 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829986500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.1829986500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/148.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_init_fail.4212256126 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 129454142 ps |
| CPU time | 3.5 seconds |
| Started | Oct 09 08:54:30 PM UTC 24 |
| Finished | Oct 09 08:54:35 PM UTC 24 |
| Peak memory | 252340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212256126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.4212256126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/149.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_parallel_lc_esc.3604980376 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 4700318130 ps |
| CPU time | 8.97 seconds |
| Started | Oct 09 08:54:30 PM UTC 24 |
| Finished | Oct 09 08:54:40 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604980376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.3604980376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/149.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_alert_test.1834963262 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 213606271 ps |
| CPU time | 2.12 seconds |
| Started | Oct 09 08:46:58 PM UTC 24 |
| Finished | Oct 09 08:47:01 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834963262 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.1834963262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_check_fail.4125165133 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 1288180908 ps |
| CPU time | 15.22 seconds |
| Started | Oct 09 08:46:52 PM UTC 24 |
| Finished | Oct 09 08:47:08 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125165133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.4125165133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_errs.870657618 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2476657129 ps |
| CPU time | 32.72 seconds |
| Started | Oct 09 08:46:49 PM UTC 24 |
| Finished | Oct 09 08:47:23 PM UTC 24 |
| Peak memory | 256564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870657618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.870657618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_init_fail.2650012937 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 137956767 ps |
| CPU time | 4.63 seconds |
| Started | Oct 09 08:46:47 PM UTC 24 |
| Finished | Oct 09 08:46:53 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650012937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.2650012937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_macro_errs.1341285909 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 286956003 ps |
| CPU time | 6.99 seconds |
| Started | Oct 09 08:46:52 PM UTC 24 |
| Finished | Oct 09 08:47:00 PM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341285909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.1341285909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_key_req.3183558512 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1093604478 ps |
| CPU time | 15.99 seconds |
| Started | Oct 09 08:46:54 PM UTC 24 |
| Finished | Oct 09 08:47:12 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183558512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.3183558512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_esc.4005734016 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 605680503 ps |
| CPU time | 7.38 seconds |
| Started | Oct 09 08:46:47 PM UTC 24 |
| Finished | Oct 09 08:46:56 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005734016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.4005734016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_req.4025817732 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 369867069 ps |
| CPU time | 14.89 seconds |
| Started | Oct 09 08:46:47 PM UTC 24 |
| Finished | Oct 09 08:47:03 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025817732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.4025817732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_regwen.3397577104 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 143483285 ps |
| CPU time | 5.2 seconds |
| Started | Oct 09 08:46:54 PM UTC 24 |
| Finished | Oct 09 08:47:01 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397577104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.3397577104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_smoke.268276588 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 362391617 ps |
| CPU time | 7 seconds |
| Started | Oct 09 08:46:47 PM UTC 24 |
| Finished | Oct 09 08:46:55 PM UTC 24 |
| Peak memory | 252524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268276588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.268276588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all.1720056933 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 6040037869 ps |
| CPU time | 14.19 seconds |
| Started | Oct 09 08:46:56 PM UTC 24 |
| Finished | Oct 09 08:47:11 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720056933 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.1720056933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.2305498376 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 1026164945 ps |
| CPU time | 27.07 seconds |
| Started | Oct 09 08:46:56 PM UTC 24 |
| Finished | Oct 09 08:47:24 PM UTC 24 |
| Peak memory | 258692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2305498376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.otp_ctrl_stress_all_with_rand_reset.2305498376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_test_access.2866622246 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 857819190 ps |
| CPU time | 9.28 seconds |
| Started | Oct 09 08:46:56 PM UTC 24 |
| Finished | Oct 09 08:47:06 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866622246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.2866622246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/15.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_init_fail.1179124533 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 2035975423 ps |
| CPU time | 4.89 seconds |
| Started | Oct 09 08:54:30 PM UTC 24 |
| Finished | Oct 09 08:54:36 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179124533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.1179124533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/150.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_parallel_lc_esc.2716664080 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 1523858655 ps |
| CPU time | 4.84 seconds |
| Started | Oct 09 08:54:30 PM UTC 24 |
| Finished | Oct 09 08:54:36 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716664080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.2716664080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/150.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_init_fail.4109354076 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 1740971630 ps |
| CPU time | 5.05 seconds |
| Started | Oct 09 08:54:30 PM UTC 24 |
| Finished | Oct 09 08:54:36 PM UTC 24 |
| Peak memory | 252408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109354076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.4109354076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/151.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_parallel_lc_esc.4274637129 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 10322666302 ps |
| CPU time | 20.65 seconds |
| Started | Oct 09 08:54:30 PM UTC 24 |
| Finished | Oct 09 08:54:52 PM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274637129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.4274637129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/151.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_init_fail.1833011629 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 399862299 ps |
| CPU time | 4.58 seconds |
| Started | Oct 09 08:54:35 PM UTC 24 |
| Finished | Oct 09 08:54:41 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833011629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.1833011629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/152.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_parallel_lc_esc.2959237636 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 252075648 ps |
| CPU time | 9.06 seconds |
| Started | Oct 09 08:54:35 PM UTC 24 |
| Finished | Oct 09 08:54:45 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959237636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.2959237636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/152.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_init_fail.291817947 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 110679163 ps |
| CPU time | 3.3 seconds |
| Started | Oct 09 08:54:35 PM UTC 24 |
| Finished | Oct 09 08:54:40 PM UTC 24 |
| Peak memory | 252396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291817947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.291817947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/153.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_parallel_lc_esc.2073749709 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 139870904 ps |
| CPU time | 5.59 seconds |
| Started | Oct 09 08:54:35 PM UTC 24 |
| Finished | Oct 09 08:54:42 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073749709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.2073749709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/153.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_init_fail.25858947 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 347745073 ps |
| CPU time | 3.95 seconds |
| Started | Oct 09 08:54:35 PM UTC 24 |
| Finished | Oct 09 08:54:41 PM UTC 24 |
| Peak memory | 252476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25858947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.25858947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/154.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_parallel_lc_esc.1961224243 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 490118908 ps |
| CPU time | 6.55 seconds |
| Started | Oct 09 08:54:35 PM UTC 24 |
| Finished | Oct 09 08:54:43 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961224243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.1961224243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/154.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_parallel_lc_esc.2760325937 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 3481795624 ps |
| CPU time | 26.97 seconds |
| Started | Oct 09 08:54:35 PM UTC 24 |
| Finished | Oct 09 08:55:04 PM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760325937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.2760325937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/155.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_init_fail.236323427 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 443291490 ps |
| CPU time | 3.12 seconds |
| Started | Oct 09 08:54:35 PM UTC 24 |
| Finished | Oct 09 08:54:40 PM UTC 24 |
| Peak memory | 252312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236323427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.236323427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/156.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_parallel_lc_esc.1578129439 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 116087199 ps |
| CPU time | 3.63 seconds |
| Started | Oct 09 08:54:35 PM UTC 24 |
| Finished | Oct 09 08:54:40 PM UTC 24 |
| Peak memory | 252312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578129439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.1578129439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/156.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_init_fail.1843447596 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 1913417402 ps |
| CPU time | 5.55 seconds |
| Started | Oct 09 08:54:35 PM UTC 24 |
| Finished | Oct 09 08:54:42 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843447596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.1843447596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/157.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_parallel_lc_esc.655721515 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 422872574 ps |
| CPU time | 20.82 seconds |
| Started | Oct 09 08:54:35 PM UTC 24 |
| Finished | Oct 09 08:54:58 PM UTC 24 |
| Peak memory | 252336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655721515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.655721515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/157.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_init_fail.708345153 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 450356171 ps |
| CPU time | 3.22 seconds |
| Started | Oct 09 08:54:35 PM UTC 24 |
| Finished | Oct 09 08:54:40 PM UTC 24 |
| Peak memory | 252308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708345153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.708345153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/158.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_parallel_lc_esc.2949942890 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 1059173604 ps |
| CPU time | 16.25 seconds |
| Started | Oct 09 08:54:35 PM UTC 24 |
| Finished | Oct 09 08:54:53 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949942890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.2949942890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/158.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_init_fail.4074865496 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 400968488 ps |
| CPU time | 3.44 seconds |
| Started | Oct 09 08:54:35 PM UTC 24 |
| Finished | Oct 09 08:54:40 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074865496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.4074865496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/159.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_parallel_lc_esc.2778194568 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 609542721 ps |
| CPU time | 7.04 seconds |
| Started | Oct 09 08:54:35 PM UTC 24 |
| Finished | Oct 09 08:54:44 PM UTC 24 |
| Peak memory | 252304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778194568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.2778194568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/159.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_alert_test.3460206703 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 718265119 ps |
| CPU time | 2.73 seconds |
| Started | Oct 09 08:47:09 PM UTC 24 |
| Finished | Oct 09 08:47:13 PM UTC 24 |
| Peak memory | 252240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460206703 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.3460206703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_errs.899697372 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1275304309 ps |
| CPU time | 19.2 seconds |
| Started | Oct 09 08:47:03 PM UTC 24 |
| Finished | Oct 09 08:47:23 PM UTC 24 |
| Peak memory | 252396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899697372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.899697372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_lock.3378520977 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 520524096 ps |
| CPU time | 8.39 seconds |
| Started | Oct 09 08:47:03 PM UTC 24 |
| Finished | Oct 09 08:47:12 PM UTC 24 |
| Peak memory | 252528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378520977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.3378520977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_init_fail.3111973605 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 488031742 ps |
| CPU time | 4.84 seconds |
| Started | Oct 09 08:46:59 PM UTC 24 |
| Finished | Oct 09 08:47:05 PM UTC 24 |
| Peak memory | 252320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111973605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.3111973605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_macro_errs.2088265763 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 743947822 ps |
| CPU time | 15.57 seconds |
| Started | Oct 09 08:47:03 PM UTC 24 |
| Finished | Oct 09 08:47:20 PM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088265763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.2088265763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_key_req.35338163 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1128866537 ps |
| CPU time | 8.83 seconds |
| Started | Oct 09 08:47:03 PM UTC 24 |
| Finished | Oct 09 08:47:13 PM UTC 24 |
| Peak memory | 252436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35338163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.35338163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_esc.572538039 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 202969215 ps |
| CPU time | 4.57 seconds |
| Started | Oct 09 08:47:03 PM UTC 24 |
| Finished | Oct 09 08:47:08 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572538039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.572538039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_req.341578672 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 3400954664 ps |
| CPU time | 28.18 seconds |
| Started | Oct 09 08:46:59 PM UTC 24 |
| Finished | Oct 09 08:47:29 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341578672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.341578672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_regwen.2926519357 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 309369304 ps |
| CPU time | 6.33 seconds |
| Started | Oct 09 08:47:09 PM UTC 24 |
| Finished | Oct 09 08:47:16 PM UTC 24 |
| Peak memory | 252352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926519357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.2926519357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_smoke.1233690986 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 398367880 ps |
| CPU time | 8.08 seconds |
| Started | Oct 09 08:46:58 PM UTC 24 |
| Finished | Oct 09 08:47:07 PM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233690986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.1233690986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all.1766236702 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 25625698058 ps |
| CPU time | 214.9 seconds |
| Started | Oct 09 08:47:09 PM UTC 24 |
| Finished | Oct 09 08:50:48 PM UTC 24 |
| Peak memory | 268876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766236702 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.1766236702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_test_access.2244323139 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 532394888 ps |
| CPU time | 11.51 seconds |
| Started | Oct 09 08:47:09 PM UTC 24 |
| Finished | Oct 09 08:47:22 PM UTC 24 |
| Peak memory | 252320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244323139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.2244323139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/16.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_init_fail.4239983752 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 400876443 ps |
| CPU time | 4.47 seconds |
| Started | Oct 09 08:54:36 PM UTC 24 |
| Finished | Oct 09 08:54:42 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239983752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.4239983752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/160.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_parallel_lc_esc.1413084774 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 341210262 ps |
| CPU time | 5.68 seconds |
| Started | Oct 09 08:54:36 PM UTC 24 |
| Finished | Oct 09 08:54:43 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413084774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.1413084774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/160.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_init_fail.1370700091 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 1761565399 ps |
| CPU time | 3.07 seconds |
| Started | Oct 09 08:54:36 PM UTC 24 |
| Finished | Oct 09 08:54:40 PM UTC 24 |
| Peak memory | 252408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370700091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.1370700091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/161.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_parallel_lc_esc.1410866781 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 553054762 ps |
| CPU time | 3.75 seconds |
| Started | Oct 09 08:54:36 PM UTC 24 |
| Finished | Oct 09 08:54:41 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410866781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.1410866781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/161.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_init_fail.2482486128 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 484472542 ps |
| CPU time | 4.03 seconds |
| Started | Oct 09 08:54:36 PM UTC 24 |
| Finished | Oct 09 08:54:41 PM UTC 24 |
| Peak memory | 252344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482486128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.2482486128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/162.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_parallel_lc_esc.60838934 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 5901391706 ps |
| CPU time | 14.4 seconds |
| Started | Oct 09 08:54:40 PM UTC 24 |
| Finished | Oct 09 08:54:55 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60838934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.60838934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/162.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_init_fail.1654812640 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 172258028 ps |
| CPU time | 3.89 seconds |
| Started | Oct 09 08:54:40 PM UTC 24 |
| Finished | Oct 09 08:54:45 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654812640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.1654812640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/163.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_parallel_lc_esc.1737356483 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 272278577 ps |
| CPU time | 5.56 seconds |
| Started | Oct 09 08:54:40 PM UTC 24 |
| Finished | Oct 09 08:54:46 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737356483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.1737356483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/163.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_init_fail.831835696 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 167504699 ps |
| CPU time | 3.92 seconds |
| Started | Oct 09 08:54:40 PM UTC 24 |
| Finished | Oct 09 08:54:45 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831835696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.831835696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/164.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_parallel_lc_esc.2868019621 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 339250001 ps |
| CPU time | 8.17 seconds |
| Started | Oct 09 08:54:40 PM UTC 24 |
| Finished | Oct 09 08:54:49 PM UTC 24 |
| Peak memory | 252348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868019621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.2868019621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/164.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_init_fail.555727703 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 2495100266 ps |
| CPU time | 7.62 seconds |
| Started | Oct 09 08:54:40 PM UTC 24 |
| Finished | Oct 09 08:54:49 PM UTC 24 |
| Peak memory | 252392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555727703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.555727703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/165.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_parallel_lc_esc.3201600829 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 159654647 ps |
| CPU time | 4.37 seconds |
| Started | Oct 09 08:54:40 PM UTC 24 |
| Finished | Oct 09 08:54:45 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201600829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.3201600829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/165.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_init_fail.1081868770 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 272034169 ps |
| CPU time | 3.84 seconds |
| Started | Oct 09 08:54:40 PM UTC 24 |
| Finished | Oct 09 08:54:45 PM UTC 24 |
| Peak memory | 252408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081868770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.1081868770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/166.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_parallel_lc_esc.1922796357 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 302055049 ps |
| CPU time | 6.66 seconds |
| Started | Oct 09 08:54:40 PM UTC 24 |
| Finished | Oct 09 08:54:48 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922796357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.1922796357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/166.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_init_fail.3883250140 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 648457726 ps |
| CPU time | 4.71 seconds |
| Started | Oct 09 08:54:40 PM UTC 24 |
| Finished | Oct 09 08:54:46 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883250140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.3883250140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/167.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_parallel_lc_esc.1573416624 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 117922549 ps |
| CPU time | 3.48 seconds |
| Started | Oct 09 08:54:40 PM UTC 24 |
| Finished | Oct 09 08:54:45 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573416624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.1573416624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/167.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_parallel_lc_esc.3383818022 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 1213251593 ps |
| CPU time | 4.3 seconds |
| Started | Oct 09 08:54:48 PM UTC 24 |
| Finished | Oct 09 08:54:54 PM UTC 24 |
| Peak memory | 252356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383818022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.3383818022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/168.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_parallel_lc_esc.3823647778 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 3572489457 ps |
| CPU time | 6.19 seconds |
| Started | Oct 09 08:54:48 PM UTC 24 |
| Finished | Oct 09 08:54:56 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823647778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.3823647778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/169.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_alert_test.3272904427 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 121324435 ps |
| CPU time | 3.02 seconds |
| Started | Oct 09 08:47:12 PM UTC 24 |
| Finished | Oct 09 08:47:16 PM UTC 24 |
| Peak memory | 252324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272904427 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.3272904427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_check_fail.2296525276 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 477805134 ps |
| CPU time | 9.28 seconds |
| Started | Oct 09 08:47:09 PM UTC 24 |
| Finished | Oct 09 08:47:20 PM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296525276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.2296525276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_errs.2993996126 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 18617035857 ps |
| CPU time | 34.99 seconds |
| Started | Oct 09 08:47:09 PM UTC 24 |
| Finished | Oct 09 08:47:46 PM UTC 24 |
| Peak memory | 256628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993996126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.2993996126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_lock.4105724315 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 4085259424 ps |
| CPU time | 23.81 seconds |
| Started | Oct 09 08:47:09 PM UTC 24 |
| Finished | Oct 09 08:47:35 PM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105724315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.4105724315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_macro_errs.2174403774 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 7272847637 ps |
| CPU time | 46.15 seconds |
| Started | Oct 09 08:47:10 PM UTC 24 |
| Finished | Oct 09 08:47:57 PM UTC 24 |
| Peak memory | 269028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174403774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.2174403774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_key_req.2066078191 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 121303108 ps |
| CPU time | 5.73 seconds |
| Started | Oct 09 08:47:10 PM UTC 24 |
| Finished | Oct 09 08:47:17 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066078191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.2066078191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_esc.2694482507 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 460285187 ps |
| CPU time | 8.38 seconds |
| Started | Oct 09 08:47:09 PM UTC 24 |
| Finished | Oct 09 08:47:19 PM UTC 24 |
| Peak memory | 252308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694482507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.2694482507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_req.2025153709 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 896092862 ps |
| CPU time | 8.27 seconds |
| Started | Oct 09 08:47:09 PM UTC 24 |
| Finished | Oct 09 08:47:19 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025153709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.2025153709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_regwen.2148198856 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 351604018 ps |
| CPU time | 11.32 seconds |
| Started | Oct 09 08:47:10 PM UTC 24 |
| Finished | Oct 09 08:47:22 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148198856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.2148198856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_smoke.1302637490 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 483881190 ps |
| CPU time | 9.52 seconds |
| Started | Oct 09 08:47:09 PM UTC 24 |
| Finished | Oct 09 08:47:20 PM UTC 24 |
| Peak memory | 252480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302637490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.1302637490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all.310181853 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 30184510428 ps |
| CPU time | 257.23 seconds |
| Started | Oct 09 08:47:12 PM UTC 24 |
| Finished | Oct 09 08:51:33 PM UTC 24 |
| Peak memory | 291588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310181853 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.310181853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.1988735718 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 19464153438 ps |
| CPU time | 194.94 seconds |
| Started | Oct 09 08:47:12 PM UTC 24 |
| Finished | Oct 09 08:50:30 PM UTC 24 |
| Peak memory | 268996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1988735718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.otp_ctrl_stress_all_with_rand_reset.1988735718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_test_access.978527281 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 843520278 ps |
| CPU time | 12.22 seconds |
| Started | Oct 09 08:47:12 PM UTC 24 |
| Finished | Oct 09 08:47:25 PM UTC 24 |
| Peak memory | 252552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978527281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.978527281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/17.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_init_fail.144289148 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 1480610035 ps |
| CPU time | 4.17 seconds |
| Started | Oct 09 08:54:48 PM UTC 24 |
| Finished | Oct 09 08:54:54 PM UTC 24 |
| Peak memory | 252392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144289148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.144289148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/170.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_parallel_lc_esc.787548892 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 621831588 ps |
| CPU time | 7.64 seconds |
| Started | Oct 09 08:54:48 PM UTC 24 |
| Finished | Oct 09 08:54:57 PM UTC 24 |
| Peak memory | 252356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787548892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.787548892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/170.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_init_fail.3936399891 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 243484918 ps |
| CPU time | 3.39 seconds |
| Started | Oct 09 08:54:48 PM UTC 24 |
| Finished | Oct 09 08:54:53 PM UTC 24 |
| Peak memory | 252016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936399891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.3936399891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/171.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_parallel_lc_esc.1761560578 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 460857987 ps |
| CPU time | 6 seconds |
| Started | Oct 09 08:54:48 PM UTC 24 |
| Finished | Oct 09 08:54:56 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761560578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.1761560578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/171.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_init_fail.1004484643 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 291211615 ps |
| CPU time | 3.18 seconds |
| Started | Oct 09 08:54:48 PM UTC 24 |
| Finished | Oct 09 08:54:53 PM UTC 24 |
| Peak memory | 252348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004484643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.1004484643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/172.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_parallel_lc_esc.1914946511 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 138287294 ps |
| CPU time | 4.2 seconds |
| Started | Oct 09 08:54:48 PM UTC 24 |
| Finished | Oct 09 08:54:54 PM UTC 24 |
| Peak memory | 252316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914946511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.1914946511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/172.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_init_fail.1270353700 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1809989507 ps |
| CPU time | 5.49 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:55 PM UTC 24 |
| Peak memory | 252552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270353700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.1270353700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/173.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_parallel_lc_esc.1614452989 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 159850570 ps |
| CPU time | 5.62 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:56 PM UTC 24 |
| Peak memory | 252248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614452989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.1614452989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/173.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_init_fail.2088114439 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 124175711 ps |
| CPU time | 3.32 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:53 PM UTC 24 |
| Peak memory | 252108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088114439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.2088114439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/174.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_parallel_lc_esc.3557690439 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 566358423 ps |
| CPU time | 11.38 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:55:01 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557690439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.3557690439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/174.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_init_fail.2996863505 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 270960186 ps |
| CPU time | 3.48 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:54 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996863505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.2996863505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/175.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_parallel_lc_esc.3597248977 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 523983573 ps |
| CPU time | 4.88 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:55 PM UTC 24 |
| Peak memory | 252356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597248977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.3597248977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/175.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_init_fail.2427348319 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 2031706060 ps |
| CPU time | 5.44 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:56 PM UTC 24 |
| Peak memory | 252344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427348319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.2427348319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/176.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_parallel_lc_esc.3107470191 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 426225290 ps |
| CPU time | 4.95 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:55 PM UTC 24 |
| Peak memory | 252300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107470191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.3107470191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/176.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_init_fail.3384731494 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 507150935 ps |
| CPU time | 4.27 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:54 PM UTC 24 |
| Peak memory | 252344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384731494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.3384731494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/177.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_parallel_lc_esc.161439752 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 155197736 ps |
| CPU time | 4.4 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:55 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161439752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.161439752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/177.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_init_fail.1972983153 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 167032467 ps |
| CPU time | 4.88 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:55 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972983153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.1972983153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/178.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_parallel_lc_esc.2673586520 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 2015769713 ps |
| CPU time | 5.22 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:56 PM UTC 24 |
| Peak memory | 252176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673586520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.2673586520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/178.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_parallel_lc_esc.754162538 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 493494474 ps |
| CPU time | 11.36 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:55:02 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754162538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.754162538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/179.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_alert_test.4250854527 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 123864976 ps |
| CPU time | 2.17 seconds |
| Started | Oct 09 08:47:25 PM UTC 24 |
| Finished | Oct 09 08:47:28 PM UTC 24 |
| Peak memory | 252240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250854527 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.4250854527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_errs.2790737101 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1360755545 ps |
| CPU time | 36.76 seconds |
| Started | Oct 09 08:47:15 PM UTC 24 |
| Finished | Oct 09 08:47:53 PM UTC 24 |
| Peak memory | 260788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790737101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.2790737101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_lock.2749406598 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 971903448 ps |
| CPU time | 10.16 seconds |
| Started | Oct 09 08:47:15 PM UTC 24 |
| Finished | Oct 09 08:47:26 PM UTC 24 |
| Peak memory | 252528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749406598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.2749406598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_init_fail.3554985406 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 519396926 ps |
| CPU time | 5.96 seconds |
| Started | Oct 09 08:47:15 PM UTC 24 |
| Finished | Oct 09 08:47:22 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554985406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.3554985406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_macro_errs.488679643 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 745565250 ps |
| CPU time | 14.68 seconds |
| Started | Oct 09 08:47:17 PM UTC 24 |
| Finished | Oct 09 08:47:33 PM UTC 24 |
| Peak memory | 254640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488679643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.488679643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_key_req.3240432605 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 237910323 ps |
| CPU time | 7.71 seconds |
| Started | Oct 09 08:47:17 PM UTC 24 |
| Finished | Oct 09 08:47:26 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240432605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.3240432605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_esc.757192687 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1261240115 ps |
| CPU time | 6.25 seconds |
| Started | Oct 09 08:47:15 PM UTC 24 |
| Finished | Oct 09 08:47:22 PM UTC 24 |
| Peak memory | 252312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757192687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.757192687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_req.2107719730 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 348284416 ps |
| CPU time | 12.28 seconds |
| Started | Oct 09 08:47:15 PM UTC 24 |
| Finished | Oct 09 08:47:28 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107719730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.2107719730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_regwen.655616305 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 280744349 ps |
| CPU time | 9.24 seconds |
| Started | Oct 09 08:47:17 PM UTC 24 |
| Finished | Oct 09 08:47:28 PM UTC 24 |
| Peak memory | 252344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655616305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.655616305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_smoke.3870546078 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 3987575610 ps |
| CPU time | 14.73 seconds |
| Started | Oct 09 08:47:12 PM UTC 24 |
| Finished | Oct 09 08:47:28 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870546078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.3870546078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all.1474205099 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 16557327109 ps |
| CPU time | 172.2 seconds |
| Started | Oct 09 08:47:25 PM UTC 24 |
| Finished | Oct 09 08:50:20 PM UTC 24 |
| Peak memory | 258628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474205099 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.1474205099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_test_access.897571113 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 7235943694 ps |
| CPU time | 47.94 seconds |
| Started | Oct 09 08:47:25 PM UTC 24 |
| Finished | Oct 09 08:48:14 PM UTC 24 |
| Peak memory | 254656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897571113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.897571113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/18.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_init_fail.3657299850 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 123195664 ps |
| CPU time | 3.96 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:54 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657299850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.3657299850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/180.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_parallel_lc_esc.2582988372 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 153827504 ps |
| CPU time | 5.63 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:56 PM UTC 24 |
| Peak memory | 252352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582988372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.2582988372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_init_fail.2513798581 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 159319341 ps |
| CPU time | 4.45 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:55 PM UTC 24 |
| Peak memory | 252412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513798581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.2513798581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/181.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_parallel_lc_esc.2852578188 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 1541661005 ps |
| CPU time | 5.69 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:56 PM UTC 24 |
| Peak memory | 252312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852578188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.2852578188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/181.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_init_fail.208050606 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 379137208 ps |
| CPU time | 4.6 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:55 PM UTC 24 |
| Peak memory | 252320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208050606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.208050606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/182.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_parallel_lc_esc.2843625605 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 2288133012 ps |
| CPU time | 7 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:58 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843625605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.2843625605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/182.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_init_fail.313498619 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 168030983 ps |
| CPU time | 5.02 seconds |
| Started | Oct 09 08:54:49 PM UTC 24 |
| Finished | Oct 09 08:54:56 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313498619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.313498619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/183.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_parallel_lc_esc.1934231314 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 61351077 ps |
| CPU time | 2.16 seconds |
| Started | Oct 09 08:54:53 PM UTC 24 |
| Finished | Oct 09 08:54:57 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934231314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.1934231314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/183.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_init_fail.1976232613 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 452815237 ps |
| CPU time | 3.85 seconds |
| Started | Oct 09 08:54:53 PM UTC 24 |
| Finished | Oct 09 08:54:58 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976232613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.1976232613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/184.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_parallel_lc_esc.2523867967 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 4222035303 ps |
| CPU time | 7.96 seconds |
| Started | Oct 09 08:54:53 PM UTC 24 |
| Finished | Oct 09 08:55:03 PM UTC 24 |
| Peak memory | 252268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523867967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.2523867967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/184.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_init_fail.38659647 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 170790539 ps |
| CPU time | 3.5 seconds |
| Started | Oct 09 08:54:53 PM UTC 24 |
| Finished | Oct 09 08:54:58 PM UTC 24 |
| Peak memory | 252220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38659647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.38659647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/185.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.2783592029 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 364242850 ps |
| CPU time | 8.9 seconds |
| Started | Oct 09 08:54:54 PM UTC 24 |
| Finished | Oct 09 08:55:04 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783592029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.2783592029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/185.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_init_fail.2104446114 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 177760809 ps |
| CPU time | 3.43 seconds |
| Started | Oct 09 08:54:54 PM UTC 24 |
| Finished | Oct 09 08:54:58 PM UTC 24 |
| Peak memory | 252492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104446114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.2104446114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/186.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.1146163587 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 9991486467 ps |
| CPU time | 18.78 seconds |
| Started | Oct 09 08:54:54 PM UTC 24 |
| Finished | Oct 09 08:55:14 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146163587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.1146163587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/186.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_init_fail.688542345 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 457511176 ps |
| CPU time | 4.09 seconds |
| Started | Oct 09 08:54:54 PM UTC 24 |
| Finished | Oct 09 08:54:59 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688542345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.688542345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/187.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.1476314376 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 208101478 ps |
| CPU time | 4.1 seconds |
| Started | Oct 09 08:54:54 PM UTC 24 |
| Finished | Oct 09 08:54:59 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476314376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.1476314376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/187.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_init_fail.1976330542 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 343610419 ps |
| CPU time | 4.73 seconds |
| Started | Oct 09 08:55:01 PM UTC 24 |
| Finished | Oct 09 08:55:07 PM UTC 24 |
| Peak memory | 252344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976330542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.1976330542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/188.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.1933759418 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 1302200984 ps |
| CPU time | 25.15 seconds |
| Started | Oct 09 08:55:01 PM UTC 24 |
| Finished | Oct 09 08:55:28 PM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933759418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.1933759418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/188.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_init_fail.2379083470 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 178712031 ps |
| CPU time | 4.17 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:07 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379083470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.2379083470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/189.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.2265603405 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 1170911773 ps |
| CPU time | 8.1 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:11 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265603405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.2265603405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/189.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_alert_test.3240452391 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 153141183 ps |
| CPU time | 3.49 seconds |
| Started | Oct 09 08:47:27 PM UTC 24 |
| Finished | Oct 09 08:47:32 PM UTC 24 |
| Peak memory | 252292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240452391 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.3240452391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_check_fail.3158786274 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1138494505 ps |
| CPU time | 15.43 seconds |
| Started | Oct 09 08:47:25 PM UTC 24 |
| Finished | Oct 09 08:47:42 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158786274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.3158786274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_errs.2965734929 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 1366491618 ps |
| CPU time | 26.24 seconds |
| Started | Oct 09 08:47:25 PM UTC 24 |
| Finished | Oct 09 08:47:53 PM UTC 24 |
| Peak memory | 252464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965734929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.2965734929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_lock.3016695942 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 938420133 ps |
| CPU time | 6.32 seconds |
| Started | Oct 09 08:47:25 PM UTC 24 |
| Finished | Oct 09 08:47:33 PM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016695942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.3016695942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_init_fail.2584727576 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 98903219 ps |
| CPU time | 3.32 seconds |
| Started | Oct 09 08:47:25 PM UTC 24 |
| Finished | Oct 09 08:47:29 PM UTC 24 |
| Peak memory | 252340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584727576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.2584727576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_macro_errs.4293423426 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1016968457 ps |
| CPU time | 9.9 seconds |
| Started | Oct 09 08:47:25 PM UTC 24 |
| Finished | Oct 09 08:47:36 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293423426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.4293423426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_key_req.2812169778 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 4263702620 ps |
| CPU time | 42.48 seconds |
| Started | Oct 09 08:47:25 PM UTC 24 |
| Finished | Oct 09 08:48:09 PM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812169778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.2812169778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_esc.685551077 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 1130179424 ps |
| CPU time | 19.12 seconds |
| Started | Oct 09 08:47:25 PM UTC 24 |
| Finished | Oct 09 08:47:46 PM UTC 24 |
| Peak memory | 252352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685551077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.685551077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_req.2784181649 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 2457421239 ps |
| CPU time | 17.31 seconds |
| Started | Oct 09 08:47:25 PM UTC 24 |
| Finished | Oct 09 08:47:44 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784181649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.2784181649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_smoke.2277039568 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 519220737 ps |
| CPU time | 6.31 seconds |
| Started | Oct 09 08:47:25 PM UTC 24 |
| Finished | Oct 09 08:47:32 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277039568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.2277039568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all.149980825 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 95949476153 ps |
| CPU time | 152.46 seconds |
| Started | Oct 09 08:47:27 PM UTC 24 |
| Finished | Oct 09 08:50:03 PM UTC 24 |
| Peak memory | 268572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149980825 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.149980825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_test_access.2074035750 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 2063127227 ps |
| CPU time | 31.46 seconds |
| Started | Oct 09 08:47:25 PM UTC 24 |
| Finished | Oct 09 08:47:58 PM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074035750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.2074035750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.1410778421 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 182130833 ps |
| CPU time | 4.37 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:07 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410778421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.1410778421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/190.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.3639635595 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 236649758 ps |
| CPU time | 5.84 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:09 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639635595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.3639635595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/190.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_init_fail.2674033463 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 126036038 ps |
| CPU time | 3.89 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:07 PM UTC 24 |
| Peak memory | 252412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674033463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.2674033463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/191.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.2596905121 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 167517856 ps |
| CPU time | 4.1 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:07 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596905121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.2596905121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/191.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_init_fail.1991269115 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 259569127 ps |
| CPU time | 3.58 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:07 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991269115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.1991269115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/192.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.609614743 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 572442422 ps |
| CPU time | 5.46 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:09 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609614743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.609614743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/192.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.3569107884 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 1568771809 ps |
| CPU time | 4.88 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:08 PM UTC 24 |
| Peak memory | 252616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569107884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.3569107884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/193.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.3401322595 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 4073213379 ps |
| CPU time | 6.24 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:10 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401322595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.3401322595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/193.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_init_fail.4209605714 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 2125120235 ps |
| CPU time | 5.06 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:09 PM UTC 24 |
| Peak memory | 252344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209605714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.4209605714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/194.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.900134050 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 1221605246 ps |
| CPU time | 8.9 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:12 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900134050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.900134050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/194.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.1842674 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 323207567 ps |
| CPU time | 4.23 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:08 PM UTC 24 |
| Peak memory | 252532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.1842674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/195.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.3871816631 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 2419463235 ps |
| CPU time | 24.34 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:28 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871816631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.3871816631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/195.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.2345461783 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 166256804 ps |
| CPU time | 3.68 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:07 PM UTC 24 |
| Peak memory | 252128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345461783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.2345461783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/196.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.1165213894 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 6539277553 ps |
| CPU time | 17.98 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:22 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165213894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.1165213894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/196.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.2512350989 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 126943230 ps |
| CPU time | 4.05 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:08 PM UTC 24 |
| Peak memory | 252160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512350989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.2512350989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/197.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.2274522729 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 921814843 ps |
| CPU time | 4.19 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:08 PM UTC 24 |
| Peak memory | 252228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274522729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.2274522729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/197.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.3750662696 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 2037044265 ps |
| CPU time | 6.24 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:10 PM UTC 24 |
| Peak memory | 252324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750662696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.3750662696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/198.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.2348785245 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 444536989 ps |
| CPU time | 3.25 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:07 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348785245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2348785245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/198.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.4110555026 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 403871596 ps |
| CPU time | 3.97 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:08 PM UTC 24 |
| Peak memory | 252408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110555026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.4110555026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/199.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.1370232405 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 266298055 ps |
| CPU time | 4.38 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:08 PM UTC 24 |
| Peak memory | 252220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370232405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.1370232405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/199.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_background_chks.1575065778 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2105915586 ps |
| CPU time | 18.69 seconds |
| Started | Oct 09 08:44:19 PM UTC 24 |
| Finished | Oct 09 08:44:39 PM UTC 24 |
| Peak memory | 252308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575065778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.1575065778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_check_fail.1665840526 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 462354930 ps |
| CPU time | 8.81 seconds |
| Started | Oct 09 08:44:23 PM UTC 24 |
| Finished | Oct 09 08:44:33 PM UTC 24 |
| Peak memory | 252592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665840526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.1665840526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_errs.264589595 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3109677898 ps |
| CPU time | 32.95 seconds |
| Started | Oct 09 08:44:23 PM UTC 24 |
| Finished | Oct 09 08:44:58 PM UTC 24 |
| Peak memory | 254492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264589595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.264589595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_lock.1461031025 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 966021707 ps |
| CPU time | 11.93 seconds |
| Started | Oct 09 08:44:21 PM UTC 24 |
| Finished | Oct 09 08:44:35 PM UTC 24 |
| Peak memory | 252592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461031025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.1461031025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_macro_errs.202274708 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 637186109 ps |
| CPU time | 13.39 seconds |
| Started | Oct 09 08:44:25 PM UTC 24 |
| Finished | Oct 09 08:44:40 PM UTC 24 |
| Peak memory | 252548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202274708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.202274708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_key_req.1697791466 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 8739220109 ps |
| CPU time | 36.48 seconds |
| Started | Oct 09 08:44:25 PM UTC 24 |
| Finished | Oct 09 08:45:03 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697791466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.1697791466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_esc.1631491866 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1240540826 ps |
| CPU time | 7.36 seconds |
| Started | Oct 09 08:44:19 PM UTC 24 |
| Finished | Oct 09 08:44:27 PM UTC 24 |
| Peak memory | 252308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631491866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.1631491866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_req.772990341 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 625796091 ps |
| CPU time | 13.89 seconds |
| Started | Oct 09 08:44:19 PM UTC 24 |
| Finished | Oct 09 08:44:34 PM UTC 24 |
| Peak memory | 252072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772990341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.772990341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_sec_cm.2941874865 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9927489640 ps |
| CPU time | 180.5 seconds |
| Started | Oct 09 08:44:31 PM UTC 24 |
| Finished | Oct 09 08:47:35 PM UTC 24 |
| Peak memory | 286716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941874865 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.2941874865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_smoke.1784569331 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 701172255 ps |
| CPU time | 7.74 seconds |
| Started | Oct 09 08:44:15 PM UTC 24 |
| Finished | Oct 09 08:44:24 PM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784569331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.1784569331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all.3840254557 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 39834205141 ps |
| CPU time | 328.52 seconds |
| Started | Oct 09 08:44:29 PM UTC 24 |
| Finished | Oct 09 08:50:03 PM UTC 24 |
| Peak memory | 288148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840254557 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.3840254557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_alert_test.670169417 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 87849888 ps |
| CPU time | 2.67 seconds |
| Started | Oct 09 08:47:34 PM UTC 24 |
| Finished | Oct 09 08:47:38 PM UTC 24 |
| Peak memory | 252244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670169417 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.670169417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/20.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_check_fail.3412350428 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 336344269 ps |
| CPU time | 6.02 seconds |
| Started | Oct 09 08:47:30 PM UTC 24 |
| Finished | Oct 09 08:47:37 PM UTC 24 |
| Peak memory | 252528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412350428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.3412350428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_lock.3655043137 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1541579043 ps |
| CPU time | 16.28 seconds |
| Started | Oct 09 08:47:29 PM UTC 24 |
| Finished | Oct 09 08:47:47 PM UTC 24 |
| Peak memory | 252524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655043137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.3655043137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/20.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_macro_errs.307321975 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 913727955 ps |
| CPU time | 24.65 seconds |
| Started | Oct 09 08:47:31 PM UTC 24 |
| Finished | Oct 09 08:47:57 PM UTC 24 |
| Peak memory | 254504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307321975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.307321975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/20.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_key_req.3218851828 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 692266881 ps |
| CPU time | 23.46 seconds |
| Started | Oct 09 08:47:31 PM UTC 24 |
| Finished | Oct 09 08:47:56 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218851828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.3218851828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_esc.668533793 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 394449384 ps |
| CPU time | 10.76 seconds |
| Started | Oct 09 08:47:29 PM UTC 24 |
| Finished | Oct 09 08:47:42 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668533793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.668533793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_req.121938521 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 9183607901 ps |
| CPU time | 34.27 seconds |
| Started | Oct 09 08:47:28 PM UTC 24 |
| Finished | Oct 09 08:48:04 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121938521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.121938521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_regwen.3265476886 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 147949733 ps |
| CPU time | 6.5 seconds |
| Started | Oct 09 08:47:32 PM UTC 24 |
| Finished | Oct 09 08:47:39 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265476886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.3265476886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/20.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_smoke.610777372 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 4676396694 ps |
| CPU time | 12.19 seconds |
| Started | Oct 09 08:47:28 PM UTC 24 |
| Finished | Oct 09 08:47:41 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610777372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.610777372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/20.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.3032163871 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 43692098689 ps |
| CPU time | 132.83 seconds |
| Started | Oct 09 08:47:34 PM UTC 24 |
| Finished | Oct 09 08:49:50 PM UTC 24 |
| Peak memory | 268968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3032163871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 20.otp_ctrl_stress_all_with_rand_reset.3032163871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_test_access.3516825280 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 434250742 ps |
| CPU time | 14.88 seconds |
| Started | Oct 09 08:47:33 PM UTC 24 |
| Finished | Oct 09 08:47:49 PM UTC 24 |
| Peak memory | 252528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516825280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.3516825280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/20.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.814828421 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 192301173 ps |
| CPU time | 4.06 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:08 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814828421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.814828421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/200.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.1888970501 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 146626695 ps |
| CPU time | 4.76 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:09 PM UTC 24 |
| Peak memory | 252408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888970501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.1888970501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/201.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.314860050 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 2030724485 ps |
| CPU time | 6.14 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:10 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314860050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.314860050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/202.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.3283008783 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 1863866182 ps |
| CPU time | 3.86 seconds |
| Started | Oct 09 08:55:02 PM UTC 24 |
| Finished | Oct 09 08:55:08 PM UTC 24 |
| Peak memory | 252476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283008783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.3283008783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/203.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.464118873 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 264563284 ps |
| CPU time | 3.84 seconds |
| Started | Oct 09 08:55:03 PM UTC 24 |
| Finished | Oct 09 08:55:08 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464118873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.464118873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/204.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.243144543 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 148965148 ps |
| CPU time | 4.63 seconds |
| Started | Oct 09 08:55:03 PM UTC 24 |
| Finished | Oct 09 08:55:09 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243144543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.243144543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/205.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.4288518600 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 322888248 ps |
| CPU time | 4.08 seconds |
| Started | Oct 09 08:55:03 PM UTC 24 |
| Finished | Oct 09 08:55:08 PM UTC 24 |
| Peak memory | 252344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288518600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.4288518600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/206.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.1628540697 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 654905659 ps |
| CPU time | 5.52 seconds |
| Started | Oct 09 08:55:03 PM UTC 24 |
| Finished | Oct 09 08:55:10 PM UTC 24 |
| Peak memory | 252344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628540697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.1628540697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/207.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.3434136949 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 211476202 ps |
| CPU time | 4.65 seconds |
| Started | Oct 09 08:55:03 PM UTC 24 |
| Finished | Oct 09 08:55:09 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434136949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.3434136949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/208.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.3376113462 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 2270941406 ps |
| CPU time | 6.96 seconds |
| Started | Oct 09 08:55:03 PM UTC 24 |
| Finished | Oct 09 08:55:11 PM UTC 24 |
| Peak memory | 252408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376113462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.3376113462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/209.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_alert_test.2328357153 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 153521889 ps |
| CPU time | 2.29 seconds |
| Started | Oct 09 08:47:48 PM UTC 24 |
| Finished | Oct 09 08:47:52 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328357153 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.2328357153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/21.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_check_fail.573529607 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1008307450 ps |
| CPU time | 26.51 seconds |
| Started | Oct 09 08:47:40 PM UTC 24 |
| Finished | Oct 09 08:48:08 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573529607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.573529607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/21.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_errs.3401240522 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 19622164804 ps |
| CPU time | 49.1 seconds |
| Started | Oct 09 08:47:38 PM UTC 24 |
| Finished | Oct 09 08:48:29 PM UTC 24 |
| Peak memory | 260492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401240522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.3401240522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/21.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_lock.4030934459 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 605193503 ps |
| CPU time | 22.95 seconds |
| Started | Oct 09 08:47:38 PM UTC 24 |
| Finished | Oct 09 08:48:02 PM UTC 24 |
| Peak memory | 252528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030934459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.4030934459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/21.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_init_fail.3472161359 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 215369230 ps |
| CPU time | 6.15 seconds |
| Started | Oct 09 08:47:36 PM UTC 24 |
| Finished | Oct 09 08:47:43 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472161359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.3472161359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/21.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_macro_errs.3258882489 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 8582497698 ps |
| CPU time | 42.4 seconds |
| Started | Oct 09 08:47:40 PM UTC 24 |
| Finished | Oct 09 08:48:24 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258882489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.3258882489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/21.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_key_req.2943065151 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1478372358 ps |
| CPU time | 16.81 seconds |
| Started | Oct 09 08:47:40 PM UTC 24 |
| Finished | Oct 09 08:47:58 PM UTC 24 |
| Peak memory | 252432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943065151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.2943065151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_esc.3358358073 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 2123096401 ps |
| CPU time | 8.34 seconds |
| Started | Oct 09 08:47:38 PM UTC 24 |
| Finished | Oct 09 08:47:48 PM UTC 24 |
| Peak memory | 252248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358358073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.3358358073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_req.2857453035 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 5376932393 ps |
| CPU time | 10.51 seconds |
| Started | Oct 09 08:47:38 PM UTC 24 |
| Finished | Oct 09 08:47:50 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857453035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.2857453035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_regwen.3143529949 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 2217642550 ps |
| CPU time | 6.28 seconds |
| Started | Oct 09 08:47:41 PM UTC 24 |
| Finished | Oct 09 08:47:48 PM UTC 24 |
| Peak memory | 252432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143529949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.3143529949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/21.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_smoke.2394605036 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 192638054 ps |
| CPU time | 6.66 seconds |
| Started | Oct 09 08:47:36 PM UTC 24 |
| Finished | Oct 09 08:47:44 PM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394605036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.2394605036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/21.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all.1047261789 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 623088631 ps |
| CPU time | 24.6 seconds |
| Started | Oct 09 08:47:48 PM UTC 24 |
| Finished | Oct 09 08:48:14 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047261789 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.1047261789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_test_access.255541361 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1088981997 ps |
| CPU time | 25.28 seconds |
| Started | Oct 09 08:47:48 PM UTC 24 |
| Finished | Oct 09 08:48:15 PM UTC 24 |
| Peak memory | 252556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255541361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.255541361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/21.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.2795570510 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 545778167 ps |
| CPU time | 3.84 seconds |
| Started | Oct 09 08:55:03 PM UTC 24 |
| Finished | Oct 09 08:55:08 PM UTC 24 |
| Peak memory | 252408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795570510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.2795570510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/210.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.2433088769 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 350241067 ps |
| CPU time | 4.5 seconds |
| Started | Oct 09 08:55:03 PM UTC 24 |
| Finished | Oct 09 08:55:09 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433088769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.2433088769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/211.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.3680002874 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 144700973 ps |
| CPU time | 3.31 seconds |
| Started | Oct 09 08:55:06 PM UTC 24 |
| Finished | Oct 09 08:55:11 PM UTC 24 |
| Peak memory | 252476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680002874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.3680002874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/212.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.2262023811 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 395267330 ps |
| CPU time | 3.22 seconds |
| Started | Oct 09 08:55:06 PM UTC 24 |
| Finished | Oct 09 08:55:11 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262023811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.2262023811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/213.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.852577220 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 96760363 ps |
| CPU time | 3.05 seconds |
| Started | Oct 09 08:55:06 PM UTC 24 |
| Finished | Oct 09 08:55:11 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852577220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.852577220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/214.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.2224316347 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 300344120 ps |
| CPU time | 3.48 seconds |
| Started | Oct 09 08:55:07 PM UTC 24 |
| Finished | Oct 09 08:55:11 PM UTC 24 |
| Peak memory | 252492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224316347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.2224316347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/216.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.2306069353 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 328466275 ps |
| CPU time | 3.28 seconds |
| Started | Oct 09 08:55:07 PM UTC 24 |
| Finished | Oct 09 08:55:11 PM UTC 24 |
| Peak memory | 252552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306069353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.2306069353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/217.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.1257214888 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 263258924 ps |
| CPU time | 3.97 seconds |
| Started | Oct 09 08:55:07 PM UTC 24 |
| Finished | Oct 09 08:55:12 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257214888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.1257214888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/218.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.1576798031 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 1943333771 ps |
| CPU time | 5.58 seconds |
| Started | Oct 09 08:55:07 PM UTC 24 |
| Finished | Oct 09 08:55:14 PM UTC 24 |
| Peak memory | 252476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576798031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.1576798031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/219.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_alert_test.496323532 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 284752932 ps |
| CPU time | 3.06 seconds |
| Started | Oct 09 08:47:52 PM UTC 24 |
| Finished | Oct 09 08:47:56 PM UTC 24 |
| Peak memory | 252308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496323532 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.496323532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/22.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_check_fail.1997826374 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 8993646298 ps |
| CPU time | 22.43 seconds |
| Started | Oct 09 08:47:49 PM UTC 24 |
| Finished | Oct 09 08:48:13 PM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997826374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.1997826374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/22.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_errs.3906287654 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1475891602 ps |
| CPU time | 27.89 seconds |
| Started | Oct 09 08:47:49 PM UTC 24 |
| Finished | Oct 09 08:48:18 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906287654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.3906287654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/22.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_lock.2035358428 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 3540269937 ps |
| CPU time | 16.37 seconds |
| Started | Oct 09 08:47:49 PM UTC 24 |
| Finished | Oct 09 08:48:06 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035358428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.2035358428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/22.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_init_fail.1748072280 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 88117908 ps |
| CPU time | 4.56 seconds |
| Started | Oct 09 08:47:48 PM UTC 24 |
| Finished | Oct 09 08:47:54 PM UTC 24 |
| Peak memory | 252356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748072280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.1748072280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/22.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_macro_errs.219630093 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 568025292 ps |
| CPU time | 13.65 seconds |
| Started | Oct 09 08:47:51 PM UTC 24 |
| Finished | Oct 09 08:48:06 PM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219630093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.219630093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/22.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_key_req.3146648688 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 23769584354 ps |
| CPU time | 47.15 seconds |
| Started | Oct 09 08:47:51 PM UTC 24 |
| Finished | Oct 09 08:48:40 PM UTC 24 |
| Peak memory | 254624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146648688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.3146648688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_esc.2393933767 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 146279011 ps |
| CPU time | 7.48 seconds |
| Started | Oct 09 08:47:49 PM UTC 24 |
| Finished | Oct 09 08:47:57 PM UTC 24 |
| Peak memory | 252356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393933767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.2393933767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_req.1013742304 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 213733472 ps |
| CPU time | 9.55 seconds |
| Started | Oct 09 08:47:49 PM UTC 24 |
| Finished | Oct 09 08:48:00 PM UTC 24 |
| Peak memory | 252316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013742304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.1013742304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_regwen.699785136 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 485427781 ps |
| CPU time | 10.78 seconds |
| Started | Oct 09 08:47:51 PM UTC 24 |
| Finished | Oct 09 08:48:03 PM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699785136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.699785136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/22.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_smoke.2534787257 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 406607642 ps |
| CPU time | 11.1 seconds |
| Started | Oct 09 08:47:48 PM UTC 24 |
| Finished | Oct 09 08:48:01 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534787257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.2534787257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/22.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all.311235404 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 9158841897 ps |
| CPU time | 204.05 seconds |
| Started | Oct 09 08:47:51 PM UTC 24 |
| Finished | Oct 09 08:51:18 PM UTC 24 |
| Peak memory | 285404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311235404 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.311235404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.3687736920 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 15954472947 ps |
| CPU time | 189.52 seconds |
| Started | Oct 09 08:47:51 PM UTC 24 |
| Finished | Oct 09 08:51:04 PM UTC 24 |
| Peak memory | 258688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3687736920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 22.otp_ctrl_stress_all_with_rand_reset.3687736920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_test_access.3688132386 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1770059217 ps |
| CPU time | 52.67 seconds |
| Started | Oct 09 08:47:51 PM UTC 24 |
| Finished | Oct 09 08:48:45 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688132386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.3688132386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/22.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.2730113353 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 477931519 ps |
| CPU time | 3.58 seconds |
| Started | Oct 09 08:55:13 PM UTC 24 |
| Finished | Oct 09 08:55:18 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730113353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.2730113353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/220.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.3003940704 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 168126612 ps |
| CPU time | 3.86 seconds |
| Started | Oct 09 08:55:13 PM UTC 24 |
| Finished | Oct 09 08:55:18 PM UTC 24 |
| Peak memory | 252408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003940704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.3003940704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/221.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.1513807352 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 2397093142 ps |
| CPU time | 4.93 seconds |
| Started | Oct 09 08:55:13 PM UTC 24 |
| Finished | Oct 09 08:55:19 PM UTC 24 |
| Peak memory | 252472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513807352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.1513807352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/222.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.1354864715 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 158168321 ps |
| CPU time | 4.83 seconds |
| Started | Oct 09 08:55:13 PM UTC 24 |
| Finished | Oct 09 08:55:19 PM UTC 24 |
| Peak memory | 252552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354864715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.1354864715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/223.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.2384953826 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 128736412 ps |
| CPU time | 3.64 seconds |
| Started | Oct 09 08:55:13 PM UTC 24 |
| Finished | Oct 09 08:55:18 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384953826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.2384953826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/224.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.312474405 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 343316558 ps |
| CPU time | 3.18 seconds |
| Started | Oct 09 08:55:13 PM UTC 24 |
| Finished | Oct 09 08:55:18 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312474405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.312474405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/225.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.273381915 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 149834722 ps |
| CPU time | 4.02 seconds |
| Started | Oct 09 08:55:13 PM UTC 24 |
| Finished | Oct 09 08:55:19 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273381915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.273381915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/226.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.3896313560 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 471901665 ps |
| CPU time | 2.92 seconds |
| Started | Oct 09 08:55:13 PM UTC 24 |
| Finished | Oct 09 08:55:18 PM UTC 24 |
| Peak memory | 252480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896313560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.3896313560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/227.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.2536228948 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 1998110511 ps |
| CPU time | 4.26 seconds |
| Started | Oct 09 08:55:13 PM UTC 24 |
| Finished | Oct 09 08:55:19 PM UTC 24 |
| Peak memory | 252340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536228948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.2536228948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/228.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.3099094763 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 115715586 ps |
| CPU time | 3.86 seconds |
| Started | Oct 09 08:55:13 PM UTC 24 |
| Finished | Oct 09 08:55:19 PM UTC 24 |
| Peak memory | 252356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099094763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.3099094763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/229.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_alert_test.1597492991 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 131751392 ps |
| CPU time | 2.93 seconds |
| Started | Oct 09 08:48:02 PM UTC 24 |
| Finished | Oct 09 08:48:07 PM UTC 24 |
| Peak memory | 252328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597492991 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.1597492991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/23.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_check_fail.4197208900 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 8521289005 ps |
| CPU time | 34.62 seconds |
| Started | Oct 09 08:47:59 PM UTC 24 |
| Finished | Oct 09 08:48:36 PM UTC 24 |
| Peak memory | 254692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197208900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.4197208900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/23.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_errs.3693347494 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 11862424299 ps |
| CPU time | 31.55 seconds |
| Started | Oct 09 08:47:59 PM UTC 24 |
| Finished | Oct 09 08:48:32 PM UTC 24 |
| Peak memory | 252536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693347494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.3693347494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/23.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_lock.694213982 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 458752408 ps |
| CPU time | 13.55 seconds |
| Started | Oct 09 08:47:59 PM UTC 24 |
| Finished | Oct 09 08:48:14 PM UTC 24 |
| Peak memory | 252524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694213982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.694213982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/23.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_init_fail.2252688981 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 649740960 ps |
| CPU time | 4.25 seconds |
| Started | Oct 09 08:47:56 PM UTC 24 |
| Finished | Oct 09 08:48:01 PM UTC 24 |
| Peak memory | 252352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252688981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.2252688981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/23.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_macro_errs.3407970455 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 538859032 ps |
| CPU time | 13.64 seconds |
| Started | Oct 09 08:47:59 PM UTC 24 |
| Finished | Oct 09 08:48:14 PM UTC 24 |
| Peak memory | 254496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407970455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.3407970455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/23.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_key_req.2864407404 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 553911054 ps |
| CPU time | 7.98 seconds |
| Started | Oct 09 08:48:02 PM UTC 24 |
| Finished | Oct 09 08:48:12 PM UTC 24 |
| Peak memory | 258520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864407404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.2864407404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_esc.810556103 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 132543455 ps |
| CPU time | 6.29 seconds |
| Started | Oct 09 08:47:56 PM UTC 24 |
| Finished | Oct 09 08:48:04 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810556103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.810556103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_req.2468569421 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 582851979 ps |
| CPU time | 11.49 seconds |
| Started | Oct 09 08:47:56 PM UTC 24 |
| Finished | Oct 09 08:48:09 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468569421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.2468569421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_regwen.4282570795 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 333873337 ps |
| CPU time | 8.27 seconds |
| Started | Oct 09 08:48:02 PM UTC 24 |
| Finished | Oct 09 08:48:12 PM UTC 24 |
| Peak memory | 252260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282570795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.4282570795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/23.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_smoke.1370727064 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 5075480617 ps |
| CPU time | 11.71 seconds |
| Started | Oct 09 08:47:53 PM UTC 24 |
| Finished | Oct 09 08:48:06 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370727064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.1370727064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/23.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.235757758 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 10544253307 ps |
| CPU time | 144.18 seconds |
| Started | Oct 09 08:48:02 PM UTC 24 |
| Finished | Oct 09 08:50:30 PM UTC 24 |
| Peak memory | 264980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=235757758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.235757758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_test_access.3183671241 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 17173232703 ps |
| CPU time | 27.53 seconds |
| Started | Oct 09 08:48:02 PM UTC 24 |
| Finished | Oct 09 08:48:32 PM UTC 24 |
| Peak memory | 254532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183671241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.3183671241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/23.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.2148989565 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 340764967 ps |
| CPU time | 4.25 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:19 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148989565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.2148989565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/230.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.3179233837 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 2520436542 ps |
| CPU time | 5.15 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:20 PM UTC 24 |
| Peak memory | 252476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179233837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.3179233837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/231.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.2553199562 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 504784505 ps |
| CPU time | 3.63 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:19 PM UTC 24 |
| Peak memory | 252340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553199562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.2553199562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/232.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.2215737800 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 107678320 ps |
| CPU time | 2.87 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:18 PM UTC 24 |
| Peak memory | 252540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215737800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.2215737800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/233.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.817043241 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 247310851 ps |
| CPU time | 3.95 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:19 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817043241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.817043241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/234.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.2079318789 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 2806005000 ps |
| CPU time | 5.6 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:21 PM UTC 24 |
| Peak memory | 252412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079318789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.2079318789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/235.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.2338092137 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 201088513 ps |
| CPU time | 4.54 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:20 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338092137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.2338092137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/237.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.1548982178 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 126755372 ps |
| CPU time | 3.23 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:18 PM UTC 24 |
| Peak memory | 252408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548982178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.1548982178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/238.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.1476123902 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 260529787 ps |
| CPU time | 3.42 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:19 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476123902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.1476123902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/239.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_alert_test.427392353 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 286149679 ps |
| CPU time | 4.15 seconds |
| Started | Oct 09 08:48:12 PM UTC 24 |
| Finished | Oct 09 08:48:17 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427392353 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.427392353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/24.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_errs.975526036 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 615324352 ps |
| CPU time | 19.37 seconds |
| Started | Oct 09 08:48:08 PM UTC 24 |
| Finished | Oct 09 08:48:29 PM UTC 24 |
| Peak memory | 252600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975526036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.975526036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/24.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_lock.1014134891 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 2993558893 ps |
| CPU time | 29.18 seconds |
| Started | Oct 09 08:48:08 PM UTC 24 |
| Finished | Oct 09 08:48:39 PM UTC 24 |
| Peak memory | 252596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014134891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.1014134891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/24.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_init_fail.4254731594 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 330656892 ps |
| CPU time | 5.23 seconds |
| Started | Oct 09 08:48:05 PM UTC 24 |
| Finished | Oct 09 08:48:11 PM UTC 24 |
| Peak memory | 252432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254731594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.4254731594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/24.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_macro_errs.1053141692 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 2300520201 ps |
| CPU time | 42.86 seconds |
| Started | Oct 09 08:48:08 PM UTC 24 |
| Finished | Oct 09 08:48:53 PM UTC 24 |
| Peak memory | 258640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053141692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.1053141692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/24.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_key_req.3383337114 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 1680648058 ps |
| CPU time | 36.41 seconds |
| Started | Oct 09 08:48:08 PM UTC 24 |
| Finished | Oct 09 08:48:46 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383337114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.3383337114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_esc.1521917356 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1964515544 ps |
| CPU time | 16.82 seconds |
| Started | Oct 09 08:48:05 PM UTC 24 |
| Finished | Oct 09 08:48:23 PM UTC 24 |
| Peak memory | 252308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521917356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.1521917356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_req.2354039185 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 1162358585 ps |
| CPU time | 20.4 seconds |
| Started | Oct 09 08:48:05 PM UTC 24 |
| Finished | Oct 09 08:48:27 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354039185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.2354039185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_regwen.1940860095 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 1158147505 ps |
| CPU time | 11.82 seconds |
| Started | Oct 09 08:48:08 PM UTC 24 |
| Finished | Oct 09 08:48:22 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940860095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.1940860095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/24.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_smoke.532618631 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 411929720 ps |
| CPU time | 11.07 seconds |
| Started | Oct 09 08:48:05 PM UTC 24 |
| Finished | Oct 09 08:48:17 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532618631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.532618631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/24.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all.2734847906 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 14058731065 ps |
| CPU time | 170.41 seconds |
| Started | Oct 09 08:48:12 PM UTC 24 |
| Finished | Oct 09 08:51:06 PM UTC 24 |
| Peak memory | 268952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734847906 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all.2734847906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_test_access.459386977 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 31718861301 ps |
| CPU time | 50.52 seconds |
| Started | Oct 09 08:48:10 PM UTC 24 |
| Finished | Oct 09 08:49:02 PM UTC 24 |
| Peak memory | 252536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459386977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.459386977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/24.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.277768429 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 428298963 ps |
| CPU time | 4.1 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:19 PM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277768429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.277768429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/240.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.3205484575 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 1657504698 ps |
| CPU time | 5.65 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:21 PM UTC 24 |
| Peak memory | 252492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205484575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.3205484575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/241.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.2755275979 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 466770065 ps |
| CPU time | 3.43 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:19 PM UTC 24 |
| Peak memory | 252312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755275979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.2755275979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/242.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.711492848 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 309001288 ps |
| CPU time | 4.07 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:19 PM UTC 24 |
| Peak memory | 252316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711492848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.711492848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/243.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.2911701809 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 216191746 ps |
| CPU time | 3.93 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:19 PM UTC 24 |
| Peak memory | 252348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911701809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.2911701809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/244.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.3741296540 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 143633748 ps |
| CPU time | 2.93 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:18 PM UTC 24 |
| Peak memory | 252476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741296540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.3741296540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/245.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.1868856249 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 477923831 ps |
| CPU time | 4.63 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:20 PM UTC 24 |
| Peak memory | 252392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868856249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.1868856249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/246.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.3203016162 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 163945148 ps |
| CPU time | 4.08 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:20 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203016162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.3203016162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/247.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.2448900376 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 2174148941 ps |
| CPU time | 5.88 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:22 PM UTC 24 |
| Peak memory | 252616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448900376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.2448900376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/248.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.3580352939 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 631188022 ps |
| CPU time | 4.86 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:20 PM UTC 24 |
| Peak memory | 252408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580352939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.3580352939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/249.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_alert_test.2116854079 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 575292866 ps |
| CPU time | 3.48 seconds |
| Started | Oct 09 08:48:23 PM UTC 24 |
| Finished | Oct 09 08:48:28 PM UTC 24 |
| Peak memory | 252292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116854079 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.2116854079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/25.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_check_fail.2494770707 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 784906077 ps |
| CPU time | 14.44 seconds |
| Started | Oct 09 08:48:18 PM UTC 24 |
| Finished | Oct 09 08:48:34 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494770707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.2494770707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/25.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_errs.2548189391 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 335819210 ps |
| CPU time | 21.45 seconds |
| Started | Oct 09 08:48:18 PM UTC 24 |
| Finished | Oct 09 08:48:41 PM UTC 24 |
| Peak memory | 252396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548189391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.2548189391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/25.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_lock.483333807 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 3706174548 ps |
| CPU time | 26.17 seconds |
| Started | Oct 09 08:48:18 PM UTC 24 |
| Finished | Oct 09 08:48:46 PM UTC 24 |
| Peak memory | 254564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483333807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.483333807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/25.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_init_fail.3840672760 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 197786134 ps |
| CPU time | 5.08 seconds |
| Started | Oct 09 08:48:18 PM UTC 24 |
| Finished | Oct 09 08:48:25 PM UTC 24 |
| Peak memory | 252188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840672760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.3840672760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/25.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_macro_errs.4225250565 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 12288712828 ps |
| CPU time | 25.41 seconds |
| Started | Oct 09 08:48:18 PM UTC 24 |
| Finished | Oct 09 08:48:46 PM UTC 24 |
| Peak memory | 256652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225250565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.4225250565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/25.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_key_req.534713455 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1994422401 ps |
| CPU time | 13.79 seconds |
| Started | Oct 09 08:48:18 PM UTC 24 |
| Finished | Oct 09 08:48:34 PM UTC 24 |
| Peak memory | 252436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534713455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.534713455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_esc.1157076673 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 3962166504 ps |
| CPU time | 9.37 seconds |
| Started | Oct 09 08:48:18 PM UTC 24 |
| Finished | Oct 09 08:48:29 PM UTC 24 |
| Peak memory | 252160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157076673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.1157076673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_req.165946093 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 6369388177 ps |
| CPU time | 17.5 seconds |
| Started | Oct 09 08:48:18 PM UTC 24 |
| Finished | Oct 09 08:48:37 PM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165946093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.165946093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_regwen.2664316609 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 163453371 ps |
| CPU time | 7.24 seconds |
| Started | Oct 09 08:48:18 PM UTC 24 |
| Finished | Oct 09 08:48:27 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664316609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.2664316609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/25.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_smoke.3697735999 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 383027374 ps |
| CPU time | 11.26 seconds |
| Started | Oct 09 08:48:18 PM UTC 24 |
| Finished | Oct 09 08:48:31 PM UTC 24 |
| Peak memory | 252152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697735999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.3697735999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/25.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all.3565971663 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 39870568962 ps |
| CPU time | 323.27 seconds |
| Started | Oct 09 08:48:20 PM UTC 24 |
| Finished | Oct 09 08:53:48 PM UTC 24 |
| Peak memory | 277820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565971663 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.3565971663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.1480628315 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2072205446 ps |
| CPU time | 63.18 seconds |
| Started | Oct 09 08:48:20 PM UTC 24 |
| Finished | Oct 09 08:49:26 PM UTC 24 |
| Peak memory | 269024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1480628315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 25.otp_ctrl_stress_all_with_rand_reset.1480628315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_test_access.2193654456 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 157390315 ps |
| CPU time | 5.91 seconds |
| Started | Oct 09 08:48:18 PM UTC 24 |
| Finished | Oct 09 08:48:26 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193654456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.2193654456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/25.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.3383820648 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 186675693 ps |
| CPU time | 4.77 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:20 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383820648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.3383820648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/250.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.1803974208 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 397596159 ps |
| CPU time | 3.26 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:19 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803974208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.1803974208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/251.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.838634783 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 107443467 ps |
| CPU time | 4.62 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:20 PM UTC 24 |
| Peak memory | 252460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838634783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.838634783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/252.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.119423752 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 140974480 ps |
| CPU time | 4.24 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:20 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119423752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.119423752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/253.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.1806310718 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 159904265 ps |
| CPU time | 4.26 seconds |
| Started | Oct 09 08:55:14 PM UTC 24 |
| Finished | Oct 09 08:55:20 PM UTC 24 |
| Peak memory | 252348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806310718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.1806310718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/254.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.1157057348 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 152429293 ps |
| CPU time | 3.36 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:31 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157057348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.1157057348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/255.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.4210913928 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 107214762 ps |
| CPU time | 4.07 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:32 PM UTC 24 |
| Peak memory | 252352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210913928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.4210913928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/256.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.4248804248 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 204281541 ps |
| CPU time | 3.37 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:31 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248804248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.4248804248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/257.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.2330571660 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 182582480 ps |
| CPU time | 4.7 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:32 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330571660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.2330571660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/258.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.3040958615 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 190113229 ps |
| CPU time | 3.53 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:31 PM UTC 24 |
| Peak memory | 252312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040958615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.3040958615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/259.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_alert_test.2365725982 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 43047451 ps |
| CPU time | 2.29 seconds |
| Started | Oct 09 08:48:33 PM UTC 24 |
| Finished | Oct 09 08:48:37 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365725982 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.2365725982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/26.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_check_fail.1357721737 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2169965756 ps |
| CPU time | 15.01 seconds |
| Started | Oct 09 08:48:28 PM UTC 24 |
| Finished | Oct 09 08:48:45 PM UTC 24 |
| Peak memory | 256668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357721737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.1357721737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_errs.329285089 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 3550541543 ps |
| CPU time | 32.24 seconds |
| Started | Oct 09 08:48:28 PM UTC 24 |
| Finished | Oct 09 08:49:02 PM UTC 24 |
| Peak memory | 252600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329285089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.329285089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/26.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_lock.4038047446 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 11849147276 ps |
| CPU time | 37.77 seconds |
| Started | Oct 09 08:48:28 PM UTC 24 |
| Finished | Oct 09 08:49:08 PM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038047446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.4038047446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/26.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_init_fail.2510244418 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2513757974 ps |
| CPU time | 6.15 seconds |
| Started | Oct 09 08:48:25 PM UTC 24 |
| Finished | Oct 09 08:48:32 PM UTC 24 |
| Peak memory | 252416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510244418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.2510244418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_macro_errs.934477373 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 3668697845 ps |
| CPU time | 36.49 seconds |
| Started | Oct 09 08:48:28 PM UTC 24 |
| Finished | Oct 09 08:49:06 PM UTC 24 |
| Peak memory | 256748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934477373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.934477373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/26.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_key_req.1016532078 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 341539146 ps |
| CPU time | 13.08 seconds |
| Started | Oct 09 08:48:28 PM UTC 24 |
| Finished | Oct 09 08:48:43 PM UTC 24 |
| Peak memory | 252492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016532078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.1016532078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_esc.2241602539 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 68351995 ps |
| CPU time | 4.89 seconds |
| Started | Oct 09 08:48:28 PM UTC 24 |
| Finished | Oct 09 08:48:34 PM UTC 24 |
| Peak memory | 252224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241602539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.2241602539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_req.5379459 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 6617653251 ps |
| CPU time | 20.52 seconds |
| Started | Oct 09 08:48:28 PM UTC 24 |
| Finished | Oct 09 08:48:50 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5379459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_t est +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.5379459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_regwen.629663363 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 311446274 ps |
| CPU time | 6.59 seconds |
| Started | Oct 09 08:48:31 PM UTC 24 |
| Finished | Oct 09 08:48:39 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629663363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.629663363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/26.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_smoke.692762527 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 1505303463 ps |
| CPU time | 13.55 seconds |
| Started | Oct 09 08:48:23 PM UTC 24 |
| Finished | Oct 09 08:48:38 PM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692762527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.692762527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/26.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all.3295804458 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 17501723105 ps |
| CPU time | 118.99 seconds |
| Started | Oct 09 08:48:31 PM UTC 24 |
| Finished | Oct 09 08:50:33 PM UTC 24 |
| Peak memory | 258636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295804458 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.3295804458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.2561638215 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 5410050468 ps |
| CPU time | 79.4 seconds |
| Started | Oct 09 08:48:31 PM UTC 24 |
| Finished | Oct 09 08:49:53 PM UTC 24 |
| Peak memory | 258848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2561638215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 26.otp_ctrl_stress_all_with_rand_reset.2561638215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_test_access.1927433241 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 779138907 ps |
| CPU time | 17.48 seconds |
| Started | Oct 09 08:48:31 PM UTC 24 |
| Finished | Oct 09 08:48:50 PM UTC 24 |
| Peak memory | 252592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927433241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.1927433241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/26.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.786327518 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 125445215 ps |
| CPU time | 3.35 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:31 PM UTC 24 |
| Peak memory | 252308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786327518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.786327518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/261.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.2036455212 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2145384459 ps |
| CPU time | 4.73 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:32 PM UTC 24 |
| Peak memory | 252348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036455212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.2036455212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/262.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.2071994432 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 1714907232 ps |
| CPU time | 4.85 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:33 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071994432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.2071994432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/263.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.716005866 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 143801300 ps |
| CPU time | 3.24 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:31 PM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716005866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.716005866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/264.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.3841606282 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 163950635 ps |
| CPU time | 3.3 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:31 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841606282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.3841606282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/265.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.3790200058 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 243622736 ps |
| CPU time | 4.2 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:32 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790200058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.3790200058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/266.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.2340058950 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 142836407 ps |
| CPU time | 3.55 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:32 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340058950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.2340058950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/267.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.1442318532 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 1862237630 ps |
| CPU time | 6.35 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:34 PM UTC 24 |
| Peak memory | 252396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442318532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.1442318532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/268.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.3073783247 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 1837909236 ps |
| CPU time | 6.24 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:34 PM UTC 24 |
| Peak memory | 252312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073783247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.3073783247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/269.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_alert_test.2054332415 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 158977055 ps |
| CPU time | 2.44 seconds |
| Started | Oct 09 08:48:43 PM UTC 24 |
| Finished | Oct 09 08:48:46 PM UTC 24 |
| Peak memory | 252324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054332415 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.2054332415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/27.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_check_fail.1631185412 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12183729978 ps |
| CPU time | 49.21 seconds |
| Started | Oct 09 08:48:40 PM UTC 24 |
| Finished | Oct 09 08:49:31 PM UTC 24 |
| Peak memory | 254768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631185412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.1631185412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/27.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_errs.4215534388 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 1278657618 ps |
| CPU time | 34.17 seconds |
| Started | Oct 09 08:48:36 PM UTC 24 |
| Finished | Oct 09 08:49:12 PM UTC 24 |
| Peak memory | 256504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215534388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.4215534388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/27.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_lock.4095584506 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 286272149 ps |
| CPU time | 5.83 seconds |
| Started | Oct 09 08:48:36 PM UTC 24 |
| Finished | Oct 09 08:48:43 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095584506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.4095584506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/27.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_init_fail.25039658 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 247761067 ps |
| CPU time | 5.44 seconds |
| Started | Oct 09 08:48:33 PM UTC 24 |
| Finished | Oct 09 08:48:40 PM UTC 24 |
| Peak memory | 252324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25039658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.25039658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/27.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_macro_errs.3688000825 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1086894542 ps |
| CPU time | 19.72 seconds |
| Started | Oct 09 08:48:40 PM UTC 24 |
| Finished | Oct 09 08:49:01 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688000825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.3688000825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/27.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_key_req.982858479 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 2184173294 ps |
| CPU time | 20.9 seconds |
| Started | Oct 09 08:48:40 PM UTC 24 |
| Finished | Oct 09 08:49:02 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982858479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.982858479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_esc.54096746 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 561953513 ps |
| CPU time | 12.69 seconds |
| Started | Oct 09 08:48:36 PM UTC 24 |
| Finished | Oct 09 08:48:50 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54096746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.54096746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_req.300932773 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 203625018 ps |
| CPU time | 8.18 seconds |
| Started | Oct 09 08:48:36 PM UTC 24 |
| Finished | Oct 09 08:48:45 PM UTC 24 |
| Peak memory | 252300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300932773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.300932773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_regwen.47445703 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 395528837 ps |
| CPU time | 4.55 seconds |
| Started | Oct 09 08:48:40 PM UTC 24 |
| Finished | Oct 09 08:48:46 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47445703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ot p_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.47445703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/27.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_smoke.2614849409 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1387928155 ps |
| CPU time | 7.2 seconds |
| Started | Oct 09 08:48:33 PM UTC 24 |
| Finished | Oct 09 08:48:42 PM UTC 24 |
| Peak memory | 252320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614849409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.2614849409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/27.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all.2466237073 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 6111607458 ps |
| CPU time | 166.5 seconds |
| Started | Oct 09 08:48:40 PM UTC 24 |
| Finished | Oct 09 08:51:30 PM UTC 24 |
| Peak memory | 258844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466237073 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.2466237073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_test_access.367219090 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 9767519430 ps |
| CPU time | 29.27 seconds |
| Started | Oct 09 08:48:40 PM UTC 24 |
| Finished | Oct 09 08:49:11 PM UTC 24 |
| Peak memory | 252604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367219090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.367219090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/27.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.1943027226 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 1735294849 ps |
| CPU time | 5.06 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:33 PM UTC 24 |
| Peak memory | 252460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943027226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.1943027226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/270.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.1045953580 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 176021261 ps |
| CPU time | 3.76 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:32 PM UTC 24 |
| Peak memory | 252280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045953580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.1045953580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/271.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.1579698390 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 491043261 ps |
| CPU time | 3.32 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:31 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579698390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.1579698390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/272.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.1767271185 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 440980934 ps |
| CPU time | 3.18 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:31 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767271185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.1767271185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/273.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.2731801990 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 325305050 ps |
| CPU time | 4.59 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:33 PM UTC 24 |
| Peak memory | 252344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731801990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.2731801990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/274.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.1652971693 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 343107424 ps |
| CPU time | 3.92 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:32 PM UTC 24 |
| Peak memory | 252412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652971693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.1652971693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/275.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.3394113505 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 176474864 ps |
| CPU time | 4.28 seconds |
| Started | Oct 09 08:55:26 PM UTC 24 |
| Finished | Oct 09 08:55:32 PM UTC 24 |
| Peak memory | 252540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394113505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.3394113505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/276.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.3292403325 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 253573400 ps |
| CPU time | 4.4 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:33 PM UTC 24 |
| Peak memory | 252344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292403325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.3292403325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/277.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.745056080 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 170813839 ps |
| CPU time | 3.72 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:32 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745056080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.745056080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/278.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.3698379811 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 289929577 ps |
| CPU time | 3.55 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:32 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698379811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.3698379811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/279.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_alert_test.235903648 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 58556503 ps |
| CPU time | 2.76 seconds |
| Started | Oct 09 08:48:50 PM UTC 24 |
| Finished | Oct 09 08:48:54 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235903648 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.235903648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/28.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_check_fail.2650035700 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 4225191814 ps |
| CPU time | 58.3 seconds |
| Started | Oct 09 08:48:46 PM UTC 24 |
| Finished | Oct 09 08:49:46 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650035700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.2650035700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/28.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_errs.3222188686 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 4681225949 ps |
| CPU time | 28.44 seconds |
| Started | Oct 09 08:48:46 PM UTC 24 |
| Finished | Oct 09 08:49:16 PM UTC 24 |
| Peak memory | 252596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222188686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.3222188686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/28.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_lock.2824282784 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 7574396335 ps |
| CPU time | 22.97 seconds |
| Started | Oct 09 08:48:45 PM UTC 24 |
| Finished | Oct 09 08:49:09 PM UTC 24 |
| Peak memory | 254632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824282784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.2824282784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/28.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_init_fail.4166389159 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 125100315 ps |
| CPU time | 4.81 seconds |
| Started | Oct 09 08:48:43 PM UTC 24 |
| Finished | Oct 09 08:48:49 PM UTC 24 |
| Peak memory | 252432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166389159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.4166389159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/28.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_macro_errs.3011744798 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 2970012005 ps |
| CPU time | 21.43 seconds |
| Started | Oct 09 08:48:50 PM UTC 24 |
| Finished | Oct 09 08:49:13 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011744798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.3011744798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/28.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_key_req.2261672909 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 5389836051 ps |
| CPU time | 46.93 seconds |
| Started | Oct 09 08:48:50 PM UTC 24 |
| Finished | Oct 09 08:49:38 PM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261672909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.2261672909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_req.1308162250 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 945469126 ps |
| CPU time | 15.53 seconds |
| Started | Oct 09 08:48:43 PM UTC 24 |
| Finished | Oct 09 08:49:00 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308162250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.1308162250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_regwen.80530163 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 5257565805 ps |
| CPU time | 20.34 seconds |
| Started | Oct 09 08:48:50 PM UTC 24 |
| Finished | Oct 09 08:49:12 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80530163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ot p_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.80530163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/28.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_smoke.395580801 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 3157744275 ps |
| CPU time | 8.98 seconds |
| Started | Oct 09 08:48:43 PM UTC 24 |
| Finished | Oct 09 08:48:53 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395580801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.395580801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/28.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_test_access.3405971365 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 602562610 ps |
| CPU time | 22.83 seconds |
| Started | Oct 09 08:48:50 PM UTC 24 |
| Finished | Oct 09 08:49:14 PM UTC 24 |
| Peak memory | 252528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405971365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.3405971365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/28.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.1441543610 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 635116297 ps |
| CPU time | 4.7 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:33 PM UTC 24 |
| Peak memory | 252144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441543610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.1441543610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/280.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.945362302 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 297633263 ps |
| CPU time | 4.19 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:33 PM UTC 24 |
| Peak memory | 252312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945362302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.945362302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/281.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.80365595 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 467458255 ps |
| CPU time | 4.64 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:33 PM UTC 24 |
| Peak memory | 252148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80365595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.80365595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/282.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.3750908125 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 158366251 ps |
| CPU time | 3.89 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:32 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750908125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.3750908125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/283.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.3065950152 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 142840503 ps |
| CPU time | 3.76 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:32 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065950152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.3065950152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/284.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.1059039213 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 433610348 ps |
| CPU time | 4.21 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:33 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059039213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.1059039213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/285.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.3351762446 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 2032970127 ps |
| CPU time | 5.71 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:35 PM UTC 24 |
| Peak memory | 252316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351762446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.3351762446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/286.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.2810004944 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 324154949 ps |
| CPU time | 5.01 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:34 PM UTC 24 |
| Peak memory | 252476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810004944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.2810004944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/287.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.1209399777 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 598330064 ps |
| CPU time | 3.95 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:33 PM UTC 24 |
| Peak memory | 252232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209399777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.1209399777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/288.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.48635604 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 148519461 ps |
| CPU time | 4.12 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:33 PM UTC 24 |
| Peak memory | 252412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48635604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.48635604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/289.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_alert_test.1375200999 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 134793332 ps |
| CPU time | 3.81 seconds |
| Started | Oct 09 08:49:05 PM UTC 24 |
| Finished | Oct 09 08:49:10 PM UTC 24 |
| Peak memory | 252308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375200999 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.1375200999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/29.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_check_fail.3385548065 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 372614631 ps |
| CPU time | 11.67 seconds |
| Started | Oct 09 08:48:55 PM UTC 24 |
| Finished | Oct 09 08:49:08 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385548065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.3385548065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_errs.3393204977 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 4521617166 ps |
| CPU time | 37.29 seconds |
| Started | Oct 09 08:48:55 PM UTC 24 |
| Finished | Oct 09 08:49:34 PM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393204977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.3393204977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/29.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_lock.1768337222 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 13759302642 ps |
| CPU time | 48.1 seconds |
| Started | Oct 09 08:48:52 PM UTC 24 |
| Finished | Oct 09 08:49:42 PM UTC 24 |
| Peak memory | 254640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768337222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.1768337222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/29.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_init_fail.3674962347 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 128009138 ps |
| CPU time | 4.56 seconds |
| Started | Oct 09 08:48:52 PM UTC 24 |
| Finished | Oct 09 08:48:58 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674962347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.3674962347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/29.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_macro_errs.980478965 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1204383519 ps |
| CPU time | 14.59 seconds |
| Started | Oct 09 08:48:55 PM UTC 24 |
| Finished | Oct 09 08:49:11 PM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980478965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.980478965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/29.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_key_req.4068752268 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 9917838303 ps |
| CPU time | 34.16 seconds |
| Started | Oct 09 08:48:57 PM UTC 24 |
| Finished | Oct 09 08:49:33 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068752268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.4068752268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_esc.1647584062 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1180871238 ps |
| CPU time | 10.14 seconds |
| Started | Oct 09 08:48:52 PM UTC 24 |
| Finished | Oct 09 08:49:04 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647584062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.1647584062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_req.4177233962 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 11160744147 ps |
| CPU time | 24.85 seconds |
| Started | Oct 09 08:48:52 PM UTC 24 |
| Finished | Oct 09 08:49:19 PM UTC 24 |
| Peak memory | 252492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177233962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.4177233962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_regwen.2545337563 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 1207749710 ps |
| CPU time | 18.38 seconds |
| Started | Oct 09 08:48:59 PM UTC 24 |
| Finished | Oct 09 08:49:19 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545337563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.2545337563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/29.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_smoke.2173461752 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 909960150 ps |
| CPU time | 11.47 seconds |
| Started | Oct 09 08:48:50 PM UTC 24 |
| Finished | Oct 09 08:49:03 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173461752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.2173461752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/29.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all.2711909502 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 47485498950 ps |
| CPU time | 169.17 seconds |
| Started | Oct 09 08:49:05 PM UTC 24 |
| Finished | Oct 09 08:51:57 PM UTC 24 |
| Peak memory | 285356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711909502 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.2711909502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_test_access.1318247307 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1464769530 ps |
| CPU time | 10.97 seconds |
| Started | Oct 09 08:49:01 PM UTC 24 |
| Finished | Oct 09 08:49:13 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318247307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.1318247307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/29.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.547906333 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 319774914 ps |
| CPU time | 4.18 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:33 PM UTC 24 |
| Peak memory | 252232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547906333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.547906333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/290.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.6263522 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 153320321 ps |
| CPU time | 3.52 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:32 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6263522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.6263522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/291.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.3438416133 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 386172793 ps |
| CPU time | 4.23 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:33 PM UTC 24 |
| Peak memory | 252412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438416133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.3438416133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/293.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.1542146303 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 282240865 ps |
| CPU time | 3.65 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:33 PM UTC 24 |
| Peak memory | 252476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542146303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.1542146303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/294.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.517667680 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 1597465238 ps |
| CPU time | 4 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:33 PM UTC 24 |
| Peak memory | 252156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517667680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.517667680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/295.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.257632210 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 519856795 ps |
| CPU time | 5.28 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:34 PM UTC 24 |
| Peak memory | 252392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257632210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.257632210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/296.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.2781467485 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 305904448 ps |
| CPU time | 3.93 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:33 PM UTC 24 |
| Peak memory | 252480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781467485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.2781467485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/297.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.677247929 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 112449945 ps |
| CPU time | 4.12 seconds |
| Started | Oct 09 08:55:27 PM UTC 24 |
| Finished | Oct 09 08:55:33 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677247929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.677247929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/298.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.2502574048 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 239953875 ps |
| CPU time | 3.35 seconds |
| Started | Oct 09 08:55:38 PM UTC 24 |
| Finished | Oct 09 08:55:42 PM UTC 24 |
| Peak memory | 252344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502574048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.2502574048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/299.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_alert_test.1129173271 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 75315211 ps |
| CPU time | 3.42 seconds |
| Started | Oct 09 08:44:48 PM UTC 24 |
| Finished | Oct 09 08:44:53 PM UTC 24 |
| Peak memory | 252328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129173271 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.1129173271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_background_chks.1644858594 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 11946226129 ps |
| CPU time | 31.74 seconds |
| Started | Oct 09 08:44:37 PM UTC 24 |
| Finished | Oct 09 08:45:10 PM UTC 24 |
| Peak memory | 254824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644858594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.1644858594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_errs.2963272949 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 505700046 ps |
| CPU time | 18.73 seconds |
| Started | Oct 09 08:44:42 PM UTC 24 |
| Finished | Oct 09 08:45:02 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963272949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.2963272949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_lock.3798894297 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1469268866 ps |
| CPU time | 22.67 seconds |
| Started | Oct 09 08:44:40 PM UTC 24 |
| Finished | Oct 09 08:45:04 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798894297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.3798894297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_init_fail.4018151974 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 498158384 ps |
| CPU time | 6.22 seconds |
| Started | Oct 09 08:44:36 PM UTC 24 |
| Finished | Oct 09 08:44:44 PM UTC 24 |
| Peak memory | 252492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018151974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.4018151974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_macro_errs.3934540472 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 746579473 ps |
| CPU time | 22.76 seconds |
| Started | Oct 09 08:44:42 PM UTC 24 |
| Finished | Oct 09 08:45:06 PM UTC 24 |
| Peak memory | 254080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934540472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.3934540472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_esc.1492788113 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 419128729 ps |
| CPU time | 14.74 seconds |
| Started | Oct 09 08:44:40 PM UTC 24 |
| Finished | Oct 09 08:44:56 PM UTC 24 |
| Peak memory | 252352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492788113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.1492788113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_regwen.3797445484 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 381962637 ps |
| CPU time | 4.82 seconds |
| Started | Oct 09 08:44:42 PM UTC 24 |
| Finished | Oct 09 08:44:48 PM UTC 24 |
| Peak memory | 252320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797445484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.3797445484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_sec_cm.639366464 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 30227872086 ps |
| CPU time | 191.59 seconds |
| Started | Oct 09 08:44:47 PM UTC 24 |
| Finished | Oct 09 08:48:02 PM UTC 24 |
| Peak memory | 297032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639366464 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.639366464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_smoke.855731615 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 105497349 ps |
| CPU time | 4.81 seconds |
| Started | Oct 09 08:44:35 PM UTC 24 |
| Finished | Oct 09 08:44:41 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855731615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.855731615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_alert_test.1378379555 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 188298517 ps |
| CPU time | 2.32 seconds |
| Started | Oct 09 08:49:15 PM UTC 24 |
| Finished | Oct 09 08:49:18 PM UTC 24 |
| Peak memory | 252244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378379555 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.1378379555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/30.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_check_fail.1310985969 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 3124839565 ps |
| CPU time | 35.11 seconds |
| Started | Oct 09 08:49:10 PM UTC 24 |
| Finished | Oct 09 08:49:47 PM UTC 24 |
| Peak memory | 254700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310985969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.1310985969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/30.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_errs.240587772 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 3725536317 ps |
| CPU time | 37.52 seconds |
| Started | Oct 09 08:49:10 PM UTC 24 |
| Finished | Oct 09 08:49:49 PM UTC 24 |
| Peak memory | 254580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240587772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.240587772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/30.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_lock.2634410813 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 799883560 ps |
| CPU time | 14.11 seconds |
| Started | Oct 09 08:49:09 PM UTC 24 |
| Finished | Oct 09 08:49:24 PM UTC 24 |
| Peak memory | 252528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634410813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.2634410813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/30.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_init_fail.407994532 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 294393048 ps |
| CPU time | 5.91 seconds |
| Started | Oct 09 08:49:05 PM UTC 24 |
| Finished | Oct 09 08:49:12 PM UTC 24 |
| Peak memory | 252548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407994532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.407994532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/30.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_macro_errs.355786045 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 5224714868 ps |
| CPU time | 13.21 seconds |
| Started | Oct 09 08:49:11 PM UTC 24 |
| Finished | Oct 09 08:49:26 PM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355786045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.355786045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/30.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_key_req.2552757082 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 7584668896 ps |
| CPU time | 113.22 seconds |
| Started | Oct 09 08:49:14 PM UTC 24 |
| Finished | Oct 09 08:51:10 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552757082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.2552757082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_esc.2522095354 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 571003125 ps |
| CPU time | 14.29 seconds |
| Started | Oct 09 08:49:09 PM UTC 24 |
| Finished | Oct 09 08:49:24 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522095354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.2522095354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_req.50823119 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 1060260926 ps |
| CPU time | 17.75 seconds |
| Started | Oct 09 08:49:05 PM UTC 24 |
| Finished | Oct 09 08:49:24 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50823119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.50823119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_regwen.104026068 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 434167073 ps |
| CPU time | 5.29 seconds |
| Started | Oct 09 08:49:14 PM UTC 24 |
| Finished | Oct 09 08:49:21 PM UTC 24 |
| Peak memory | 252416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104026068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.104026068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/30.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_smoke.2045886045 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 355778252 ps |
| CPU time | 8.09 seconds |
| Started | Oct 09 08:49:05 PM UTC 24 |
| Finished | Oct 09 08:49:14 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045886045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.2045886045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/30.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all.624315758 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 28676103010 ps |
| CPU time | 250.55 seconds |
| Started | Oct 09 08:49:14 PM UTC 24 |
| Finished | Oct 09 08:53:29 PM UTC 24 |
| Peak memory | 289536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624315758 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.624315758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_test_access.3447869382 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 553806860 ps |
| CPU time | 14.59 seconds |
| Started | Oct 09 08:49:14 PM UTC 24 |
| Finished | Oct 09 08:49:30 PM UTC 24 |
| Peak memory | 252464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447869382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.3447869382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/30.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_alert_test.4153881177 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 81356300 ps |
| CPU time | 2.37 seconds |
| Started | Oct 09 08:49:28 PM UTC 24 |
| Finished | Oct 09 08:49:31 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153881177 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.4153881177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/31.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_check_fail.2165097590 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1236820977 ps |
| CPU time | 15.74 seconds |
| Started | Oct 09 08:49:20 PM UTC 24 |
| Finished | Oct 09 08:49:37 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165097590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.2165097590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/31.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_errs.3052343972 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 3833374285 ps |
| CPU time | 24.87 seconds |
| Started | Oct 09 08:49:20 PM UTC 24 |
| Finished | Oct 09 08:49:46 PM UTC 24 |
| Peak memory | 252432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052343972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.3052343972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/31.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_lock.6621102 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 2824373775 ps |
| CPU time | 34.88 seconds |
| Started | Oct 09 08:49:18 PM UTC 24 |
| Finished | Oct 09 08:49:55 PM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6621102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.6621102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/31.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_init_fail.2194862283 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 236403638 ps |
| CPU time | 5.17 seconds |
| Started | Oct 09 08:49:16 PM UTC 24 |
| Finished | Oct 09 08:49:23 PM UTC 24 |
| Peak memory | 252432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194862283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.2194862283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/31.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_macro_errs.1503760655 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 733489980 ps |
| CPU time | 6.28 seconds |
| Started | Oct 09 08:49:20 PM UTC 24 |
| Finished | Oct 09 08:49:28 PM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503760655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.1503760655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/31.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_key_req.1435861816 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1555362099 ps |
| CPU time | 12.14 seconds |
| Started | Oct 09 08:49:21 PM UTC 24 |
| Finished | Oct 09 08:49:35 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435861816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.1435861816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_esc.2817471211 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 3741330162 ps |
| CPU time | 16.3 seconds |
| Started | Oct 09 08:49:16 PM UTC 24 |
| Finished | Oct 09 08:49:34 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817471211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.2817471211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_req.2246873955 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 2057390025 ps |
| CPU time | 22.41 seconds |
| Started | Oct 09 08:49:16 PM UTC 24 |
| Finished | Oct 09 08:49:40 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246873955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.2246873955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_regwen.1817299068 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 594673575 ps |
| CPU time | 9.09 seconds |
| Started | Oct 09 08:49:24 PM UTC 24 |
| Finished | Oct 09 08:49:34 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817299068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.1817299068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/31.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_smoke.287712804 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 3079082901 ps |
| CPU time | 9.42 seconds |
| Started | Oct 09 08:49:15 PM UTC 24 |
| Finished | Oct 09 08:49:25 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287712804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.287712804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/31.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all.3605096400 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 52051522369 ps |
| CPU time | 308.22 seconds |
| Started | Oct 09 08:49:28 PM UTC 24 |
| Finished | Oct 09 08:54:41 PM UTC 24 |
| Peak memory | 261512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605096400 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.3605096400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.2516829887 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 14450434493 ps |
| CPU time | 74.65 seconds |
| Started | Oct 09 08:49:25 PM UTC 24 |
| Finished | Oct 09 08:50:42 PM UTC 24 |
| Peak memory | 258852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2516829887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 31.otp_ctrl_stress_all_with_rand_reset.2516829887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_test_access.4003089836 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1040394914 ps |
| CPU time | 40.32 seconds |
| Started | Oct 09 08:49:25 PM UTC 24 |
| Finished | Oct 09 08:50:07 PM UTC 24 |
| Peak memory | 252492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003089836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.4003089836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/31.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_alert_test.3923639516 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 624370729 ps |
| CPU time | 2.71 seconds |
| Started | Oct 09 08:49:37 PM UTC 24 |
| Finished | Oct 09 08:49:41 PM UTC 24 |
| Peak memory | 252244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923639516 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.3923639516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/32.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_check_fail.120651521 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 90936916 ps |
| CPU time | 3.24 seconds |
| Started | Oct 09 08:49:32 PM UTC 24 |
| Finished | Oct 09 08:49:36 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120651521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.120651521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/32.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_errs.3016632588 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 525919870 ps |
| CPU time | 17.43 seconds |
| Started | Oct 09 08:49:32 PM UTC 24 |
| Finished | Oct 09 08:49:51 PM UTC 24 |
| Peak memory | 252076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016632588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.3016632588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/32.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_lock.4045047097 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 11511763014 ps |
| CPU time | 21.23 seconds |
| Started | Oct 09 08:49:32 PM UTC 24 |
| Finished | Oct 09 08:49:54 PM UTC 24 |
| Peak memory | 254564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045047097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.4045047097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/32.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_init_fail.767859034 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 191208345 ps |
| CPU time | 3.67 seconds |
| Started | Oct 09 08:49:28 PM UTC 24 |
| Finished | Oct 09 08:49:33 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767859034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.767859034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/32.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_macro_errs.4275755749 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 360885221 ps |
| CPU time | 5.29 seconds |
| Started | Oct 09 08:49:32 PM UTC 24 |
| Finished | Oct 09 08:49:38 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275755749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.4275755749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/32.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_key_req.246445234 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 404060341 ps |
| CPU time | 9.46 seconds |
| Started | Oct 09 08:49:32 PM UTC 24 |
| Finished | Oct 09 08:49:43 PM UTC 24 |
| Peak memory | 252244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246445234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.246445234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_esc.1643882225 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 291784620 ps |
| CPU time | 8.21 seconds |
| Started | Oct 09 08:49:28 PM UTC 24 |
| Finished | Oct 09 08:49:38 PM UTC 24 |
| Peak memory | 252240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643882225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.1643882225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_req.2795878769 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 1190567277 ps |
| CPU time | 24.27 seconds |
| Started | Oct 09 08:49:28 PM UTC 24 |
| Finished | Oct 09 08:49:54 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795878769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.2795878769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_regwen.259904205 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 648965493 ps |
| CPU time | 10.1 seconds |
| Started | Oct 09 08:49:34 PM UTC 24 |
| Finished | Oct 09 08:49:45 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259904205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.259904205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/32.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_smoke.886421187 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 329075951 ps |
| CPU time | 8.46 seconds |
| Started | Oct 09 08:49:28 PM UTC 24 |
| Finished | Oct 09 08:49:38 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886421187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.886421187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/32.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all.1548100076 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 22287593830 ps |
| CPU time | 97.1 seconds |
| Started | Oct 09 08:49:37 PM UTC 24 |
| Finished | Oct 09 08:51:17 PM UTC 24 |
| Peak memory | 258700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548100076 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.1548100076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.458917651 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 19017286105 ps |
| CPU time | 49.98 seconds |
| Started | Oct 09 08:49:37 PM UTC 24 |
| Finished | Oct 09 08:50:29 PM UTC 24 |
| Peak memory | 268996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=458917651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.458917651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_test_access.2063261478 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 1703448530 ps |
| CPU time | 24.76 seconds |
| Started | Oct 09 08:49:34 PM UTC 24 |
| Finished | Oct 09 08:50:00 PM UTC 24 |
| Peak memory | 254624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063261478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.2063261478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/32.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_alert_test.1321572130 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 66981066 ps |
| CPU time | 3.31 seconds |
| Started | Oct 09 08:49:45 PM UTC 24 |
| Finished | Oct 09 08:49:50 PM UTC 24 |
| Peak memory | 252264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321572130 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.1321572130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/33.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_check_fail.3588151080 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 237634376 ps |
| CPU time | 9.55 seconds |
| Started | Oct 09 08:49:39 PM UTC 24 |
| Finished | Oct 09 08:49:50 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588151080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.3588151080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/33.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_errs.1255539301 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 1109460975 ps |
| CPU time | 18.47 seconds |
| Started | Oct 09 08:49:39 PM UTC 24 |
| Finished | Oct 09 08:49:59 PM UTC 24 |
| Peak memory | 252324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255539301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.1255539301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/33.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_lock.3111213060 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 520497624 ps |
| CPU time | 12.59 seconds |
| Started | Oct 09 08:49:39 PM UTC 24 |
| Finished | Oct 09 08:49:53 PM UTC 24 |
| Peak memory | 252524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111213060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.3111213060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/33.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_init_fail.2440152825 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 171018263 ps |
| CPU time | 6.24 seconds |
| Started | Oct 09 08:49:38 PM UTC 24 |
| Finished | Oct 09 08:49:45 PM UTC 24 |
| Peak memory | 252432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440152825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.2440152825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/33.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_macro_errs.1941319961 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 1908248888 ps |
| CPU time | 16.18 seconds |
| Started | Oct 09 08:49:40 PM UTC 24 |
| Finished | Oct 09 08:49:57 PM UTC 24 |
| Peak memory | 252596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941319961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.1941319961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/33.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_key_req.3666699289 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 6344085175 ps |
| CPU time | 13.09 seconds |
| Started | Oct 09 08:49:42 PM UTC 24 |
| Finished | Oct 09 08:49:56 PM UTC 24 |
| Peak memory | 254560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666699289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.3666699289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_esc.3312294204 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 675127430 ps |
| CPU time | 10.64 seconds |
| Started | Oct 09 08:49:38 PM UTC 24 |
| Finished | Oct 09 08:49:50 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312294204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.3312294204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_req.619754028 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 11267095297 ps |
| CPU time | 36.7 seconds |
| Started | Oct 09 08:49:38 PM UTC 24 |
| Finished | Oct 09 08:50:16 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619754028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.619754028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_regwen.3744618942 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 439945721 ps |
| CPU time | 8.3 seconds |
| Started | Oct 09 08:49:42 PM UTC 24 |
| Finished | Oct 09 08:49:51 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744618942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.3744618942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/33.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_smoke.3523383445 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 284357305 ps |
| CPU time | 5.48 seconds |
| Started | Oct 09 08:49:38 PM UTC 24 |
| Finished | Oct 09 08:49:44 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523383445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.3523383445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/33.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all.1743778520 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 3337081266 ps |
| CPU time | 55.42 seconds |
| Started | Oct 09 08:49:44 PM UTC 24 |
| Finished | Oct 09 08:50:41 PM UTC 24 |
| Peak memory | 258728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743778520 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all.1743778520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_test_access.1604077904 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 7554384991 ps |
| CPU time | 18.44 seconds |
| Started | Oct 09 08:49:42 PM UTC 24 |
| Finished | Oct 09 08:50:02 PM UTC 24 |
| Peak memory | 252592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604077904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.1604077904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/33.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_alert_test.2849163710 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 149467332 ps |
| CPU time | 2.38 seconds |
| Started | Oct 09 08:49:56 PM UTC 24 |
| Finished | Oct 09 08:50:00 PM UTC 24 |
| Peak memory | 252324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849163710 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.2849163710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/34.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_check_fail.1927319759 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 561043286 ps |
| CPU time | 21.72 seconds |
| Started | Oct 09 08:49:54 PM UTC 24 |
| Finished | Oct 09 08:50:18 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927319759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.1927319759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/34.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_errs.2399644166 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 673138917 ps |
| CPU time | 19.27 seconds |
| Started | Oct 09 08:49:54 PM UTC 24 |
| Finished | Oct 09 08:50:15 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399644166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.2399644166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/34.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_lock.2930352765 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 246068706 ps |
| CPU time | 5.54 seconds |
| Started | Oct 09 08:49:54 PM UTC 24 |
| Finished | Oct 09 08:50:02 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930352765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.2930352765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/34.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_init_fail.2268212927 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 725720395 ps |
| CPU time | 6.02 seconds |
| Started | Oct 09 08:49:53 PM UTC 24 |
| Finished | Oct 09 08:50:02 PM UTC 24 |
| Peak memory | 252476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268212927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.2268212927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/34.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_macro_errs.244243180 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 1436778589 ps |
| CPU time | 28.46 seconds |
| Started | Oct 09 08:49:54 PM UTC 24 |
| Finished | Oct 09 08:50:25 PM UTC 24 |
| Peak memory | 256548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244243180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.244243180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/34.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_key_req.1681557958 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 2700571030 ps |
| CPU time | 25.48 seconds |
| Started | Oct 09 08:49:54 PM UTC 24 |
| Finished | Oct 09 08:50:22 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681557958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.1681557958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_esc.3328490847 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 2801095665 ps |
| CPU time | 7.27 seconds |
| Started | Oct 09 08:49:54 PM UTC 24 |
| Finished | Oct 09 08:50:03 PM UTC 24 |
| Peak memory | 252436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328490847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.3328490847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_req.2299092365 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 821499084 ps |
| CPU time | 24.01 seconds |
| Started | Oct 09 08:49:54 PM UTC 24 |
| Finished | Oct 09 08:50:20 PM UTC 24 |
| Peak memory | 252356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299092365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.2299092365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_regwen.3215240269 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 109772472 ps |
| CPU time | 3.87 seconds |
| Started | Oct 09 08:49:54 PM UTC 24 |
| Finished | Oct 09 08:50:00 PM UTC 24 |
| Peak memory | 252416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215240269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.3215240269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/34.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_smoke.3285265023 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 193707155 ps |
| CPU time | 5.63 seconds |
| Started | Oct 09 08:49:53 PM UTC 24 |
| Finished | Oct 09 08:50:02 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285265023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.3285265023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/34.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all.2773925298 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 60524423189 ps |
| CPU time | 189.5 seconds |
| Started | Oct 09 08:49:54 PM UTC 24 |
| Finished | Oct 09 08:53:08 PM UTC 24 |
| Peak memory | 260844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773925298 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.2773925298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_test_access.844880560 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 602707518 ps |
| CPU time | 14.11 seconds |
| Started | Oct 09 08:49:54 PM UTC 24 |
| Finished | Oct 09 08:50:11 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844880560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.844880560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/34.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_alert_test.2317378478 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 599757270 ps |
| CPU time | 3.7 seconds |
| Started | Oct 09 08:50:04 PM UTC 24 |
| Finished | Oct 09 08:50:08 PM UTC 24 |
| Peak memory | 252320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317378478 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.2317378478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/35.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_check_fail.1046399771 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 19204783211 ps |
| CPU time | 45.8 seconds |
| Started | Oct 09 08:50:01 PM UTC 24 |
| Finished | Oct 09 08:50:49 PM UTC 24 |
| Peak memory | 254620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046399771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.1046399771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/35.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_errs.2284913068 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1217814392 ps |
| CPU time | 17.02 seconds |
| Started | Oct 09 08:49:58 PM UTC 24 |
| Finished | Oct 09 08:50:16 PM UTC 24 |
| Peak memory | 252320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284913068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.2284913068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/35.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_lock.977227406 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 657070058 ps |
| CPU time | 21.92 seconds |
| Started | Oct 09 08:49:58 PM UTC 24 |
| Finished | Oct 09 08:50:21 PM UTC 24 |
| Peak memory | 252592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977227406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.977227406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/35.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_init_fail.2859272037 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 193624349 ps |
| CPU time | 4.86 seconds |
| Started | Oct 09 08:49:56 PM UTC 24 |
| Finished | Oct 09 08:50:03 PM UTC 24 |
| Peak memory | 252560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859272037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.2859272037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/35.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_macro_errs.427390571 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 6102833448 ps |
| CPU time | 26.41 seconds |
| Started | Oct 09 08:50:01 PM UTC 24 |
| Finished | Oct 09 08:50:29 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427390571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.427390571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/35.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_key_req.207355652 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 2400268422 ps |
| CPU time | 28.52 seconds |
| Started | Oct 09 08:50:01 PM UTC 24 |
| Finished | Oct 09 08:50:31 PM UTC 24 |
| Peak memory | 252484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207355652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.207355652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_esc.405518587 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 3495479310 ps |
| CPU time | 12.03 seconds |
| Started | Oct 09 08:49:56 PM UTC 24 |
| Finished | Oct 09 08:50:10 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405518587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.405518587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_req.2304984002 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 612815516 ps |
| CPU time | 19.37 seconds |
| Started | Oct 09 08:49:56 PM UTC 24 |
| Finished | Oct 09 08:50:17 PM UTC 24 |
| Peak memory | 258508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304984002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.2304984002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_regwen.4099639664 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 646462511 ps |
| CPU time | 6.38 seconds |
| Started | Oct 09 08:50:02 PM UTC 24 |
| Finished | Oct 09 08:50:09 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099639664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.4099639664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/35.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_smoke.692362863 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 198710858 ps |
| CPU time | 8.28 seconds |
| Started | Oct 09 08:49:56 PM UTC 24 |
| Finished | Oct 09 08:50:06 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692362863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.692362863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/35.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all.2814939278 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 30995736826 ps |
| CPU time | 248.6 seconds |
| Started | Oct 09 08:50:04 PM UTC 24 |
| Finished | Oct 09 08:54:16 PM UTC 24 |
| Peak memory | 291496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814939278 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.2814939278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.2096465306 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 4813033528 ps |
| CPU time | 83.1 seconds |
| Started | Oct 09 08:50:03 PM UTC 24 |
| Finished | Oct 09 08:51:29 PM UTC 24 |
| Peak memory | 269020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2096465306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.otp_ctrl_stress_all_with_rand_reset.2096465306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_test_access.2684114126 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 1257603098 ps |
| CPU time | 17.28 seconds |
| Started | Oct 09 08:50:03 PM UTC 24 |
| Finished | Oct 09 08:50:22 PM UTC 24 |
| Peak memory | 252528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684114126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.2684114126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/35.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_alert_test.3902627179 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 204335166 ps |
| CPU time | 2.82 seconds |
| Started | Oct 09 08:50:17 PM UTC 24 |
| Finished | Oct 09 08:50:21 PM UTC 24 |
| Peak memory | 251804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902627179 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.3902627179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/36.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_check_fail.2448962041 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 2904060767 ps |
| CPU time | 26.57 seconds |
| Started | Oct 09 08:50:14 PM UTC 24 |
| Finished | Oct 09 08:50:42 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448962041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.2448962041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/36.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_errs.3657238516 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 325532217 ps |
| CPU time | 9.42 seconds |
| Started | Oct 09 08:50:14 PM UTC 24 |
| Finished | Oct 09 08:50:24 PM UTC 24 |
| Peak memory | 252392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657238516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.3657238516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/36.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_lock.3887093060 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 1239241437 ps |
| CPU time | 23.87 seconds |
| Started | Oct 09 08:50:13 PM UTC 24 |
| Finished | Oct 09 08:50:39 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887093060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.3887093060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/36.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_init_fail.4108627430 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 2128530522 ps |
| CPU time | 8.1 seconds |
| Started | Oct 09 08:50:13 PM UTC 24 |
| Finished | Oct 09 08:50:23 PM UTC 24 |
| Peak memory | 252624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108627430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.4108627430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/36.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_macro_errs.1076380963 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 403726975 ps |
| CPU time | 13.61 seconds |
| Started | Oct 09 08:50:14 PM UTC 24 |
| Finished | Oct 09 08:50:29 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076380963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.1076380963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/36.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_key_req.1166571147 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 2583119660 ps |
| CPU time | 7.56 seconds |
| Started | Oct 09 08:50:14 PM UTC 24 |
| Finished | Oct 09 08:50:23 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166571147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.1166571147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_esc.1787258774 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 372800374 ps |
| CPU time | 11.53 seconds |
| Started | Oct 09 08:50:13 PM UTC 24 |
| Finished | Oct 09 08:50:26 PM UTC 24 |
| Peak memory | 252356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787258774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.1787258774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_req.369080833 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 488158645 ps |
| CPU time | 5.75 seconds |
| Started | Oct 09 08:50:13 PM UTC 24 |
| Finished | Oct 09 08:50:21 PM UTC 24 |
| Peak memory | 252304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369080833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.369080833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_regwen.137967855 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 149051722 ps |
| CPU time | 7.67 seconds |
| Started | Oct 09 08:50:14 PM UTC 24 |
| Finished | Oct 09 08:50:23 PM UTC 24 |
| Peak memory | 252412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137967855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.137967855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/36.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_smoke.4135130096 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 952749026 ps |
| CPU time | 14.38 seconds |
| Started | Oct 09 08:50:04 PM UTC 24 |
| Finished | Oct 09 08:50:19 PM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135130096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.4135130096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/36.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all.1508489233 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 2005665285 ps |
| CPU time | 29.96 seconds |
| Started | Oct 09 08:50:14 PM UTC 24 |
| Finished | Oct 09 08:50:46 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508489233 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.1508489233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.3349442434 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 1747535514 ps |
| CPU time | 49.34 seconds |
| Started | Oct 09 08:50:14 PM UTC 24 |
| Finished | Oct 09 08:51:05 PM UTC 24 |
| Peak memory | 258460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3349442434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.otp_ctrl_stress_all_with_rand_reset.3349442434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_test_access.2781377034 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 657999387 ps |
| CPU time | 5.79 seconds |
| Started | Oct 09 08:50:14 PM UTC 24 |
| Finished | Oct 09 08:50:21 PM UTC 24 |
| Peak memory | 258660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781377034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.2781377034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/36.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_alert_test.3108815789 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 66078861 ps |
| CPU time | 2.46 seconds |
| Started | Oct 09 08:50:30 PM UTC 24 |
| Finished | Oct 09 08:50:34 PM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108815789 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.3108815789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/37.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_check_fail.1475691331 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 818317621 ps |
| CPU time | 9.69 seconds |
| Started | Oct 09 08:50:30 PM UTC 24 |
| Finished | Oct 09 08:50:41 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475691331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.1475691331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/37.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_errs.725431198 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 2002756096 ps |
| CPU time | 26.16 seconds |
| Started | Oct 09 08:50:30 PM UTC 24 |
| Finished | Oct 09 08:50:58 PM UTC 24 |
| Peak memory | 256560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725431198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.725431198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/37.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_lock.417937978 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 310703759 ps |
| CPU time | 12.29 seconds |
| Started | Oct 09 08:50:21 PM UTC 24 |
| Finished | Oct 09 08:50:34 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417937978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.417937978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/37.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_init_fail.1077393286 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 146778291 ps |
| CPU time | 4.35 seconds |
| Started | Oct 09 08:50:20 PM UTC 24 |
| Finished | Oct 09 08:50:26 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077393286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.1077393286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/37.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_macro_errs.2440387106 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 3084400419 ps |
| CPU time | 22.69 seconds |
| Started | Oct 09 08:50:30 PM UTC 24 |
| Finished | Oct 09 08:50:54 PM UTC 24 |
| Peak memory | 254696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440387106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.2440387106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/37.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_key_req.2208268328 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 1746109368 ps |
| CPU time | 7.28 seconds |
| Started | Oct 09 08:50:30 PM UTC 24 |
| Finished | Oct 09 08:50:39 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208268328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.2208268328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_esc.563317529 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 4876373462 ps |
| CPU time | 9.44 seconds |
| Started | Oct 09 08:50:21 PM UTC 24 |
| Finished | Oct 09 08:50:31 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563317529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.563317529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_req.1522207365 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 693646975 ps |
| CPU time | 17.27 seconds |
| Started | Oct 09 08:50:20 PM UTC 24 |
| Finished | Oct 09 08:50:39 PM UTC 24 |
| Peak memory | 252308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522207365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.1522207365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_regwen.2429384387 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 1988042764 ps |
| CPU time | 8.13 seconds |
| Started | Oct 09 08:50:30 PM UTC 24 |
| Finished | Oct 09 08:50:40 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429384387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.2429384387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/37.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_smoke.2802421135 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 225878596 ps |
| CPU time | 6.3 seconds |
| Started | Oct 09 08:50:17 PM UTC 24 |
| Finished | Oct 09 08:50:25 PM UTC 24 |
| Peak memory | 252524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802421135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.2802421135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/37.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.343094019 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 68441390040 ps |
| CPU time | 278.52 seconds |
| Started | Oct 09 08:50:30 PM UTC 24 |
| Finished | Oct 09 08:55:13 PM UTC 24 |
| Peak memory | 268968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343094019 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.343094019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_test_access.4230306556 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 930246320 ps |
| CPU time | 25.15 seconds |
| Started | Oct 09 08:50:30 PM UTC 24 |
| Finished | Oct 09 08:50:57 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230306556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.4230306556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/37.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_alert_test.1322934032 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 76778127 ps |
| CPU time | 2.74 seconds |
| Started | Oct 09 08:50:37 PM UTC 24 |
| Finished | Oct 09 08:50:41 PM UTC 24 |
| Peak memory | 252304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322934032 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.1322934032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/38.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_check_fail.3114195161 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 14461710504 ps |
| CPU time | 25.15 seconds |
| Started | Oct 09 08:50:31 PM UTC 24 |
| Finished | Oct 09 08:50:57 PM UTC 24 |
| Peak memory | 254624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114195161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.3114195161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/38.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_errs.2513911425 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 1802434094 ps |
| CPU time | 31.55 seconds |
| Started | Oct 09 08:50:31 PM UTC 24 |
| Finished | Oct 09 08:51:04 PM UTC 24 |
| Peak memory | 258612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513911425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.2513911425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/38.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_lock.618396424 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 10250719214 ps |
| CPU time | 27.15 seconds |
| Started | Oct 09 08:50:31 PM UTC 24 |
| Finished | Oct 09 08:50:59 PM UTC 24 |
| Peak memory | 254492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618396424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.618396424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/38.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_init_fail.1980502827 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 290824399 ps |
| CPU time | 3.91 seconds |
| Started | Oct 09 08:50:31 PM UTC 24 |
| Finished | Oct 09 08:50:36 PM UTC 24 |
| Peak memory | 252324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980502827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.1980502827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/38.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_macro_errs.366876815 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 6920221609 ps |
| CPU time | 13.47 seconds |
| Started | Oct 09 08:50:31 PM UTC 24 |
| Finished | Oct 09 08:50:46 PM UTC 24 |
| Peak memory | 256812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366876815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.366876815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/38.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_key_req.1915686974 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 627545556 ps |
| CPU time | 7.85 seconds |
| Started | Oct 09 08:50:31 PM UTC 24 |
| Finished | Oct 09 08:50:40 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915686974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.1915686974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_esc.2582067044 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 402766314 ps |
| CPU time | 4.33 seconds |
| Started | Oct 09 08:50:31 PM UTC 24 |
| Finished | Oct 09 08:50:36 PM UTC 24 |
| Peak memory | 252352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582067044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.2582067044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_req.2593406494 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 1058518474 ps |
| CPU time | 13.82 seconds |
| Started | Oct 09 08:50:31 PM UTC 24 |
| Finished | Oct 09 08:50:46 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593406494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.2593406494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_regwen.4264255504 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 463799273 ps |
| CPU time | 6.43 seconds |
| Started | Oct 09 08:50:37 PM UTC 24 |
| Finished | Oct 09 08:50:44 PM UTC 24 |
| Peak memory | 252184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264255504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.4264255504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/38.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_smoke.3970615296 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 397605981 ps |
| CPU time | 6.21 seconds |
| Started | Oct 09 08:50:31 PM UTC 24 |
| Finished | Oct 09 08:50:38 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970615296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.3970615296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/38.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all.2894729337 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 13779208397 ps |
| CPU time | 113.85 seconds |
| Started | Oct 09 08:50:37 PM UTC 24 |
| Finished | Oct 09 08:52:33 PM UTC 24 |
| Peak memory | 258636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894729337 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.2894729337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_test_access.3955336698 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 1335436329 ps |
| CPU time | 17.53 seconds |
| Started | Oct 09 08:50:37 PM UTC 24 |
| Finished | Oct 09 08:50:56 PM UTC 24 |
| Peak memory | 252256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955336698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.3955336698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/38.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_alert_test.3173012229 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 207240126 ps |
| CPU time | 3.25 seconds |
| Started | Oct 09 08:50:41 PM UTC 24 |
| Finished | Oct 09 08:50:45 PM UTC 24 |
| Peak memory | 252248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173012229 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.3173012229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/39.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_check_fail.610058556 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 1344484204 ps |
| CPU time | 11.86 seconds |
| Started | Oct 09 08:50:38 PM UTC 24 |
| Finished | Oct 09 08:50:51 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610058556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.610058556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_errs.2031814360 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 590352832 ps |
| CPU time | 12.27 seconds |
| Started | Oct 09 08:50:37 PM UTC 24 |
| Finished | Oct 09 08:50:51 PM UTC 24 |
| Peak memory | 252400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031814360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.2031814360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/39.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_lock.1548464188 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 433678427 ps |
| CPU time | 19.02 seconds |
| Started | Oct 09 08:50:37 PM UTC 24 |
| Finished | Oct 09 08:50:58 PM UTC 24 |
| Peak memory | 252524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548464188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.1548464188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/39.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_init_fail.3510975567 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 421464805 ps |
| CPU time | 6.29 seconds |
| Started | Oct 09 08:50:37 PM UTC 24 |
| Finished | Oct 09 08:50:45 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510975567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.3510975567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/39.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_macro_errs.3387606120 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 595696216 ps |
| CPU time | 7.16 seconds |
| Started | Oct 09 08:50:38 PM UTC 24 |
| Finished | Oct 09 08:50:46 PM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387606120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.3387606120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/39.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_key_req.1595079252 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 938974591 ps |
| CPU time | 13.47 seconds |
| Started | Oct 09 08:50:39 PM UTC 24 |
| Finished | Oct 09 08:50:53 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595079252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.1595079252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_esc.3275862018 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 2992371583 ps |
| CPU time | 15.08 seconds |
| Started | Oct 09 08:50:37 PM UTC 24 |
| Finished | Oct 09 08:50:54 PM UTC 24 |
| Peak memory | 252408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275862018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.3275862018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_req.1862524869 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 657322565 ps |
| CPU time | 8.68 seconds |
| Started | Oct 09 08:50:37 PM UTC 24 |
| Finished | Oct 09 08:50:47 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862524869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.1862524869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_regwen.983585611 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 116558031 ps |
| CPU time | 5.5 seconds |
| Started | Oct 09 08:50:41 PM UTC 24 |
| Finished | Oct 09 08:50:48 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983585611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.983585611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/39.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_smoke.2340126994 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 774908136 ps |
| CPU time | 6.33 seconds |
| Started | Oct 09 08:50:37 PM UTC 24 |
| Finished | Oct 09 08:50:45 PM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340126994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.2340126994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/39.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all.261087300 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 23233910223 ps |
| CPU time | 151.29 seconds |
| Started | Oct 09 08:50:41 PM UTC 24 |
| Finished | Oct 09 08:53:15 PM UTC 24 |
| Peak memory | 285404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261087300 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.261087300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.675837968 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 1955671985 ps |
| CPU time | 46.1 seconds |
| Started | Oct 09 08:50:41 PM UTC 24 |
| Finished | Oct 09 08:51:29 PM UTC 24 |
| Peak memory | 269096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=675837968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.675837968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_test_access.2485041961 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 328421576 ps |
| CPU time | 10.46 seconds |
| Started | Oct 09 08:50:41 PM UTC 24 |
| Finished | Oct 09 08:50:52 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485041961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.2485041961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/39.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_alert_test.3711790087 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 56035880 ps |
| CPU time | 2.84 seconds |
| Started | Oct 09 08:45:06 PM UTC 24 |
| Finished | Oct 09 08:45:10 PM UTC 24 |
| Peak memory | 252308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711790087 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.3711790087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_background_chks.2703833164 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 856769117 ps |
| CPU time | 10.33 seconds |
| Started | Oct 09 08:44:51 PM UTC 24 |
| Finished | Oct 09 08:45:02 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703833164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.2703833164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_check_fail.1442960774 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 302881701 ps |
| CPU time | 10.86 seconds |
| Started | Oct 09 08:45:00 PM UTC 24 |
| Finished | Oct 09 08:45:12 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442960774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.1442960774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_errs.1442869853 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 5181398080 ps |
| CPU time | 47.96 seconds |
| Started | Oct 09 08:45:00 PM UTC 24 |
| Finished | Oct 09 08:45:49 PM UTC 24 |
| Peak memory | 258704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442869853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.1442869853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_lock.3810984936 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 2764997081 ps |
| CPU time | 15.6 seconds |
| Started | Oct 09 08:44:58 PM UTC 24 |
| Finished | Oct 09 08:45:15 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810984936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.3810984936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_macro_errs.1481805005 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1530624703 ps |
| CPU time | 21.1 seconds |
| Started | Oct 09 08:45:04 PM UTC 24 |
| Finished | Oct 09 08:45:26 PM UTC 24 |
| Peak memory | 258660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481805005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.1481805005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_key_req.3049027802 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 723195398 ps |
| CPU time | 25.25 seconds |
| Started | Oct 09 08:45:04 PM UTC 24 |
| Finished | Oct 09 08:45:30 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049027802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.3049027802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_esc.3501863756 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 7976061682 ps |
| CPU time | 24.82 seconds |
| Started | Oct 09 08:44:55 PM UTC 24 |
| Finished | Oct 09 08:45:21 PM UTC 24 |
| Peak memory | 252436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501863756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.3501863756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_req.164758025 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 493694933 ps |
| CPU time | 21.73 seconds |
| Started | Oct 09 08:44:54 PM UTC 24 |
| Finished | Oct 09 08:45:18 PM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164758025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.164758025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_smoke.1253379716 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 683341789 ps |
| CPU time | 12.85 seconds |
| Started | Oct 09 08:44:49 PM UTC 24 |
| Finished | Oct 09 08:45:03 PM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253379716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.1253379716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_test_access.2020242932 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 560292107 ps |
| CPU time | 15.74 seconds |
| Started | Oct 09 08:45:04 PM UTC 24 |
| Finished | Oct 09 08:45:21 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020242932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.2020242932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/4.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_alert_test.3257834693 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 537754083 ps |
| CPU time | 6.54 seconds |
| Started | Oct 09 08:50:50 PM UTC 24 |
| Finished | Oct 09 08:50:57 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257834693 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.3257834693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/40.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_check_fail.4204483115 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 706779959 ps |
| CPU time | 14.57 seconds |
| Started | Oct 09 08:50:47 PM UTC 24 |
| Finished | Oct 09 08:51:02 PM UTC 24 |
| Peak memory | 252260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204483115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.4204483115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/40.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_errs.3438653393 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 1382083674 ps |
| CPU time | 30.44 seconds |
| Started | Oct 09 08:50:46 PM UTC 24 |
| Finished | Oct 09 08:51:18 PM UTC 24 |
| Peak memory | 256644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438653393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.3438653393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/40.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_lock.3371841766 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 1475541498 ps |
| CPU time | 26.31 seconds |
| Started | Oct 09 08:50:45 PM UTC 24 |
| Finished | Oct 09 08:51:12 PM UTC 24 |
| Peak memory | 252596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371841766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.3371841766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/40.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_init_fail.4287068159 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2558993715 ps |
| CPU time | 10.77 seconds |
| Started | Oct 09 08:50:44 PM UTC 24 |
| Finished | Oct 09 08:50:56 PM UTC 24 |
| Peak memory | 252484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287068159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.4287068159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/40.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_macro_errs.4248442194 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1618879922 ps |
| CPU time | 13.77 seconds |
| Started | Oct 09 08:50:47 PM UTC 24 |
| Finished | Oct 09 08:51:02 PM UTC 24 |
| Peak memory | 254400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248442194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.4248442194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/40.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_key_req.556306135 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 645197528 ps |
| CPU time | 19.39 seconds |
| Started | Oct 09 08:50:47 PM UTC 24 |
| Finished | Oct 09 08:51:07 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556306135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.556306135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_esc.3383480902 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 3597919347 ps |
| CPU time | 12.06 seconds |
| Started | Oct 09 08:50:45 PM UTC 24 |
| Finished | Oct 09 08:50:58 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383480902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.3383480902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_req.362056486 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 308116100 ps |
| CPU time | 10.13 seconds |
| Started | Oct 09 08:50:45 PM UTC 24 |
| Finished | Oct 09 08:50:56 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362056486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.362056486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_regwen.4024815092 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 298433408 ps |
| CPU time | 5.85 seconds |
| Started | Oct 09 08:50:47 PM UTC 24 |
| Finished | Oct 09 08:50:54 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024815092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.4024815092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/40.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_smoke.3498636082 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 950182939 ps |
| CPU time | 11.53 seconds |
| Started | Oct 09 08:50:44 PM UTC 24 |
| Finished | Oct 09 08:50:57 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498636082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.3498636082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/40.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all.2981665046 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 4684303757 ps |
| CPU time | 56.11 seconds |
| Started | Oct 09 08:50:50 PM UTC 24 |
| Finished | Oct 09 08:51:48 PM UTC 24 |
| Peak memory | 258792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981665046 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.2981665046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.4054175619 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 8907011415 ps |
| CPU time | 110.05 seconds |
| Started | Oct 09 08:50:50 PM UTC 24 |
| Finished | Oct 09 08:52:42 PM UTC 24 |
| Peak memory | 285472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4054175619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 40.otp_ctrl_stress_all_with_rand_reset.4054175619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_test_access.747305296 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 719624457 ps |
| CPU time | 18.18 seconds |
| Started | Oct 09 08:50:47 PM UTC 24 |
| Finished | Oct 09 08:51:06 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747305296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.747305296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/40.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_alert_test.388131737 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 91032511 ps |
| CPU time | 2.29 seconds |
| Started | Oct 09 08:50:59 PM UTC 24 |
| Finished | Oct 09 08:51:03 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388131737 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.388131737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/41.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_check_fail.1017643162 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 349365528 ps |
| CPU time | 7.72 seconds |
| Started | Oct 09 08:50:59 PM UTC 24 |
| Finished | Oct 09 08:51:08 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017643162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.1017643162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_errs.1452553175 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 13334476334 ps |
| CPU time | 35.46 seconds |
| Started | Oct 09 08:50:59 PM UTC 24 |
| Finished | Oct 09 08:51:36 PM UTC 24 |
| Peak memory | 256624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452553175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.1452553175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/41.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_lock.3488597040 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 2196279040 ps |
| CPU time | 4.39 seconds |
| Started | Oct 09 08:50:59 PM UTC 24 |
| Finished | Oct 09 08:51:04 PM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488597040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.3488597040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/41.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_init_fail.3196053746 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 281157201 ps |
| CPU time | 4.19 seconds |
| Started | Oct 09 08:50:50 PM UTC 24 |
| Finished | Oct 09 08:50:55 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196053746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.3196053746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/41.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_macro_errs.126180804 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 15577470342 ps |
| CPU time | 39.31 seconds |
| Started | Oct 09 08:50:59 PM UTC 24 |
| Finished | Oct 09 08:51:40 PM UTC 24 |
| Peak memory | 256608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126180804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.126180804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/41.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_key_req.745049726 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 1091778451 ps |
| CPU time | 25.96 seconds |
| Started | Oct 09 08:50:59 PM UTC 24 |
| Finished | Oct 09 08:51:26 PM UTC 24 |
| Peak memory | 252436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745049726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.745049726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_esc.2173213768 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 105167772 ps |
| CPU time | 4.93 seconds |
| Started | Oct 09 08:50:59 PM UTC 24 |
| Finished | Oct 09 08:51:05 PM UTC 24 |
| Peak memory | 252288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173213768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.2173213768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_req.2139477952 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 2635937926 ps |
| CPU time | 21.33 seconds |
| Started | Oct 09 08:50:58 PM UTC 24 |
| Finished | Oct 09 08:51:21 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139477952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.2139477952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_regwen.2551568722 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 1499299810 ps |
| CPU time | 4.59 seconds |
| Started | Oct 09 08:50:59 PM UTC 24 |
| Finished | Oct 09 08:51:05 PM UTC 24 |
| Peak memory | 252312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551568722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.2551568722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/41.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_smoke.2007481157 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 302515616 ps |
| CPU time | 6.18 seconds |
| Started | Oct 09 08:50:50 PM UTC 24 |
| Finished | Oct 09 08:50:57 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007481157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.2007481157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/41.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all.2944180658 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 24574241641 ps |
| CPU time | 157.99 seconds |
| Started | Oct 09 08:50:59 PM UTC 24 |
| Finished | Oct 09 08:53:40 PM UTC 24 |
| Peak memory | 258600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944180658 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.2944180658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.163824707 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 3884951714 ps |
| CPU time | 58.32 seconds |
| Started | Oct 09 08:50:59 PM UTC 24 |
| Finished | Oct 09 08:51:59 PM UTC 24 |
| Peak memory | 258756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=163824707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.163824707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_test_access.4277769286 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 329860698 ps |
| CPU time | 7.66 seconds |
| Started | Oct 09 08:50:59 PM UTC 24 |
| Finished | Oct 09 08:51:08 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277769286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.4277769286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/41.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_alert_test.327902826 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 111718566 ps |
| CPU time | 2.81 seconds |
| Started | Oct 09 08:51:06 PM UTC 24 |
| Finished | Oct 09 08:51:10 PM UTC 24 |
| Peak memory | 252240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327902826 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.327902826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/42.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_check_fail.496677346 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1357749092 ps |
| CPU time | 21.37 seconds |
| Started | Oct 09 08:51:05 PM UTC 24 |
| Finished | Oct 09 08:51:28 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496677346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.496677346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_errs.1706683605 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 643542222 ps |
| CPU time | 18.94 seconds |
| Started | Oct 09 08:51:05 PM UTC 24 |
| Finished | Oct 09 08:51:26 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706683605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.1706683605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/42.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_lock.1086647521 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 494036141 ps |
| CPU time | 6 seconds |
| Started | Oct 09 08:50:59 PM UTC 24 |
| Finished | Oct 09 08:51:07 PM UTC 24 |
| Peak memory | 252528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086647521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.1086647521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/42.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_init_fail.4051317567 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 137491102 ps |
| CPU time | 4.71 seconds |
| Started | Oct 09 08:50:59 PM UTC 24 |
| Finished | Oct 09 08:51:05 PM UTC 24 |
| Peak memory | 252020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051317567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.4051317567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/42.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_macro_errs.2754448536 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 613879588 ps |
| CPU time | 16.08 seconds |
| Started | Oct 09 08:51:05 PM UTC 24 |
| Finished | Oct 09 08:51:23 PM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754448536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.2754448536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/42.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_key_req.900204433 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 1215350938 ps |
| CPU time | 26.04 seconds |
| Started | Oct 09 08:51:05 PM UTC 24 |
| Finished | Oct 09 08:51:33 PM UTC 24 |
| Peak memory | 252416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900204433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.900204433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_esc.1290385983 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1004717652 ps |
| CPU time | 7.4 seconds |
| Started | Oct 09 08:50:59 PM UTC 24 |
| Finished | Oct 09 08:51:08 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290385983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.1290385983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_req.1444319227 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 381320598 ps |
| CPU time | 11.28 seconds |
| Started | Oct 09 08:50:59 PM UTC 24 |
| Finished | Oct 09 08:51:12 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444319227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.1444319227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_regwen.1472801496 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 831848157 ps |
| CPU time | 6 seconds |
| Started | Oct 09 08:51:06 PM UTC 24 |
| Finished | Oct 09 08:51:13 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472801496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.1472801496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/42.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_smoke.3345344136 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 2635992765 ps |
| CPU time | 5.97 seconds |
| Started | Oct 09 08:50:59 PM UTC 24 |
| Finished | Oct 09 08:51:06 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345344136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.3345344136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/42.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all.997576150 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 22656283464 ps |
| CPU time | 146.19 seconds |
| Started | Oct 09 08:51:06 PM UTC 24 |
| Finished | Oct 09 08:53:35 PM UTC 24 |
| Peak memory | 258640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997576150 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.997576150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_test_access.1391475756 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 1301481008 ps |
| CPU time | 24.99 seconds |
| Started | Oct 09 08:51:06 PM UTC 24 |
| Finished | Oct 09 08:51:32 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391475756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.1391475756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/42.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_alert_test.2697698660 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 245841089 ps |
| CPU time | 2.96 seconds |
| Started | Oct 09 08:51:12 PM UTC 24 |
| Finished | Oct 09 08:51:16 PM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697698660 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.2697698660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/43.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_check_fail.4231020378 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1090042412 ps |
| CPU time | 14.67 seconds |
| Started | Oct 09 08:51:12 PM UTC 24 |
| Finished | Oct 09 08:51:28 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231020378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.4231020378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/43.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_errs.2514353786 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 1091485892 ps |
| CPU time | 29.44 seconds |
| Started | Oct 09 08:51:11 PM UTC 24 |
| Finished | Oct 09 08:51:42 PM UTC 24 |
| Peak memory | 256632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514353786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.2514353786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/43.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_lock.1664762045 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 6869531840 ps |
| CPU time | 40.48 seconds |
| Started | Oct 09 08:51:11 PM UTC 24 |
| Finished | Oct 09 08:51:53 PM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664762045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.1664762045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/43.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_init_fail.2311048541 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 633087853 ps |
| CPU time | 4.84 seconds |
| Started | Oct 09 08:51:06 PM UTC 24 |
| Finished | Oct 09 08:51:12 PM UTC 24 |
| Peak memory | 252392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311048541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.2311048541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/43.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_macro_errs.1307381118 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 35929211094 ps |
| CPU time | 32.94 seconds |
| Started | Oct 09 08:51:12 PM UTC 24 |
| Finished | Oct 09 08:51:46 PM UTC 24 |
| Peak memory | 256740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307381118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.1307381118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/43.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_key_req.2798419507 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 852136247 ps |
| CPU time | 23.71 seconds |
| Started | Oct 09 08:51:12 PM UTC 24 |
| Finished | Oct 09 08:51:37 PM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798419507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.2798419507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_esc.413919393 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 328890676 ps |
| CPU time | 9.06 seconds |
| Started | Oct 09 08:51:06 PM UTC 24 |
| Finished | Oct 09 08:51:16 PM UTC 24 |
| Peak memory | 252416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413919393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.413919393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_req.842336606 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 765494014 ps |
| CPU time | 18.74 seconds |
| Started | Oct 09 08:51:06 PM UTC 24 |
| Finished | Oct 09 08:51:26 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842336606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.842336606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_regwen.3799915925 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 980182402 ps |
| CPU time | 6.03 seconds |
| Started | Oct 09 08:51:12 PM UTC 24 |
| Finished | Oct 09 08:51:19 PM UTC 24 |
| Peak memory | 252436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799915925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.3799915925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/43.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_smoke.2578918320 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 538053739 ps |
| CPU time | 8.28 seconds |
| Started | Oct 09 08:51:06 PM UTC 24 |
| Finished | Oct 09 08:51:15 PM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578918320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.2578918320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/43.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.2896687214 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 7079898188 ps |
| CPU time | 72.73 seconds |
| Started | Oct 09 08:51:12 PM UTC 24 |
| Finished | Oct 09 08:52:27 PM UTC 24 |
| Peak memory | 258636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896687214 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.2896687214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_test_access.673484103 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 1385184774 ps |
| CPU time | 16.48 seconds |
| Started | Oct 09 08:51:12 PM UTC 24 |
| Finished | Oct 09 08:51:30 PM UTC 24 |
| Peak memory | 252476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673484103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.673484103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/43.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_alert_test.337050676 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 232707538 ps |
| CPU time | 2.65 seconds |
| Started | Oct 09 08:51:22 PM UTC 24 |
| Finished | Oct 09 08:51:25 PM UTC 24 |
| Peak memory | 252244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337050676 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.337050676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/44.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_check_fail.4103093418 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 598322564 ps |
| CPU time | 13.49 seconds |
| Started | Oct 09 08:51:16 PM UTC 24 |
| Finished | Oct 09 08:51:30 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103093418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.4103093418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/44.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_errs.1790721021 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1016246054 ps |
| CPU time | 24.61 seconds |
| Started | Oct 09 08:51:16 PM UTC 24 |
| Finished | Oct 09 08:51:42 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790721021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.1790721021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/44.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_lock.2735453477 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 1982736562 ps |
| CPU time | 33.78 seconds |
| Started | Oct 09 08:51:16 PM UTC 24 |
| Finished | Oct 09 08:51:51 PM UTC 24 |
| Peak memory | 252524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735453477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.2735453477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/44.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_init_fail.3070049532 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 265934304 ps |
| CPU time | 4.42 seconds |
| Started | Oct 09 08:51:12 PM UTC 24 |
| Finished | Oct 09 08:51:18 PM UTC 24 |
| Peak memory | 252496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070049532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.3070049532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/44.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_macro_errs.1959063384 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 659171231 ps |
| CPU time | 9.12 seconds |
| Started | Oct 09 08:51:16 PM UTC 24 |
| Finished | Oct 09 08:51:26 PM UTC 24 |
| Peak memory | 252592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959063384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.1959063384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/44.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_key_req.4230226772 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 313248160 ps |
| CPU time | 13.57 seconds |
| Started | Oct 09 08:51:18 PM UTC 24 |
| Finished | Oct 09 08:51:32 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230226772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.4230226772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_esc.3815710705 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 194286832 ps |
| CPU time | 5.21 seconds |
| Started | Oct 09 08:51:15 PM UTC 24 |
| Finished | Oct 09 08:51:22 PM UTC 24 |
| Peak memory | 252352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815710705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.3815710705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_req.386178079 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 565502152 ps |
| CPU time | 14.73 seconds |
| Started | Oct 09 08:51:12 PM UTC 24 |
| Finished | Oct 09 08:51:28 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386178079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.386178079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_regwen.3916671382 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 306829405 ps |
| CPU time | 7.46 seconds |
| Started | Oct 09 08:51:18 PM UTC 24 |
| Finished | Oct 09 08:51:26 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916671382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.3916671382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/44.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_smoke.3570800252 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 392403226 ps |
| CPU time | 4.16 seconds |
| Started | Oct 09 08:51:12 PM UTC 24 |
| Finished | Oct 09 08:51:18 PM UTC 24 |
| Peak memory | 252256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570800252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.3570800252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/44.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.3161206945 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 4963304741 ps |
| CPU time | 65.44 seconds |
| Started | Oct 09 08:51:22 PM UTC 24 |
| Finished | Oct 09 08:52:29 PM UTC 24 |
| Peak memory | 258732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161206945 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.3161206945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_test_access.2273098076 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 1312193543 ps |
| CPU time | 9.44 seconds |
| Started | Oct 09 08:51:18 PM UTC 24 |
| Finished | Oct 09 08:51:28 PM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273098076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.2273098076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/44.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_alert_test.766766807 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 134498494 ps |
| CPU time | 2.19 seconds |
| Started | Oct 09 08:51:31 PM UTC 24 |
| Finished | Oct 09 08:51:35 PM UTC 24 |
| Peak memory | 252308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766766807 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.766766807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/45.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_check_fail.636887688 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 2666181775 ps |
| CPU time | 36.15 seconds |
| Started | Oct 09 08:51:31 PM UTC 24 |
| Finished | Oct 09 08:52:09 PM UTC 24 |
| Peak memory | 254688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636887688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.636887688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_errs.3258130988 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 14873712491 ps |
| CPU time | 27.31 seconds |
| Started | Oct 09 08:51:31 PM UTC 24 |
| Finished | Oct 09 08:52:00 PM UTC 24 |
| Peak memory | 256612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258130988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.3258130988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/45.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_lock.1348221496 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 4220436920 ps |
| CPU time | 17.98 seconds |
| Started | Oct 09 08:51:31 PM UTC 24 |
| Finished | Oct 09 08:51:50 PM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348221496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.1348221496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/45.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_init_fail.3898241398 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 243963028 ps |
| CPU time | 5.19 seconds |
| Started | Oct 09 08:51:22 PM UTC 24 |
| Finished | Oct 09 08:51:28 PM UTC 24 |
| Peak memory | 252332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898241398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.3898241398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/45.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_macro_errs.2321931997 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 2675593241 ps |
| CPU time | 50.87 seconds |
| Started | Oct 09 08:51:31 PM UTC 24 |
| Finished | Oct 09 08:52:24 PM UTC 24 |
| Peak memory | 258784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321931997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.2321931997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/45.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_key_req.1788709226 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 2010677788 ps |
| CPU time | 13.59 seconds |
| Started | Oct 09 08:51:31 PM UTC 24 |
| Finished | Oct 09 08:51:46 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788709226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.1788709226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_esc.1053902384 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 3430279960 ps |
| CPU time | 9.4 seconds |
| Started | Oct 09 08:51:31 PM UTC 24 |
| Finished | Oct 09 08:51:42 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053902384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.1053902384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_req.2527171970 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 3317994248 ps |
| CPU time | 25.72 seconds |
| Started | Oct 09 08:51:31 PM UTC 24 |
| Finished | Oct 09 08:51:58 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527171970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.2527171970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_regwen.574741602 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 220576824 ps |
| CPU time | 4.46 seconds |
| Started | Oct 09 08:51:31 PM UTC 24 |
| Finished | Oct 09 08:51:37 PM UTC 24 |
| Peak memory | 252248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574741602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.574741602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/45.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_smoke.3600159386 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 897621947 ps |
| CPU time | 8.86 seconds |
| Started | Oct 09 08:51:22 PM UTC 24 |
| Finished | Oct 09 08:51:32 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600159386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.3600159386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/45.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.4237066624 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 26428249265 ps |
| CPU time | 268.28 seconds |
| Started | Oct 09 08:51:31 PM UTC 24 |
| Finished | Oct 09 08:56:04 PM UTC 24 |
| Peak memory | 281420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237066624 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.4237066624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_test_access.3688450646 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 968414654 ps |
| CPU time | 10.33 seconds |
| Started | Oct 09 08:51:31 PM UTC 24 |
| Finished | Oct 09 08:51:43 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688450646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.3688450646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/45.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_alert_test.4265086336 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 154027522 ps |
| CPU time | 3.09 seconds |
| Started | Oct 09 08:51:41 PM UTC 24 |
| Finished | Oct 09 08:51:46 PM UTC 24 |
| Peak memory | 252240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265086336 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.4265086336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/46.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_check_fail.1565714490 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 547491140 ps |
| CPU time | 5.71 seconds |
| Started | Oct 09 08:51:41 PM UTC 24 |
| Finished | Oct 09 08:51:48 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565714490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.1565714490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_errs.2815997599 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 491531447 ps |
| CPU time | 10.15 seconds |
| Started | Oct 09 08:51:41 PM UTC 24 |
| Finished | Oct 09 08:51:52 PM UTC 24 |
| Peak memory | 252532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815997599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.2815997599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/46.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_lock.2768654193 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 566085539 ps |
| CPU time | 10.5 seconds |
| Started | Oct 09 08:51:41 PM UTC 24 |
| Finished | Oct 09 08:51:53 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768654193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.2768654193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/46.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_init_fail.2631274593 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 225884880 ps |
| CPU time | 4 seconds |
| Started | Oct 09 08:51:31 PM UTC 24 |
| Finished | Oct 09 08:51:37 PM UTC 24 |
| Peak memory | 252496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631274593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.2631274593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/46.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_macro_errs.3402805360 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 6079338030 ps |
| CPU time | 17.14 seconds |
| Started | Oct 09 08:51:41 PM UTC 24 |
| Finished | Oct 09 08:52:00 PM UTC 24 |
| Peak memory | 254620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402805360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.3402805360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/46.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_key_req.2978776386 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 9087567935 ps |
| CPU time | 26.63 seconds |
| Started | Oct 09 08:51:41 PM UTC 24 |
| Finished | Oct 09 08:52:09 PM UTC 24 |
| Peak memory | 254540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978776386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.2978776386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_esc.4037552757 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 10590338352 ps |
| CPU time | 28.77 seconds |
| Started | Oct 09 08:51:31 PM UTC 24 |
| Finished | Oct 09 08:52:02 PM UTC 24 |
| Peak memory | 252436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037552757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.4037552757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_req.1198691808 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 12688230887 ps |
| CPU time | 34.57 seconds |
| Started | Oct 09 08:51:31 PM UTC 24 |
| Finished | Oct 09 08:52:08 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198691808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.1198691808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_regwen.1040375366 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 157413772 ps |
| CPU time | 6.41 seconds |
| Started | Oct 09 08:51:41 PM UTC 24 |
| Finished | Oct 09 08:51:49 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040375366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.1040375366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/46.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_smoke.594323905 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 742157961 ps |
| CPU time | 5.38 seconds |
| Started | Oct 09 08:51:31 PM UTC 24 |
| Finished | Oct 09 08:51:38 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594323905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.594323905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/46.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all.806671845 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 1674843830 ps |
| CPU time | 27.46 seconds |
| Started | Oct 09 08:51:41 PM UTC 24 |
| Finished | Oct 09 08:52:10 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806671845 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.806671845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_test_access.2478135196 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 1624304302 ps |
| CPU time | 12.31 seconds |
| Started | Oct 09 08:51:41 PM UTC 24 |
| Finished | Oct 09 08:51:55 PM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478135196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.2478135196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/46.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_alert_test.601995164 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 902696208 ps |
| CPU time | 4.49 seconds |
| Started | Oct 09 08:51:47 PM UTC 24 |
| Finished | Oct 09 08:51:53 PM UTC 24 |
| Peak memory | 252292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601995164 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.601995164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/47.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_check_fail.1104949600 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1725750281 ps |
| CPU time | 22.31 seconds |
| Started | Oct 09 08:51:41 PM UTC 24 |
| Finished | Oct 09 08:52:06 PM UTC 24 |
| Peak memory | 252612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104949600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.1104949600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/47.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_errs.3844655992 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 2874372401 ps |
| CPU time | 23.84 seconds |
| Started | Oct 09 08:51:41 PM UTC 24 |
| Finished | Oct 09 08:52:07 PM UTC 24 |
| Peak memory | 252528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844655992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.3844655992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/47.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_lock.787641129 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 1826860378 ps |
| CPU time | 16.57 seconds |
| Started | Oct 09 08:51:41 PM UTC 24 |
| Finished | Oct 09 08:52:00 PM UTC 24 |
| Peak memory | 252532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787641129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.787641129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/47.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_init_fail.2493394863 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 1532283073 ps |
| CPU time | 4.37 seconds |
| Started | Oct 09 08:51:41 PM UTC 24 |
| Finished | Oct 09 08:51:47 PM UTC 24 |
| Peak memory | 252404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493394863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.2493394863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/47.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_macro_errs.363539028 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 903883347 ps |
| CPU time | 25.45 seconds |
| Started | Oct 09 08:51:41 PM UTC 24 |
| Finished | Oct 09 08:52:09 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363539028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.363539028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/47.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_key_req.1821386006 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 1860480521 ps |
| CPU time | 17.98 seconds |
| Started | Oct 09 08:51:47 PM UTC 24 |
| Finished | Oct 09 08:52:06 PM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821386006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.1821386006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_esc.1705488560 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 537369373 ps |
| CPU time | 8.89 seconds |
| Started | Oct 09 08:51:41 PM UTC 24 |
| Finished | Oct 09 08:51:52 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705488560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.1705488560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_req.4211381918 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 163605796 ps |
| CPU time | 3.32 seconds |
| Started | Oct 09 08:51:41 PM UTC 24 |
| Finished | Oct 09 08:51:46 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211381918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.4211381918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_regwen.2245183490 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 321999885 ps |
| CPU time | 3.97 seconds |
| Started | Oct 09 08:51:47 PM UTC 24 |
| Finished | Oct 09 08:51:52 PM UTC 24 |
| Peak memory | 252356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245183490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.2245183490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/47.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_smoke.2445537544 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 390546190 ps |
| CPU time | 10.58 seconds |
| Started | Oct 09 08:51:41 PM UTC 24 |
| Finished | Oct 09 08:51:53 PM UTC 24 |
| Peak memory | 252524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445537544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.2445537544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/47.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all.3660207506 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 11053085813 ps |
| CPU time | 54.65 seconds |
| Started | Oct 09 08:51:47 PM UTC 24 |
| Finished | Oct 09 08:52:43 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660207506 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.3660207506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.1687598803 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 3642154468 ps |
| CPU time | 79.29 seconds |
| Started | Oct 09 08:51:47 PM UTC 24 |
| Finished | Oct 09 08:53:08 PM UTC 24 |
| Peak memory | 268956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1687598803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 47.otp_ctrl_stress_all_with_rand_reset.1687598803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_test_access.2974206029 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 1752368137 ps |
| CPU time | 13.57 seconds |
| Started | Oct 09 08:51:47 PM UTC 24 |
| Finished | Oct 09 08:52:02 PM UTC 24 |
| Peak memory | 252524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974206029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.2974206029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/47.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_alert_test.1763823041 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 186924655 ps |
| CPU time | 2.04 seconds |
| Started | Oct 09 08:51:56 PM UTC 24 |
| Finished | Oct 09 08:51:59 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763823041 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.1763823041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/48.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_check_fail.3875995600 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 330124855 ps |
| CPU time | 8.08 seconds |
| Started | Oct 09 08:51:51 PM UTC 24 |
| Finished | Oct 09 08:52:01 PM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875995600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.3875995600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/48.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_errs.3816470984 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 314240981 ps |
| CPU time | 16.67 seconds |
| Started | Oct 09 08:51:51 PM UTC 24 |
| Finished | Oct 09 08:52:10 PM UTC 24 |
| Peak memory | 252392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816470984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.3816470984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/48.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_lock.2590307952 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 246071990 ps |
| CPU time | 6.5 seconds |
| Started | Oct 09 08:51:51 PM UTC 24 |
| Finished | Oct 09 08:51:59 PM UTC 24 |
| Peak memory | 252160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590307952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.2590307952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/48.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_init_fail.2023508415 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 142439972 ps |
| CPU time | 6.65 seconds |
| Started | Oct 09 08:51:47 PM UTC 24 |
| Finished | Oct 09 08:51:55 PM UTC 24 |
| Peak memory | 252496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023508415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.2023508415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/48.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_macro_errs.2775120036 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 13961777038 ps |
| CPU time | 35.57 seconds |
| Started | Oct 09 08:51:51 PM UTC 24 |
| Finished | Oct 09 08:52:29 PM UTC 24 |
| Peak memory | 256576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775120036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.2775120036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/48.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_key_req.3797417293 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 519028496 ps |
| CPU time | 12.09 seconds |
| Started | Oct 09 08:51:51 PM UTC 24 |
| Finished | Oct 09 08:52:05 PM UTC 24 |
| Peak memory | 252116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797417293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.3797417293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_esc.2394381068 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 2299613163 ps |
| CPU time | 24.08 seconds |
| Started | Oct 09 08:51:51 PM UTC 24 |
| Finished | Oct 09 08:52:17 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394381068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.2394381068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_req.3624228278 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 228664213 ps |
| CPU time | 6.5 seconds |
| Started | Oct 09 08:51:47 PM UTC 24 |
| Finished | Oct 09 08:51:55 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624228278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.3624228278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_regwen.3557711958 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 610354003 ps |
| CPU time | 13.2 seconds |
| Started | Oct 09 08:51:55 PM UTC 24 |
| Finished | Oct 09 08:52:10 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557711958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.3557711958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/48.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_smoke.3637089125 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 378850900 ps |
| CPU time | 10.42 seconds |
| Started | Oct 09 08:51:47 PM UTC 24 |
| Finished | Oct 09 08:51:59 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637089125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.3637089125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/48.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.3524298131 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 12545957675 ps |
| CPU time | 129.81 seconds |
| Started | Oct 09 08:51:56 PM UTC 24 |
| Finished | Oct 09 08:54:08 PM UTC 24 |
| Peak memory | 258788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524298131 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.3524298131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_test_access.1815812839 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2108996446 ps |
| CPU time | 18.49 seconds |
| Started | Oct 09 08:51:55 PM UTC 24 |
| Finished | Oct 09 08:52:15 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815812839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.1815812839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/48.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_alert_test.2591718409 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 94894710 ps |
| CPU time | 1.93 seconds |
| Started | Oct 09 08:52:02 PM UTC 24 |
| Finished | Oct 09 08:52:05 PM UTC 24 |
| Peak memory | 250840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591718409 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.2591718409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/49.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_check_fail.565373110 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 709974210 ps |
| CPU time | 4.69 seconds |
| Started | Oct 09 08:51:58 PM UTC 24 |
| Finished | Oct 09 08:52:04 PM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565373110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.565373110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/49.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_errs.1977989525 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 786980659 ps |
| CPU time | 22.25 seconds |
| Started | Oct 09 08:51:58 PM UTC 24 |
| Finished | Oct 09 08:52:22 PM UTC 24 |
| Peak memory | 252392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977989525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.1977989525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/49.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_lock.2950099922 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 324766548 ps |
| CPU time | 4.39 seconds |
| Started | Oct 09 08:51:58 PM UTC 24 |
| Finished | Oct 09 08:52:03 PM UTC 24 |
| Peak memory | 252464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950099922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.2950099922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/49.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_init_fail.310241893 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 101377871 ps |
| CPU time | 5.36 seconds |
| Started | Oct 09 08:51:56 PM UTC 24 |
| Finished | Oct 09 08:52:02 PM UTC 24 |
| Peak memory | 252416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310241893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.310241893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/49.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_macro_errs.3536408223 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 579416988 ps |
| CPU time | 13.63 seconds |
| Started | Oct 09 08:52:02 PM UTC 24 |
| Finished | Oct 09 08:52:17 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536408223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.3536408223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/49.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_key_req.2527122067 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 350698203 ps |
| CPU time | 8.28 seconds |
| Started | Oct 09 08:52:02 PM UTC 24 |
| Finished | Oct 09 08:52:12 PM UTC 24 |
| Peak memory | 252416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527122067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.2527122067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_req.2366716593 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 804158631 ps |
| CPU time | 22.15 seconds |
| Started | Oct 09 08:51:56 PM UTC 24 |
| Finished | Oct 09 08:52:19 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366716593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.2366716593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_regwen.128211109 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 144263835 ps |
| CPU time | 5.39 seconds |
| Started | Oct 09 08:52:02 PM UTC 24 |
| Finished | Oct 09 08:52:09 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128211109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.128211109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/49.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_smoke.4264459056 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 657867805 ps |
| CPU time | 10.14 seconds |
| Started | Oct 09 08:51:56 PM UTC 24 |
| Finished | Oct 09 08:52:07 PM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264459056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.4264459056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/49.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all.390157599 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 5719471029 ps |
| CPU time | 131.44 seconds |
| Started | Oct 09 08:52:02 PM UTC 24 |
| Finished | Oct 09 08:54:16 PM UTC 24 |
| Peak memory | 268948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390157599 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.390157599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.1679021164 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 2385583335 ps |
| CPU time | 71.21 seconds |
| Started | Oct 09 08:52:02 PM UTC 24 |
| Finished | Oct 09 08:53:15 PM UTC 24 |
| Peak memory | 268996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1679021164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 49.otp_ctrl_stress_all_with_rand_reset.1679021164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_test_access.3624001339 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 478775979 ps |
| CPU time | 12.31 seconds |
| Started | Oct 09 08:52:02 PM UTC 24 |
| Finished | Oct 09 08:52:16 PM UTC 24 |
| Peak memory | 252492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624001339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.3624001339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/49.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_alert_test.131369416 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 54049496 ps |
| CPU time | 2.75 seconds |
| Started | Oct 09 08:45:23 PM UTC 24 |
| Finished | Oct 09 08:45:27 PM UTC 24 |
| Peak memory | 252288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131369416 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.131369416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_background_chks.2926466924 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 13808935087 ps |
| CPU time | 33.36 seconds |
| Started | Oct 09 08:45:11 PM UTC 24 |
| Finished | Oct 09 08:45:46 PM UTC 24 |
| Peak memory | 254436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926466924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.2926466924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_lock.3531743916 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1446545623 ps |
| CPU time | 27.68 seconds |
| Started | Oct 09 08:45:14 PM UTC 24 |
| Finished | Oct 09 08:45:43 PM UTC 24 |
| Peak memory | 252524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531743916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.3531743916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_init_fail.751191360 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 114702564 ps |
| CPU time | 5.07 seconds |
| Started | Oct 09 08:45:08 PM UTC 24 |
| Finished | Oct 09 08:45:14 PM UTC 24 |
| Peak memory | 252432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751191360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.751191360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_macro_errs.712303445 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 359641840 ps |
| CPU time | 8.35 seconds |
| Started | Oct 09 08:45:17 PM UTC 24 |
| Finished | Oct 09 08:45:27 PM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712303445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.712303445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_key_req.2300184745 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 190961103 ps |
| CPU time | 6.73 seconds |
| Started | Oct 09 08:45:19 PM UTC 24 |
| Finished | Oct 09 08:45:27 PM UTC 24 |
| Peak memory | 252428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300184745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.2300184745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_esc.3359909949 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1986052368 ps |
| CPU time | 17.55 seconds |
| Started | Oct 09 08:45:13 PM UTC 24 |
| Finished | Oct 09 08:45:32 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359909949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.3359909949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_req.3104898054 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 862564783 ps |
| CPU time | 23.49 seconds |
| Started | Oct 09 08:45:12 PM UTC 24 |
| Finished | Oct 09 08:45:36 PM UTC 24 |
| Peak memory | 252044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104898054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.3104898054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_regwen.1274316288 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 493529414 ps |
| CPU time | 8.16 seconds |
| Started | Oct 09 08:45:19 PM UTC 24 |
| Finished | Oct 09 08:45:28 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274316288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.1274316288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_smoke.1137976292 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 522955701 ps |
| CPU time | 8.26 seconds |
| Started | Oct 09 08:45:08 PM UTC 24 |
| Finished | Oct 09 08:45:17 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137976292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.1137976292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all.365245893 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 13193462481 ps |
| CPU time | 260.16 seconds |
| Started | Oct 09 08:45:22 PM UTC 24 |
| Finished | Oct 09 08:49:46 PM UTC 24 |
| Peak memory | 258768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365245893 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.365245893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_test_access.1328729902 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 558605105 ps |
| CPU time | 15.6 seconds |
| Started | Oct 09 08:45:20 PM UTC 24 |
| Finished | Oct 09 08:45:37 PM UTC 24 |
| Peak memory | 252524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328729902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.1328729902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/5.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_init_fail.1385030460 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 2441913696 ps |
| CPU time | 5.56 seconds |
| Started | Oct 09 08:52:02 PM UTC 24 |
| Finished | Oct 09 08:52:09 PM UTC 24 |
| Peak memory | 252148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385030460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.1385030460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/50.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_parallel_lc_esc.2095484871 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 454645815 ps |
| CPU time | 8.88 seconds |
| Started | Oct 09 08:52:02 PM UTC 24 |
| Finished | Oct 09 08:52:13 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095484871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.2095484871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/50.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_init_fail.1738986166 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1826375167 ps |
| CPU time | 7.59 seconds |
| Started | Oct 09 08:52:09 PM UTC 24 |
| Finished | Oct 09 08:52:18 PM UTC 24 |
| Peak memory | 252460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738986166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.1738986166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/51.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_parallel_lc_esc.4108148050 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 1946151884 ps |
| CPU time | 6.7 seconds |
| Started | Oct 09 08:52:09 PM UTC 24 |
| Finished | Oct 09 08:52:17 PM UTC 24 |
| Peak memory | 252436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108148050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.4108148050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/51.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_init_fail.3783710420 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 406660346 ps |
| CPU time | 4.99 seconds |
| Started | Oct 09 08:52:09 PM UTC 24 |
| Finished | Oct 09 08:52:16 PM UTC 24 |
| Peak memory | 252496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783710420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.3783710420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/52.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_parallel_lc_esc.729249062 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 117355435 ps |
| CPU time | 6.51 seconds |
| Started | Oct 09 08:52:09 PM UTC 24 |
| Finished | Oct 09 08:52:17 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729249062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.729249062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/52.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.250827525 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 2687859975 ps |
| CPU time | 99.73 seconds |
| Started | Oct 09 08:52:09 PM UTC 24 |
| Finished | Oct 09 08:53:51 PM UTC 24 |
| Peak memory | 269092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=250827525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.250827525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_parallel_lc_esc.3126523325 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 314792287 ps |
| CPU time | 7.07 seconds |
| Started | Oct 09 08:52:09 PM UTC 24 |
| Finished | Oct 09 08:52:18 PM UTC 24 |
| Peak memory | 252300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126523325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.3126523325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/53.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.717045162 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 12567185827 ps |
| CPU time | 115.45 seconds |
| Started | Oct 09 08:52:09 PM UTC 24 |
| Finished | Oct 09 08:54:08 PM UTC 24 |
| Peak memory | 269032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=717045162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.717045162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_init_fail.320185029 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 416669956 ps |
| CPU time | 4.58 seconds |
| Started | Oct 09 08:52:09 PM UTC 24 |
| Finished | Oct 09 08:52:16 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320185029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.320185029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/54.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_parallel_lc_esc.3736060989 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 162238283 ps |
| CPU time | 4.17 seconds |
| Started | Oct 09 08:52:09 PM UTC 24 |
| Finished | Oct 09 08:52:15 PM UTC 24 |
| Peak memory | 252228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736060989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.3736060989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/54.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.3217877199 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 1217165147 ps |
| CPU time | 24.53 seconds |
| Started | Oct 09 08:52:09 PM UTC 24 |
| Finished | Oct 09 08:52:36 PM UTC 24 |
| Peak memory | 258724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3217877199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 54.otp_ctrl_stress_all_with_rand_reset.3217877199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/54.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_init_fail.1606205749 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 285232726 ps |
| CPU time | 6.01 seconds |
| Started | Oct 09 08:52:14 PM UTC 24 |
| Finished | Oct 09 08:52:22 PM UTC 24 |
| Peak memory | 252496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606205749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.1606205749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/55.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_parallel_lc_esc.2568475048 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 748598585 ps |
| CPU time | 9.96 seconds |
| Started | Oct 09 08:52:14 PM UTC 24 |
| Finished | Oct 09 08:52:26 PM UTC 24 |
| Peak memory | 252356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568475048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.2568475048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/55.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.3987996622 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 17538463535 ps |
| CPU time | 151.88 seconds |
| Started | Oct 09 08:52:14 PM UTC 24 |
| Finished | Oct 09 08:54:49 PM UTC 24 |
| Peak memory | 275076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3987996622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 55.otp_ctrl_stress_all_with_rand_reset.3987996622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/55.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_init_fail.3160248612 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 267012835 ps |
| CPU time | 5.05 seconds |
| Started | Oct 09 08:52:14 PM UTC 24 |
| Finished | Oct 09 08:52:21 PM UTC 24 |
| Peak memory | 252416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160248612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.3160248612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/56.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_init_fail.94959674 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 252169673 ps |
| CPU time | 4.2 seconds |
| Started | Oct 09 08:52:15 PM UTC 24 |
| Finished | Oct 09 08:52:20 PM UTC 24 |
| Peak memory | 252320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94959674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.94959674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/57.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_parallel_lc_esc.3287564635 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 1820374489 ps |
| CPU time | 7.45 seconds |
| Started | Oct 09 08:52:15 PM UTC 24 |
| Finished | Oct 09 08:52:23 PM UTC 24 |
| Peak memory | 252308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287564635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.3287564635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/57.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_init_fail.244276824 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 486275602 ps |
| CPU time | 3.78 seconds |
| Started | Oct 09 08:52:15 PM UTC 24 |
| Finished | Oct 09 08:52:20 PM UTC 24 |
| Peak memory | 252412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244276824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.244276824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/58.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_parallel_lc_esc.4196306949 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2612611649 ps |
| CPU time | 19.61 seconds |
| Started | Oct 09 08:52:15 PM UTC 24 |
| Finished | Oct 09 08:52:36 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196306949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.4196306949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/58.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.2057627614 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 42564123719 ps |
| CPU time | 209 seconds |
| Started | Oct 09 08:52:15 PM UTC 24 |
| Finished | Oct 09 08:55:47 PM UTC 24 |
| Peak memory | 289572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2057627614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 58.otp_ctrl_stress_all_with_rand_reset.2057627614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_init_fail.3437949048 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 257428771 ps |
| CPU time | 4.36 seconds |
| Started | Oct 09 08:52:15 PM UTC 24 |
| Finished | Oct 09 08:52:21 PM UTC 24 |
| Peak memory | 252484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437949048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.3437949048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/59.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_parallel_lc_esc.1964864887 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 792118405 ps |
| CPU time | 11.95 seconds |
| Started | Oct 09 08:52:18 PM UTC 24 |
| Finished | Oct 09 08:52:31 PM UTC 24 |
| Peak memory | 252348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964864887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.1964864887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_alert_test.3584273745 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 55828599 ps |
| CPU time | 2.81 seconds |
| Started | Oct 09 08:45:33 PM UTC 24 |
| Finished | Oct 09 08:45:37 PM UTC 24 |
| Peak memory | 252396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584273745 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.3584273745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_background_chks.4284728871 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1521101060 ps |
| CPU time | 33.53 seconds |
| Started | Oct 09 08:45:26 PM UTC 24 |
| Finished | Oct 09 08:46:01 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284728871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.4284728871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_check_fail.3826996080 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 17876957899 ps |
| CPU time | 43.6 seconds |
| Started | Oct 09 08:45:28 PM UTC 24 |
| Finished | Oct 09 08:46:13 PM UTC 24 |
| Peak memory | 252620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826996080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.3826996080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_errs.1093537945 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 1073733249 ps |
| CPU time | 19.73 seconds |
| Started | Oct 09 08:45:28 PM UTC 24 |
| Finished | Oct 09 08:45:49 PM UTC 24 |
| Peak memory | 252404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093537945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.1093537945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_lock.221978468 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 509905491 ps |
| CPU time | 12.38 seconds |
| Started | Oct 09 08:45:28 PM UTC 24 |
| Finished | Oct 09 08:45:41 PM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221978468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.221978468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_key_req.1862140614 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 845816719 ps |
| CPU time | 20.78 seconds |
| Started | Oct 09 08:45:29 PM UTC 24 |
| Finished | Oct 09 08:45:52 PM UTC 24 |
| Peak memory | 252556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862140614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.1862140614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_esc.2441954461 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 829438979 ps |
| CPU time | 13.35 seconds |
| Started | Oct 09 08:45:28 PM UTC 24 |
| Finished | Oct 09 08:45:42 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441954461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.2441954461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_regwen.1599257307 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 838541091 ps |
| CPU time | 14.86 seconds |
| Started | Oct 09 08:45:33 PM UTC 24 |
| Finished | Oct 09 08:45:49 PM UTC 24 |
| Peak memory | 252248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599257307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.1599257307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_smoke.598526357 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 829066720 ps |
| CPU time | 6.75 seconds |
| Started | Oct 09 08:45:23 PM UTC 24 |
| Finished | Oct 09 08:45:31 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598526357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.598526357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all.3241746238 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1041668177 ps |
| CPU time | 26.99 seconds |
| Started | Oct 09 08:45:33 PM UTC 24 |
| Finished | Oct 09 08:46:01 PM UTC 24 |
| Peak memory | 254440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241746238 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.3241746238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_test_access.1426376900 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 166863286 ps |
| CPU time | 7.25 seconds |
| Started | Oct 09 08:45:33 PM UTC 24 |
| Finished | Oct 09 08:45:41 PM UTC 24 |
| Peak memory | 252364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426376900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.1426376900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/6.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_init_fail.1733028351 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 306124380 ps |
| CPU time | 4.31 seconds |
| Started | Oct 09 08:52:18 PM UTC 24 |
| Finished | Oct 09 08:52:24 PM UTC 24 |
| Peak memory | 252352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733028351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.1733028351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/60.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_parallel_lc_esc.208957792 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 93709500 ps |
| CPU time | 5.36 seconds |
| Started | Oct 09 08:52:18 PM UTC 24 |
| Finished | Oct 09 08:52:25 PM UTC 24 |
| Peak memory | 252292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208957792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.208957792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/60.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_init_fail.2321638035 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 154598141 ps |
| CPU time | 3.55 seconds |
| Started | Oct 09 08:52:18 PM UTC 24 |
| Finished | Oct 09 08:52:23 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321638035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.2321638035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/61.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_parallel_lc_esc.2810552048 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 740733603 ps |
| CPU time | 21.96 seconds |
| Started | Oct 09 08:52:24 PM UTC 24 |
| Finished | Oct 09 08:52:48 PM UTC 24 |
| Peak memory | 252056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810552048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.2810552048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/61.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_init_fail.946361983 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 119809175 ps |
| CPU time | 4.43 seconds |
| Started | Oct 09 08:52:24 PM UTC 24 |
| Finished | Oct 09 08:52:30 PM UTC 24 |
| Peak memory | 252560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946361983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.946361983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/62.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_parallel_lc_esc.3245536481 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 280843461 ps |
| CPU time | 3.91 seconds |
| Started | Oct 09 08:52:24 PM UTC 24 |
| Finished | Oct 09 08:52:29 PM UTC 24 |
| Peak memory | 252352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245536481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.3245536481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/62.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.395338398 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 15971683357 ps |
| CPU time | 124.42 seconds |
| Started | Oct 09 08:52:24 PM UTC 24 |
| Finished | Oct 09 08:54:31 PM UTC 24 |
| Peak memory | 269160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=395338398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.395338398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_init_fail.4156850838 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 481094816 ps |
| CPU time | 3.73 seconds |
| Started | Oct 09 08:52:24 PM UTC 24 |
| Finished | Oct 09 08:52:30 PM UTC 24 |
| Peak memory | 252484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156850838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.4156850838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/63.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_parallel_lc_esc.1075633702 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 305400707 ps |
| CPU time | 9.83 seconds |
| Started | Oct 09 08:52:24 PM UTC 24 |
| Finished | Oct 09 08:52:36 PM UTC 24 |
| Peak memory | 252312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075633702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.1075633702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/63.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.2054020037 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 4039043604 ps |
| CPU time | 136.77 seconds |
| Started | Oct 09 08:52:24 PM UTC 24 |
| Finished | Oct 09 08:54:44 PM UTC 24 |
| Peak memory | 269072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2054020037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 63.otp_ctrl_stress_all_with_rand_reset.2054020037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_init_fail.1428064842 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 299494525 ps |
| CPU time | 6.11 seconds |
| Started | Oct 09 08:52:25 PM UTC 24 |
| Finished | Oct 09 08:52:32 PM UTC 24 |
| Peak memory | 252432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428064842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.1428064842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/64.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.908891689 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 2183173630 ps |
| CPU time | 27.79 seconds |
| Started | Oct 09 08:52:25 PM UTC 24 |
| Finished | Oct 09 08:52:54 PM UTC 24 |
| Peak memory | 258696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=908891689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.908891689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_init_fail.3352865662 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 605990133 ps |
| CPU time | 4.69 seconds |
| Started | Oct 09 08:52:25 PM UTC 24 |
| Finished | Oct 09 08:52:31 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352865662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.3352865662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/65.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_parallel_lc_esc.3442745002 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1191915113 ps |
| CPU time | 19.82 seconds |
| Started | Oct 09 08:52:25 PM UTC 24 |
| Finished | Oct 09 08:52:46 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442745002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.3442745002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/65.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.1781865638 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 6119049316 ps |
| CPU time | 81.02 seconds |
| Started | Oct 09 08:52:28 PM UTC 24 |
| Finished | Oct 09 08:53:51 PM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1781865638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 65.otp_ctrl_stress_all_with_rand_reset.1781865638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_init_fail.1327980372 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 2335992380 ps |
| CPU time | 8.8 seconds |
| Started | Oct 09 08:52:28 PM UTC 24 |
| Finished | Oct 09 08:52:38 PM UTC 24 |
| Peak memory | 252396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327980372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.1327980372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/66.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_parallel_lc_esc.3672852337 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 155854603 ps |
| CPU time | 4.18 seconds |
| Started | Oct 09 08:52:28 PM UTC 24 |
| Finished | Oct 09 08:52:33 PM UTC 24 |
| Peak memory | 252304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672852337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.3672852337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/66.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.869478405 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 19805763713 ps |
| CPU time | 110.56 seconds |
| Started | Oct 09 08:52:28 PM UTC 24 |
| Finished | Oct 09 08:54:21 PM UTC 24 |
| Peak memory | 271060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=869478405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.869478405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_parallel_lc_esc.1315194285 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 887884324 ps |
| CPU time | 10.78 seconds |
| Started | Oct 09 08:52:28 PM UTC 24 |
| Finished | Oct 09 08:52:41 PM UTC 24 |
| Peak memory | 252268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315194285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.1315194285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/67.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_init_fail.712658736 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 168387757 ps |
| CPU time | 3.89 seconds |
| Started | Oct 09 08:52:28 PM UTC 24 |
| Finished | Oct 09 08:52:34 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712658736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.712658736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/68.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_parallel_lc_esc.192242560 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 190892981 ps |
| CPU time | 7.49 seconds |
| Started | Oct 09 08:52:34 PM UTC 24 |
| Finished | Oct 09 08:52:43 PM UTC 24 |
| Peak memory | 252352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192242560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.192242560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/68.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_init_fail.412075715 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 303877357 ps |
| CPU time | 4.1 seconds |
| Started | Oct 09 08:52:34 PM UTC 24 |
| Finished | Oct 09 08:52:40 PM UTC 24 |
| Peak memory | 252348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412075715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.412075715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/69.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_parallel_lc_esc.2033246141 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 8249477217 ps |
| CPU time | 22.73 seconds |
| Started | Oct 09 08:52:34 PM UTC 24 |
| Finished | Oct 09 08:52:58 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033246141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.2033246141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/69.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_alert_test.3503447974 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 177319629 ps |
| CPU time | 3.34 seconds |
| Started | Oct 09 08:45:45 PM UTC 24 |
| Finished | Oct 09 08:45:49 PM UTC 24 |
| Peak memory | 252312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503447974 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.3503447974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_background_chks.254985834 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 942423918 ps |
| CPU time | 18.68 seconds |
| Started | Oct 09 08:45:37 PM UTC 24 |
| Finished | Oct 09 08:45:57 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254985834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.254985834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_errs.317951065 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 666156213 ps |
| CPU time | 21.44 seconds |
| Started | Oct 09 08:45:39 PM UTC 24 |
| Finished | Oct 09 08:46:02 PM UTC 24 |
| Peak memory | 252320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317951065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.317951065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_lock.1745234993 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 12181838525 ps |
| CPU time | 26.14 seconds |
| Started | Oct 09 08:45:39 PM UTC 24 |
| Finished | Oct 09 08:46:06 PM UTC 24 |
| Peak memory | 254704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745234993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.1745234993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_init_fail.1523101147 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 207043360 ps |
| CPU time | 5.77 seconds |
| Started | Oct 09 08:45:34 PM UTC 24 |
| Finished | Oct 09 08:45:41 PM UTC 24 |
| Peak memory | 252400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523101147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.1523101147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_macro_errs.1204022064 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2794907532 ps |
| CPU time | 18.79 seconds |
| Started | Oct 09 08:45:42 PM UTC 24 |
| Finished | Oct 09 08:46:03 PM UTC 24 |
| Peak memory | 256668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204022064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.1204022064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_key_req.3713938889 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1375043815 ps |
| CPU time | 10.15 seconds |
| Started | Oct 09 08:45:42 PM UTC 24 |
| Finished | Oct 09 08:45:54 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713938889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.3713938889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_esc.3544373546 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 2713104688 ps |
| CPU time | 6.42 seconds |
| Started | Oct 09 08:45:39 PM UTC 24 |
| Finished | Oct 09 08:45:47 PM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544373546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.3544373546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_smoke.1916134852 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 619235347 ps |
| CPU time | 7.38 seconds |
| Started | Oct 09 08:45:34 PM UTC 24 |
| Finished | Oct 09 08:45:43 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916134852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.1916134852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.880908314 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 127885601735 ps |
| CPU time | 166.71 seconds |
| Started | Oct 09 08:45:45 PM UTC 24 |
| Finished | Oct 09 08:48:35 PM UTC 24 |
| Peak memory | 273056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880908314 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.880908314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_test_access.2946755527 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 645441555 ps |
| CPU time | 15.37 seconds |
| Started | Oct 09 08:45:43 PM UTC 24 |
| Finished | Oct 09 08:45:59 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946755527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2946755527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/7.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_init_fail.414874311 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1565934439 ps |
| CPU time | 4.67 seconds |
| Started | Oct 09 08:52:35 PM UTC 24 |
| Finished | Oct 09 08:52:41 PM UTC 24 |
| Peak memory | 252424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414874311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.414874311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/71.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_parallel_lc_esc.4087235271 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 311487848 ps |
| CPU time | 8.37 seconds |
| Started | Oct 09 08:52:35 PM UTC 24 |
| Finished | Oct 09 08:52:44 PM UTC 24 |
| Peak memory | 252236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087235271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.4087235271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/71.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.3713945937 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 5231392301 ps |
| CPU time | 66.05 seconds |
| Started | Oct 09 08:52:35 PM UTC 24 |
| Finished | Oct 09 08:53:43 PM UTC 24 |
| Peak memory | 258640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3713945937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 71.otp_ctrl_stress_all_with_rand_reset.3713945937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_init_fail.1287291630 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 402465077 ps |
| CPU time | 4.51 seconds |
| Started | Oct 09 08:52:35 PM UTC 24 |
| Finished | Oct 09 08:52:41 PM UTC 24 |
| Peak memory | 252472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287291630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.1287291630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/72.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_parallel_lc_esc.1491462841 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 275970618 ps |
| CPU time | 13.07 seconds |
| Started | Oct 09 08:52:35 PM UTC 24 |
| Finished | Oct 09 08:52:49 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491462841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.1491462841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/72.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_init_fail.2838675684 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 176518633 ps |
| CPU time | 6.84 seconds |
| Started | Oct 09 08:52:42 PM UTC 24 |
| Finished | Oct 09 08:52:50 PM UTC 24 |
| Peak memory | 252396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838675684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.2838675684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/73.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_parallel_lc_esc.895188097 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 1156878197 ps |
| CPU time | 21.36 seconds |
| Started | Oct 09 08:52:42 PM UTC 24 |
| Finished | Oct 09 08:53:05 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895188097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.895188097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/73.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.3311839241 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 17005128062 ps |
| CPU time | 171.85 seconds |
| Started | Oct 09 08:52:42 PM UTC 24 |
| Finished | Oct 09 08:55:37 PM UTC 24 |
| Peak memory | 268968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3311839241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 73.otp_ctrl_stress_all_with_rand_reset.3311839241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_init_fail.2559695527 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 171262757 ps |
| CPU time | 4.13 seconds |
| Started | Oct 09 08:52:42 PM UTC 24 |
| Finished | Oct 09 08:52:48 PM UTC 24 |
| Peak memory | 252416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559695527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.2559695527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/74.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_parallel_lc_esc.3585706140 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 161203010 ps |
| CPU time | 8.18 seconds |
| Started | Oct 09 08:52:42 PM UTC 24 |
| Finished | Oct 09 08:52:52 PM UTC 24 |
| Peak memory | 252344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585706140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.3585706140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/74.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.2044442900 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 17628408996 ps |
| CPU time | 154.51 seconds |
| Started | Oct 09 08:52:42 PM UTC 24 |
| Finished | Oct 09 08:55:20 PM UTC 24 |
| Peak memory | 270996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2044442900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 74.otp_ctrl_stress_all_with_rand_reset.2044442900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/74.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_init_fail.4153310807 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 360027444 ps |
| CPU time | 4.46 seconds |
| Started | Oct 09 08:52:43 PM UTC 24 |
| Finished | Oct 09 08:52:48 PM UTC 24 |
| Peak memory | 252464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153310807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.4153310807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/75.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_parallel_lc_esc.3816206439 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 292706880 ps |
| CPU time | 4.21 seconds |
| Started | Oct 09 08:52:43 PM UTC 24 |
| Finished | Oct 09 08:52:48 PM UTC 24 |
| Peak memory | 252352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816206439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.3816206439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/75.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.1035220855 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 28942911224 ps |
| CPU time | 83.66 seconds |
| Started | Oct 09 08:52:43 PM UTC 24 |
| Finished | Oct 09 08:54:08 PM UTC 24 |
| Peak memory | 258700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1035220855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 75.otp_ctrl_stress_all_with_rand_reset.1035220855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/75.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_init_fail.2121363313 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 132394452 ps |
| CPU time | 3.27 seconds |
| Started | Oct 09 08:52:43 PM UTC 24 |
| Finished | Oct 09 08:52:47 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121363313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.2121363313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/76.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_parallel_lc_esc.3383190534 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 1977986628 ps |
| CPU time | 6.41 seconds |
| Started | Oct 09 08:52:43 PM UTC 24 |
| Finished | Oct 09 08:52:50 PM UTC 24 |
| Peak memory | 252484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383190534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.3383190534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/76.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.4283685976 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 18035347564 ps |
| CPU time | 131.53 seconds |
| Started | Oct 09 08:52:43 PM UTC 24 |
| Finished | Oct 09 08:54:57 PM UTC 24 |
| Peak memory | 258788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4283685976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 76.otp_ctrl_stress_all_with_rand_reset.4283685976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/76.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_init_fail.3311459502 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 248430943 ps |
| CPU time | 4.45 seconds |
| Started | Oct 09 08:52:43 PM UTC 24 |
| Finished | Oct 09 08:52:49 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311459502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.3311459502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/77.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_parallel_lc_esc.1574864161 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 2352819734 ps |
| CPU time | 10.57 seconds |
| Started | Oct 09 08:52:46 PM UTC 24 |
| Finished | Oct 09 08:52:58 PM UTC 24 |
| Peak memory | 252484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574864161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.1574864161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/77.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.2759880816 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 12380594089 ps |
| CPU time | 89.43 seconds |
| Started | Oct 09 08:52:46 PM UTC 24 |
| Finished | Oct 09 08:54:18 PM UTC 24 |
| Peak memory | 268928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2759880816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 77.otp_ctrl_stress_all_with_rand_reset.2759880816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/77.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_init_fail.2287708973 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 141113581 ps |
| CPU time | 5.24 seconds |
| Started | Oct 09 08:52:47 PM UTC 24 |
| Finished | Oct 09 08:52:53 PM UTC 24 |
| Peak memory | 252324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287708973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.2287708973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/78.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_parallel_lc_esc.2829744450 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 1273828738 ps |
| CPU time | 12.13 seconds |
| Started | Oct 09 08:52:47 PM UTC 24 |
| Finished | Oct 09 08:53:00 PM UTC 24 |
| Peak memory | 252312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829744450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.2829744450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/78.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.536818479 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 11821131934 ps |
| CPU time | 201.95 seconds |
| Started | Oct 09 08:52:47 PM UTC 24 |
| Finished | Oct 09 08:56:12 PM UTC 24 |
| Peak memory | 269096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=536818479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.536818479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/78.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_init_fail.2154331651 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 129050430 ps |
| CPU time | 4.18 seconds |
| Started | Oct 09 08:52:47 PM UTC 24 |
| Finished | Oct 09 08:52:52 PM UTC 24 |
| Peak memory | 252484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154331651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.2154331651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/79.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_parallel_lc_esc.3626717356 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 663620314 ps |
| CPU time | 17.07 seconds |
| Started | Oct 09 08:52:47 PM UTC 24 |
| Finished | Oct 09 08:53:05 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626717356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.3626717356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/79.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_alert_test.4287000659 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 194868928 ps |
| CPU time | 2.72 seconds |
| Started | Oct 09 08:45:53 PM UTC 24 |
| Finished | Oct 09 08:45:57 PM UTC 24 |
| Peak memory | 252296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287000659 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.4287000659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_background_chks.1389785583 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 8322561579 ps |
| CPU time | 15.01 seconds |
| Started | Oct 09 08:45:48 PM UTC 24 |
| Finished | Oct 09 08:46:04 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389785583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.1389785583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_check_fail.3406613270 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 961200362 ps |
| CPU time | 19.37 seconds |
| Started | Oct 09 08:45:51 PM UTC 24 |
| Finished | Oct 09 08:46:11 PM UTC 24 |
| Peak memory | 254636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406613270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.3406613270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_errs.1665241650 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1006238823 ps |
| CPU time | 36.28 seconds |
| Started | Oct 09 08:45:50 PM UTC 24 |
| Finished | Oct 09 08:46:28 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665241650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.1665241650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_lock.2154674935 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1401877665 ps |
| CPU time | 15.33 seconds |
| Started | Oct 09 08:45:50 PM UTC 24 |
| Finished | Oct 09 08:46:07 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154674935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.2154674935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_init_fail.1086020275 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 249274782 ps |
| CPU time | 3.82 seconds |
| Started | Oct 09 08:45:46 PM UTC 24 |
| Finished | Oct 09 08:45:51 PM UTC 24 |
| Peak memory | 252412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086020275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.1086020275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_key_req.2152817638 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1730718112 ps |
| CPU time | 22.13 seconds |
| Started | Oct 09 08:45:53 PM UTC 24 |
| Finished | Oct 09 08:46:17 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152817638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.2152817638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_esc.2620612613 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1120161671 ps |
| CPU time | 8.76 seconds |
| Started | Oct 09 08:45:50 PM UTC 24 |
| Finished | Oct 09 08:46:00 PM UTC 24 |
| Peak memory | 252444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620612613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.2620612613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_req.2434099893 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 255092014 ps |
| CPU time | 8 seconds |
| Started | Oct 09 08:45:48 PM UTC 24 |
| Finished | Oct 09 08:45:57 PM UTC 24 |
| Peak memory | 252304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434099893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.2434099893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_smoke.2291209951 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1602673850 ps |
| CPU time | 15.9 seconds |
| Started | Oct 09 08:45:45 PM UTC 24 |
| Finished | Oct 09 08:46:02 PM UTC 24 |
| Peak memory | 252524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291209951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.2291209951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all.1114970000 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 2035062095 ps |
| CPU time | 33.07 seconds |
| Started | Oct 09 08:45:53 PM UTC 24 |
| Finished | Oct 09 08:46:28 PM UTC 24 |
| Peak memory | 258576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114970000 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.1114970000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.4230713566 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1850899042 ps |
| CPU time | 66.24 seconds |
| Started | Oct 09 08:45:53 PM UTC 24 |
| Finished | Oct 09 08:47:01 PM UTC 24 |
| Peak memory | 258680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4230713566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.otp_ctrl_stress_all_with_rand_reset.4230713566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_init_fail.3694960055 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 198242620 ps |
| CPU time | 5.41 seconds |
| Started | Oct 09 08:52:50 PM UTC 24 |
| Finished | Oct 09 08:52:56 PM UTC 24 |
| Peak memory | 252432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694960055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.3694960055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/80.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_parallel_lc_esc.2865634416 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 360962369 ps |
| CPU time | 8.74 seconds |
| Started | Oct 09 08:52:50 PM UTC 24 |
| Finished | Oct 09 08:53:00 PM UTC 24 |
| Peak memory | 252436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865634416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.2865634416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/80.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_init_fail.490819603 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 150524398 ps |
| CPU time | 5.21 seconds |
| Started | Oct 09 08:52:50 PM UTC 24 |
| Finished | Oct 09 08:52:56 PM UTC 24 |
| Peak memory | 252340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490819603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.490819603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/81.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_parallel_lc_esc.2418024474 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 394493225 ps |
| CPU time | 8.23 seconds |
| Started | Oct 09 08:52:50 PM UTC 24 |
| Finished | Oct 09 08:52:59 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418024474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.2418024474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/81.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.3499233835 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 2158760238 ps |
| CPU time | 62.81 seconds |
| Started | Oct 09 08:52:53 PM UTC 24 |
| Finished | Oct 09 08:53:57 PM UTC 24 |
| Peak memory | 258756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3499233835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 81.otp_ctrl_stress_all_with_rand_reset.3499233835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_init_fail.1113207678 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 426764420 ps |
| CPU time | 5.09 seconds |
| Started | Oct 09 08:52:53 PM UTC 24 |
| Finished | Oct 09 08:52:59 PM UTC 24 |
| Peak memory | 252352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113207678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.1113207678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/82.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_parallel_lc_esc.1261857011 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 117098654 ps |
| CPU time | 3.98 seconds |
| Started | Oct 09 08:52:53 PM UTC 24 |
| Finished | Oct 09 08:52:58 PM UTC 24 |
| Peak memory | 252308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261857011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.1261857011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/82.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_init_fail.3877914236 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 420648332 ps |
| CPU time | 4.51 seconds |
| Started | Oct 09 08:52:53 PM UTC 24 |
| Finished | Oct 09 08:52:59 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877914236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.3877914236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/83.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_parallel_lc_esc.224371182 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 2160846241 ps |
| CPU time | 8.34 seconds |
| Started | Oct 09 08:52:53 PM UTC 24 |
| Finished | Oct 09 08:53:03 PM UTC 24 |
| Peak memory | 252436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224371182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.224371182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/83.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_init_fail.357640900 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 614383237 ps |
| CPU time | 5.08 seconds |
| Started | Oct 09 08:52:55 PM UTC 24 |
| Finished | Oct 09 08:53:01 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357640900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.357640900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/84.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_parallel_lc_esc.2714817690 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 658477162 ps |
| CPU time | 16.21 seconds |
| Started | Oct 09 08:52:56 PM UTC 24 |
| Finished | Oct 09 08:53:14 PM UTC 24 |
| Peak memory | 252420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714817690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.2714817690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/84.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_init_fail.3173740867 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 337287482 ps |
| CPU time | 4.45 seconds |
| Started | Oct 09 08:52:59 PM UTC 24 |
| Finished | Oct 09 08:53:04 PM UTC 24 |
| Peak memory | 252412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173740867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.3173740867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/85.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_parallel_lc_esc.2251886710 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 392217494 ps |
| CPU time | 11.02 seconds |
| Started | Oct 09 08:52:59 PM UTC 24 |
| Finished | Oct 09 08:53:11 PM UTC 24 |
| Peak memory | 252284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251886710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.2251886710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.2085884668 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 5980266493 ps |
| CPU time | 84.4 seconds |
| Started | Oct 09 08:52:59 PM UTC 24 |
| Finished | Oct 09 08:54:25 PM UTC 24 |
| Peak memory | 268996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2085884668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 85.otp_ctrl_stress_all_with_rand_reset.2085884668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_init_fail.378445220 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 188646071 ps |
| CPU time | 6.19 seconds |
| Started | Oct 09 08:53:01 PM UTC 24 |
| Finished | Oct 09 08:53:09 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378445220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.378445220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/86.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_parallel_lc_esc.2053395482 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 296050106 ps |
| CPU time | 4.74 seconds |
| Started | Oct 09 08:53:01 PM UTC 24 |
| Finished | Oct 09 08:53:07 PM UTC 24 |
| Peak memory | 252352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053395482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.2053395482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/86.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_init_fail.66868810 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 122920634 ps |
| CPU time | 6.08 seconds |
| Started | Oct 09 08:53:01 PM UTC 24 |
| Finished | Oct 09 08:53:09 PM UTC 24 |
| Peak memory | 252404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66868810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.66868810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/87.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_parallel_lc_esc.2665761083 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 699551611 ps |
| CPU time | 11.22 seconds |
| Started | Oct 09 08:53:01 PM UTC 24 |
| Finished | Oct 09 08:53:14 PM UTC 24 |
| Peak memory | 252484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665761083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.2665761083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/87.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_init_fail.4095214849 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 158995128 ps |
| CPU time | 5.62 seconds |
| Started | Oct 09 08:53:02 PM UTC 24 |
| Finished | Oct 09 08:53:08 PM UTC 24 |
| Peak memory | 252316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095214849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.4095214849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/88.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_parallel_lc_esc.433697540 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 1038101224 ps |
| CPU time | 8.49 seconds |
| Started | Oct 09 08:53:03 PM UTC 24 |
| Finished | Oct 09 08:53:13 PM UTC 24 |
| Peak memory | 252304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433697540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.433697540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/88.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_init_fail.1998762446 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 493015268 ps |
| CPU time | 5.93 seconds |
| Started | Oct 09 08:53:07 PM UTC 24 |
| Finished | Oct 09 08:53:14 PM UTC 24 |
| Peak memory | 252472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998762446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.1998762446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/89.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_parallel_lc_esc.2642606318 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 213492802 ps |
| CPU time | 4.46 seconds |
| Started | Oct 09 08:53:07 PM UTC 24 |
| Finished | Oct 09 08:53:12 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642606318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.2642606318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/89.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.2135270933 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 15252663181 ps |
| CPU time | 59.69 seconds |
| Started | Oct 09 08:53:07 PM UTC 24 |
| Finished | Oct 09 08:54:08 PM UTC 24 |
| Peak memory | 269016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2135270933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 89.otp_ctrl_stress_all_with_rand_reset.2135270933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/89.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_alert_test.4023226045 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 108031056 ps |
| CPU time | 2.11 seconds |
| Started | Oct 09 08:46:04 PM UTC 24 |
| Finished | Oct 09 08:46:08 PM UTC 24 |
| Peak memory | 252396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023226045 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.4023226045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_background_chks.1449163181 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 387123971 ps |
| CPU time | 7.85 seconds |
| Started | Oct 09 08:45:58 PM UTC 24 |
| Finished | Oct 09 08:46:08 PM UTC 24 |
| Peak memory | 252636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449163181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.1449163181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_errs.1180985185 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 3976730730 ps |
| CPU time | 16.77 seconds |
| Started | Oct 09 08:46:00 PM UTC 24 |
| Finished | Oct 09 08:46:19 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180985185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.1180985185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_lock.3772409901 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 2216893440 ps |
| CPU time | 21.33 seconds |
| Started | Oct 09 08:46:00 PM UTC 24 |
| Finished | Oct 09 08:46:23 PM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772409901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.3772409901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_init_fail.608625296 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1750569743 ps |
| CPU time | 7.69 seconds |
| Started | Oct 09 08:45:56 PM UTC 24 |
| Finished | Oct 09 08:46:05 PM UTC 24 |
| Peak memory | 252560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608625296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.608625296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_macro_errs.3897091082 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 532204791 ps |
| CPU time | 18.36 seconds |
| Started | Oct 09 08:46:04 PM UTC 24 |
| Finished | Oct 09 08:46:24 PM UTC 24 |
| Peak memory | 252256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897091082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.3897091082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_key_req.4046800199 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1179780833 ps |
| CPU time | 30.26 seconds |
| Started | Oct 09 08:46:04 PM UTC 24 |
| Finished | Oct 09 08:46:36 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046800199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.4046800199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_esc.2058073658 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 247363123 ps |
| CPU time | 12.68 seconds |
| Started | Oct 09 08:45:59 PM UTC 24 |
| Finished | Oct 09 08:46:13 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058073658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.2058073658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_req.3768489700 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1147332218 ps |
| CPU time | 12.35 seconds |
| Started | Oct 09 08:45:59 PM UTC 24 |
| Finished | Oct 09 08:46:12 PM UTC 24 |
| Peak memory | 252356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768489700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.3768489700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_regwen.1364206486 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 302689349 ps |
| CPU time | 8.13 seconds |
| Started | Oct 09 08:46:04 PM UTC 24 |
| Finished | Oct 09 08:46:14 PM UTC 24 |
| Peak memory | 252256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364206486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.1364206486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_smoke.849865591 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 129603676 ps |
| CPU time | 4.91 seconds |
| Started | Oct 09 08:45:55 PM UTC 24 |
| Finished | Oct 09 08:46:01 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849865591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.849865591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all.1002399767 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 72018492112 ps |
| CPU time | 62.07 seconds |
| Started | Oct 09 08:46:04 PM UTC 24 |
| Finished | Oct 09 08:47:08 PM UTC 24 |
| Peak memory | 254692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002399767 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.1002399767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_test_access.3461116536 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 10912835053 ps |
| CPU time | 25.59 seconds |
| Started | Oct 09 08:46:04 PM UTC 24 |
| Finished | Oct 09 08:46:31 PM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461116536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.3461116536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/9.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_init_fail.3645024591 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 184009913 ps |
| CPU time | 5.25 seconds |
| Started | Oct 09 08:53:08 PM UTC 24 |
| Finished | Oct 09 08:53:14 PM UTC 24 |
| Peak memory | 252324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645024591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.3645024591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/90.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_parallel_lc_esc.1873486357 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 231121514 ps |
| CPU time | 5.73 seconds |
| Started | Oct 09 08:53:17 PM UTC 24 |
| Finished | Oct 09 08:53:24 PM UTC 24 |
| Peak memory | 252032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873486357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.1873486357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/90.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_init_fail.4206615497 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 168521931 ps |
| CPU time | 6.3 seconds |
| Started | Oct 09 08:53:17 PM UTC 24 |
| Finished | Oct 09 08:53:25 PM UTC 24 |
| Peak memory | 252432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206615497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.4206615497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/91.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_parallel_lc_esc.1097105327 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 101368253 ps |
| CPU time | 4.92 seconds |
| Started | Oct 09 08:53:17 PM UTC 24 |
| Finished | Oct 09 08:53:23 PM UTC 24 |
| Peak memory | 252356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097105327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.1097105327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/91.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.3779390860 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 4054551682 ps |
| CPU time | 94.46 seconds |
| Started | Oct 09 08:53:17 PM UTC 24 |
| Finished | Oct 09 08:54:54 PM UTC 24 |
| Peak memory | 258788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3779390860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 91.otp_ctrl_stress_all_with_rand_reset.3779390860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_init_fail.3838712383 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 553066032 ps |
| CPU time | 5.48 seconds |
| Started | Oct 09 08:53:17 PM UTC 24 |
| Finished | Oct 09 08:53:24 PM UTC 24 |
| Peak memory | 252380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838712383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.3838712383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/92.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_parallel_lc_esc.3200344432 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 655593271 ps |
| CPU time | 8.37 seconds |
| Started | Oct 09 08:53:18 PM UTC 24 |
| Finished | Oct 09 08:53:27 PM UTC 24 |
| Peak memory | 252368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200344432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.3200344432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/92.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.1513725035 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 4599363251 ps |
| CPU time | 39.22 seconds |
| Started | Oct 09 08:53:18 PM UTC 24 |
| Finished | Oct 09 08:53:58 PM UTC 24 |
| Peak memory | 258404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1513725035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 92.otp_ctrl_stress_all_with_rand_reset.1513725035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/92.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_init_fail.1487417779 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 155822621 ps |
| CPU time | 5.62 seconds |
| Started | Oct 09 08:53:18 PM UTC 24 |
| Finished | Oct 09 08:53:24 PM UTC 24 |
| Peak memory | 252128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487417779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.1487417779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/93.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_parallel_lc_esc.2887898730 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 1095734212 ps |
| CPU time | 21.65 seconds |
| Started | Oct 09 08:53:18 PM UTC 24 |
| Finished | Oct 09 08:53:41 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887898730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.2887898730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/93.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_init_fail.3320678913 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 415848216 ps |
| CPU time | 5.78 seconds |
| Started | Oct 09 08:53:18 PM UTC 24 |
| Finished | Oct 09 08:53:25 PM UTC 24 |
| Peak memory | 252396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320678913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.3320678913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/94.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_parallel_lc_esc.2645840535 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 423608283 ps |
| CPU time | 8.04 seconds |
| Started | Oct 09 08:53:22 PM UTC 24 |
| Finished | Oct 09 08:53:32 PM UTC 24 |
| Peak memory | 252308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645840535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.2645840535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/94.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.848822964 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 6211545379 ps |
| CPU time | 122.12 seconds |
| Started | Oct 09 08:53:23 PM UTC 24 |
| Finished | Oct 09 08:55:27 PM UTC 24 |
| Peak memory | 258792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=848822964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.848822964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_init_fail.2617959878 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 108361735 ps |
| CPU time | 6 seconds |
| Started | Oct 09 08:53:23 PM UTC 24 |
| Finished | Oct 09 08:53:30 PM UTC 24 |
| Peak memory | 252400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617959878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.2617959878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/95.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_parallel_lc_esc.1962320332 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 917451349 ps |
| CPU time | 12.01 seconds |
| Started | Oct 09 08:53:24 PM UTC 24 |
| Finished | Oct 09 08:53:38 PM UTC 24 |
| Peak memory | 252500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962320332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.1962320332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.988349756 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 3167674607 ps |
| CPU time | 48.86 seconds |
| Started | Oct 09 08:53:24 PM UTC 24 |
| Finished | Oct 09 08:54:15 PM UTC 24 |
| Peak memory | 262952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=988349756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.988349756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/95.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_init_fail.2835835424 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2396017700 ps |
| CPU time | 6.94 seconds |
| Started | Oct 09 08:53:27 PM UTC 24 |
| Finished | Oct 09 08:53:35 PM UTC 24 |
| Peak memory | 252416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835835424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.2835835424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/96.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_parallel_lc_esc.861517680 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 291732587 ps |
| CPU time | 11.87 seconds |
| Started | Oct 09 08:53:27 PM UTC 24 |
| Finished | Oct 09 08:53:40 PM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861517680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.861517680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/96.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.299954501 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 36722965042 ps |
| CPU time | 75.39 seconds |
| Started | Oct 09 08:53:27 PM UTC 24 |
| Finished | Oct 09 08:54:44 PM UTC 24 |
| Peak memory | 269092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=299954501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.299954501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/96.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_init_fail.1969563543 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 153205089 ps |
| CPU time | 5.94 seconds |
| Started | Oct 09 08:53:27 PM UTC 24 |
| Finished | Oct 09 08:53:34 PM UTC 24 |
| Peak memory | 252352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969563543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.1969563543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/97.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_parallel_lc_esc.4210228041 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 580416669 ps |
| CPU time | 7.34 seconds |
| Started | Oct 09 08:53:27 PM UTC 24 |
| Finished | Oct 09 08:53:36 PM UTC 24 |
| Peak memory | 252248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210228041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.4210228041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/97.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.3687902708 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 3657536214 ps |
| CPU time | 149.95 seconds |
| Started | Oct 09 08:53:28 PM UTC 24 |
| Finished | Oct 09 08:56:01 PM UTC 24 |
| Peak memory | 258768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3687902708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 97.otp_ctrl_stress_all_with_rand_reset.3687902708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/97.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_init_fail.2437421105 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 2387688972 ps |
| CPU time | 8.94 seconds |
| Started | Oct 09 08:53:34 PM UTC 24 |
| Finished | Oct 09 08:53:44 PM UTC 24 |
| Peak memory | 252412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437421105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.2437421105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/98.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_parallel_lc_esc.4060697249 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 1563803390 ps |
| CPU time | 15.14 seconds |
| Started | Oct 09 08:53:34 PM UTC 24 |
| Finished | Oct 09 08:53:50 PM UTC 24 |
| Peak memory | 252312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060697249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.4060697249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/98.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.4268478457 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 16816917706 ps |
| CPU time | 99.48 seconds |
| Started | Oct 09 08:53:34 PM UTC 24 |
| Finished | Oct 09 08:55:15 PM UTC 24 |
| Peak memory | 268952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4268478457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 98.otp_ctrl_stress_all_with_rand_reset.4268478457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/98.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_init_fail.2382460586 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 324048240 ps |
| CPU time | 6.43 seconds |
| Started | Oct 09 08:53:35 PM UTC 24 |
| Finished | Oct 09 08:53:43 PM UTC 24 |
| Peak memory | 252432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382460586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.2382460586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/99.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_parallel_lc_esc.228777931 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 139788396 ps |
| CPU time | 8.19 seconds |
| Started | Oct 09 08:53:43 PM UTC 24 |
| Finished | Oct 09 08:53:53 PM UTC 24 |
| Peak memory | 252360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228777931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.228777931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/99.otp_ctrl_parallel_lc_esc/latest |
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