Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1468020
Category 01468020

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1468020
Severity 01468020

Summary for Assertions
NUMBERPERCENT
Total Number1468100.00
Uncovered543.68
Success141496.32
Failure00.00
Incomplete110.75
Without Attempts50.34

Summary for Cover Sequences
NUMBERPERCENT
Total Number20100.00
Uncovered00.00
All Matches20100.00
First Matches20100.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.prim_tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 001296129600
tb.dut.prim_tlul_assert_device.gen_device.aDataKnown_M 0095417231115198800
tb.dut.prim_tlul_assert_device.gen_device.addrSizeAlignedErr_A 009541631510980200
tb.dut.prim_tlul_assert_device.gen_device.contigMask_M 00954172319292400
tb.dut.prim_tlul_assert_device.gen_device.dDataKnown_A 009541723111409200
tb.dut.prim_tlul_assert_device.gen_device.legalAOpcodeErr_A 009541631512028200
tb.dut.prim_tlul_assert_device.gen_device.legalAParam_M 0095417231153060600
tb.dut.prim_tlul_assert_device.gen_device.legalDParam_A 0095417231146710800
tb.dut.prim_tlul_assert_device.gen_device.pendingReqPerSrc_M 0095417231153060600
tb.dut.prim_tlul_assert_device.gen_device.respMustHaveReq_A 0095417231146710800
tb.dut.prim_tlul_assert_device.gen_device.respOpcode_A 0095417231146710800
tb.dut.prim_tlul_assert_device.gen_device.respSzEqReqSz_A 0095417231146710800
tb.dut.prim_tlul_assert_device.gen_device.sizeGTEMaskErr_A 00954163158374100
tb.dut.prim_tlul_assert_device.gen_device.sizeMatchesMaskErr_A 00954163156939300
tb.dut.prim_tlul_assert_device.p_dbw.TlDbw_A 001296129600
tb.dut.u_edn_arb.CheckHotOne_A 00923716669149871600
tb.dut.u_edn_arb.CheckNGreaterZero_A 001121112100
tb.dut.u_edn_arb.GntImpliesReady_A 009237166621447200
tb.dut.u_edn_arb.GntImpliesValid_A 009237166621447200
tb.dut.u_edn_arb.GrantKnown_A 00923716669149871600
tb.dut.u_edn_arb.IdxKnown_A 00923716669149871600
tb.dut.u_edn_arb.IndexIsCorrect_A 009237166621447200
tb.dut.u_edn_arb.LockArbDecision_A 00923716661992774700
tb.dut.u_edn_arb.NoReadyValidNoGrant_A 00923716667133064200
tb.dut.u_edn_arb.ReadyAndValidImplyGrant_A 009237166621447200
tb.dut.u_edn_arb.ReqAndReadyImplyGrant_A 009237166621447200
tb.dut.u_edn_arb.ReqImpliesValid_A 00923716662016807400
tb.dut.u_edn_arb.ReqStaysHighUntilGranted0_M 00923716661992774700
tb.dut.u_edn_arb.ValidKnown_A 00923716669149871600
tb.dut.u_intr_error.IntrTKind_A 001121112100
tb.dut.u_intr_operation_done.IntrTKind_A 001121112100
tb.dut.u_otp.gen_generic.u_impl_generic.CheckCommands0_A 00923716661194700
tb.dut.u_otp.gen_generic.u_impl_generic.CheckCommands1_A 0092371666117615900
tb.dut.u_otp.gen_generic.u_impl_generic.NoWrapArounds_A 0092371666370529600
tb.dut.u_otp.gen_generic.u_impl_generic.SecDecWidth_A 001121112100
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.CannotHaveEccAndParity_A 001121112100
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 001121112100
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[10].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[11].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[12].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[13].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[14].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[15].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[16].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[17].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[18].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[19].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[1].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[20].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[21].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[2].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[3].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[4].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[5].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[6].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[7].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[8].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.gen_wmask[9].MaskCheck_A 009237166652938600
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.en2addrHit 00954163153834800
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.reAfterRv 00954163153834800
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.rePulse 00954163152394800
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_chk.PayLoadWidthCheck 001296129600
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_reg_if.AllowedLatency_A 001296129600
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_reg_if.MatchedWidthAssert 001296129600
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err.dataWidthOnly32_A 001296129600
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 001296129600
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 001296129600
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.DataWidthCheck_A 001296129600
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.PayLoadWidthCheck 001296129600
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.wePulse 00954163151440000
tb.dut.u_otp.gen_generic.u_impl_generic.u_state_regs.AssertConnected_A 001121112100
tb.dut.u_otp.gen_generic.u_impl_generic.u_state_regs_A 00923716669149871600
tb.dut.u_otp_arb.CheckHotOne_A 00923716669149871600
tb.dut.u_otp_arb.CheckNGreaterZero_A 001121112100
tb.dut.u_otp_arb.GntImpliesReady_A 0092371666118810600
tb.dut.u_otp_arb.GntImpliesValid_A 0092371666118810600
tb.dut.u_otp_arb.GrantKnown_A 00923716669149871600
tb.dut.u_otp_arb.IdxKnown_A 00923716669149871600
tb.dut.u_otp_arb.IndexIsCorrect_A 0092371666118810600
tb.dut.u_otp_arb.LockArbDecision_A 0092371666672218700
tb.dut.u_otp_arb.NoReadyValidNoGrant_A 0092371666653581300
tb.dut.u_otp_arb.ReadyAndValidImplyGrant_A 0092371666118810600
tb.dut.u_otp_arb.ReqAndReadyImplyGrant_A 0092371666118810600
tb.dut.u_otp_arb.ReqImpliesValid_A 0092371666791179100
tb.dut.u_otp_arb.ReqStaysHighUntilGranted0_M 0092371666672218700
tb.dut.u_otp_arb.ValidKnown_A 00923716669149871600
tb.dut.u_otp_arb.gen_data_port_assertion.DataFlow_A 0092371666118810600
tb.dut.u_otp_ctrl_dai.CheckNativeOtpWidth0_A 001121112100
tb.dut.u_otp_ctrl_dai.CheckNativeOtpWidth1_A 001121112100
tb.dut.u_otp_ctrl_dai.DaiIdleKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.DaiRdataKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.ErrorKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.InitDoneKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.OtpAddrKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.OtpCmdKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.OtpErrorState_A 009237166630900
tb.dut.u_otp_ctrl_dai.OtpReqKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.OtpSizeKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.OtpWdataKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.PartInitReqKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.PartSelMustBeOnehot_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.ScrmblBlockWidthGe8_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.ScrmblCmdKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.ScrmblDataKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.ScrmblModeKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.ScrmblMtxReqKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.ScrmblSelKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.ScrmblValidKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.gen_part_sel[0].PartEndMax_A 001121112100
tb.dut.u_otp_ctrl_dai.gen_part_sel[10].PartEndMax_A 001121112100
tb.dut.u_otp_ctrl_dai.gen_part_sel[1].PartEndMax_A 001121112100
tb.dut.u_otp_ctrl_dai.gen_part_sel[2].PartEndMax_A 001121112100
tb.dut.u_otp_ctrl_dai.gen_part_sel[3].PartEndMax_A 001121112100
tb.dut.u_otp_ctrl_dai.gen_part_sel[4].PartEndMax_A 001121112100
tb.dut.u_otp_ctrl_dai.gen_part_sel[5].PartEndMax_A 001121112100
tb.dut.u_otp_ctrl_dai.gen_part_sel[6].PartEndMax_A 001121112100
tb.dut.u_otp_ctrl_dai.gen_part_sel[7].PartEndMax_A 001121112100
tb.dut.u_otp_ctrl_dai.gen_part_sel[8].PartEndMax_A 001121112100
tb.dut.u_otp_ctrl_dai.gen_part_sel[9].PartEndMax_A 001121112100
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.CheckHotOne_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.CheckNGreaterZero_A 001121112100
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.GrantKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.IdxKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.Priority_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.ReqImpliesValid_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.ValidKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_dai.u_state_regs.AssertConnected_A 001121112100
tb.dut.u_otp_ctrl_dai.u_state_regs_A 00923716669149871600
tb.dut.u_otp_ctrl_kdi.EdnReqKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_kdi.EntropyWidthDividesDigestBlockWidth_A 001121112100
tb.dut.u_otp_ctrl_kdi.FlashOtpKeyRspKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_kdi.FsmErrKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_kdi.KeyNonceSize0_A 001121112100
tb.dut.u_otp_ctrl_kdi.KeyNonceSize1_A 001121112100
tb.dut.u_otp_ctrl_kdi.KeyNonceSize2_A 001121112100
tb.dut.u_otp_ctrl_kdi.KeyNonceSize3_A 001121112100
tb.dut.u_otp_ctrl_kdi.KeyNonceSize4_A 001121112100
tb.dut.u_otp_ctrl_kdi.KeyNonceSize5_A 001121112100
tb.dut.u_otp_ctrl_kdi.KeyNonceSize6_A 001121112100
tb.dut.u_otp_ctrl_kdi.NonceWidth_A 001121112100
tb.dut.u_otp_ctrl_kdi.OtbnOtpKeyRspKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_kdi.ScrmblCmdKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_kdi.ScrmblDataKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_kdi.ScrmblModeKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_kdi.ScrmblMtxReqKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_kdi.ScrmblSelKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_kdi.ScrmblValidKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_kdi.SramOtpKeyRspKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_kdi.u_req_arb.CheckHotOne_A 00923716669149871600
tb.dut.u_otp_ctrl_kdi.u_req_arb.CheckNGreaterZero_A 001121112100
tb.dut.u_otp_ctrl_kdi.u_req_arb.GntImpliesReady_A 00923716663390200
tb.dut.u_otp_ctrl_kdi.u_req_arb.GntImpliesValid_A 00923716663390200
tb.dut.u_otp_ctrl_kdi.u_req_arb.GrantKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_kdi.u_req_arb.IdxKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_kdi.u_req_arb.IndexIsCorrect_A 00923716663390200
tb.dut.u_otp_ctrl_kdi.u_req_arb.LockArbDecision_A 00923716662999310500
tb.dut.u_otp_ctrl_kdi.u_req_arb.NoReadyValidNoGrant_A 00923716666146918600
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReadyAndValidImplyGrant_A 00923716663390200
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqAndReadyImplyGrant_A 00923716663390200
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqImpliesValid_A 00923716663002953000
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqStaysHighUntilGranted0_M 00923716662999310500
tb.dut.u_otp_ctrl_kdi.u_req_arb.ValidKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_kdi.u_req_arb.gen_data_port_assertion.DataFlow_A 00923716663390200
tb.dut.u_otp_ctrl_kdi.u_state_regs.AssertConnected_A 001121112100
tb.dut.u_otp_ctrl_kdi.u_state_regs_A 00923716669149871600
tb.dut.u_otp_ctrl_lci.ErrorKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_lci.LcAckKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_lci.LcErrKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_lci.LcValueMustBeWiderThanNativeOtpWidth_A 001121112100
tb.dut.u_otp_ctrl_lci.LciIdleKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_lci.OtpAddrKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_lci.OtpCmdKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_lci.OtpReqKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_lci.OtpSizeKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_lci.OtpWdataKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_lci.u_state_regs.AssertConnected_A 001121112100
tb.dut.u_otp_ctrl_lci.u_state_regs_A 00923716669149871600
tb.dut.u_otp_ctrl_lfsr_timer.ChkPendingKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_lfsr_timer.ChkTimeoutKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_lfsr_timer.CnstyChkReqKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_lfsr_timer.EdnIsWideEnough_A 001121112100
tb.dut.u_otp_ctrl_lfsr_timer.EdnReqKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_lfsr_timer.IntegChkReqKnown_A 00923716669149871600
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.AssertConnected_A 001121112100
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