Module Definition
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Module : prim_sparse_fsm_flop
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs 100.00 100.00 100.00
tb.dut.u_tlul_lc_gate.u_state_regs 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_state_regs 100.00 100.00 100.00
tb.dut.u_otp_ctrl_scrmbl.u_state_regs 100.00 100.00 100.00
tb.dut.u_otp_ctrl_dai.u_state_regs 100.00 100.00 100.00
tb.dut.u_otp_ctrl_lci.u_state_regs 100.00 100.00 100.00
tb.dut.u_otp_ctrl_kdi.u_state_regs 100.00 100.00 100.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_state_regs 100.00 100.00 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_state_regs 100.00 100.00 100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_state_regs 100.00 100.00 100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_state_regs 100.00 100.00 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_state_regs 100.00 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_state_regs 100.00 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_state_regs 100.00 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_state_regs 100.00 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_state_regs 100.00 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_state_regs 100.00 100.00 100.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_state_regs 100.00 100.00 100.00



Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.16 100.00 89.61 100.00 91.18 100.00 u_otp_ctrl_lfsr_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
89.21 98.04 100.00 85.71 95.65 66.67 u_tlul_lc_gate


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.45 97.27 100.00 100.00 100.00 100.00 gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_otp_ctrl_scrmbl.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 91.67 100.00 100.00 100.00 100.00 u_otp_ctrl_scrmbl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_otp_ctrl_dai.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.38 94.33 95.06 89.47 88.04 100.00 u_otp_ctrl_dai


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_otp_ctrl_lci.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 u_otp_ctrl_lci


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_otp_ctrl_kdi.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.27 99.32 100.00 90.91 91.11 100.00 u_otp_ctrl_kdi


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.20 94.51 100.00 85.00 95.35 96.15 gen_partitions[0].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 100.00 91.67 100.00 100.00 gen_partitions[1].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.13 100.00 100.00 95.65 100.00 100.00 gen_partitions[2].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 100.00 91.67 100.00 100.00 gen_partitions[3].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.05 100.00 100.00 95.24 100.00 100.00 gen_partitions[4].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.98 97.64 95.24 96.00 98.15 82.86 gen_partitions[5].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.75 95.45 92.86 91.67 90.91 82.86 gen_partitions[6].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.95 98.00 93.75 91.67 96.88 94.44 gen_partitions[7].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.95 98.00 93.75 91.67 96.88 94.44 gen_partitions[8].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.95 98.00 93.75 91.67 96.88 94.44 gen_partitions[9].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.90 96.91 100.00 95.24 100.00 82.35 gen_partitions[10].gen_lifecycle.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00

Line Coverage for Module : prim_sparse_fsm_flop
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Module : prim_sparse_fsm_flop
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 20178 20178 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20178 20178 0 0
T1 18 18 0 0
T2 18 18 0 0
T3 18 18 0 0
T4 18 18 0 0
T5 18 18 0 0
T6 18 18 0 0
T7 18 18 0 0
T8 18 18 0 0
T9 18 18 0 0
T13 18 18 0 0

Line Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1121 1121 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1121 1121 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_tlul_lc_gate.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1121 1121 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1121 1121 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1121 1121 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1121 1121 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1121 1121 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1121 1121 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.u_otp_ctrl_dai.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_otp_ctrl_dai.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1121 1121 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1121 1121 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.u_otp_ctrl_lci.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_otp_ctrl_lci.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1121 1121 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1121 1121 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.u_otp_ctrl_kdi.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_otp_ctrl_kdi.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1121 1121 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1121 1121 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1121 1121 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1121 1121 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1121 1121 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1121 1121 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1121 1121 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1121 1121 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1121 1121 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1121 1121 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1121 1121 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1121 1121 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1121 1121 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1121 1121 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1121 1121 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1121 1121 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1121 1121 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1121 1121 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1121 1121 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1121 1121 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1121 1121 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1121 1121 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1121 1121 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1121 1121 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0