Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4425906	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2507220

1

T1

4

T2

19

T3

488

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5875582	1			T1	4		T2	1		T3	1041
values[0x0]	500174	1			T1	8		T2	38		T3	75
values[0x1]	557370	1			T1	7		T2	32		T3	78

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3269751	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3663375

1

T1

5

T2

26

T3

633

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27156	1			T3	12		T5	9		T6	6
valid_sources[0x01]	25817	1			T3	8		T5	2		T6	7
valid_sources[0x02]	36129	1			T3	9		T5	3		T6	1
valid_sources[0x03]	19812	1			T5	1		T6	4		T7	8
valid_sources[0x04]	25630	1			T3	1		T6	7		T7	5
valid_sources[0x05]	24553	1			T2	1		T3	3		T4	6
valid_sources[0x06]	31840	1			T5	3		T6	5		T7	3
valid_sources[0x07]	21794	1			T3	4		T6	2		T7	5
valid_sources[0x08]	23657	1			T3	3		T5	13		T6	9
valid_sources[0x09]	26998	1			T3	2		T5	3		T6	4
valid_sources[0x0a]	50622	1			T5	1		T6	6		T7	7
valid_sources[0x0b]	19175	1			T3	4		T5	6		T6	3
valid_sources[0x0c]	25035	1			T3	4		T5	5		T6	3
valid_sources[0x0d]	21252	1			T2	2		T5	1		T6	3
valid_sources[0x0e]	31035	1			T2	5		T3	10		T6	5
valid_sources[0x0f]	21755	1			T2	1		T3	1		T5	6
valid_sources[0x10]	33131	1			T3	10		T5	3		T6	5
valid_sources[0x11]	39997	1			T3	5		T5	7		T6	1
valid_sources[0x12]	26010	1			T3	7		T5	3		T6	3
valid_sources[0x13]	36388	1			T3	5		T6	2		T7	5
valid_sources[0x14]	20566	1			T3	2		T5	3		T6	4
valid_sources[0x15]	22262	1			T5	10		T6	4		T7	8
valid_sources[0x16]	19965	1			T3	1		T5	1		T6	5
valid_sources[0x17]	22003	1			T3	4		T5	1		T6	3
valid_sources[0x18]	22167	1			T3	5		T4	79		T5	10
valid_sources[0x19]	21545	1			T3	9		T5	4		T6	2
valid_sources[0x1a]	33019	1			T3	1		T5	2		T6	2
valid_sources[0x1b]	19837	1			T3	7		T5	2		T7	4
valid_sources[0x1c]	25253	1			T3	15		T5	3		T6	5
valid_sources[0x1d]	19207	1			T5	4		T6	4		T7	3
valid_sources[0x1e]	19069	1			T3	7		T4	4		T5	5
valid_sources[0x1f]	111790	1			T2	1		T3	9		T5	2
valid_sources[0x20]	20658	1			T3	3		T5	2		T6	8
valid_sources[0x21]	19492	1			T2	1		T3	5		T5	4
valid_sources[0x22]	23952	1			T3	2		T5	5		T6	4
valid_sources[0x23]	19427	1			T3	14		T5	4		T6	2
valid_sources[0x24]	21299	1			T3	9		T4	180		T6	4
valid_sources[0x25]	20611	1			T3	10		T5	4		T6	3
valid_sources[0x26]	19984	1			T3	4		T5	3		T6	12
valid_sources[0x27]	31833	1			T3	2		T6	7		T7	4
valid_sources[0x28]	20819	1			T2	2		T3	6		T5	4
valid_sources[0x29]	21767	1			T2	3		T5	3		T6	9
valid_sources[0x2a]	21287	1			T2	1		T3	10		T7	7
valid_sources[0x2b]	22974	1			T3	4		T6	3		T7	8
valid_sources[0x2c]	26516	1			T3	6		T5	11		T6	3
valid_sources[0x2d]	19252	1			T3	6		T5	28		T7	7
valid_sources[0x2e]	21277	1			T3	5		T5	3		T6	3
valid_sources[0x2f]	20184	1			T3	4		T5	9		T6	11
valid_sources[0x30]	56605	1			T3	3		T6	3		T9	18
valid_sources[0x31]	19890	1			T3	2		T5	10		T6	1
valid_sources[0x32]	34080	1			T3	3		T5	1		T6	6
valid_sources[0x33]	34754	1			T3	6		T5	13		T6	7
valid_sources[0x34]	19091	1			T2	1		T5	3		T6	4
valid_sources[0x35]	24636	1			T3	6		T5	2		T6	5
valid_sources[0x36]	22128	1			T3	3		T4	50		T5	14
valid_sources[0x37]	21645	1			T3	1		T5	14		T6	3
valid_sources[0x38]	37597	1			T3	4		T5	2		T6	5
valid_sources[0x39]	27626	1			T2	1		T3	6		T5	21
valid_sources[0x3a]	23933	1			T6	2		T7	3		T9	8
valid_sources[0x3b]	19153	1			T3	2		T5	15		T6	11
valid_sources[0x3c]	20069	1			T3	1		T6	5		T7	5
valid_sources[0x3d]	20498	1			T3	6		T5	5		T6	11
valid_sources[0x3e]	20845	1			T3	11		T6	8		T7	10
valid_sources[0x3f]	23273	1			T3	6		T5	10		T6	7
valid_sources[0x40]	37397	1			T3	3		T6	6		T7	3
valid_sources[0x41]	38451	1			T2	3		T3	1		T5	8
valid_sources[0x42]	20780	1			T3	11		T5	2		T6	15
valid_sources[0x43]	33645	1			T2	2		T3	9		T5	4
valid_sources[0x44]	20695	1			T3	5		T5	4		T6	10
valid_sources[0x45]	20724	1			T3	6		T5	5		T6	1
valid_sources[0x46]	44590	1			T3	6		T5	2		T6	1
valid_sources[0x47]	19151	1			T3	4		T5	2		T6	3
valid_sources[0x48]	27253	1			T3	3		T4	205		T5	5
valid_sources[0x49]	23652	1			T3	9		T5	3		T6	1
valid_sources[0x4a]	19549	1			T3	2		T6	2		T7	6
valid_sources[0x4b]	21024	1			T3	1		T4	13		T5	3
valid_sources[0x4c]	27476	1			T3	8		T6	4		T7	4
valid_sources[0x4d]	24731	1			T3	9		T6	5		T7	8
valid_sources[0x4e]	19333	1			T3	5		T5	2		T6	15
valid_sources[0x4f]	62558	1			T3	9		T5	3		T6	5
valid_sources[0x50]	60926	1			T3	7		T6	7		T7	7
valid_sources[0x51]	20065	1			T5	6		T6	7		T7	5
valid_sources[0x52]	159294	1			T3	3		T5	3		T6	8
valid_sources[0x53]	18550	1			T5	1		T6	1		T7	5
valid_sources[0x54]	19373	1			T3	3		T5	2		T6	13
valid_sources[0x55]	19128	1			T3	6		T5	6		T6	5
valid_sources[0x56]	32531	1			T3	5		T5	5		T6	9
valid_sources[0x57]	24316	1			T3	5		T7	1		T9	15
valid_sources[0x58]	21894	1			T3	5		T5	2		T6	2
valid_sources[0x59]	19606	1			T3	9		T5	4		T6	3
valid_sources[0x5a]	22016	1			T3	8		T5	7		T6	4
valid_sources[0x5b]	35082	1			T3	4		T5	9		T6	5
valid_sources[0x5c]	19770	1			T3	3		T5	5		T6	4
valid_sources[0x5d]	19674	1			T2	1		T3	12		T5	2
valid_sources[0x5e]	21029	1			T3	1		T6	10		T7	1
valid_sources[0x5f]	45042	1			T3	2		T5	2		T6	7
valid_sources[0x60]	20031	1			T3	4		T6	5		T7	5
valid_sources[0x61]	20037	1			T3	3		T5	2		T6	1
valid_sources[0x62]	79428	1			T3	3		T6	4		T7	4
valid_sources[0x63]	24519	1			T3	2		T5	5		T6	7
valid_sources[0x64]	24187	1			T2	1		T3	12		T5	4
valid_sources[0x65]	23112	1			T6	11		T7	3		T9	46
valid_sources[0x66]	22480	1			T3	2		T5	12		T6	8
valid_sources[0x67]	24026	1			T3	13		T5	3		T6	4
valid_sources[0x68]	18870	1			T3	2		T5	12		T6	2
valid_sources[0x69]	20288	1			T3	7		T6	15		T7	7
valid_sources[0x6a]	24578	1			T3	3		T5	7		T6	6
valid_sources[0x6b]	20299	1			T3	17		T5	3		T6	10
valid_sources[0x6c]	20975	1			T3	5		T5	14		T6	2
valid_sources[0x6d]	23331	1			T3	3		T6	4		T7	3
valid_sources[0x6e]	19105	1			T5	3		T6	3		T7	4
valid_sources[0x6f]	20878	1			T3	5		T5	4		T6	8
valid_sources[0x70]	24162	1			T2	2		T5	6		T6	5
valid_sources[0x71]	19322	1			T3	2		T5	4		T6	2
valid_sources[0x72]	22976	1			T5	6		T6	4		T7	2
valid_sources[0x73]	19651	1			T3	3		T5	1		T6	6
valid_sources[0x74]	18469	1			T2	3		T3	4		T6	5
valid_sources[0x75]	19990	1			T3	5		T5	5		T6	5
valid_sources[0x76]	20461	1			T3	2		T6	7		T7	3
valid_sources[0x77]	18714	1			T3	3		T5	8		T6	4
valid_sources[0x78]	19341	1			T3	2		T6	2		T7	4
valid_sources[0x79]	20950	1			T3	3		T6	5		T7	3
valid_sources[0x7a]	19698	1			T3	1		T5	16		T6	4
valid_sources[0x7b]	36115	1			T3	10		T6	6		T7	2
valid_sources[0x7c]	19878	1			T3	9		T5	2		T6	9
valid_sources[0x7d]	19143	1			T2	1		T3	2		T5	2
valid_sources[0x7e]	19398	1			T3	6		T5	6		T6	3
valid_sources[0x7f]	23399	1			T3	7		T6	6		T7	6
valid_sources[0x80]	22099	1			T2	3		T3	6		T6	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2010455

1

T2

1

T3

431

T4

152

values[0x0]

all_enables

biggest_size

279506

1

T1

2

T2

10

T3

31

values[0x1]

all_enables

biggest_size

217259

1

T1

2

T2

8

T3

26

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25269	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

470732

1

T3

20

T5

20

T8

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	162683	1			T3	10		T5	10		T8	10
values[0x0]	162161	1			T3	4		T5	6		T8	9
values[0x1]	171157	1			T3	6		T5	4		T8	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14123	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

481878

1

T3

20

T5

20

T8

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1907	1			T106	1		T88	2		T156	1
valid_sources[0x01]	1710	1			T97	1		T106	2		T113	2
valid_sources[0x02]	2072	1			T25	1		T130	6		T88	3
valid_sources[0x03]	1753	1			T106	3		T88	1		T157	1
valid_sources[0x04]	1966	1			T123	1		T144	1		T377	1
valid_sources[0x05]	1508	1			T13	1		T120	1		T121	2
valid_sources[0x06]	1635	1			T8	1		T13	4		T106	1
valid_sources[0x07]	1691	1			T13	1		T117	2		T123	1
valid_sources[0x08]	1680	1			T13	2		T117	5		T120	1
valid_sources[0x09]	2412	1			T129	3		T106	1		T131	1
valid_sources[0x0a]	1676	1			T9	4		T106	1		T121	1
valid_sources[0x0b]	1873	1			T97	2		T129	1		T106	2
valid_sources[0x0c]	1922	1			T13	1		T95	1		T106	1
valid_sources[0x0d]	1993	1			T106	1		T117	5		T199	6
valid_sources[0x0e]	1978	1			T13	1		T95	1		T106	2
valid_sources[0x0f]	1612	1			T88	3		T122	1		T102	1
valid_sources[0x10]	1789	1			T96	1		T123	1		T407	1
valid_sources[0x11]	1759	1			T13	1		T117	1		T99	1
valid_sources[0x12]	1798	1			T25	3		T174	1		T100	3
valid_sources[0x13]	1756	1			T8	5		T13	1		T106	1
valid_sources[0x14]	2070	1			T7	3		T106	1		T120	1
valid_sources[0x15]	1826	1			T9	3		T125	2		T199	3
valid_sources[0x16]	1798	1			T117	6		T103	11		T156	2
valid_sources[0x17]	2129	1			T13	1		T106	3		T102	1
valid_sources[0x18]	2073	1			T121	1		T123	1		T156	7
valid_sources[0x19]	2092	1			T13	1		T106	1		T120	1
valid_sources[0x1a]	1745	1			T9	1		T132	1		T117	1
valid_sources[0x1b]	1752	1			T132	7		T88	1		T51	1
valid_sources[0x1c]	1636	1			T13	1		T97	1		T122	1
valid_sources[0x1d]	2525	1			T106	3		T113	4		T96	3
valid_sources[0x1e]	1951	1			T13	1		T106	1		T131	3
valid_sources[0x1f]	3064	1			T13	1		T106	1		T119	3
valid_sources[0x20]	1642	1			T13	1		T10	3		T88	1
valid_sources[0x21]	1854	1			T13	1		T130	1		T106	1
valid_sources[0x22]	1915	1			T106	2		T88	1		T102	1
valid_sources[0x23]	1904	1			T8	1		T13	1		T25	2
valid_sources[0x24]	3215	1			T13	3		T119	3		T120	1
valid_sources[0x25]	1941	1			T9	5		T96	1		T99	1
valid_sources[0x26]	2427	1			T9	8		T106	1		T144	5
valid_sources[0x27]	1759	1			T106	1		T96	2		T99	1
valid_sources[0x28]	1932	1			T9	3		T106	1		T88	1
valid_sources[0x29]	1695	1			T106	2		T378	2		T51	7
valid_sources[0x2a]	2139	1			T13	1		T96	3		T102	1
valid_sources[0x2b]	1615	1			T13	1		T106	1		T132	5
valid_sources[0x2c]	2315	1			T13	1		T106	3		T113	6
valid_sources[0x2d]	1450	1			T13	1		T97	1		T121	1
valid_sources[0x2e]	2019	1			T13	1		T11	3		T121	1
valid_sources[0x2f]	1950	1			T106	1		T96	1		T120	1
valid_sources[0x30]	1860	1			T7	1		T132	1		T88	1
valid_sources[0x31]	2990	1			T106	1		T96	2		T123	1
valid_sources[0x32]	2008	1			T106	2		T113	1		T96	1
valid_sources[0x33]	1891	1			T106	1		T96	2		T102	2
valid_sources[0x34]	1823	1			T13	2		T122	1		T171	2
valid_sources[0x35]	1964	1			T13	1		T113	3		T132	6
valid_sources[0x36]	1532	1			T106	1		T88	1		T120	1
valid_sources[0x37]	2041	1			T130	1		T124	31		T144	3
valid_sources[0x38]	2103	1			T88	1		T102	1		T103	14
valid_sources[0x39]	1785	1			T130	1		T106	1		T102	1
valid_sources[0x3a]	1630	1			T9	6		T13	1		T96	5
valid_sources[0x3b]	2266	1			T106	1		T120	1		T218	3
valid_sources[0x3c]	1794	1			T106	1		T18	11		T64	1
valid_sources[0x3d]	1771	1			T106	1		T113	3		T123	1
valid_sources[0x3e]	2194	1			T9	7		T106	1		T11	1
valid_sources[0x3f]	1890	1			T13	2		T106	1		T88	1
valid_sources[0x40]	1698	1			T13	1		T106	2		T96	1
valid_sources[0x41]	1664	1			T3	1		T106	2		T113	6
valid_sources[0x42]	2078	1			T8	3		T13	2		T106	1
valid_sources[0x43]	2008	1			T97	1		T113	1		T88	3
valid_sources[0x44]	1784	1			T13	1		T106	1		T102	1
valid_sources[0x45]	1949	1			T13	3		T106	1		T122	1
valid_sources[0x46]	1851	1			T106	1		T96	1		T378	1
valid_sources[0x47]	1947	1			T122	1		T102	2		T218	2
valid_sources[0x48]	1711	1			T13	1		T106	1		T102	1
valid_sources[0x49]	1933	1			T13	3		T88	2		T117	8
valid_sources[0x4a]	1824	1			T13	2		T97	2		T130	1
valid_sources[0x4b]	1808	1			T113	8		T131	1		T120	2
valid_sources[0x4c]	2736	1			T13	3		T131	1		T96	3
valid_sources[0x4d]	2260	1			T13	1		T97	2		T106	1
valid_sources[0x4e]	1730	1			T13	2		T106	1		T88	1
valid_sources[0x4f]	1557	1			T13	2		T88	1		T102	1
valid_sources[0x50]	1910	1			T13	1		T106	2		T88	1
valid_sources[0x51]	1891	1			T99	3		T219	1		T299	1
valid_sources[0x52]	1734	1			T13	2		T106	1		T11	1
valid_sources[0x53]	1624	1			T7	1		T106	2		T378	1
valid_sources[0x54]	1800	1			T9	13		T13	4		T106	1
valid_sources[0x55]	1851	1			T106	1		T132	1		T88	1
valid_sources[0x56]	1467	1			T13	1		T106	2		T113	2
valid_sources[0x57]	1604	1			T9	4		T88	2		T102	1
valid_sources[0x58]	2464	1			T106	1		T103	2		T115	2
valid_sources[0x59]	1927	1			T13	1		T106	1		T122	2
valid_sources[0x5a]	2053	1			T96	2		T120	1		T122	1
valid_sources[0x5b]	1850	1			T13	2		T106	1		T88	2
valid_sources[0x5c]	1999	1			T9	2		T13	2		T130	1
valid_sources[0x5d]	1553	1			T13	1		T96	2		T88	1
valid_sources[0x5e]	1926	1			T106	1		T121	1		T199	6
valid_sources[0x5f]	2107	1			T13	1		T96	5		T123	1
valid_sources[0x60]	1901	1			T117	3		T102	1		T318	4
valid_sources[0x61]	1821	1			T3	2		T106	1		T131	4
valid_sources[0x62]	1795	1			T9	16		T131	1		T218	2
valid_sources[0x63]	2147	1			T25	1		T106	2		T132	6
valid_sources[0x64]	1782	1			T13	2		T113	2		T117	1
valid_sources[0x65]	1649	1			T13	1		T120	1		T102	2
valid_sources[0x66]	3423	1			T106	1		T96	1		T88	1
valid_sources[0x67]	1914	1			T13	2		T95	4		T106	1
valid_sources[0x68]	1742	1			T13	1		T97	1		T99	1
valid_sources[0x69]	1866	1			T106	2		T117	4		T120	1
valid_sources[0x6a]	1826	1			T106	1		T99	2		T156	1
valid_sources[0x6b]	1989	1			T96	3		T117	2		T99	1
valid_sources[0x6c]	2005	1			T102	1		T156	6		T51	1
valid_sources[0x6d]	1898	1			T13	1		T106	1		T117	1
valid_sources[0x6e]	2296	1			T13	1		T10	6		T117	8
valid_sources[0x6f]	1764	1			T9	6		T13	3		T106	1
valid_sources[0x70]	2206	1			T13	2		T25	1		T130	4
valid_sources[0x71]	1922	1			T106	1		T117	5		T90	140
valid_sources[0x72]	1907	1			T3	1		T13	1		T97	1
valid_sources[0x73]	1754	1			T106	2		T88	2		T120	1
valid_sources[0x74]	2200	1			T13	3		T106	1		T116	140
valid_sources[0x75]	1743	1			T106	2		T131	2		T88	2
valid_sources[0x76]	1719	1			T106	3		T96	3		T88	1
valid_sources[0x77]	1957	1			T106	1		T132	1		T96	1
valid_sources[0x78]	2114	1			T13	3		T171	2		T144	3
valid_sources[0x79]	1838	1			T113	1		T132	5		T120	1
valid_sources[0x7a]	2240	1			T13	1		T106	3		T120	1
valid_sources[0x7b]	1846	1			T113	3		T88	1		T120	1
valid_sources[0x7c]	1669	1			T13	2		T96	2		T88	1
valid_sources[0x7d]	2317	1			T8	1		T106	3		T99	1
valid_sources[0x7e]	2253	1			T95	1		T106	1		T102	2
valid_sources[0x7f]	1942	1			T117	3		T99	1		T157	3
valid_sources[0x80]	1909	1			T120	1		T122	1		T103	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

149476

1

T3

10

T5

10

T8

10

values[0x0]

all_enables

biggest_size

160702

1

T3

4

T5

6

T8

9

values[0x1]

all_enables

biggest_size

160554

1

T3

6

T5

4

T8

1