Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5123047

1

T1

15

T2

52

T3

706

full_word

2549374

1

T1

4

T2

19

T3

488

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7672111	1			T1	19		T2	71		T3	1194
auto[TlIntgErrCmd]	100	1			T302	4		T303	1		T304	2
auto[TlIntgErrData]	116	1			T302	2		T303	6		T304	5
auto[TlIntgErrBoth]	94	1			T302	4		T303	3		T304	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5926321

1

T1

4

T2

1

T3

1041

auto[1]

1746100

1

T1

15

T2

70

T3

153

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3910728	1			T1	4		T3	610		T4	753
auto[TlIntgErrNone]	partial	auto[1]	1212036	1			T1	11		T2	52		T3	96
auto[TlIntgErrNone]	full_word	auto[0]	2015445	1			T2	1		T3	431		T4	152
auto[TlIntgErrNone]	full_word	auto[1]	533902	1			T1	4		T2	18		T3	57
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T302	2		T303	1		T315	3
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T302	2		T304	2		T316	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T400	1		T312	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T398	2		T397	3		T401	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T302	2		T303	3		T304	1
auto[TlIntgErrData]	partial	auto[1]	49	1			T303	3		T304	4		T315	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T402	1		T394	1		T396	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T315	1		T310	1		T398	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T302	1		T303	1		T304	3
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T302	3		T303	2		T402	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T392	1		T393	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T316	1		T397	1		T403	3