Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.01	94.16	95.24	97.06		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	95416315	319204	0	0
check_regwen_rd_A	95416315	2241	0	0
check_timeout_rd_A	95416315	1448	0	0
check_trigger_regwen_rd_A	95416315	2097	0	0
consistency_check_period_rd_A	95416315	2241	0	0
creator_sw_cfg_read_lock_rd_A	95416315	1434	0	0
direct_access_address_rd_A	95416315	443	0	0
direct_access_wdata_0_rd_A	95416315	52	0	0
direct_access_wdata_1_rd_A	95416315	74	0	0
integrity_check_period_rd_A	95416315	2209	0	0
intr_enable_rd_A	95416315	2728	0	0
owner_sw_cfg_read_lock_rd_A	95416315	1328	0	0
rot_creator_auth_codesign_read_lock_rd_A	95416315	1388	0	0
rot_creator_auth_state_read_lock_rd_A	95416315	1421	0	0
vendor_test_read_lock_rd_A	95416315	1269	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95416315	319204	0	0
T14	189208	3415	0	0
T15	0	4038	0	0
T16	0	1044	0	0
T20	0	7082	0	0
T21	0	5851	0	0
T22	0	4662	0	0
T26	0	3441	0	0
T50	137127	0	0	0
T92	0	2588	0	0
T93	0	13104	0	0
T94	0	8868	0	0
T135	14317	0	0	0
T217	63590	0	0	0
T285	29017	0	0	0
T321	13873	0	0	0
T322	22370	0	0	0
T323	4450	0	0	0
T324	16477	0	0	0
T325	60237	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95416315	2241	0	0
T14	189208	32	0	0
T21	0	18	0	0
T22	0	6	0	0
T23	0	29	0	0
T50	137127	0	0	0
T135	14317	0	0	0
T217	63590	0	0	0
T285	29017	0	0	0
T321	13873	0	0	0
T322	22370	0	0	0
T323	4450	0	0	0
T324	16477	0	0	0
T325	60237	0	0	0
T360	0	16	0	0
T361	0	25	0	0
T362	0	13	0	0
T363	0	16	0	0
T364	0	30	0	0
T365	0	13	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95416315	1448	0	0
T14	189208	21	0	0
T21	0	18	0	0
T22	0	10	0	0
T23	0	21	0	0
T50	137127	0	0	0
T135	14317	0	0	0
T217	63590	0	0	0
T285	29017	0	0	0
T321	13873	0	0	0
T322	22370	0	0	0
T323	4450	0	0	0
T324	16477	0	0	0
T325	60237	0	0	0
T360	0	28	0	0
T361	0	34	0	0
T362	0	22	0	0
T363	0	27	0	0
T364	0	15	0	0
T365	0	9	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95416315	2097	0	0
T14	189208	22	0	0
T21	0	13	0	0
T22	0	19	0	0
T23	0	24	0	0
T50	137127	0	0	0
T135	14317	0	0	0
T217	63590	0	0	0
T285	29017	0	0	0
T321	13873	0	0	0
T322	22370	0	0	0
T323	4450	0	0	0
T324	16477	0	0	0
T325	60237	0	0	0
T360	0	28	0	0
T361	0	24	0	0
T362	0	18	0	0
T363	0	25	0	0
T364	0	28	0	0
T365	0	15	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95416315	2241	0	0
T14	189208	25	0	0
T21	0	1	0	0
T22	0	29	0	0
T23	0	16	0	0
T50	137127	0	0	0
T135	14317	0	0	0
T217	63590	0	0	0
T285	29017	0	0	0
T321	13873	0	0	0
T322	22370	0	0	0
T323	4450	0	0	0
T324	16477	0	0	0
T325	60237	0	0	0
T360	0	24	0	0
T361	0	30	0	0
T362	0	17	0	0
T363	0	19	0	0
T364	0	36	0	0
T365	0	17	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95416315	1434	0	0
T14	189208	31	0	0
T21	0	23	0	0
T22	0	4	0	0
T23	0	15	0	0
T50	137127	0	0	0
T135	14317	0	0	0
T217	63590	0	0	0
T285	29017	0	0	0
T321	13873	0	0	0
T322	22370	0	0	0
T323	4450	0	0	0
T324	16477	0	0	0
T325	60237	0	0	0
T360	0	15	0	0
T361	0	22	0	0
T362	0	20	0	0
T363	0	15	0	0
T364	0	19	0	0
T365	0	12	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95416315	443	0	0
T14	189208	23	0	0
T21	0	20	0	0
T22	0	19	0	0
T23	0	14	0	0
T50	137127	0	0	0
T135	14317	0	0	0
T217	63590	0	0	0
T285	29017	0	0	0
T321	13873	0	0	0
T322	22370	0	0	0
T323	4450	0	0	0
T324	16477	0	0	0
T325	60237	0	0	0
T360	0	42	0	0
T361	0	21	0	0
T362	0	25	0	0
T363	0	22	0	0
T364	0	24	0	0
T365	0	10	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95416315	52	0	0
T14	189208	13	0	0
T50	137127	0	0	0
T135	14317	0	0	0
T217	63590	0	0	0
T285	29017	0	0	0
T321	13873	0	0	0
T322	22370	0	0	0
T323	4450	0	0	0
T324	16477	0	0	0
T325	60237	0	0	0
T360	0	5	0	0
T364	0	16	0	0
T366	0	8	0	0
T367	0	6	0	0
T368	0	4	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95416315	74	0	0
T14	189208	1	0	0
T21	0	8	0	0
T50	137127	0	0	0
T135	14317	0	0	0
T217	63590	0	0	0
T250	0	5	0	0
T285	29017	0	0	0
T321	13873	0	0	0
T322	22370	0	0	0
T323	4450	0	0	0
T324	16477	0	0	0
T325	60237	0	0	0
T363	0	7	0	0
T366	0	1	0	0
T368	0	18	0	0
T369	0	11	0	0
T370	0	9	0	0
T371	0	1	0	0
T372	0	13	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95416315	2209	0	0
T14	189208	26	0	0
T21	0	19	0	0
T22	0	13	0	0
T23	0	29	0	0
T50	137127	0	0	0
T135	14317	0	0	0
T217	63590	0	0	0
T285	29017	0	0	0
T321	13873	0	0	0
T322	22370	0	0	0
T323	4450	0	0	0
T324	16477	0	0	0
T325	60237	0	0	0
T360	0	21	0	0
T361	0	16	0	0
T362	0	21	0	0
T363	0	11	0	0
T364	0	27	0	0
T365	0	18	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95416315	2728	0	0
T14	189208	75	0	0
T21	0	12	0	0
T22	0	6	0	0
T23	0	45	0	0
T50	137127	0	0	0
T135	14317	0	0	0
T143	0	4	0	0
T217	63590	0	0	0
T246	0	40	0	0
T265	0	2	0	0
T285	29017	0	0	0
T321	13873	0	0	0
T322	22370	0	0	0
T323	4450	0	0	0
T324	16477	0	0	0
T325	60237	0	0	0
T360	0	35	0	0
T373	0	23	0	0
T374	0	27	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95416315	1328	0	0
T14	189208	27	0	0
T21	0	8	0	0
T22	0	7	0	0
T23	0	14	0	0
T50	137127	0	0	0
T135	14317	0	0	0
T217	63590	0	0	0
T285	29017	0	0	0
T321	13873	0	0	0
T322	22370	0	0	0
T323	4450	0	0	0
T324	16477	0	0	0
T325	60237	0	0	0
T360	0	28	0	0
T361	0	19	0	0
T362	0	16	0	0
T363	0	21	0	0
T364	0	9	0	0
T365	0	10	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95416315	1388	0	0
T14	189208	27	0	0
T21	0	17	0	0
T22	0	14	0	0
T23	0	26	0	0
T50	137127	0	0	0
T135	14317	0	0	0
T217	63590	0	0	0
T285	29017	0	0	0
T321	13873	0	0	0
T322	22370	0	0	0
T323	4450	0	0	0
T324	16477	0	0	0
T325	60237	0	0	0
T360	0	31	0	0
T361	0	13	0	0
T362	0	19	0	0
T363	0	16	0	0
T364	0	24	0	0
T365	0	13	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95416315	1421	0	0
T14	189208	14	0	0
T21	0	24	0	0
T22	0	7	0	0
T23	0	21	0	0
T50	137127	0	0	0
T135	14317	0	0	0
T217	63590	0	0	0
T285	29017	0	0	0
T321	13873	0	0	0
T322	22370	0	0	0
T323	4450	0	0	0
T324	16477	0	0	0
T325	60237	0	0	0
T360	0	28	0	0
T361	0	21	0	0
T362	0	22	0	0
T363	0	11	0	0
T364	0	12	0	0
T365	0	8	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95416315	1269	0	0
T14	189208	24	0	0
T21	0	7	0	0
T22	0	12	0	0
T23	0	20	0	0
T50	137127	0	0	0
T135	14317	0	0	0
T217	63590	0	0	0
T285	29017	0	0	0
T321	13873	0	0	0
T322	22370	0	0	0
T323	4450	0	0	0
T324	16477	0	0	0
T325	60237	0	0	0
T360	0	15	0	0
T361	0	27	0	0
T362	0	15	0	0
T363	0	26	0	0
T364	0	14	0	0
T365	0	14	0	0