Line Coverage for Module :
prim_edn_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 6 | 6 | 100.00 |
| CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| ALWAYS | 143 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
| ALWAYS | 163 | 0 | 0 | |
53 logic word_req, word_ack;
54 1/1 assign word_req = req_i & ~ack_o;
Tests: T1 T2 T3
55
56 logic [edn_pkg::ENDPOINT_BUS_WIDTH-1:0] word_data;
57 logic word_fips;
58 localparam int SyncWidth = $bits({edn_i.edn_fips, edn_i.edn_bus});
59 prim_sync_reqack_data #(
60 .Width(SyncWidth),
61 .EnRstChks(EnRstChks),
62 .DataSrc2Dst(1'b0),
63 .DataReg(1'b0)
64 ) u_prim_sync_reqack_data (
65 .clk_src_i ( clk_i ),
66 .rst_src_ni ( rst_ni ),
67 .clk_dst_i ( clk_edn_i ),
68 .rst_dst_ni ( rst_edn_ni ),
69 .req_chk_i ( req_chk_i ),
70 .src_req_i ( word_req ),
71 .src_ack_o ( word_ack ),
72 .dst_req_o ( edn_o.edn_req ),
73 .dst_ack_i ( edn_i.edn_ack ),
74 .data_i ( {edn_i.edn_fips, edn_i.edn_bus} ),
75 .data_o ( {word_fips, word_data} )
76 );
77
78 if (RepCheck) begin : gen_rep_chk
79 logic [edn_pkg::ENDPOINT_BUS_WIDTH-1:0] word_data_q;
80 always_ff @(posedge clk_i) begin
81 if (word_ack) begin
82 word_data_q <= word_data;
83 end
84 end
85
86 // do not check until we have received at least the first entry
87 logic chk_rep;
88 always_ff @(posedge clk_i or negedge rst_ni) begin
89 if (!rst_ni) begin
90 chk_rep <= '0;
91 end else if (word_ack) begin
92 chk_rep <= 1'b1;
93 end
94 end
95
96 // Need to track if any of the packed words has failed the repetition check, i.e., is identical
97 // to the last packed word.
98 logic err_d, err_q;
99 assign err_d = (req_i && ack_o) ? 1'b0 : // clear
100 (chk_rep && word_ack && word_data == word_data_q) ? 1'b1 : // set
101 err_q; // keep
102 always_ff @(posedge clk_i or negedge rst_ni) begin
103 if (!rst_ni) begin
104 err_q <= 1'b0;
105 end else begin
106 err_q <= err_d;
107 end
108 end
109 assign err_o = err_q;
110
111 end else begin : gen_no_rep_chk // block: gen_rep_chk
112 assign err_o = '0;
113 end
114
115 prim_packer_fifo #(
116 .InW(edn_pkg::ENDPOINT_BUS_WIDTH),
117 .OutW(OutWidth),
118 .ClearOnRead(1'b0)
119 ) u_prim_packer_fifo (
120 .clk_i,
121 .rst_ni,
122 .clr_i ( 1'b0 ), // not needed
123 .wvalid_i ( word_ack ),
124 .wdata_i ( word_data ),
125 // no need for backpressure since we're always ready to
126 // sink data at this point.
127 .wready_o ( ),
128 .rvalid_o ( ack_o ),
129 .rdata_o ( data_o ),
130 // we're always ready to receive the packed output word
131 // at this point.
132 .rready_i ( 1'b1 ),
133 .depth_o ( )
134 );
135
136 // Need to track if any of the packed words has been generated with a pre-FIPS seed, i.e., has
137 // fips == 1'b0.
138 logic fips_d, fips_q;
139 1/1 assign fips_d = (req_i && ack_o) ? 1'b1 : // clear
Tests: T1 T2 T3
140 (word_ack) ? fips_q & word_fips : // accumulate
141 fips_q; // keep
142 always_ff @(posedge clk_i or negedge rst_ni) begin
143 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
144 1/1 fips_q <= 1'b1;
Tests: T1 T2 T3
145 end else begin
146 1/1 fips_q <= fips_d;
Tests: T1 T2 T3
147 end
148 end
149 1/1 assign fips_o = fips_q;
Tests: T1 T2 T3
150
151 ////////////////
152 // Assertions //
153 ////////////////
154
155 // Check EDN data is valid: Not all zeros, all ones, or not the same as previous data.
156 `ifdef INC_ASSERT
157 //VCS coverage off
158 // pragma coverage off
159
160 logic [OutWidth-1:0] data_prev, data_curr;
161
162 always_ff @(posedge ack_o or negedge rst_ni) begin
163 unreachable if (!rst_ni) begin
164 unreachable data_prev <= '0;
165 unreachable data_curr <= '0;
166 unreachable end else if (ack_o) begin
167 unreachable data_curr <= data_o;
168 unreachable data_prev <= data_curr;
169 end
==> MISSING_ELSE
Cond Coverage for Module :
prim_edn_req
| Total | Covered | Percent |
|---|
| Conditions | 13 | 12 | 92.31 |
| Logical | 13 | 12 | 92.31 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 54
EXPRESSION (req_i & ((~ack_o)))
--1-- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T5,T8,T9 |
| 1 | 1 | Covered | T5,T8,T9 |
LINE 139
EXPRESSION ((req_i && ack_o) ? 1'b1 : (word_ack ? (fips_q & word_fips) : fips_q))
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T8,T9 |
LINE 139
SUB-EXPRESSION (req_i && ack_o)
--1-- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T5,T8,T9 |
| 1 | 1 | Covered | T5,T8,T9 |
LINE 139
SUB-EXPRESSION (word_ack ? (fips_q & word_fips) : fips_q)
----1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T8,T9 |
LINE 139
SUB-EXPRESSION (fips_q & word_fips)
---1-- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T8,T9 |
| 1 | 0 | Covered | T5,T8,T9 |
| 1 | 1 | Covered | T5,T8,T9 |
Branch Coverage for Module :
prim_edn_req
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
139 |
3 |
3 |
100.00 |
| IF |
143 |
2 |
2 |
100.00 |
139 assign fips_d = (req_i && ack_o) ? 1'b1 : // clear
-1-
==>
140 (word_ack) ? fips_q & word_fips : // accumulate
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T5,T8,T9 |
| 0 |
1 |
Covered |
T5,T8,T9 |
| 0 |
0 |
Covered |
T1,T2,T3 |
143 if (!rst_ni) begin
-1-
144 fips_q <= 1'b1;
==>
145 end else begin
146 fips_q <= fips_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_edn_req
Assertion Details
DataOutputDiffFromPrev_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
40260877 |
0 |
0 |
| T5 |
13096 |
3111 |
0 |
0 |
| T6 |
10777 |
0 |
0 |
0 |
| T7 |
11887 |
0 |
0 |
0 |
| T8 |
14599 |
3119 |
0 |
0 |
| T9 |
86346 |
21506 |
0 |
0 |
| T10 |
0 |
15198 |
0 |
0 |
| T13 |
30320 |
0 |
0 |
0 |
| T17 |
5523 |
0 |
0 |
0 |
| T25 |
65064 |
48676 |
0 |
0 |
| T91 |
10687 |
0 |
0 |
0 |
| T95 |
0 |
5378 |
0 |
0 |
| T112 |
4712 |
0 |
0 |
0 |
| T113 |
0 |
17165 |
0 |
0 |
| T130 |
0 |
8281 |
0 |
0 |
| T131 |
0 |
23758 |
0 |
0 |
| T132 |
0 |
6449 |
0 |
0 |
DataOutputValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
214472 |
0 |
0 |
| T5 |
13096 |
47 |
0 |
0 |
| T6 |
10777 |
0 |
0 |
0 |
| T7 |
11887 |
0 |
0 |
0 |
| T8 |
14599 |
47 |
0 |
0 |
| T9 |
86346 |
319 |
0 |
0 |
| T10 |
0 |
47 |
0 |
0 |
| T13 |
30320 |
0 |
0 |
0 |
| T17 |
5523 |
0 |
0 |
0 |
| T25 |
65064 |
66 |
0 |
0 |
| T91 |
10687 |
0 |
0 |
0 |
| T95 |
0 |
47 |
0 |
0 |
| T112 |
4712 |
0 |
0 |
0 |
| T113 |
0 |
307 |
0 |
0 |
| T130 |
0 |
167 |
0 |
0 |
| T131 |
0 |
93 |
0 |
0 |
| T132 |
0 |
90 |
0 |
0 |
