Line Coverage for Module :
prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Line Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T3 T4 T5
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T3 T4 T5
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T3 T4 T5
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Line Coverage for Module :
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T3 T4 T5
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T3 T4 T5
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T3 T4 T5
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Line Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T3 T4 T5
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T3 T4 T5
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Line Coverage for Module :
prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T2 T3
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 11 | 68.75 |
| Logical | 16 | 11 | 68.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T3,T4,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T3,T4,T5 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T4,T5 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 24 | 18 | 75.00 |
| Logical | 24 | 18 | 75.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T13,T25 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T3,T4,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T3,T9,T13 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T4,T5 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T3,T4,T5 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T13,T25 |
| 1 | 0 | Covered | T3,T4,T5 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T4,T5 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 11 | 68.75 |
| Logical | 16 | 11 | 68.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T3,T4,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T3,T4,T5 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T4,T5 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 24 | 18 | 75.00 |
| Logical | 24 | 18 | 75.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
9 |
9 |
100.00 |
| TERNARY |
130 |
2 |
2 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T3,T4,T5 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
941984554 |
61614983 |
0 |
0 |
| T1 |
23565 |
1650 |
0 |
0 |
| T2 |
21765 |
1220 |
0 |
0 |
| T3 |
128900 |
6701 |
0 |
0 |
| T4 |
99190 |
7948 |
0 |
0 |
| T5 |
130960 |
8486 |
0 |
0 |
| T6 |
107770 |
8128 |
0 |
0 |
| T7 |
118870 |
9344 |
0 |
0 |
| T8 |
145990 |
13007 |
0 |
0 |
| T9 |
863460 |
49482 |
0 |
0 |
| T13 |
303200 |
25251 |
0 |
0 |
| T17 |
27615 |
0 |
0 |
0 |
| T25 |
0 |
210 |
0 |
0 |
| T91 |
0 |
69 |
0 |
0 |
| T97 |
0 |
46 |
0 |
0 |
| T112 |
23560 |
0 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
941984554 |
932932440 |
0 |
0 |
| T1 |
47130 |
46580 |
0 |
0 |
| T2 |
43530 |
43010 |
0 |
0 |
| T3 |
128900 |
121870 |
0 |
0 |
| T4 |
99190 |
96920 |
0 |
0 |
| T5 |
130960 |
128310 |
0 |
0 |
| T6 |
107770 |
104850 |
0 |
0 |
| T7 |
118870 |
116430 |
0 |
0 |
| T8 |
145990 |
143260 |
0 |
0 |
| T9 |
863460 |
845820 |
0 |
0 |
| T13 |
303200 |
300180 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
941984554 |
932932440 |
0 |
0 |
| T1 |
47130 |
46580 |
0 |
0 |
| T2 |
43530 |
43010 |
0 |
0 |
| T3 |
128900 |
121870 |
0 |
0 |
| T4 |
99190 |
96920 |
0 |
0 |
| T5 |
130960 |
128310 |
0 |
0 |
| T6 |
107770 |
104850 |
0 |
0 |
| T7 |
118870 |
116430 |
0 |
0 |
| T8 |
145990 |
143260 |
0 |
0 |
| T9 |
863460 |
845820 |
0 |
0 |
| T13 |
303200 |
300180 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
941984554 |
932932440 |
0 |
0 |
| T1 |
47130 |
46580 |
0 |
0 |
| T2 |
43530 |
43010 |
0 |
0 |
| T3 |
128900 |
121870 |
0 |
0 |
| T4 |
99190 |
96920 |
0 |
0 |
| T5 |
130960 |
128310 |
0 |
0 |
| T6 |
107770 |
104850 |
0 |
0 |
| T7 |
118870 |
116430 |
0 |
0 |
| T8 |
145990 |
143260 |
0 |
0 |
| T9 |
863460 |
845820 |
0 |
0 |
| T13 |
303200 |
300180 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
941984554 |
932932440 |
0 |
0 |
| T1 |
47130 |
46580 |
0 |
0 |
| T2 |
43530 |
43010 |
0 |
0 |
| T3 |
128900 |
121870 |
0 |
0 |
| T4 |
99190 |
96920 |
0 |
0 |
| T5 |
130960 |
128310 |
0 |
0 |
| T6 |
107770 |
104850 |
0 |
0 |
| T7 |
118870 |
116430 |
0 |
0 |
| T8 |
145990 |
143260 |
0 |
0 |
| T9 |
863460 |
845820 |
0 |
0 |
| T13 |
303200 |
300180 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
369486664 |
17223203 |
0 |
0 |
| T1 |
4713 |
1574 |
0 |
0 |
| T2 |
4353 |
936 |
0 |
0 |
| T3 |
51560 |
1893 |
0 |
0 |
| T4 |
39676 |
3204 |
0 |
0 |
| T5 |
52384 |
4310 |
0 |
0 |
| T6 |
43108 |
3172 |
0 |
0 |
| T7 |
47548 |
4424 |
0 |
0 |
| T8 |
58396 |
3759 |
0 |
0 |
| T9 |
345384 |
23558 |
0 |
0 |
| T13 |
121280 |
3793 |
0 |
0 |
| T17 |
16569 |
0 |
0 |
0 |
| T25 |
0 |
174 |
0 |
0 |
| T91 |
0 |
63 |
0 |
0 |
| T97 |
0 |
42 |
0 |
0 |
| T112 |
14136 |
0 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
7776 |
7776 |
0 |
0 |
| T1 |
6 |
6 |
0 |
0 |
| T2 |
6 |
6 |
0 |
0 |
| T3 |
6 |
6 |
0 |
0 |
| T4 |
6 |
6 |
0 |
0 |
| T5 |
6 |
6 |
0 |
0 |
| T6 |
6 |
6 |
0 |
0 |
| T7 |
6 |
6 |
0 |
0 |
| T8 |
6 |
6 |
0 |
0 |
| T9 |
6 |
6 |
0 |
0 |
| T13 |
6 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
9070085 |
0 |
0 |
| T1 |
4713 |
19 |
0 |
0 |
| T2 |
4353 |
71 |
0 |
0 |
| T3 |
12890 |
1194 |
0 |
0 |
| T4 |
9919 |
1186 |
0 |
0 |
| T5 |
13096 |
1044 |
0 |
0 |
| T6 |
10777 |
1239 |
0 |
0 |
| T7 |
11887 |
1230 |
0 |
0 |
| T8 |
14599 |
2312 |
0 |
0 |
| T9 |
86346 |
6481 |
0 |
0 |
| T13 |
30320 |
1945 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1296 |
1296 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
13372029 |
0 |
0 |
| T1 |
4713 |
19 |
0 |
0 |
| T2 |
4353 |
71 |
0 |
0 |
| T3 |
12890 |
1210 |
0 |
0 |
| T4 |
9919 |
1186 |
0 |
0 |
| T5 |
13096 |
1044 |
0 |
0 |
| T6 |
10777 |
1239 |
0 |
0 |
| T7 |
11887 |
1230 |
0 |
0 |
| T8 |
14599 |
2312 |
0 |
0 |
| T9 |
86346 |
6481 |
0 |
0 |
| T13 |
30320 |
8784 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1296 |
1296 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
1141341 |
0 |
0 |
| T3 |
12890 |
9 |
0 |
0 |
| T4 |
9919 |
26 |
0 |
0 |
| T5 |
13096 |
4 |
0 |
0 |
| T6 |
10777 |
24 |
0 |
0 |
| T7 |
11887 |
0 |
0 |
0 |
| T8 |
14599 |
13 |
0 |
0 |
| T9 |
86346 |
18 |
0 |
0 |
| T13 |
30320 |
14 |
0 |
0 |
| T17 |
5523 |
0 |
0 |
0 |
| T25 |
0 |
6 |
0 |
0 |
| T91 |
0 |
3 |
0 |
0 |
| T97 |
0 |
2 |
0 |
0 |
| T112 |
4712 |
0 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1296 |
1296 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
1030254 |
0 |
0 |
| T3 |
12890 |
25 |
0 |
0 |
| T4 |
9919 |
26 |
0 |
0 |
| T5 |
13096 |
4 |
0 |
0 |
| T6 |
10777 |
24 |
0 |
0 |
| T7 |
11887 |
0 |
0 |
0 |
| T8 |
14599 |
13 |
0 |
0 |
| T9 |
86346 |
18 |
0 |
0 |
| T13 |
30320 |
61 |
0 |
0 |
| T17 |
5523 |
0 |
0 |
0 |
| T25 |
0 |
30 |
0 |
0 |
| T91 |
0 |
3 |
0 |
0 |
| T97 |
0 |
2 |
0 |
0 |
| T112 |
4712 |
0 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1296 |
1296 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
7436296 |
0 |
0 |
| T1 |
4713 |
19 |
0 |
0 |
| T2 |
4353 |
71 |
0 |
0 |
| T3 |
12890 |
1185 |
0 |
0 |
| T4 |
9919 |
1160 |
0 |
0 |
| T5 |
13096 |
1040 |
0 |
0 |
| T6 |
10777 |
1215 |
0 |
0 |
| T7 |
11887 |
1230 |
0 |
0 |
| T8 |
14599 |
2299 |
0 |
0 |
| T9 |
86346 |
6463 |
0 |
0 |
| T13 |
30320 |
1931 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1296 |
1296 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
12341775 |
0 |
0 |
| T1 |
4713 |
19 |
0 |
0 |
| T2 |
4353 |
71 |
0 |
0 |
| T3 |
12890 |
1185 |
0 |
0 |
| T4 |
9919 |
1160 |
0 |
0 |
| T5 |
13096 |
1040 |
0 |
0 |
| T6 |
10777 |
1215 |
0 |
0 |
| T7 |
11887 |
1230 |
0 |
0 |
| T8 |
14599 |
2299 |
0 |
0 |
| T9 |
86346 |
6463 |
0 |
0 |
| T13 |
30320 |
8723 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95416315 |
94489596 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1296 |
1296 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T3 T4 T5
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T3 T4 T5
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T3 T4 T5
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
| Total | Covered | Percent |
|---|
| Conditions | 11 | 11 | 100.00 |
| Logical | 11 | 11 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T3,T4,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Covered | T3,T4,T5 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T4,T5 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T3,T4,T5 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
1396061 |
0 |
0 |
| T3 |
12890 |
52 |
0 |
0 |
| T4 |
9919 |
260 |
0 |
0 |
| T5 |
13096 |
40 |
0 |
0 |
| T6 |
10777 |
240 |
0 |
0 |
| T7 |
11887 |
0 |
0 |
0 |
| T8 |
14599 |
130 |
0 |
0 |
| T9 |
86346 |
56 |
0 |
0 |
| T13 |
30320 |
79 |
0 |
0 |
| T17 |
5523 |
0 |
0 |
0 |
| T25 |
0 |
84 |
0 |
0 |
| T91 |
0 |
30 |
0 |
0 |
| T97 |
0 |
20 |
0 |
0 |
| T112 |
4712 |
0 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
91498716 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
91498716 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
91498716 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
91498716 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
1396061 |
0 |
0 |
| T3 |
12890 |
52 |
0 |
0 |
| T4 |
9919 |
260 |
0 |
0 |
| T5 |
13096 |
40 |
0 |
0 |
| T6 |
10777 |
240 |
0 |
0 |
| T7 |
11887 |
0 |
0 |
0 |
| T8 |
14599 |
130 |
0 |
0 |
| T9 |
86346 |
56 |
0 |
0 |
| T13 |
30320 |
79 |
0 |
0 |
| T17 |
5523 |
0 |
0 |
0 |
| T25 |
0 |
84 |
0 |
0 |
| T91 |
0 |
30 |
0 |
0 |
| T97 |
0 |
20 |
0 |
0 |
| T112 |
4712 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T3 T4 T5
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T3 T4 T5
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T3 T4 T5
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
| Total | Covered | Percent |
|---|
| Conditions | 11 | 11 | 100.00 |
| Logical | 11 | 11 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T3,T4,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Covered | T3,T4,T5 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T4,T5 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T3,T4,T5 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
466907 |
0 |
0 |
| T3 |
12890 |
36 |
0 |
0 |
| T4 |
9919 |
260 |
0 |
0 |
| T5 |
13096 |
40 |
0 |
0 |
| T6 |
10777 |
240 |
0 |
0 |
| T7 |
11887 |
0 |
0 |
0 |
| T8 |
14599 |
130 |
0 |
0 |
| T9 |
86346 |
56 |
0 |
0 |
| T13 |
30320 |
32 |
0 |
0 |
| T17 |
5523 |
0 |
0 |
0 |
| T25 |
0 |
60 |
0 |
0 |
| T91 |
0 |
30 |
0 |
0 |
| T97 |
0 |
20 |
0 |
0 |
| T112 |
4712 |
0 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
91498716 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
91498716 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
91498716 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
91498716 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
466907 |
0 |
0 |
| T3 |
12890 |
36 |
0 |
0 |
| T4 |
9919 |
260 |
0 |
0 |
| T5 |
13096 |
40 |
0 |
0 |
| T6 |
10777 |
240 |
0 |
0 |
| T7 |
11887 |
0 |
0 |
0 |
| T8 |
14599 |
130 |
0 |
0 |
| T9 |
86346 |
56 |
0 |
0 |
| T13 |
30320 |
32 |
0 |
0 |
| T17 |
5523 |
0 |
0 |
0 |
| T25 |
0 |
60 |
0 |
0 |
| T91 |
0 |
30 |
0 |
0 |
| T97 |
0 |
20 |
0 |
0 |
| T112 |
4712 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T3 T4 T5
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T3 T4 T5
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
| Total | Covered | Percent |
|---|
| Conditions | 18 | 18 | 100.00 |
| Logical | 18 | 18 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T13,T25 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T3,T4,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Covered | T3,T9,T13 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T4,T5 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T3,T4,T5 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T13,T25 |
| 1 | 0 | Covered | T3,T4,T5 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T4,T5 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
9 |
9 |
100.00 |
| TERNARY |
130 |
2 |
2 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T3,T4,T5 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
174905 |
0 |
0 |
| T3 |
12890 |
25 |
0 |
0 |
| T4 |
9919 |
26 |
0 |
0 |
| T5 |
13096 |
4 |
0 |
0 |
| T6 |
10777 |
24 |
0 |
0 |
| T7 |
11887 |
0 |
0 |
0 |
| T8 |
14599 |
13 |
0 |
0 |
| T9 |
86346 |
18 |
0 |
0 |
| T13 |
30320 |
61 |
0 |
0 |
| T17 |
5523 |
0 |
0 |
0 |
| T25 |
0 |
30 |
0 |
0 |
| T91 |
0 |
3 |
0 |
0 |
| T97 |
0 |
2 |
0 |
0 |
| T112 |
4712 |
0 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
91498716 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
91498716 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
91498716 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
91498716 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
174905 |
0 |
0 |
| T3 |
12890 |
25 |
0 |
0 |
| T4 |
9919 |
26 |
0 |
0 |
| T5 |
13096 |
4 |
0 |
0 |
| T6 |
10777 |
24 |
0 |
0 |
| T7 |
11887 |
0 |
0 |
0 |
| T8 |
14599 |
13 |
0 |
0 |
| T9 |
86346 |
18 |
0 |
0 |
| T13 |
30320 |
61 |
0 |
0 |
| T17 |
5523 |
0 |
0 |
0 |
| T25 |
0 |
30 |
0 |
0 |
| T91 |
0 |
3 |
0 |
0 |
| T97 |
0 |
2 |
0 |
0 |
| T112 |
4712 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_otp_rsp_fifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T2 T3
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp_rsp_fifo
| Total | Covered | Percent |
|---|
| Conditions | 18 | 18 | 100.00 |
| Logical | 18 | 18 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_otp_rsp_fifo
| Line No. | Total | Covered | Percent |
| Branches |
|
9 |
9 |
100.00 |
| TERNARY |
130 |
2 |
2 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_otp_rsp_fifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
15185330 |
0 |
0 |
| T1 |
4713 |
1574 |
0 |
0 |
| T2 |
4353 |
936 |
0 |
0 |
| T3 |
12890 |
1780 |
0 |
0 |
| T4 |
9919 |
2658 |
0 |
0 |
| T5 |
13096 |
4226 |
0 |
0 |
| T6 |
10777 |
2668 |
0 |
0 |
| T7 |
11887 |
4424 |
0 |
0 |
| T8 |
14599 |
3486 |
0 |
0 |
| T9 |
86346 |
23428 |
0 |
0 |
| T13 |
30320 |
3621 |
0 |
0 |
DataKnown_AKnownEnable
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
91498716 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
91498716 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
91498716 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
91498716 |
0 |
0 |
| T1 |
4713 |
4658 |
0 |
0 |
| T2 |
4353 |
4301 |
0 |
0 |
| T3 |
12890 |
12187 |
0 |
0 |
| T4 |
9919 |
9692 |
0 |
0 |
| T5 |
13096 |
12831 |
0 |
0 |
| T6 |
10777 |
10485 |
0 |
0 |
| T7 |
11887 |
11643 |
0 |
0 |
| T8 |
14599 |
14326 |
0 |
0 |
| T9 |
86346 |
84582 |
0 |
0 |
| T13 |
30320 |
30018 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
92371666 |
15185330 |
0 |
0 |
| T1 |
4713 |
1574 |
0 |
0 |
| T2 |
4353 |
936 |
0 |
0 |
| T3 |
12890 |
1780 |
0 |
0 |
| T4 |
9919 |
2658 |
0 |
0 |
| T5 |
13096 |
4226 |
0 |
0 |
| T6 |
10777 |
2668 |
0 |
0 |
| T7 |
11887 |
4424 |
0 |
0 |
| T8 |
14599 |
3486 |
0 |
0 |
| T9 |
86346 |
23428 |
0 |
0 |
| T13 |
30320 |
3621 |
0 |
0 |