Unified Coverage Report :: Module :: prim_secded_inv_72_64_dec

Module : prim_secded_inv_72_64_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	69.12			69.12
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	70.59			70.59
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	70.59			70.59
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	70.59			70.59
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	70.59			70.59
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	70.59			70.59
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	73.53			73.53
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	75.00			75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	76.47			76.47
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	80.88			80.88
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	83.82			83.82
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.12			69.12

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.12			69.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.59			70.59

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.59			70.59

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.59			70.59

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.59			70.59

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.59			70.59

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.59			70.59

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.59			70.59

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.59			70.59

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.59			70.59

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.59			70.59

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.47			76.47

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.47			76.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.88			80.88

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.88			80.88

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.82			83.82

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.82			83.82

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T4,T130,T113	Yes	T4,T130,T113	INPUT
data_o[63:0]	Yes	Yes	T4,T130,T113	Yes	T4,T130,T113	OUTPUT
syndrome_o[2:0]	Yes	Yes	T107,T108,T168	Yes	T107,T108,T168	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T107,*T108,*T168	Yes	T107,T108,T168	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	188	69.12
Total Bits 0->1	136	94	69.12
Total Bits 1->0	136	94	69.12

Ports	2	0	0.00
Port Bits	272	188	69.12
Port Bits 0->1	136	94	69.12
Port Bits 1->0	136	94	69.12

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[6:0]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[8:7]	No	No		No		INPUT
data_i[10:9]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[11]	No	No		No		INPUT
data_i[14:12]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[15]	No	No		No		INPUT
data_i[16]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[17]	No	No		No		INPUT
data_i[21:18]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[22]	No	No		No		INPUT
data_i[23]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[24]	No	No		No		INPUT
data_i[26:25]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[28:27]	No	No		No		INPUT
data_i[32:29]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[36:33]	No	No		No		INPUT
data_i[39:37]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[40]	No	No		No		INPUT
data_i[44:41]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[45]	No	No		No		INPUT
data_i[47:46]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[51:48]	No	No		No		INPUT
data_i[52]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[53]	No	No		No		INPUT
data_i[54]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[55]	No	No		No		INPUT
data_i[71:56]	Yes	Yes	T5,T9,T95	Yes	T5,T9,T25	INPUT
data_o[6:0]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[8:7]	No	No		No		OUTPUT
data_o[10:9]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[14:12]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[16]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[21:18]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[23]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[26:25]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[28:27]	No	No		No		OUTPUT
data_o[32:29]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[36:33]	No	No		No		OUTPUT
data_o[39:37]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[44:41]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[45]	No	No		No		OUTPUT
data_o[47:46]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[51:48]	No	No		No		OUTPUT
data_o[52]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[54]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[63:56]	Yes	Yes	T5,T9,T95	Yes	T5,T9,T25	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	192	70.59
Total Bits 0->1	136	96	70.59
Total Bits 1->0	136	96	70.59

Ports	2	0	0.00
Port Bits	272	192	70.59
Port Bits 0->1	136	96	70.59
Port Bits 1->0	136	96	70.59

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[6:1]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[7]	No	No		No		INPUT
data_i[9:8]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[12:10]	No	No		No		INPUT
data_i[16:13]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[17]	No	No		No		INPUT
data_i[19:18]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[20]	No	No		No		INPUT
data_i[21]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[22]	No	No		No		INPUT
data_i[35:23]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[36]	No	No		No		INPUT
data_i[39:37]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[42:40]	No	No		No		INPUT
data_i[43]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[44]	No	No		No		INPUT
data_i[49:45]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[52:50]	No	No		No		INPUT
data_i[53]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[55:54]	No	No		No		INPUT
data_i[59:56]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[60]	No	No		No		INPUT
data_i[61]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[62]	No	No		No		INPUT
data_i[71:63]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[6:1]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[9:8]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[12:10]	No	No		No		OUTPUT
data_o[16:13]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[19:18]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[21]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[35:23]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[36]	No	No		No		OUTPUT
data_o[39:37]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[42:40]	No	No		No		OUTPUT
data_o[43]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[49:45]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[52:50]	No	No		No		OUTPUT
data_o[53]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[55:54]	No	No		No		OUTPUT
data_o[59:56]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[61]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[62]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	192	70.59
Total Bits 0->1	136	96	70.59
Total Bits 1->0	136	96	70.59

Ports	2	0	0.00
Port Bits	272	192	70.59
Port Bits 0->1	136	96	70.59
Port Bits 1->0	136	96	70.59

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[1]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[2]	No	No		No		INPUT
data_i[8:3]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[9]	No	No		No		INPUT
data_i[10]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[11]	No	No		No		INPUT
data_i[12]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[13]	No	No		No		INPUT
data_i[15:14]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[16]	No	No		No		INPUT
data_i[21:17]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[22]	No	No		No		INPUT
data_i[30:23]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[32:31]	No	No		No		INPUT
data_i[36:33]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[37]	No	No		No		INPUT
data_i[39:38]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[43:40]	No	No		No		INPUT
data_i[46:44]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[47]	No	No		No		INPUT
data_i[50:48]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[51]	No	No		No		INPUT
data_i[53:52]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[54]	No	No		No		INPUT
data_i[56:55]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[57]	No	No		No		INPUT
data_i[59:58]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[61:60]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[1]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[8:3]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[10]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[12]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[15:14]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[21:17]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[30:23]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[32:31]	No	No		No		OUTPUT
data_o[36:33]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[39:38]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[43:40]	No	No		No		OUTPUT
data_o[46:44]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[50:48]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[51]	No	No		No		OUTPUT
data_o[53:52]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[56:55]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[57]	No	No		No		OUTPUT
data_o[59:58]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[61:60]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	192	70.59
Total Bits 0->1	136	96	70.59
Total Bits 1->0	136	96	70.59

Ports	2	0	0.00
Port Bits	272	192	70.59
Port Bits 0->1	136	96	70.59
Port Bits 1->0	136	96	70.59

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[5:1]	Yes	Yes	*T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[6]	No	No		No		INPUT
data_i[7]	Yes	Yes	*T9,*T95,*T113	Yes	T8,T9,T95	INPUT
data_i[9:8]	No	No		No		INPUT
data_i[10]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[11]	No	No		No		INPUT
data_i[16:12]	Yes	Yes	*T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[17]	No	No		No		INPUT
data_i[18]	Yes	Yes	*T9,*T95,*T113	Yes	T8,T9,T95	INPUT
data_i[19]	No	No		No		INPUT
data_i[23:20]	Yes	Yes	*T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[24]	No	No		No		INPUT
data_i[27:25]	Yes	Yes	T9,T95,T113	Yes	T8,T9,T95	INPUT
data_i[28]	No	No		No		INPUT
data_i[29]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[30]	No	No		No		INPUT
data_i[31]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[32]	No	No		No		INPUT
data_i[37:33]	Yes	Yes	T9,T113,T132	Yes	T8,T9,T130	INPUT
data_i[38]	No	No		No		INPUT
data_i[43:39]	Yes	Yes	*T5,T9,*T95	Yes	T5,T8,T9	INPUT
data_i[45:44]	No	No		No		INPUT
data_i[48:46]	Yes	Yes	T9,T113,T132	Yes	T8,T9,T130	INPUT
data_i[50:49]	No	No		No		INPUT
data_i[55:51]	Yes	Yes	*T5,T9,*T95	Yes	T5,T8,T9	INPUT
data_i[56]	No	No		No		INPUT
data_i[57]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[59:58]	No	No		No		INPUT
data_i[60]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T9,T113,T132	Yes	T8,T9,T130	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[5:1]	Yes	Yes	*T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[7]	Yes	Yes	*T9,*T95,*T113	Yes	T8,T9,T95	OUTPUT
data_o[9:8]	No	No		No		OUTPUT
data_o[10]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[16:12]	Yes	Yes	*T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[18]	Yes	Yes	*T9,*T95,*T113	Yes	T8,T9,T95	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[23:20]	Yes	Yes	*T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[27:25]	Yes	Yes	T9,T95,T113	Yes	T8,T9,T95	OUTPUT
data_o[28]	No	No		No		OUTPUT
data_o[29]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[30]	No	No		No		OUTPUT
data_o[31]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[37:33]	Yes	Yes	T9,T113,T132	Yes	T8,T9,T130	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[43:39]	Yes	Yes	*T5,T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[45:44]	No	No		No		OUTPUT
data_o[48:46]	Yes	Yes	T9,T113,T132	Yes	T8,T9,T130	OUTPUT
data_o[50:49]	No	No		No		OUTPUT
data_o[55:51]	Yes	Yes	*T5,T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[57]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[59:58]	No	No		No		OUTPUT
data_o[60]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T9,T113,T132	Yes	T8,T9,T130	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	192	70.59
Total Bits 0->1	136	96	70.59
Total Bits 1->0	136	96	70.59

Ports	2	0	0.00
Port Bits	272	192	70.59
Port Bits 0->1	136	96	70.59
Port Bits 1->0	136	96	70.59

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[1:0]	Yes	Yes	*T5,T9,*T95	Yes	T5,T8,T9	INPUT
data_i[4:2]	No	No		No		INPUT
data_i[9:5]	Yes	Yes	T9,T113,T132	Yes	T8,T9,T130	INPUT
data_i[10]	No	No		No		INPUT
data_i[17:11]	Yes	Yes	T9,T113,T132	Yes	T8,T9,T130	INPUT
data_i[19:18]	No	No		No		INPUT
data_i[27:20]	Yes	Yes	*T5,T9,*T95	Yes	T5,T8,T9	INPUT
data_i[29:28]	No	No		No		INPUT
data_i[33:30]	Yes	Yes	T9,T113,T132	Yes	T9,T130,T113	INPUT
data_i[34]	No	No		No		INPUT
data_i[38:35]	Yes	Yes	T9,T113,T132	Yes	T9,T130,T113	INPUT
data_i[42:39]	No	No		No		INPUT
data_i[43]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[44]	No	No		No		INPUT
data_i[46:45]	Yes	Yes	T9,T113,T132	Yes	T9,T130,T113	INPUT
data_i[47]	No	No		No		INPUT
data_i[48]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[49]	No	No		No		INPUT
data_i[55:50]	Yes	Yes	T9,T113,T132	Yes	T9,T113,T132	INPUT
data_i[57:56]	No	No		No		INPUT
data_i[60:58]	Yes	Yes	*T5,T9,*T95	Yes	T5,T8,T9	INPUT
data_i[61]	No	No		No		INPUT
data_i[62]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[63]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T9,T113,T132	Yes	T9,T113,T132	INPUT
data_o[1:0]	Yes	Yes	*T5,T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[4:2]	No	No		No		OUTPUT
data_o[9:5]	Yes	Yes	T9,T113,T132	Yes	T8,T9,T130	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[17:11]	Yes	Yes	T9,T113,T132	Yes	T8,T9,T130	OUTPUT
data_o[19:18]	No	No		No		OUTPUT
data_o[27:20]	Yes	Yes	*T5,T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[29:28]	No	No		No		OUTPUT
data_o[33:30]	Yes	Yes	T9,T113,T132	Yes	T9,T130,T113	OUTPUT
data_o[34]	No	No		No		OUTPUT
data_o[38:35]	Yes	Yes	T9,T113,T132	Yes	T9,T130,T113	OUTPUT
data_o[42:39]	No	No		No		OUTPUT
data_o[43]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[46:45]	Yes	Yes	T9,T113,T132	Yes	T9,T130,T113	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[48]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[55:50]	Yes	Yes	T9,T113,T132	Yes	T9,T113,T132	OUTPUT
data_o[57:56]	No	No		No		OUTPUT
data_o[60:58]	Yes	Yes	*T5,T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[62]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	192	70.59
Total Bits 0->1	136	96	70.59
Total Bits 1->0	136	96	70.59

Ports	2	0	0.00
Port Bits	272	192	70.59
Port Bits 0->1	136	96	70.59
Port Bits 1->0	136	96	70.59

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[1]	Yes	Yes	*T9,*T113,*T132	Yes	T9,T113,T132	INPUT
data_i[2]	No	No		No		INPUT
data_i[4:3]	Yes	Yes	T9,T113,T132	Yes	T9,T113,T132	INPUT
data_i[5]	No	No		No		INPUT
data_i[6]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[7]	No	No		No		INPUT
data_i[10:8]	Yes	Yes	T9,T113,T132	Yes	T9,T113,T132	INPUT
data_i[12:11]	No	No		No		INPUT
data_i[13]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[15:14]	No	No		No		INPUT
data_i[21:16]	Yes	Yes	T9,T113,T132	Yes	T9,T113,T132	INPUT
data_i[24:22]	No	No		No		INPUT
data_i[28:25]	Yes	Yes	*T5,T9,*T95	Yes	T5,T8,T9	INPUT
data_i[29]	No	No		No		INPUT
data_i[33:30]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[34]	No	No		No		INPUT
data_i[35]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[36]	No	No		No		INPUT
data_i[37]	Yes	Yes	*T113,*T132,*T96	Yes	T113,T132,T96	INPUT
data_i[38]	No	No		No		INPUT
data_i[42:39]	Yes	Yes	T113,T132,T96	Yes	T113,T132,T96	INPUT
data_i[43]	No	No		No		INPUT
data_i[48:44]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[49]	No	No		No		INPUT
data_i[54:50]	Yes	Yes	T113,T132,T96	Yes	T113,T132,T96	INPUT
data_i[55]	No	No		No		INPUT
data_i[59:56]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[61:60]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T113,T132,T96	Yes	T113,T132,T96	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[1]	Yes	Yes	*T9,*T113,*T132	Yes	T9,T113,T132	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[4:3]	Yes	Yes	T9,T113,T132	Yes	T9,T113,T132	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[6]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[10:8]	Yes	Yes	T9,T113,T132	Yes	T9,T113,T132	OUTPUT
data_o[12:11]	No	No		No		OUTPUT
data_o[13]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[15:14]	No	No		No		OUTPUT
data_o[21:16]	Yes	Yes	T9,T113,T132	Yes	T9,T113,T132	OUTPUT
data_o[24:22]	No	No		No		OUTPUT
data_o[28:25]	Yes	Yes	*T5,T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[33:30]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[34]	No	No		No		OUTPUT
data_o[35]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[36]	No	No		No		OUTPUT
data_o[37]	Yes	Yes	*T113,*T132,*T96	Yes	T113,T132,T96	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[42:39]	Yes	Yes	T113,T132,T96	Yes	T113,T132,T96	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[48:44]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[54:50]	Yes	Yes	T113,T132,T96	Yes	T113,T132,T96	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[59:56]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[61:60]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T113,T132,T96	Yes	T113,T132,T96	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	200	73.53
Total Bits 0->1	136	100	73.53
Total Bits 1->0	136	100	73.53

Ports	2	0	0.00
Port Bits	272	200	73.53
Port Bits 0->1	136	100	73.53
Port Bits 1->0	136	100	73.53

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[3]	No	No		No		INPUT
data_i[5:4]	Yes	Yes	T9,T95,T113	Yes	T8,T9,T25	INPUT
data_i[7:6]	No	No		No		INPUT
data_i[8]	Yes	Yes	*T9,*T95,*T113	Yes	T8,T9,T25	INPUT
data_i[10:9]	No	No		No		INPUT
data_i[19:11]	Yes	Yes	*T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[20]	No	No		No		INPUT
data_i[26:21]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[27]	No	No		No		INPUT
data_i[30:28]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[31]	No	No		No		INPUT
data_i[33:32]	Yes	Yes	*T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[35:34]	No	No		No		INPUT
data_i[41:36]	Yes	Yes	*T9,*T95,*T113	Yes	T8,T9,T25	INPUT
data_i[43:42]	No	No		No		INPUT
data_i[46:44]	Yes	Yes	T9,T95,T113	Yes	T8,T9,T25	INPUT
data_i[47]	No	No		No		INPUT
data_i[48]	Yes	Yes	*T9,*T95,*T113	Yes	T8,T9,T95	INPUT
data_i[49]	No	No		No		INPUT
data_i[56:50]	Yes	Yes	*T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[58:57]	No	No		No		INPUT
data_i[61:59]	Yes	Yes	*T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[63:62]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_o[2:0]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[5:4]	Yes	Yes	T9,T95,T113	Yes	T8,T9,T25	OUTPUT
data_o[7:6]	No	No		No		OUTPUT
data_o[8]	Yes	Yes	*T9,*T95,*T113	Yes	T8,T9,T25	OUTPUT
data_o[10:9]	No	No		No		OUTPUT
data_o[19:11]	Yes	Yes	*T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[26:21]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[27]	No	No		No		OUTPUT
data_o[30:28]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[33:32]	Yes	Yes	*T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[35:34]	No	No		No		OUTPUT
data_o[41:36]	Yes	Yes	*T9,*T95,*T113	Yes	T8,T9,T25	OUTPUT
data_o[43:42]	No	No		No		OUTPUT
data_o[46:44]	Yes	Yes	T9,T95,T113	Yes	T8,T9,T25	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[48]	Yes	Yes	*T9,*T95,*T113	Yes	T8,T9,T95	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[56:50]	Yes	Yes	*T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[58:57]	No	No		No		OUTPUT
data_o[61:59]	Yes	Yes	*T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[63:62]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	204	75.00
Total Bits 0->1	136	102	75.00
Total Bits 1->0	136	102	75.00

Ports	2	0	0.00
Port Bits	272	204	75.00
Port Bits 0->1	136	102	75.00
Port Bits 1->0	136	102	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[4:3]	No	No		No		INPUT
data_i[5]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[6]	No	No		No		INPUT
data_i[14:7]	Yes	Yes	T5,T96,T73	Yes	T5,T96,T73	INPUT
data_i[16:15]	No	No		No		INPUT
data_i[19:17]	Yes	Yes	T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[20]	No	No		No		INPUT
data_i[22:21]	Yes	Yes	T5,T96,T73	Yes	T5,T96,T73	INPUT
data_i[23]	No	No		No		INPUT
data_i[40:24]	Yes	Yes	T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[41]	No	No		No		INPUT
data_i[42]	Yes	Yes	*T5,*T96,*T73	Yes	T5,T96,T73	INPUT
data_i[45:43]	No	No		No		INPUT
data_i[46]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[47]	No	No		No		INPUT
data_i[56:48]	Yes	Yes	T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[61:57]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_o[2:0]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[4:3]	No	No		No		OUTPUT
data_o[5]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[14:7]	Yes	Yes	T5,T96,T73	Yes	T5,T96,T73	OUTPUT
data_o[16:15]	No	No		No		OUTPUT
data_o[19:17]	Yes	Yes	T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[22:21]	Yes	Yes	T5,T96,T73	Yes	T5,T96,T73	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[40:24]	Yes	Yes	T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[42]	Yes	Yes	*T5,*T96,*T73	Yes	T5,T96,T73	OUTPUT
data_o[45:43]	No	No		No		OUTPUT
data_o[46]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[56:48]	Yes	Yes	T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[61:57]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	208	76.47
Total Bits 0->1	136	104	76.47
Total Bits 1->0	136	104	76.47

Ports	2	0	0.00
Port Bits	272	208	76.47
Port Bits 0->1	136	104	76.47
Port Bits 1->0	136	104	76.47

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	Yes	Yes	*T5,*T9,*T130	Yes	T5,T9,T25	INPUT
data_i[1]	No	No		No		INPUT
data_i[3:2]	Yes	Yes	T5,T9,T130	Yes	T5,T9,T25	INPUT
data_i[4]	No	No		No		INPUT
data_i[8:5]	Yes	Yes	T5,T9,*T95	Yes	T5,T8,T9	INPUT
data_i[9]	No	No		No		INPUT
data_i[10]	Yes	Yes	*T5,*T9,*T130	Yes	T5,T9,T25	INPUT
data_i[12:11]	No	No		No		INPUT
data_i[15:13]	Yes	Yes	T5,T9,*T95	Yes	T5,T8,T9	INPUT
data_i[16]	No	No		No		INPUT
data_i[17]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[18]	No	No		No		INPUT
data_i[24:19]	Yes	Yes	T5,T9,*T95	Yes	T5,T8,T9	INPUT
data_i[26:25]	No	No		No		INPUT
data_i[31:27]	Yes	Yes	T5,T9,*T95	Yes	T5,T8,T9	INPUT
data_i[32]	No	No		No		INPUT
data_i[36:33]	Yes	Yes	T5,T9,*T95	Yes	T5,T8,T9	INPUT
data_i[37]	No	No		No		INPUT
data_i[40:38]	Yes	Yes	T5,T9,*T95	Yes	T5,T8,T9	INPUT
data_i[41]	No	No		No		INPUT
data_i[45:42]	Yes	Yes	T5,T9,*T95	Yes	T5,T8,T9	INPUT
data_i[46]	No	No		No		INPUT
data_i[48:47]	Yes	Yes	T5,T9,T130	Yes	T5,T9,T25	INPUT
data_i[49]	No	No		No		INPUT
data_i[51:50]	Yes	Yes	*T111,*T5,*T9	Yes	T111,T5,T8	INPUT
data_i[52]	No	No		No		INPUT
data_i[61:53]	Yes	Yes	*T5,*T130,*T132	Yes	T5,T130,T131	INPUT
data_i[62]	No	No		No		INPUT
data_i[71:63]	Yes	Yes	T5,T130,T132	Yes	T5,T130,T131	INPUT
data_o[0]	Yes	Yes	*T5,*T9,*T130	Yes	T5,T9,T25	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[3:2]	Yes	Yes	T5,T9,T130	Yes	T5,T9,T25	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[8:5]	Yes	Yes	T5,T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[10]	Yes	Yes	*T5,*T9,*T130	Yes	T5,T9,T25	OUTPUT
data_o[12:11]	No	No		No		OUTPUT
data_o[15:13]	Yes	Yes	T5,T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[17]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[24:19]	Yes	Yes	T5,T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[26:25]	No	No		No		OUTPUT
data_o[31:27]	Yes	Yes	T5,T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[36:33]	Yes	Yes	T5,T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[40:38]	Yes	Yes	T5,T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[45:42]	Yes	Yes	T5,T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[48:47]	Yes	Yes	T5,T9,T130	Yes	T5,T9,T25	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[51:50]	Yes	Yes	*T111,*T5,*T9	Yes	T111,T5,T8	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[61:53]	Yes	Yes	*T5,*T130,*T132	Yes	T5,T130,T131	OUTPUT
data_o[62]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T5,T130,T132	Yes	T5,T130,T131	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	220	80.88
Total Bits 0->1	136	110	80.88
Total Bits 1->0	136	110	80.88

Ports	2	0	0.00
Port Bits	272	220	80.88
Port Bits 0->1	136	110	80.88
Port Bits 1->0	136	110	80.88

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[11:0]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[12]	No	No		No		INPUT
data_i[15:13]	Yes	Yes	T5,T9,T95	Yes	T5,T9,T25	INPUT
data_i[16]	No	No		No		INPUT
data_i[18:17]	Yes	Yes	T5,T9,T95	Yes	T5,T9,T25	INPUT
data_i[20:19]	No	No		No		INPUT
data_i[25:21]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[26]	No	No		No		INPUT
data_i[28:27]	Yes	Yes	T5,T9,T95	Yes	T5,T9,T25	INPUT
data_i[29]	No	No		No		INPUT
data_i[36:30]	Yes	Yes	T5,T9,T95	Yes	T5,T9,T25	INPUT
data_i[37]	No	No		No		INPUT
data_i[40:38]	Yes	Yes	T5,T9,T95	Yes	T5,T9,T25	INPUT
data_i[41]	No	No		No		INPUT
data_i[42]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T9,T25	INPUT
data_i[43]	No	No		No		INPUT
data_i[47:44]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	INPUT
data_i[48]	No	No		No		INPUT
data_i[49]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[50]	No	No		No		INPUT
data_i[60:51]	Yes	Yes	T5,T9,*T95	Yes	T5,T8,T9	INPUT
data_i[61]	No	No		No		INPUT
data_i[62]	Yes	Yes	*T5,*T9,*T130	Yes	T5,T9,T25	INPUT
data_i[63]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T5,T9,T95	Yes	T5,T9,T25	INPUT
data_o[11:0]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[12]	No	No		No		OUTPUT
data_o[15:13]	Yes	Yes	T5,T9,T95	Yes	T5,T9,T25	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[18:17]	Yes	Yes	T5,T9,T95	Yes	T5,T9,T25	OUTPUT
data_o[20:19]	No	No		No		OUTPUT
data_o[25:21]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[28:27]	Yes	Yes	T5,T9,T95	Yes	T5,T9,T25	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[36:30]	Yes	Yes	T5,T9,T95	Yes	T5,T9,T25	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[40:38]	Yes	Yes	T5,T9,T95	Yes	T5,T9,T25	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[42]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T9,T25	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[47:44]	Yes	Yes	T5,T9,T95	Yes	T5,T8,T9	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[49]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[60:51]	Yes	Yes	T5,T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[62]	Yes	Yes	*T5,*T9,*T130	Yes	T5,T9,T25	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	228	83.82
Total Bits 0->1	136	114	83.82
Total Bits 1->0	136	114	83.82

Ports	2	0	0.00
Port Bits	272	228	83.82
Port Bits 0->1	136	114	83.82
Port Bits 1->0	136	114	83.82

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[1]	No	No		No		INPUT
data_i[11:2]	Yes	Yes	T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[13:12]	No	No		No		INPUT
data_i[16:14]	Yes	Yes	*T5,*T130,*T132	Yes	T5,T130,T131	INPUT
data_i[17]	No	No		No		INPUT
data_i[20:18]	Yes	Yes	T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[21]	No	No		No		INPUT
data_i[24:22]	Yes	Yes	T5,T130,T132	Yes	T5,T130,T132	INPUT
data_i[26:25]	No	No		No		INPUT
data_i[28:27]	Yes	Yes	T5,*T9,*T95	Yes	T5,T8,T9	INPUT
data_i[29]	No	No		No		INPUT
data_i[33:30]	Yes	Yes	T5,T130,T132	Yes	T5,T130,T132	INPUT
data_i[34]	No	No		No		INPUT
data_i[35]	Yes	Yes	*T6	Yes	T6	INPUT
data_i[36]	No	No		No		INPUT
data_i[52:37]	Yes	Yes	*T6,*T5,*T130	Yes	T6,T5,T130	INPUT
data_i[53]	No	No		No		INPUT
data_i[71:54]	Yes	Yes	T6,T5,T9	Yes	T6,T5,T8	INPUT
data_o[0]	Yes	Yes	*T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[11:2]	Yes	Yes	T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[13:12]	No	No		No		OUTPUT
data_o[16:14]	Yes	Yes	*T5,*T130,*T132	Yes	T5,T130,T131	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[20:18]	Yes	Yes	T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[21]	No	No		No		OUTPUT
data_o[24:22]	Yes	Yes	T5,T130,T132	Yes	T5,T130,T132	OUTPUT
data_o[26:25]	No	No		No		OUTPUT
data_o[28:27]	Yes	Yes	T5,*T9,*T95	Yes	T5,T8,T9	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[33:30]	Yes	Yes	T5,T130,T132	Yes	T5,T130,T132	OUTPUT
data_o[34]	No	No		No		OUTPUT
data_o[35]	Yes	Yes	*T6	Yes	T6	OUTPUT
data_o[36]	No	No		No		OUTPUT
data_o[52:37]	Yes	Yes	*T6,*T5,*T130	Yes	T6,T5,T130	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[63:54]	Yes	Yes	T6,T5,T9	Yes	T6,T5,T8	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T4,T113,T96	Yes	T4,T113,T96	INPUT
data_o[63:0]	Yes	Yes	T4,T113,T96	Yes	T4,T113,T96	OUTPUT
syndrome_o[2:0]	Yes	Yes	T108,T151,T152	Yes	T108,T151,T152	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T108,*T151,*T152	Yes	T108,T151,T152	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T96,T102,T74	Yes	T96,T102,T74	INPUT
data_o[63:0]	Yes	Yes	T96,T102,T74	Yes	T96,T102,T74	OUTPUT
syndrome_o[2:0]	Yes	Yes	T152	Yes	T152	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T152	Yes	T152	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T130,T73,T102	Yes	T130,T73,T102	INPUT
data_o[63:0]	Yes	Yes	T130,T73,T102	Yes	T130,T73,T102	OUTPUT
syndrome_o[2:0]	Yes	Yes	T151	Yes	T151	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T151	Yes	T151	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T95,T130,T96	Yes	T95,T130,T96	INPUT
data_o[63:0]	Yes	Yes	T95,T130,T96	Yes	T95,T130,T96	OUTPUT
syndrome_o[2:0]	Yes	Yes	T107,T168,T169	Yes	T107,T168,T169	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T107,*T168,*T169	Yes	T107,T168,T169	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T113,T132,T96	Yes	T113,T132,T96	INPUT
data_o[63:0]	Yes	Yes	T113,T132,T96	Yes	T113,T132,T96	OUTPUT
syndrome_o[7:0]	Excluded	Excluded	T107,T152	Excluded	T107,T152	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded	T107,T152	Excluded	T107,T152	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T6,T96,T89	Yes	T6,T96,T89	INPUT
data_o[63:0]	Yes	Yes	T6,T96,T89	Yes	T6,T96,T89	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T89,T267,T228	Yes	T119,T89,T267	INPUT
data_o[63:0]	Yes	Yes	T89,T267,T228	Yes	T119,T89,T267	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T6,T140,T64	Yes	T6,T140,T64	INPUT
data_o[63:0]	Yes	Yes	T6,T140,T64	Yes	T6,T140,T64	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T121,T201,T263	Yes	T121,T201,T263	INPUT
data_o[63:0]	Yes	Yes	T121,T201,T263	Yes	T121,T201,T263	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T167,T295,T296	Yes	T219,T167,T295	INPUT
data_o[63:0]	Yes	Yes	T167,T295,T296	Yes	T219,T167,T295	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T82,T140,T297	Yes	T82,T140,T297	INPUT
data_o[63:0]	Yes	Yes	T82,T140,T297	Yes	T82,T140,T297	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T76,T298,T49	Yes	T76,T298,T49	INPUT
data_o[63:0]	Yes	Yes	T76,T298,T49	Yes	T76,T298,T49	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T82,T299,T294	Yes	T91,T82,T299	INPUT
data_o[63:0]	Yes	Yes	T82,T299,T294	Yes	T91,T82,T299	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T113,T96,T102	Yes	T91,T113,T96	INPUT
data_o[63:0]	Yes	Yes	T113,T96,T102	Yes	T91,T113,T96	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T106,T131,T89	Yes	T106,T131,T119	INPUT
data_o[63:0]	Yes	Yes	T106,T131,T89	Yes	T106,T131,T119	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T7,T106,T113	Yes	T8,T7,T25	INPUT
data_o[63:0]	Yes	Yes	T7,T106,T113	Yes	T8,T7,T25	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T9,T129,T130	Yes	T9,T91,T129	INPUT
data_o[63:0]	Yes	Yes	T9,T129,T130	Yes	T9,T91,T129	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T6,T9,T91	Yes	T6,T8,T9	INPUT
data_o[63:0]	Yes	Yes	T6,T9,T91	Yes	T6,T8,T9	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	INPUT
data_o[63:0]	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T96,T89,T102	Yes	T96,T89,T102	INPUT
data_o[63:0]	Yes	Yes	T96,T89,T102	Yes	T96,T89,T102	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T130,T131,T82	Yes	T91,T130,T131	INPUT
data_o[63:0]	Yes	Yes	T130,T131,T82	Yes	T91,T130,T131	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T7,T95,T131	Yes	T7,T95,T129	INPUT
data_o[63:0]	Yes	Yes	T7,T95,T131	Yes	T7,T95,T129	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T7,T113,T132	Yes	T7,T91,T97	INPUT
data_o[63:0]	Yes	Yes	T7,T113,T132	Yes	T7,T91,T97	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR