| T1073 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.5096766 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:27 PM UTC 24 |
122323002 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_init_fail.1859871578 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:28 PM UTC 24 |
594937248 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.1030697317 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:28 PM UTC 24 |
439092247 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.2491621472 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:28 PM UTC 24 |
213839323 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.2714046203 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:28 PM UTC 24 |
323996696 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.92947790 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:28 PM UTC 24 |
542350210 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.3893758825 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:28 PM UTC 24 |
427801397 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.3635863358 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:28 PM UTC 24 |
540679008 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.3660643951 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:28 PM UTC 24 |
94329831 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.3939105029 |
|
|
Oct 12 05:45:22 PM UTC 24 |
Oct 12 05:45:28 PM UTC 24 |
318152582 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.2511673115 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:28 PM UTC 24 |
2045290473 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.2355682947 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:28 PM UTC 24 |
487849898 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.1870531743 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:28 PM UTC 24 |
234144082 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.2684717791 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:28 PM UTC 24 |
163259813 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.1691282779 |
|
|
Oct 12 05:45:24 PM UTC 24 |
Oct 12 05:45:29 PM UTC 24 |
1411527248 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.3872486271 |
|
|
Oct 12 05:45:24 PM UTC 24 |
Oct 12 05:45:29 PM UTC 24 |
309322060 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.2841388476 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:29 PM UTC 24 |
401370791 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.3048083497 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:29 PM UTC 24 |
392735599 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.934250302 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:29 PM UTC 24 |
374842805 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.2328652761 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:29 PM UTC 24 |
125980315 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.45111856 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:29 PM UTC 24 |
288200364 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.2128170219 |
|
|
Oct 12 05:45:24 PM UTC 24 |
Oct 12 05:45:29 PM UTC 24 |
98960988 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.845864058 |
|
|
Oct 12 05:45:24 PM UTC 24 |
Oct 12 05:45:29 PM UTC 24 |
276267661 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.2060015753 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:29 PM UTC 24 |
408412624 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.516767616 |
|
|
Oct 12 05:45:24 PM UTC 24 |
Oct 12 05:45:30 PM UTC 24 |
211962564 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.2176179325 |
|
|
Oct 12 05:45:24 PM UTC 24 |
Oct 12 05:45:30 PM UTC 24 |
326367939 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.4021608655 |
|
|
Oct 12 05:45:24 PM UTC 24 |
Oct 12 05:45:30 PM UTC 24 |
260321253 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.2849149031 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:30 PM UTC 24 |
250469407 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.2612365352 |
|
|
Oct 12 05:45:24 PM UTC 24 |
Oct 12 05:45:30 PM UTC 24 |
328914818 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all.68378710 |
|
|
Oct 12 05:42:49 PM UTC 24 |
Oct 12 05:45:30 PM UTC 24 |
18951405881 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.1920126460 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
1460481081 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.1949844253 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:30 PM UTC 24 |
684654514 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.2634485633 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:30 PM UTC 24 |
2088509169 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.3411542333 |
|
|
Oct 12 05:45:24 PM UTC 24 |
Oct 12 05:45:31 PM UTC 24 |
1759217106 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all.3419801474 |
|
|
Oct 12 05:40:43 PM UTC 24 |
Oct 12 05:45:31 PM UTC 24 |
122361979163 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.371185130 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:32 PM UTC 24 |
730710027 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.1326318192 |
|
|
Oct 12 05:45:28 PM UTC 24 |
Oct 12 05:45:32 PM UTC 24 |
338392933 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.2449003133 |
|
|
Oct 12 05:45:29 PM UTC 24 |
Oct 12 05:45:33 PM UTC 24 |
110204101 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.3733076799 |
|
|
Oct 12 05:45:28 PM UTC 24 |
Oct 12 05:45:33 PM UTC 24 |
116661366 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.1908735835 |
|
|
Oct 12 05:45:28 PM UTC 24 |
Oct 12 05:45:33 PM UTC 24 |
387089790 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.3976505466 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
369230721 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.3447770559 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
210644402 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.569383993 |
|
|
Oct 12 05:45:29 PM UTC 24 |
Oct 12 05:45:33 PM UTC 24 |
226199086 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.3960724249 |
|
|
Oct 12 05:45:28 PM UTC 24 |
Oct 12 05:45:33 PM UTC 24 |
106737686 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.2031688039 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:47 PM UTC 24 |
565761312 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.393097055 |
|
|
Oct 12 05:45:29 PM UTC 24 |
Oct 12 05:45:33 PM UTC 24 |
114517717 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.3873019541 |
|
|
Oct 12 05:45:29 PM UTC 24 |
Oct 12 05:45:33 PM UTC 24 |
101108942 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.1955137111 |
|
|
Oct 12 05:45:28 PM UTC 24 |
Oct 12 05:45:33 PM UTC 24 |
2421344132 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.3270743424 |
|
|
Oct 12 05:45:29 PM UTC 24 |
Oct 12 05:45:33 PM UTC 24 |
171579404 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.892392100 |
|
|
Oct 12 05:45:29 PM UTC 24 |
Oct 12 05:45:34 PM UTC 24 |
170701751 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.1140681454 |
|
|
Oct 12 05:45:29 PM UTC 24 |
Oct 12 05:45:34 PM UTC 24 |
144913976 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.787683094 |
|
|
Oct 12 05:45:22 PM UTC 24 |
Oct 12 05:45:35 PM UTC 24 |
7778941640 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.309881217 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:35 PM UTC 24 |
710999018 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.2131266364 |
|
|
Oct 12 05:45:28 PM UTC 24 |
Oct 12 05:45:35 PM UTC 24 |
2169457111 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.2936794990 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:35 PM UTC 24 |
174835751 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.1628889413 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:35 PM UTC 24 |
93088474 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.2930652347 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:35 PM UTC 24 |
367243391 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.1392099681 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:36 PM UTC 24 |
150141628 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.2097697166 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:36 PM UTC 24 |
160901936 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.3134700459 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:36 PM UTC 24 |
116695197 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.2492057503 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:36 PM UTC 24 |
152543727 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.1041270153 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:36 PM UTC 24 |
389049985 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.1952622697 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:36 PM UTC 24 |
318167525 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.750262099 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:36 PM UTC 24 |
119558949 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.2761162116 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:36 PM UTC 24 |
124587397 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.2660260569 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:36 PM UTC 24 |
137029968 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.847865005 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:36 PM UTC 24 |
188872254 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.4111456966 |
|
|
Oct 12 05:45:32 PM UTC 24 |
Oct 12 05:45:36 PM UTC 24 |
181571345 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.1855750565 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:36 PM UTC 24 |
496463906 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.99008221 |
|
|
Oct 12 05:45:32 PM UTC 24 |
Oct 12 05:45:36 PM UTC 24 |
108619715 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.537649580 |
|
|
Oct 12 05:45:32 PM UTC 24 |
Oct 12 05:45:36 PM UTC 24 |
209533927 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.2776272968 |
|
|
Oct 12 05:45:32 PM UTC 24 |
Oct 12 05:45:37 PM UTC 24 |
291601417 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.476820326 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:37 PM UTC 24 |
530107363 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.3335578094 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:37 PM UTC 24 |
331278107 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.2889961542 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:37 PM UTC 24 |
577764354 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.92169844 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:37 PM UTC 24 |
1557737376 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.3503157694 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:37 PM UTC 24 |
174130209 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.2606656221 |
|
|
Oct 12 05:45:32 PM UTC 24 |
Oct 12 05:45:37 PM UTC 24 |
154826012 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.3905497898 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:37 PM UTC 24 |
2734056062 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.920298875 |
|
|
Oct 12 05:45:32 PM UTC 24 |
Oct 12 05:45:37 PM UTC 24 |
645826703 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.1026155881 |
|
|
Oct 12 05:45:31 PM UTC 24 |
Oct 12 05:45:38 PM UTC 24 |
2512402295 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.2186045877 |
|
|
Oct 12 05:41:24 PM UTC 24 |
Oct 12 05:45:38 PM UTC 24 |
43978305522 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.240970902 |
|
|
Oct 12 05:45:32 PM UTC 24 |
Oct 12 05:45:38 PM UTC 24 |
1273124192 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.290191254 |
|
|
Oct 12 05:45:32 PM UTC 24 |
Oct 12 05:45:39 PM UTC 24 |
2355053833 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.742125163 |
|
|
Oct 12 05:45:23 PM UTC 24 |
Oct 12 05:45:39 PM UTC 24 |
618422200 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.1114793066 |
|
|
Oct 12 05:45:22 PM UTC 24 |
Oct 12 05:45:39 PM UTC 24 |
8871156168 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.4134564283 |
|
|
Oct 12 05:44:01 PM UTC 24 |
Oct 12 05:45:42 PM UTC 24 |
11934516212 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.2529474614 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:45 PM UTC 24 |
307075508 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.2563651290 |
|
|
Oct 12 05:43:29 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
6249811608 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.3892030915 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
1462460208 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.2156765939 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
546106721 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.2739450095 |
|
|
Oct 12 05:45:42 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
91609442 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.2704459508 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
187243547 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.4178504187 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
2118509278 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.512092860 |
|
|
Oct 12 05:45:42 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
132859341 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.3965127821 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
351847397 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.3618044318 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
185750638 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.1337096667 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:47 PM UTC 24 |
181186879 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.2072312588 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
2151342760 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.3466115282 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
154174424 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.2520339551 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
442243659 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.3903190686 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
305177139 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.2829671412 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
127647229 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.1747703250 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
120073464 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.129959057 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:46 PM UTC 24 |
2182893357 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.2209490241 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:47 PM UTC 24 |
2142955990 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.1014482448 |
|
|
Oct 12 05:45:42 PM UTC 24 |
Oct 12 05:45:47 PM UTC 24 |
1542142886 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.559865017 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:48 PM UTC 24 |
2715853221 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.600437182 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:48 PM UTC 24 |
1699550918 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.62223716 |
|
|
Oct 12 05:45:41 PM UTC 24 |
Oct 12 05:45:48 PM UTC 24 |
2550496570 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.2785765019 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:49 PM UTC 24 |
220414450 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.1166950398 |
|
|
Oct 12 05:45:44 PM UTC 24 |
Oct 12 05:45:49 PM UTC 24 |
282395277 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.446216608 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:49 PM UTC 24 |
173869846 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.854589506 |
|
|
Oct 12 05:45:44 PM UTC 24 |
Oct 12 05:45:49 PM UTC 24 |
419974897 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.941270873 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:50 PM UTC 24 |
1781690539 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.3916218033 |
|
|
Oct 12 05:42:20 PM UTC 24 |
Oct 12 05:46:26 PM UTC 24 |
52638986627 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.1156376826 |
|
|
Oct 12 05:43:25 PM UTC 24 |
Oct 12 05:46:28 PM UTC 24 |
16215238768 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.1273809638 |
|
|
Oct 12 05:43:13 PM UTC 24 |
Oct 12 05:46:29 PM UTC 24 |
85452436854 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.3099847081 |
|
|
Oct 12 05:43:43 PM UTC 24 |
Oct 12 05:46:34 PM UTC 24 |
70649674025 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all.3363707645 |
|
|
Oct 12 05:41:45 PM UTC 24 |
Oct 12 05:47:25 PM UTC 24 |
59405803351 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all.2271434928 |
|
|
Oct 12 05:40:05 PM UTC 24 |
Oct 12 05:48:18 PM UTC 24 |
99837374159 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.2776954889 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:47 PM UTC 24 |
142311020 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.3069646933 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:47 PM UTC 24 |
76740132 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2120892693 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:47 PM UTC 24 |
39553550 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2292113763 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:47 PM UTC 24 |
149468192 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2002791010 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:48 PM UTC 24 |
130305197 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.2999485287 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:48 PM UTC 24 |
116867595 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.1022755269 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:48 PM UTC 24 |
498327875 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.2855681593 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:48 PM UTC 24 |
189711171 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.4169937171 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:48 PM UTC 24 |
254782195 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2248383462 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:48 PM UTC 24 |
75215486 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2114952924 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:48 PM UTC 24 |
536034790 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.3271804405 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:49 PM UTC 24 |
1532081707 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.368108002 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:49 PM UTC 24 |
178753814 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.604402483 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:50 PM UTC 24 |
880527235 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2733273337 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:50 PM UTC 24 |
40398001 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.850564876 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:50 PM UTC 24 |
199423713 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.4272052627 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:50 PM UTC 24 |
72706499 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.1776944963 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:50 PM UTC 24 |
66835726 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1415517290 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:50 PM UTC 24 |
88260894 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1505730495 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:50 PM UTC 24 |
76813628 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3601114904 |
|
|
Oct 12 05:45:46 PM UTC 24 |
Oct 12 05:45:50 PM UTC 24 |
100941148 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3533081950 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:50 PM UTC 24 |
37691938 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.774284295 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:51 PM UTC 24 |
58965895 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.810578388 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:51 PM UTC 24 |
43776089 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2940386363 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:51 PM UTC 24 |
40625650 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.3178211041 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:51 PM UTC 24 |
129050337 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2675491458 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:51 PM UTC 24 |
77262720 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.2861916293 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:51 PM UTC 24 |
281974512 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.2948955339 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:51 PM UTC 24 |
74657614 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.956446630 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:51 PM UTC 24 |
824317297 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.89046453 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:51 PM UTC 24 |
104751683 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3547569984 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:51 PM UTC 24 |
166112223 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1518021388 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:52 PM UTC 24 |
174287943 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.1686891020 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:57 PM UTC 24 |
686824374 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.1144589945 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:52 PM UTC 24 |
103430692 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.2253748390 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:52 PM UTC 24 |
177105855 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.692392528 |
|
|
Oct 12 05:45:46 PM UTC 24 |
Oct 12 05:45:55 PM UTC 24 |
1191592734 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.352336657 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:52 PM UTC 24 |
326379196 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.334133745 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:52 PM UTC 24 |
91610303 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.4032956376 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:53 PM UTC 24 |
91526929 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.1746992784 |
|
|
Oct 12 05:45:50 PM UTC 24 |
Oct 12 05:45:53 PM UTC 24 |
111630799 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.25591478 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:53 PM UTC 24 |
1564221767 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.456827425 |
|
|
Oct 12 05:45:50 PM UTC 24 |
Oct 12 05:45:53 PM UTC 24 |
541229409 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.4150425866 |
|
|
Oct 12 05:45:50 PM UTC 24 |
Oct 12 05:45:53 PM UTC 24 |
71480992 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.395499764 |
|
|
Oct 12 05:45:50 PM UTC 24 |
Oct 12 05:45:53 PM UTC 24 |
629437622 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2168258139 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:53 PM UTC 24 |
386424642 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.4037844343 |
|
|
Oct 12 05:45:50 PM UTC 24 |
Oct 12 05:45:53 PM UTC 24 |
83565434 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2579221129 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:53 PM UTC 24 |
730893780 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.3901393144 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:53 PM UTC 24 |
117701822 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.601385597 |
|
|
Oct 12 05:45:50 PM UTC 24 |
Oct 12 05:45:53 PM UTC 24 |
74803418 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.778110117 |
|
|
Oct 12 05:45:50 PM UTC 24 |
Oct 12 05:45:53 PM UTC 24 |
101471588 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.40976181 |
|
|
Oct 12 05:45:50 PM UTC 24 |
Oct 12 05:45:54 PM UTC 24 |
97393664 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.888235285 |
|
|
Oct 12 05:45:52 PM UTC 24 |
Oct 12 05:45:55 PM UTC 24 |
43118595 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.37514771 |
|
|
Oct 12 05:45:52 PM UTC 24 |
Oct 12 05:45:55 PM UTC 24 |
45635662 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.1539277534 |
|
|
Oct 12 05:45:52 PM UTC 24 |
Oct 12 05:45:55 PM UTC 24 |
70983305 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.712180085 |
|
|
Oct 12 05:45:50 PM UTC 24 |
Oct 12 05:45:54 PM UTC 24 |
75604620 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1332690578 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:54 PM UTC 24 |
157232017 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.483240757 |
|
|
Oct 12 05:45:50 PM UTC 24 |
Oct 12 05:45:54 PM UTC 24 |
777699762 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.3840427745 |
|
|
Oct 12 05:45:50 PM UTC 24 |
Oct 12 05:45:54 PM UTC 24 |
227602202 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.4179721516 |
|
|
Oct 12 05:45:52 PM UTC 24 |
Oct 12 05:45:55 PM UTC 24 |
76755405 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3498766283 |
|
|
Oct 12 05:45:52 PM UTC 24 |
Oct 12 05:45:56 PM UTC 24 |
613228658 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.1680152444 |
|
|
Oct 12 05:45:52 PM UTC 24 |
Oct 12 05:45:54 PM UTC 24 |
51001349 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.4097858443 |
|
|
Oct 12 05:45:50 PM UTC 24 |
Oct 12 05:45:55 PM UTC 24 |
163290589 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1620217760 |
|
|
Oct 12 05:45:50 PM UTC 24 |
Oct 12 05:45:55 PM UTC 24 |
234926720 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1616240018 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:55 PM UTC 24 |
640899865 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.981684676 |
|
|
Oct 12 05:45:52 PM UTC 24 |
Oct 12 05:45:55 PM UTC 24 |
94725932 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.4031684447 |
|
|
Oct 12 05:45:52 PM UTC 24 |
Oct 12 05:45:55 PM UTC 24 |
110307423 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.496258031 |
|
|
Oct 12 05:45:53 PM UTC 24 |
Oct 12 05:45:55 PM UTC 24 |
136605788 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.4159698370 |
|
|
Oct 12 05:45:54 PM UTC 24 |
Oct 12 05:45:57 PM UTC 24 |
630999255 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1847432365 |
|
|
Oct 12 05:45:53 PM UTC 24 |
Oct 12 05:45:56 PM UTC 24 |
178544373 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.3686182904 |
|
|
Oct 12 05:45:55 PM UTC 24 |
Oct 12 05:45:57 PM UTC 24 |
91453467 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.2159628938 |
|
|
Oct 12 05:45:53 PM UTC 24 |
Oct 12 05:45:56 PM UTC 24 |
704164705 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.2324298397 |
|
|
Oct 12 05:45:54 PM UTC 24 |
Oct 12 05:45:57 PM UTC 24 |
72596296 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1641016440 |
|
|
Oct 12 05:45:52 PM UTC 24 |
Oct 12 05:45:56 PM UTC 24 |
414128023 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3585121095 |
|
|
Oct 12 05:45:51 PM UTC 24 |
Oct 12 05:45:56 PM UTC 24 |
75218963 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3622473675 |
|
|
Oct 12 05:45:50 PM UTC 24 |
Oct 12 05:45:56 PM UTC 24 |
327105147 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1361672401 |
|
|
Oct 12 05:45:45 PM UTC 24 |
Oct 12 05:45:56 PM UTC 24 |
10438408613 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.4119558651 |
|
|
Oct 12 05:45:54 PM UTC 24 |
Oct 12 05:45:57 PM UTC 24 |
39773127 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.10867879 |
|
|
Oct 12 05:45:56 PM UTC 24 |
Oct 12 05:45:59 PM UTC 24 |
45377381 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.307423910 |
|
|
Oct 12 05:45:52 PM UTC 24 |
Oct 12 05:45:57 PM UTC 24 |
398652040 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2183128828 |
|
|
Oct 12 05:45:54 PM UTC 24 |
Oct 12 05:45:57 PM UTC 24 |
84225729 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.2319338472 |
|
|
Oct 12 05:46:03 PM UTC 24 |
Oct 12 05:46:06 PM UTC 24 |
70106548 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.3754311572 |
|
|
Oct 12 05:45:54 PM UTC 24 |
Oct 12 05:45:58 PM UTC 24 |
75267361 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.6040934 |
|
|
Oct 12 05:45:54 PM UTC 24 |
Oct 12 05:45:58 PM UTC 24 |
667372272 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3591138006 |
|
|
Oct 12 05:45:52 PM UTC 24 |
Oct 12 05:45:58 PM UTC 24 |
158769063 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.4250698443 |
|
|
Oct 12 05:45:55 PM UTC 24 |
Oct 12 05:45:58 PM UTC 24 |
525397382 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1498788951 |
|
|
Oct 12 05:45:54 PM UTC 24 |
Oct 12 05:45:58 PM UTC 24 |
131598826 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.3506403481 |
|
|
Oct 12 05:45:54 PM UTC 24 |
Oct 12 05:45:58 PM UTC 24 |
684241121 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.4070861449 |
|
|
Oct 12 05:45:54 PM UTC 24 |
Oct 12 05:45:58 PM UTC 24 |
209679851 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.925412534 |
|
|
Oct 12 05:45:52 PM UTC 24 |
Oct 12 05:45:58 PM UTC 24 |
123420539 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.1579840192 |
|
|
Oct 12 05:45:54 PM UTC 24 |
Oct 12 05:45:59 PM UTC 24 |
218819683 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.935086928 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:59 PM UTC 24 |
563952324 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.3247670369 |
|
|
Oct 12 05:45:48 PM UTC 24 |
Oct 12 05:45:59 PM UTC 24 |
700227209 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.4223005045 |
|
|
Oct 12 05:45:56 PM UTC 24 |
Oct 12 05:45:59 PM UTC 24 |
93927824 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.2206008389 |
|
|
Oct 12 05:45:56 PM UTC 24 |
Oct 12 05:45:59 PM UTC 24 |
41534004 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3718211885 |
|
|
Oct 12 05:45:56 PM UTC 24 |
Oct 12 05:45:59 PM UTC 24 |
684108309 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.4063114689 |
|
|
Oct 12 05:45:56 PM UTC 24 |
Oct 12 05:45:59 PM UTC 24 |
240421467 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.1127560480 |
|
|
Oct 12 05:45:52 PM UTC 24 |
Oct 12 05:45:59 PM UTC 24 |
2201605862 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.2701446132 |
|
|
Oct 12 05:45:56 PM UTC 24 |
Oct 12 05:45:59 PM UTC 24 |
345503781 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.4051058631 |
|
|
Oct 12 05:45:56 PM UTC 24 |
Oct 12 05:46:00 PM UTC 24 |
671822682 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3009220308 |
|
|
Oct 12 05:45:54 PM UTC 24 |
Oct 12 05:46:00 PM UTC 24 |
166890275 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1446312156 |
|
|
Oct 12 05:45:56 PM UTC 24 |
Oct 12 05:46:00 PM UTC 24 |
141664150 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1120187053 |
|
|
Oct 12 05:45:56 PM UTC 24 |
Oct 12 05:46:00 PM UTC 24 |
993092236 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.3465052202 |
|
|
Oct 12 05:45:56 PM UTC 24 |
Oct 12 05:46:01 PM UTC 24 |
233834546 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.486007824 |
|
|
Oct 12 05:45:58 PM UTC 24 |
Oct 12 05:46:01 PM UTC 24 |
90024331 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.627584831 |
|
|
Oct 12 05:45:50 PM UTC 24 |
Oct 12 05:46:01 PM UTC 24 |
3006991891 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.3067430156 |
|
|
Oct 12 05:45:58 PM UTC 24 |
Oct 12 05:46:01 PM UTC 24 |
83419169 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.4279354423 |
|
|
Oct 12 05:45:50 PM UTC 24 |
Oct 12 05:46:01 PM UTC 24 |
1848602784 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.2017806450 |
|
|
Oct 12 05:45:58 PM UTC 24 |
Oct 12 05:46:01 PM UTC 24 |
154263357 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3117896597 |
|
|
Oct 12 05:45:53 PM UTC 24 |
Oct 12 05:46:01 PM UTC 24 |
671404559 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.4153071205 |
|
|
Oct 12 05:45:58 PM UTC 24 |
Oct 12 05:46:01 PM UTC 24 |
74526287 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3063238 |
|
|
Oct 12 05:45:54 PM UTC 24 |
Oct 12 05:46:01 PM UTC 24 |
142275237 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.479319804 |
|
|
Oct 12 05:45:58 PM UTC 24 |
Oct 12 05:46:01 PM UTC 24 |
158749052 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.3576833853 |
|
|
Oct 12 05:45:58 PM UTC 24 |
Oct 12 05:46:01 PM UTC 24 |
1055598833 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.4159139558 |
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Oct 12 05:45:56 PM UTC 24 |
Oct 12 05:46:01 PM UTC 24 |
274286277 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.2824296230 |
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Oct 12 05:45:56 PM UTC 24 |
Oct 12 05:46:02 PM UTC 24 |
74250530 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.4090432152 |
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Oct 12 05:45:58 PM UTC 24 |
Oct 12 05:46:02 PM UTC 24 |
121367676 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.1609201925 |
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Oct 12 05:46:00 PM UTC 24 |
Oct 12 05:46:02 PM UTC 24 |
108998747 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.4034877205 |
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Oct 12 05:46:00 PM UTC 24 |
Oct 12 05:46:02 PM UTC 24 |
46029977 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.1007742356 |
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Oct 12 05:46:00 PM UTC 24 |
Oct 12 05:46:02 PM UTC 24 |
128943087 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.592319205 |
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Oct 12 05:46:00 PM UTC 24 |
Oct 12 05:46:02 PM UTC 24 |
611375002 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3568386471 |
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Oct 12 05:46:00 PM UTC 24 |
Oct 12 05:46:02 PM UTC 24 |
44907288 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.1633254831 |
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Oct 12 05:46:00 PM UTC 24 |
Oct 12 05:46:02 PM UTC 24 |
85978127 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.3764436117 |
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Oct 12 05:45:58 PM UTC 24 |
Oct 12 05:46:02 PM UTC 24 |
261939219 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.1755436780 |
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Oct 12 05:46:00 PM UTC 24 |
Oct 12 05:46:02 PM UTC 24 |
148565435 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.884763212 |
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Oct 12 05:45:56 PM UTC 24 |
Oct 12 05:46:02 PM UTC 24 |
1651017636 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.3900191619 |
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Oct 12 05:46:00 PM UTC 24 |
Oct 12 05:46:02 PM UTC 24 |
41741165 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.2147531394 |
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Oct 12 05:46:00 PM UTC 24 |
Oct 12 05:46:03 PM UTC 24 |
41360640 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.738448923 |
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Oct 12 05:45:54 PM UTC 24 |
Oct 12 05:46:03 PM UTC 24 |
2891478814 ps |