| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 95.12 | 93.73 | 96.73 | 95.73 | 92.53 | 97.54 | 96.37 | 93.21 |
| T1265 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.404138536 | Oct 12 05:46:00 PM UTC 24 | Oct 12 05:46:03 PM UTC 24 | 50930607 ps | ||
| T1266 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.2238520697 | Oct 12 05:46:00 PM UTC 24 | Oct 12 05:46:03 PM UTC 24 | 581144868 ps | ||
| T1267 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2607876332 | Oct 12 05:45:58 PM UTC 24 | Oct 12 05:46:03 PM UTC 24 | 150066706 ps | ||
| T1268 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.155868347 | Oct 12 05:46:00 PM UTC 24 | Oct 12 05:46:03 PM UTC 24 | 39179091 ps | ||
| T1269 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.128194176 | Oct 12 05:45:58 PM UTC 24 | Oct 12 05:46:03 PM UTC 24 | 1583020114 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1709618120 | Oct 12 05:45:52 PM UTC 24 | Oct 12 05:46:03 PM UTC 24 | 926490213 ps | ||
| T1270 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3628575550 | Oct 12 05:46:00 PM UTC 24 | Oct 12 05:46:03 PM UTC 24 | 171382585 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3049618300 | Oct 12 05:46:00 PM UTC 24 | Oct 12 05:46:04 PM UTC 24 | 120804006 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.2565174091 | Oct 12 05:45:54 PM UTC 24 | Oct 12 05:46:04 PM UTC 24 | 662615937 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1948032539 | Oct 12 05:46:00 PM UTC 24 | Oct 12 05:46:04 PM UTC 24 | 122837662 ps | ||
| T1273 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3623916236 | Oct 12 05:46:00 PM UTC 24 | Oct 12 05:46:04 PM UTC 24 | 249833708 ps | ||
| T1274 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3944350480 | Oct 12 05:46:00 PM UTC 24 | Oct 12 05:46:04 PM UTC 24 | 1050198844 ps | ||
| T1275 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.4166455020 | Oct 12 05:46:02 PM UTC 24 | Oct 12 05:46:05 PM UTC 24 | 557597542 ps | ||
| T1276 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.2830355766 | Oct 12 05:46:02 PM UTC 24 | Oct 12 05:46:05 PM UTC 24 | 56597824 ps | ||
| T1277 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.391464921 | Oct 12 05:46:02 PM UTC 24 | Oct 12 05:46:05 PM UTC 24 | 49383813 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2894867742 | Oct 12 05:45:53 PM UTC 24 | Oct 12 05:46:05 PM UTC 24 | 1422612660 ps | ||
| T1278 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.655147826 | Oct 12 05:46:02 PM UTC 24 | Oct 12 05:46:05 PM UTC 24 | 35916695 ps | ||
| T1279 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.3604024871 | Oct 12 05:46:02 PM UTC 24 | Oct 12 05:46:05 PM UTC 24 | 76329254 ps | ||
| T1280 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.2797661893 | Oct 12 05:46:03 PM UTC 24 | Oct 12 05:46:05 PM UTC 24 | 41869551 ps | ||
| T1281 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.606447865 | Oct 12 05:46:02 PM UTC 24 | Oct 12 05:46:05 PM UTC 24 | 38300232 ps | ||
| T1282 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.1482300835 | Oct 12 05:46:02 PM UTC 24 | Oct 12 05:46:05 PM UTC 24 | 37673815 ps | ||
| T1283 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.2809931358 | Oct 12 05:46:03 PM UTC 24 | Oct 12 05:46:06 PM UTC 24 | 143127615 ps | ||
| T1284 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.3634439230 | Oct 12 05:46:02 PM UTC 24 | Oct 12 05:46:06 PM UTC 24 | 48394923 ps | ||
| T1285 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.4257106490 | Oct 12 05:46:03 PM UTC 24 | Oct 12 05:46:06 PM UTC 24 | 42337119 ps | ||
| T1286 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.2895439929 | Oct 12 05:46:03 PM UTC 24 | Oct 12 05:46:06 PM UTC 24 | 146579399 ps | ||
| T1287 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.2993686528 | Oct 12 05:46:02 PM UTC 24 | Oct 12 05:46:06 PM UTC 24 | 526260813 ps | ||
| T1288 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.3523090396 | Oct 12 05:46:02 PM UTC 24 | Oct 12 05:46:06 PM UTC 24 | 144379571 ps | ||
| T1289 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.40030977 | Oct 12 05:46:03 PM UTC 24 | Oct 12 05:46:06 PM UTC 24 | 584832086 ps | ||
| T1290 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.3236451093 | Oct 12 05:46:03 PM UTC 24 | Oct 12 05:46:06 PM UTC 24 | 47514364 ps | ||
| T1291 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.2277303420 | Oct 12 05:46:03 PM UTC 24 | Oct 12 05:46:06 PM UTC 24 | 87745380 ps | ||
| T1292 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.2836771706 | Oct 12 05:46:03 PM UTC 24 | Oct 12 05:46:06 PM UTC 24 | 99154671 ps | ||
| T1293 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.2058953180 | Oct 12 05:46:04 PM UTC 24 | Oct 12 05:46:07 PM UTC 24 | 134467904 ps | ||
| T1294 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.1888868151 | Oct 12 05:46:04 PM UTC 24 | Oct 12 05:46:07 PM UTC 24 | 132366689 ps | ||
| T1295 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.2686287557 | Oct 12 05:46:04 PM UTC 24 | Oct 12 05:46:07 PM UTC 24 | 565682361 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2540190819 | Oct 12 05:45:58 PM UTC 24 | Oct 12 05:46:08 PM UTC 24 | 9711041908 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1967578305 | Oct 12 05:45:50 PM UTC 24 | Oct 12 05:46:11 PM UTC 24 | 3104821511 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3947709978 | Oct 12 05:45:52 PM UTC 24 | Oct 12 05:46:13 PM UTC 24 | 5148754978 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.2759177577 | Oct 12 05:45:52 PM UTC 24 | Oct 12 05:46:14 PM UTC 24 | 2546611028 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2268426059 | Oct 12 05:45:56 PM UTC 24 | Oct 12 05:46:14 PM UTC 24 | 4258375447 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1280274906 | Oct 12 05:45:54 PM UTC 24 | Oct 12 05:46:14 PM UTC 24 | 3050560445 ps | ||
| T1296 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.4293567173 | Oct 12 05:45:54 PM UTC 24 | Oct 12 05:46:15 PM UTC 24 | 4861341035 ps | ||
| T403 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2876094040 | Oct 12 05:46:00 PM UTC 24 | Oct 12 05:46:17 PM UTC 24 | 1335752903 ps | ||
| T399 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.233193975 | Oct 12 05:45:56 PM UTC 24 | Oct 12 05:46:19 PM UTC 24 | 3841042267 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.2018020164 | Oct 12 05:45:48 PM UTC 24 | Oct 12 05:46:19 PM UTC 24 | 18826582795 ps | ||
| T401 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1626300688 | Oct 12 05:46:00 PM UTC 24 | Oct 12 05:46:20 PM UTC 24 | 19016425560 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.790067339 | Oct 12 05:45:58 PM UTC 24 | Oct 12 05:46:23 PM UTC 24 | 4860950239 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_macro_errs.3133609061 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1439158595 ps |
| CPU time | 18.53 seconds |
| Started | Oct 12 05:37:29 PM UTC 24 |
| Finished | Oct 12 05:37:49 PM UTC 24 |
| Peak memory | 255216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133609061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.3133609061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_key_req.623256394 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1346209253 ps |
| CPU time | 13.39 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:37:26 PM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623256394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.623256394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.1381784473 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2119048116 ps |
| CPU time | 50.45 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:38:03 PM UTC 24 |
| Peak memory | 259032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1381784473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.otp_ctrl_stress_all_with_rand_reset.1381784473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_test_access.865844016 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 1084667909 ps |
| CPU time | 20.6 seconds |
| Started | Oct 12 05:37:15 PM UTC 24 |
| Finished | Oct 12 05:37:37 PM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865844016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.865844016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_check_fail.3493650696 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 9545225072 ps |
| CPU time | 22.57 seconds |
| Started | Oct 12 05:37:21 PM UTC 24 |
| Finished | Oct 12 05:37:46 PM UTC 24 |
| Peak memory | 259028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493650696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.3493650696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_req.3698620749 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1313783894 ps |
| CPU time | 18.69 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:31 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698620749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.3698620749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all.2828239876 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 7383889921 ps |
| CPU time | 127.79 seconds |
| Started | Oct 12 05:37:48 PM UTC 24 |
| Finished | Oct 12 05:39:59 PM UTC 24 |
| Peak memory | 269528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828239876 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.2828239876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_background_chks.3660996693 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 327830988 ps |
| CPU time | 4.95 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:23 PM UTC 24 |
| Peak memory | 252900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660996693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.3660996693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_sec_cm.1204238350 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 20286389485 ps |
| CPU time | 157.81 seconds |
| Started | Oct 12 05:37:25 PM UTC 24 |
| Finished | Oct 12 05:40:06 PM UTC 24 |
| Peak memory | 289192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204238350 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.1204238350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all.2964255348 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3240445779 ps |
| CPU time | 90.37 seconds |
| Started | Oct 12 05:37:25 PM UTC 24 |
| Finished | Oct 12 05:38:58 PM UTC 24 |
| Peak memory | 258904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964255348 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.2964255348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_check_fail.2050162450 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3005803500 ps |
| CPU time | 31.56 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:37:44 PM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050162450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.2050162450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_esc.1568327036 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 754754626 ps |
| CPU time | 6.77 seconds |
| Started | Oct 12 05:37:44 PM UTC 24 |
| Finished | Oct 12 05:37:53 PM UTC 24 |
| Peak memory | 252624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568327036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.1568327036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_init_fail.3346803972 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 190603836 ps |
| CPU time | 4.21 seconds |
| Started | Oct 12 05:43:41 PM UTC 24 |
| Finished | Oct 12 05:43:46 PM UTC 24 |
| Peak memory | 254756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346803972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.3346803972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/86.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_background_chks.3076914766 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1508976611 ps |
| CPU time | 16.29 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:28 PM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076914766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.3076914766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all.2749275784 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 13320431646 ps |
| CPU time | 107.43 seconds |
| Started | Oct 12 05:37:19 PM UTC 24 |
| Finished | Oct 12 05:39:08 PM UTC 24 |
| Peak memory | 258964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749275784 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.2749275784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.2448886462 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 12652757683 ps |
| CPU time | 175.61 seconds |
| Started | Oct 12 05:37:41 PM UTC 24 |
| Finished | Oct 12 05:40:40 PM UTC 24 |
| Peak memory | 269412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2448886462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.otp_ctrl_stress_all_with_rand_reset.2448886462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.692392528 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1191592734 ps |
| CPU time | 8.74 seconds |
| Started | Oct 12 05:45:46 PM UTC 24 |
| Finished | Oct 12 05:45:55 PM UTC 24 |
| Peak memory | 254856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692392528 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_intg_err.692392528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_lock.4087577493 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 10389029538 ps |
| CPU time | 23.46 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:37:36 PM UTC 24 |
| Peak memory | 259056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087577493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.4087577493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_init_fail.830269761 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 243783191 ps |
| CPU time | 5.48 seconds |
| Started | Oct 12 05:43:17 PM UTC 24 |
| Finished | Oct 12 05:43:24 PM UTC 24 |
| Peak memory | 252564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830269761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.830269761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/72.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_macro_errs.177207928 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 24161342319 ps |
| CPU time | 59.91 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:38:13 PM UTC 24 |
| Peak memory | 269324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177207928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.177207928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_check_fail.3844737188 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11711122387 ps |
| CPU time | 29.3 seconds |
| Started | Oct 12 05:37:29 PM UTC 24 |
| Finished | Oct 12 05:38:00 PM UTC 24 |
| Peak memory | 255216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844737188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.3844737188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_init_fail.3115715648 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 484890180 ps |
| CPU time | 4.6 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:23 PM UTC 24 |
| Peak memory | 254480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115715648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.3115715648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_init_fail.3262439293 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 588759641 ps |
| CPU time | 6.14 seconds |
| Started | Oct 12 05:38:28 PM UTC 24 |
| Finished | Oct 12 05:38:35 PM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262439293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.3262439293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_background_chks.484954042 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1410969388 ps |
| CPU time | 20.5 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:37:33 PM UTC 24 |
| Peak memory | 253036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484954042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.484954042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_esc.1486904934 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 606447064 ps |
| CPU time | 5.94 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:37:18 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486904934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.1486904934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.4012795983 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 2717237140 ps |
| CPU time | 109.87 seconds |
| Started | Oct 12 05:41:14 PM UTC 24 |
| Finished | Oct 12 05:43:06 PM UTC 24 |
| Peak memory | 258932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4012795983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.otp_ctrl_stress_all_with_rand_reset.4012795983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_alert_test.360540479 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 174177874 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:37:14 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360540479 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.360540479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_init_fail.2456854590 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 144665141 ps |
| CPU time | 4.21 seconds |
| Started | Oct 12 05:43:54 PM UTC 24 |
| Finished | Oct 12 05:43:59 PM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456854590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.2456854590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/95.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all.2391781504 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 28678785212 ps |
| CPU time | 172.37 seconds |
| Started | Oct 12 05:41:09 PM UTC 24 |
| Finished | Oct 12 05:44:04 PM UTC 24 |
| Peak memory | 259048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391781504 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.2391781504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_errs.4127022486 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3486055851 ps |
| CPU time | 13.97 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:37:26 PM UTC 24 |
| Peak memory | 252912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127022486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.4127022486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2114952924 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 536034790 ps |
| CPU time | 1.95 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:48 PM UTC 24 |
| Peak memory | 250620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114952924 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.2114952924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_init_fail.1373954216 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 191752468 ps |
| CPU time | 4.91 seconds |
| Started | Oct 12 05:37:44 PM UTC 24 |
| Finished | Oct 12 05:37:51 PM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373954216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.1373954216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_init_fail.4154299575 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 300934309 ps |
| CPU time | 5.98 seconds |
| Started | Oct 12 05:38:13 PM UTC 24 |
| Finished | Oct 12 05:38:20 PM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154299575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.4154299575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all.1449834446 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 105936218710 ps |
| CPU time | 231.63 seconds |
| Started | Oct 12 05:38:40 PM UTC 24 |
| Finished | Oct 12 05:42:35 PM UTC 24 |
| Peak memory | 285168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449834446 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.1449834446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_init_fail.2778109882 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1799116735 ps |
| CPU time | 4.96 seconds |
| Started | Oct 12 05:39:03 PM UTC 24 |
| Finished | Oct 12 05:39:09 PM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778109882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.2778109882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/20.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.4111456966 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 181571345 ps |
| CPU time | 3.25 seconds |
| Started | Oct 12 05:45:32 PM UTC 24 |
| Finished | Oct 12 05:45:36 PM UTC 24 |
| Peak memory | 253016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111456966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.4111456966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/262.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_init_fail.1708729936 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 284525255 ps |
| CPU time | 7.19 seconds |
| Started | Oct 12 05:37:19 PM UTC 24 |
| Finished | Oct 12 05:37:28 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708729936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.1708729936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.45111856 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 288200364 ps |
| CPU time | 4.22 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:29 PM UTC 24 |
| Peak memory | 252736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45111856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.45111856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/209.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_lock.3590252102 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1573089127 ps |
| CPU time | 16.54 seconds |
| Started | Oct 12 05:37:35 PM UTC 24 |
| Finished | Oct 12 05:37:53 PM UTC 24 |
| Peak memory | 254900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590252102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.3590252102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_init_fail.2806098973 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 188313987 ps |
| CPU time | 5.59 seconds |
| Started | Oct 12 05:40:43 PM UTC 24 |
| Finished | Oct 12 05:40:49 PM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806098973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.2806098973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/32.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_regwen.1676841816 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 664264766 ps |
| CPU time | 10.04 seconds |
| Started | Oct 12 05:37:25 PM UTC 24 |
| Finished | Oct 12 05:37:36 PM UTC 24 |
| Peak memory | 252964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676841816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.1676841816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all.933469432 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 18428946300 ps |
| CPU time | 106.43 seconds |
| Started | Oct 12 05:38:07 PM UTC 24 |
| Finished | Oct 12 05:39:56 PM UTC 24 |
| Peak memory | 259260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933469432 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.933469432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_check_fail.4063670145 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1819794293 ps |
| CPU time | 27.81 seconds |
| Started | Oct 12 05:37:41 PM UTC 24 |
| Finished | Oct 12 05:38:10 PM UTC 24 |
| Peak memory | 252848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063670145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.4063670145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_init_fail.2037828149 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 300663679 ps |
| CPU time | 5.5 seconds |
| Started | Oct 12 05:44:14 PM UTC 24 |
| Finished | Oct 12 05:44:21 PM UTC 24 |
| Peak memory | 254744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037828149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.2037828149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/107.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_key_req.2470742562 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 16158743822 ps |
| CPU time | 38.09 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:37:50 PM UTC 24 |
| Peak memory | 258988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470742562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.2470742562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_init_fail.1961352107 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 267502960 ps |
| CPU time | 3.82 seconds |
| Started | Oct 12 05:43:02 PM UTC 24 |
| Finished | Oct 12 05:43:07 PM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961352107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.1961352107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/59.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.2522091868 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2142625677 ps |
| CPU time | 59.69 seconds |
| Started | Oct 12 05:39:49 PM UTC 24 |
| Finished | Oct 12 05:40:50 PM UTC 24 |
| Peak memory | 259172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2522091868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 25.otp_ctrl_stress_all_with_rand_reset.2522091868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_check_fail.1766812349 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2566337575 ps |
| CPU time | 28.25 seconds |
| Started | Oct 12 05:38:26 PM UTC 24 |
| Finished | Oct 12 05:38:55 PM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766812349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.1766812349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all.279298379 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 36547018084 ps |
| CPU time | 258.91 seconds |
| Started | Oct 12 05:40:48 PM UTC 24 |
| Finished | Oct 12 05:45:11 PM UTC 24 |
| Peak memory | 302116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279298379 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.279298379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all.3967079303 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 8312897228 ps |
| CPU time | 94.89 seconds |
| Started | Oct 12 05:39:56 PM UTC 24 |
| Finished | Oct 12 05:41:33 PM UTC 24 |
| Peak memory | 256988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967079303 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.3967079303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_init_fail.3345440858 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 367871850 ps |
| CPU time | 5.71 seconds |
| Started | Oct 12 05:40:15 PM UTC 24 |
| Finished | Oct 12 05:40:22 PM UTC 24 |
| Peak memory | 252792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345440858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.3345440858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/29.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all.2714288535 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 37268538744 ps |
| CPU time | 181.31 seconds |
| Started | Oct 12 05:37:40 PM UTC 24 |
| Finished | Oct 12 05:40:45 PM UTC 24 |
| Peak memory | 275400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714288535 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.2714288535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.2759177577 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 2546611028 ps |
| CPU time | 20.55 seconds |
| Started | Oct 12 05:45:52 PM UTC 24 |
| Finished | Oct 12 05:46:14 PM UTC 24 |
| Peak memory | 254908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759177577 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_intg_err.2759177577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.2350473535 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 12841711544 ps |
| CPU time | 83.87 seconds |
| Started | Oct 12 05:43:12 PM UTC 24 |
| Finished | Oct 12 05:44:38 PM UTC 24 |
| Peak memory | 269208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2350473535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 69.otp_ctrl_stress_all_with_rand_reset.2350473535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/69.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_req.2617005432 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 7467350401 ps |
| CPU time | 22.01 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:40 PM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617005432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.2617005432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all.2950043616 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 16632696988 ps |
| CPU time | 96.84 seconds |
| Started | Oct 12 05:38:54 PM UTC 24 |
| Finished | Oct 12 05:40:33 PM UTC 24 |
| Peak memory | 269164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950043616 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.2950043616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_regwen.3561513378 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1163193562 ps |
| CPU time | 12.87 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:31 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561513378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.3561513378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_req.1589703059 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 1137956773 ps |
| CPU time | 23.77 seconds |
| Started | Oct 12 05:38:35 PM UTC 24 |
| Finished | Oct 12 05:39:00 PM UTC 24 |
| Peak memory | 259148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589703059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.1589703059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all.3419801474 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 122361979163 ps |
| CPU time | 284.38 seconds |
| Started | Oct 12 05:40:43 PM UTC 24 |
| Finished | Oct 12 05:45:31 PM UTC 24 |
| Peak memory | 269212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419801474 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.3419801474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.2761162116 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 124587397 ps |
| CPU time | 3.42 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:36 PM UTC 24 |
| Peak memory | 254696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761162116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.2761162116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/251.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.1850485912 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1641778114 ps |
| CPU time | 59.32 seconds |
| Started | Oct 12 05:42:57 PM UTC 24 |
| Finished | Oct 12 05:43:58 PM UTC 24 |
| Peak memory | 259044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1850485912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 54.otp_ctrl_stress_all_with_rand_reset.1850485912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/54.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_parallel_lc_esc.345592845 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 876914185 ps |
| CPU time | 7.95 seconds |
| Started | Oct 12 05:43:10 PM UTC 24 |
| Finished | Oct 12 05:43:19 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345592845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.345592845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/68.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_macro_errs.184478880 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2424182829 ps |
| CPU time | 34.02 seconds |
| Started | Oct 12 05:37:25 PM UTC 24 |
| Finished | Oct 12 05:38:00 PM UTC 24 |
| Peak memory | 259020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184478880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.184478880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_init_fail.2484216936 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2681927389 ps |
| CPU time | 8.17 seconds |
| Started | Oct 12 05:44:29 PM UTC 24 |
| Finished | Oct 12 05:44:38 PM UTC 24 |
| Peak memory | 254808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484216936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.2484216936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/116.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.3204098396 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 246090914 ps |
| CPU time | 6.43 seconds |
| Started | Oct 12 05:45:14 PM UTC 24 |
| Finished | Oct 12 05:45:22 PM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204098396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.3204098396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/189.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_parallel_lc_esc.2100673326 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 607459106 ps |
| CPU time | 10.82 seconds |
| Started | Oct 12 05:43:12 PM UTC 24 |
| Finished | Oct 12 05:43:24 PM UTC 24 |
| Peak memory | 252936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100673326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.2100673326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/69.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.2563651290 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 6249811608 ps |
| CPU time | 134.49 seconds |
| Started | Oct 12 05:43:29 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 269412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2563651290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 79.otp_ctrl_stress_all_with_rand_reset.2563651290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.629766996 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 3552711206 ps |
| CPU time | 80.34 seconds |
| Started | Oct 12 05:43:53 PM UTC 24 |
| Finished | Oct 12 05:45:15 PM UTC 24 |
| Peak memory | 269420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=629766996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.629766996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_test_access.2857284577 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 2832727833 ps |
| CPU time | 27.25 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:45 PM UTC 24 |
| Peak memory | 254864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857284577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.2857284577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_test_access.3390274089 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 13587059483 ps |
| CPU time | 28.56 seconds |
| Started | Oct 12 05:38:46 PM UTC 24 |
| Finished | Oct 12 05:39:16 PM UTC 24 |
| Peak memory | 259056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390274089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.3390274089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1280274906 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 3050560445 ps |
| CPU time | 18.78 seconds |
| Started | Oct 12 05:45:54 PM UTC 24 |
| Finished | Oct 12 05:46:14 PM UTC 24 |
| Peak memory | 254988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280274906 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_intg_err.1280274906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_regwen.3765208559 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 469746697 ps |
| CPU time | 10.16 seconds |
| Started | Oct 12 05:40:38 PM UTC 24 |
| Finished | Oct 12 05:40:49 PM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765208559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.3765208559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/31.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.3099847081 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 70649674025 ps |
| CPU time | 168.09 seconds |
| Started | Oct 12 05:43:43 PM UTC 24 |
| Finished | Oct 12 05:46:34 PM UTC 24 |
| Peak memory | 268904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3099847081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 87.otp_ctrl_stress_all_with_rand_reset.3099847081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/87.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all.1477825657 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 32917537919 ps |
| CPU time | 273.12 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:41:54 PM UTC 24 |
| Peak memory | 273320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477825657 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.1477825657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.790067339 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 4860950239 ps |
| CPU time | 23.51 seconds |
| Started | Oct 12 05:45:58 PM UTC 24 |
| Finished | Oct 12 05:46:23 PM UTC 24 |
| Peak memory | 250800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790067339 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_intg_err.790067339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all.2675296865 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 24838116176 ps |
| CPU time | 216.17 seconds |
| Started | Oct 12 05:37:57 PM UTC 24 |
| Finished | Oct 12 05:41:36 PM UTC 24 |
| Peak memory | 265192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675296865 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.2675296865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3547569984 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 166112223 ps |
| CPU time | 5.38 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:51 PM UTC 24 |
| Peak memory | 250588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547569984 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_aliasing.3547569984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_init_fail.1295022589 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 449122208 ps |
| CPU time | 3.94 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:37:16 PM UTC 24 |
| Peak memory | 252976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295022589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.1295022589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_check_fail.1336531075 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1443414348 ps |
| CPU time | 25.28 seconds |
| Started | Oct 12 05:37:40 PM UTC 24 |
| Finished | Oct 12 05:38:07 PM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336531075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.1336531075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all.2512315334 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 35113227330 ps |
| CPU time | 299.27 seconds |
| Started | Oct 12 05:38:26 PM UTC 24 |
| Finished | Oct 12 05:43:30 PM UTC 24 |
| Peak memory | 289768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512315334 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.2512315334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_req.4229222775 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 643152217 ps |
| CPU time | 15.75 seconds |
| Started | Oct 12 05:37:52 PM UTC 24 |
| Finished | Oct 12 05:38:08 PM UTC 24 |
| Peak memory | 252752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229222775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.4229222775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_init_fail.1448019991 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 396871828 ps |
| CPU time | 3.68 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:15 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448019991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.1448019991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_init_fail.2820489859 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1917868827 ps |
| CPU time | 7.22 seconds |
| Started | Oct 12 05:44:17 PM UTC 24 |
| Finished | Oct 12 05:44:25 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820489859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.2820489859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/108.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_init_fail.1226726691 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 635409334 ps |
| CPU time | 5.04 seconds |
| Started | Oct 12 05:44:22 PM UTC 24 |
| Finished | Oct 12 05:44:28 PM UTC 24 |
| Peak memory | 254824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226726691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.1226726691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/112.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_init_fail.2631108690 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 218142925 ps |
| CPU time | 4.69 seconds |
| Started | Oct 12 05:38:35 PM UTC 24 |
| Finished | Oct 12 05:38:41 PM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631108690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.2631108690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all.911492576 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 18632261855 ps |
| CPU time | 266.26 seconds |
| Started | Oct 12 05:38:00 PM UTC 24 |
| Finished | Oct 12 05:42:31 PM UTC 24 |
| Peak memory | 269308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911492576 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.911492576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_regwen.2154291816 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 151420686 ps |
| CPU time | 7.68 seconds |
| Started | Oct 12 05:38:38 PM UTC 24 |
| Finished | Oct 12 05:38:46 PM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154291816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.2154291816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_esc.2628861891 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 576097820 ps |
| CPU time | 17.06 seconds |
| Started | Oct 12 05:40:17 PM UTC 24 |
| Finished | Oct 12 05:40:36 PM UTC 24 |
| Peak memory | 252924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628861891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.2628861891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_regwen.2229789744 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 288560678 ps |
| CPU time | 9.71 seconds |
| Started | Oct 12 05:38:51 PM UTC 24 |
| Finished | Oct 12 05:39:02 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229789744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.2229789744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1967578305 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 3104821511 ps |
| CPU time | 19.55 seconds |
| Started | Oct 12 05:45:50 PM UTC 24 |
| Finished | Oct 12 05:46:11 PM UTC 24 |
| Peak memory | 254940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967578305 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg_err.1967578305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.1273809638 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 85452436854 ps |
| CPU time | 192.98 seconds |
| Started | Oct 12 05:43:13 PM UTC 24 |
| Finished | Oct 12 05:46:29 PM UTC 24 |
| Peak memory | 269700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1273809638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 70.otp_ctrl_stress_all_with_rand_reset.1273809638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/70.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_wake_up.1982592099 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 188571120 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:13 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982592099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes t +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.1982592099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_init_fail.2540498544 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 126411853 ps |
| CPU time | 3.1 seconds |
| Started | Oct 12 05:44:59 PM UTC 24 |
| Finished | Oct 12 05:45:03 PM UTC 24 |
| Peak memory | 254956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540498544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.2540498544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/159.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_smoke.3302505134 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 5573203596 ps |
| CPU time | 9.53 seconds |
| Started | Oct 12 05:37:44 PM UTC 24 |
| Finished | Oct 12 05:37:55 PM UTC 24 |
| Peak memory | 252860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302505134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.3302505134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_test_access.3079031263 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2437487585 ps |
| CPU time | 12.99 seconds |
| Started | Oct 12 05:37:25 PM UTC 24 |
| Finished | Oct 12 05:37:39 PM UTC 24 |
| Peak memory | 254364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079031263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.3079031263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all.2630283555 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 97122114682 ps |
| CPU time | 268.16 seconds |
| Started | Oct 12 05:40:23 PM UTC 24 |
| Finished | Oct 12 05:44:55 PM UTC 24 |
| Peak memory | 275420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630283555 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.2630283555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.1156376826 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 16215238768 ps |
| CPU time | 180.05 seconds |
| Started | Oct 12 05:43:25 PM UTC 24 |
| Finished | Oct 12 05:46:28 PM UTC 24 |
| Peak memory | 269336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1156376826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 77.otp_ctrl_stress_all_with_rand_reset.1156376826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/77.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_req.497324829 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 801446401 ps |
| CPU time | 23.73 seconds |
| Started | Oct 12 05:38:13 PM UTC 24 |
| Finished | Oct 12 05:38:38 PM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497324829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.497324829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_check_fail.1547970196 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 2829641657 ps |
| CPU time | 22.03 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:37:34 PM UTC 24 |
| Peak memory | 254956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547970196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.1547970196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_check_fail.2233216564 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2009333321 ps |
| CPU time | 35.49 seconds |
| Started | Oct 12 05:37:57 PM UTC 24 |
| Finished | Oct 12 05:38:34 PM UTC 24 |
| Peak memory | 259084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233216564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.2233216564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_init_fail.1729210639 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 462419244 ps |
| CPU time | 4.72 seconds |
| Started | Oct 12 05:43:28 PM UTC 24 |
| Finished | Oct 12 05:43:34 PM UTC 24 |
| Peak memory | 255032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729210639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.1729210639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/79.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_key_req.1342455429 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 146607735 ps |
| CPU time | 6.46 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:24 PM UTC 24 |
| Peak memory | 258876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342455429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.1342455429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.2270977481 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 87552165109 ps |
| CPU time | 165.33 seconds |
| Started | Oct 12 05:37:41 PM UTC 24 |
| Finished | Oct 12 05:40:29 PM UTC 24 |
| Peak memory | 302116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270977481 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.2270977481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_macro_errs.1557449424 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3035587549 ps |
| CPU time | 21.19 seconds |
| Started | Oct 12 05:37:57 PM UTC 24 |
| Finished | Oct 12 05:38:20 PM UTC 24 |
| Peak memory | 256956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557449424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.1557449424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.956446630 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 824317297 ps |
| CPU time | 5.16 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:51 PM UTC 24 |
| Peak memory | 250560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956446630 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_bash.956446630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.3271804405 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1532081707 ps |
| CPU time | 2.8 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:49 PM UTC 24 |
| Peak memory | 250760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271804405 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_reset.3271804405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2248383462 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 75215486 ps |
| CPU time | 2.23 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:48 PM UTC 24 |
| Peak memory | 256932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2248383462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_cs r_mem_rw_with_rand_reset.2248383462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2292113763 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 149468192 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:47 PM UTC 24 |
| Peak memory | 250440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292113763 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.2292113763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.3069646933 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 76740132 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:47 PM UTC 24 |
| Peak memory | 238836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069646933 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.3069646933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2120892693 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 39553550 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:47 PM UTC 24 |
| Peak memory | 238844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120892693 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_partial_access.2120892693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.2776954889 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 142311020 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:47 PM UTC 24 |
| Peak memory | 239064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776954889 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.2776954889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.2855681593 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 189711171 ps |
| CPU time | 1.99 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:48 PM UTC 24 |
| Peak memory | 250504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855681593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_same_csr_outstanding.2855681593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.604402483 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 880527235 ps |
| CPU time | 3.9 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:50 PM UTC 24 |
| Peak memory | 257000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604402483 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.604402483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1616240018 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 640899865 ps |
| CPU time | 8.95 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:55 PM UTC 24 |
| Peak memory | 250760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616240018 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_intg_err.1616240018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2579221129 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 730893780 ps |
| CPU time | 6.5 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:53 PM UTC 24 |
| Peak memory | 250596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579221129 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_aliasing.2579221129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.352336657 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 326379196 ps |
| CPU time | 5.66 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:52 PM UTC 24 |
| Peak memory | 250688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352336657 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_bash.352336657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.4169937171 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 254782195 ps |
| CPU time | 1.91 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:48 PM UTC 24 |
| Peak memory | 250580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169937171 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_reset.4169937171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.850564876 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 199423713 ps |
| CPU time | 3.28 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:50 PM UTC 24 |
| Peak memory | 256828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=850564876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr _mem_rw_with_rand_reset.850564876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.2999485287 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 116867595 ps |
| CPU time | 1.65 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:48 PM UTC 24 |
| Peak memory | 238776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999485287 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.2999485287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2002791010 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 130305197 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:48 PM UTC 24 |
| Peak memory | 238580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002791010 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_partial_access.2002791010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.1022755269 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 498327875 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:48 PM UTC 24 |
| Peak memory | 238640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022755269 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.1022755269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.368108002 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 178753814 ps |
| CPU time | 2.29 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:49 PM UTC 24 |
| Peak memory | 250768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368108002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_same_csr_outstanding.368108002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1518021388 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 174287943 ps |
| CPU time | 5.54 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:52 PM UTC 24 |
| Peak memory | 256876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518021388 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.1518021388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1361672401 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 10438408613 ps |
| CPU time | 10.11 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:56 PM UTC 24 |
| Peak memory | 250976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361672401 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_intg_err.1361672401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.1579840192 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 218819683 ps |
| CPU time | 3.63 seconds |
| Started | Oct 12 05:45:54 PM UTC 24 |
| Finished | Oct 12 05:45:59 PM UTC 24 |
| Peak memory | 256480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1579840192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_c sr_mem_rw_with_rand_reset.1579840192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.2159628938 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 704164705 ps |
| CPU time | 2 seconds |
| Started | Oct 12 05:45:53 PM UTC 24 |
| Finished | Oct 12 05:45:56 PM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159628938 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.2159628938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.496258031 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 136605788 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 05:45:53 PM UTC 24 |
| Finished | Oct 12 05:45:55 PM UTC 24 |
| Peak memory | 238512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496258031 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.496258031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.6040934 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 667372272 ps |
| CPU time | 2.6 seconds |
| Started | Oct 12 05:45:54 PM UTC 24 |
| Finished | Oct 12 05:45:58 PM UTC 24 |
| Peak memory | 250108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6040934 -assert nopostproc +U VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_same_csr_outstanding.6040934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3117896597 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 671404559 ps |
| CPU time | 7.11 seconds |
| Started | Oct 12 05:45:53 PM UTC 24 |
| Finished | Oct 12 05:46:01 PM UTC 24 |
| Peak memory | 256900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117896597 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.3117896597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2894867742 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 1422612660 ps |
| CPU time | 11.41 seconds |
| Started | Oct 12 05:45:53 PM UTC 24 |
| Finished | Oct 12 05:46:05 PM UTC 24 |
| Peak memory | 254820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894867742 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_intg_err.2894867742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.4070861449 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 209679851 ps |
| CPU time | 3 seconds |
| Started | Oct 12 05:45:54 PM UTC 24 |
| Finished | Oct 12 05:45:58 PM UTC 24 |
| Peak memory | 256928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4070861449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_c sr_mem_rw_with_rand_reset.4070861449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.4159698370 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 630999255 ps |
| CPU time | 2.08 seconds |
| Started | Oct 12 05:45:54 PM UTC 24 |
| Finished | Oct 12 05:45:57 PM UTC 24 |
| Peak memory | 250592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159698370 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.4159698370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.4119558651 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 39773127 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 05:45:54 PM UTC 24 |
| Finished | Oct 12 05:45:57 PM UTC 24 |
| Peak memory | 240520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119558651 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.4119558651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2183128828 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 84225729 ps |
| CPU time | 2.27 seconds |
| Started | Oct 12 05:45:54 PM UTC 24 |
| Finished | Oct 12 05:45:57 PM UTC 24 |
| Peak memory | 250684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183128828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_same_csr_outstanding.2183128828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.738448923 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 2891478814 ps |
| CPU time | 7.68 seconds |
| Started | Oct 12 05:45:54 PM UTC 24 |
| Finished | Oct 12 05:46:03 PM UTC 24 |
| Peak memory | 257060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738448923 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.738448923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.2565174091 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 662615937 ps |
| CPU time | 8.65 seconds |
| Started | Oct 12 05:45:54 PM UTC 24 |
| Finished | Oct 12 05:46:04 PM UTC 24 |
| Peak memory | 254884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565174091 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_intg_err.2565174091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1498788951 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 131598826 ps |
| CPU time | 2.26 seconds |
| Started | Oct 12 05:45:54 PM UTC 24 |
| Finished | Oct 12 05:45:58 PM UTC 24 |
| Peak memory | 256928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1498788951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_c sr_mem_rw_with_rand_reset.1498788951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.3506403481 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 684241121 ps |
| CPU time | 2.61 seconds |
| Started | Oct 12 05:45:54 PM UTC 24 |
| Finished | Oct 12 05:45:58 PM UTC 24 |
| Peak memory | 252672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506403481 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.3506403481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.2324298397 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 72596296 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 05:45:54 PM UTC 24 |
| Finished | Oct 12 05:45:57 PM UTC 24 |
| Peak memory | 240460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324298397 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.2324298397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.3754311572 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 75267361 ps |
| CPU time | 2.11 seconds |
| Started | Oct 12 05:45:54 PM UTC 24 |
| Finished | Oct 12 05:45:58 PM UTC 24 |
| Peak memory | 250820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754311572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_same_csr_outstanding.3754311572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3009220308 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 166890275 ps |
| CPU time | 4.79 seconds |
| Started | Oct 12 05:45:54 PM UTC 24 |
| Finished | Oct 12 05:46:00 PM UTC 24 |
| Peak memory | 250848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009220308 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.3009220308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.4293567173 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 4861341035 ps |
| CPU time | 19.46 seconds |
| Started | Oct 12 05:45:54 PM UTC 24 |
| Finished | Oct 12 05:46:15 PM UTC 24 |
| Peak memory | 254892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293567173 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_intg_err.4293567173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.2701446132 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 345503781 ps |
| CPU time | 2.54 seconds |
| Started | Oct 12 05:45:56 PM UTC 24 |
| Finished | Oct 12 05:45:59 PM UTC 24 |
| Peak memory | 256928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2701446132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_c sr_mem_rw_with_rand_reset.2701446132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.3686182904 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 91453467 ps |
| CPU time | 1.82 seconds |
| Started | Oct 12 05:45:55 PM UTC 24 |
| Finished | Oct 12 05:45:57 PM UTC 24 |
| Peak memory | 250580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686182904 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.3686182904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.4250698443 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 525397382 ps |
| CPU time | 2.08 seconds |
| Started | Oct 12 05:45:55 PM UTC 24 |
| Finished | Oct 12 05:45:58 PM UTC 24 |
| Peak memory | 239844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250698443 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.4250698443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1120187053 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 993092236 ps |
| CPU time | 3.43 seconds |
| Started | Oct 12 05:45:56 PM UTC 24 |
| Finished | Oct 12 05:46:00 PM UTC 24 |
| Peak memory | 250624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120187053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_same_csr_outstanding.1120187053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3063238 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 142275237 ps |
| CPU time | 5.71 seconds |
| Started | Oct 12 05:45:54 PM UTC 24 |
| Finished | Oct 12 05:46:01 PM UTC 24 |
| Peak memory | 257180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_ base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.3063238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1446312156 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 141664150 ps |
| CPU time | 2.89 seconds |
| Started | Oct 12 05:45:56 PM UTC 24 |
| Finished | Oct 12 05:46:00 PM UTC 24 |
| Peak memory | 256924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1446312156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_c sr_mem_rw_with_rand_reset.1446312156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.10867879 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 45377381 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 05:45:56 PM UTC 24 |
| Finished | Oct 12 05:45:59 PM UTC 24 |
| Peak memory | 250504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10867879 -assert nopostproc +UVM_TESTNAME=otp_c trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.10867879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.4223005045 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 93927824 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 05:45:56 PM UTC 24 |
| Finished | Oct 12 05:45:59 PM UTC 24 |
| Peak memory | 240460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223005045 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.4223005045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.4063114689 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 240421467 ps |
| CPU time | 2.07 seconds |
| Started | Oct 12 05:45:56 PM UTC 24 |
| Finished | Oct 12 05:45:59 PM UTC 24 |
| Peak memory | 250692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063114689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_same_csr_outstanding.4063114689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.4159139558 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 274286277 ps |
| CPU time | 4.46 seconds |
| Started | Oct 12 05:45:56 PM UTC 24 |
| Finished | Oct 12 05:46:01 PM UTC 24 |
| Peak memory | 257004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159139558 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.4159139558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.233193975 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 3841042267 ps |
| CPU time | 21.86 seconds |
| Started | Oct 12 05:45:56 PM UTC 24 |
| Finished | Oct 12 05:46:19 PM UTC 24 |
| Peak memory | 254792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233193975 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_intg_err.233193975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.884763212 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 1651017636 ps |
| CPU time | 5.02 seconds |
| Started | Oct 12 05:45:56 PM UTC 24 |
| Finished | Oct 12 05:46:02 PM UTC 24 |
| Peak memory | 257004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=884763212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_cs r_mem_rw_with_rand_reset.884763212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3718211885 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 684108309 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 05:45:56 PM UTC 24 |
| Finished | Oct 12 05:45:59 PM UTC 24 |
| Peak memory | 250500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718211885 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.3718211885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.2206008389 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 41534004 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 05:45:56 PM UTC 24 |
| Finished | Oct 12 05:45:59 PM UTC 24 |
| Peak memory | 240520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206008389 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.2206008389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.4051058631 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 671822682 ps |
| CPU time | 2.28 seconds |
| Started | Oct 12 05:45:56 PM UTC 24 |
| Finished | Oct 12 05:46:00 PM UTC 24 |
| Peak memory | 252804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051058631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_same_csr_outstanding.4051058631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.3465052202 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 233834546 ps |
| CPU time | 3.37 seconds |
| Started | Oct 12 05:45:56 PM UTC 24 |
| Finished | Oct 12 05:46:01 PM UTC 24 |
| Peak memory | 257004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465052202 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.3465052202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2268426059 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 4258375447 ps |
| CPU time | 16.7 seconds |
| Started | Oct 12 05:45:56 PM UTC 24 |
| Finished | Oct 12 05:46:14 PM UTC 24 |
| Peak memory | 250984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268426059 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_intg_err.2268426059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.3764436117 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 261939219 ps |
| CPU time | 3.45 seconds |
| Started | Oct 12 05:45:58 PM UTC 24 |
| Finished | Oct 12 05:46:02 PM UTC 24 |
| Peak memory | 256900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3764436117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_c sr_mem_rw_with_rand_reset.3764436117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.486007824 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 90024331 ps |
| CPU time | 1.74 seconds |
| Started | Oct 12 05:45:58 PM UTC 24 |
| Finished | Oct 12 05:46:01 PM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486007824 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.486007824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.3067430156 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 83419169 ps |
| CPU time | 1.81 seconds |
| Started | Oct 12 05:45:58 PM UTC 24 |
| Finished | Oct 12 05:46:01 PM UTC 24 |
| Peak memory | 240460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067430156 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.3067430156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.4090432152 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 121367676 ps |
| CPU time | 3.02 seconds |
| Started | Oct 12 05:45:58 PM UTC 24 |
| Finished | Oct 12 05:46:02 PM UTC 24 |
| Peak memory | 250688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090432152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_same_csr_outstanding.4090432152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.2824296230 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 74250530 ps |
| CPU time | 4.33 seconds |
| Started | Oct 12 05:45:56 PM UTC 24 |
| Finished | Oct 12 05:46:02 PM UTC 24 |
| Peak memory | 256784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824296230 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.2824296230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2540190819 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 9711041908 ps |
| CPU time | 9.25 seconds |
| Started | Oct 12 05:45:58 PM UTC 24 |
| Finished | Oct 12 05:46:08 PM UTC 24 |
| Peak memory | 254816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540190819 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_intg_err.2540190819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.479319804 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 158749052 ps |
| CPU time | 2.16 seconds |
| Started | Oct 12 05:45:58 PM UTC 24 |
| Finished | Oct 12 05:46:01 PM UTC 24 |
| Peak memory | 256728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=479319804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_cs r_mem_rw_with_rand_reset.479319804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.4153071205 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 74526287 ps |
| CPU time | 1.8 seconds |
| Started | Oct 12 05:45:58 PM UTC 24 |
| Finished | Oct 12 05:46:01 PM UTC 24 |
| Peak memory | 250500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153071205 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.4153071205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.2017806450 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 154263357 ps |
| CPU time | 1.6 seconds |
| Started | Oct 12 05:45:58 PM UTC 24 |
| Finished | Oct 12 05:46:01 PM UTC 24 |
| Peak memory | 240520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017806450 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.2017806450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.3576833853 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 1055598833 ps |
| CPU time | 2.22 seconds |
| Started | Oct 12 05:45:58 PM UTC 24 |
| Finished | Oct 12 05:46:01 PM UTC 24 |
| Peak memory | 250688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576833853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_same_csr_outstanding.3576833853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.128194176 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 1583020114 ps |
| CPU time | 4.07 seconds |
| Started | Oct 12 05:45:58 PM UTC 24 |
| Finished | Oct 12 05:46:03 PM UTC 24 |
| Peak memory | 256904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128194176 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.128194176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3049618300 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 120804006 ps |
| CPU time | 2.89 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:04 PM UTC 24 |
| Peak memory | 257004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3049618300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_c sr_mem_rw_with_rand_reset.3049618300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.4034877205 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 46029977 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:02 PM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034877205 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.4034877205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.1609201925 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 108998747 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:02 PM UTC 24 |
| Peak memory | 238840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609201925 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.1609201925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3623916236 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 249833708 ps |
| CPU time | 3.47 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:04 PM UTC 24 |
| Peak memory | 250756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623916236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_same_csr_outstanding.3623916236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2607876332 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 150066706 ps |
| CPU time | 3.74 seconds |
| Started | Oct 12 05:45:58 PM UTC 24 |
| Finished | Oct 12 05:46:03 PM UTC 24 |
| Peak memory | 257004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607876332 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.2607876332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1626300688 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 19016425560 ps |
| CPU time | 19.6 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:20 PM UTC 24 |
| Peak memory | 255076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626300688 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_intg_err.1626300688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1948032539 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 122837662 ps |
| CPU time | 2.97 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:04 PM UTC 24 |
| Peak memory | 256904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1948032539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_c sr_mem_rw_with_rand_reset.1948032539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3568386471 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 44907288 ps |
| CPU time | 1.65 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:02 PM UTC 24 |
| Peak memory | 250640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568386471 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.3568386471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.1755436780 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 148565435 ps |
| CPU time | 1.65 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:02 PM UTC 24 |
| Peak memory | 240460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755436780 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.1755436780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3944350480 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 1050198844 ps |
| CPU time | 3.28 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:04 PM UTC 24 |
| Peak memory | 250788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944350480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_same_csr_outstanding.3944350480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3628575550 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 171382585 ps |
| CPU time | 2.64 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:03 PM UTC 24 |
| Peak memory | 256840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628575550 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.3628575550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2876094040 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1335752903 ps |
| CPU time | 15.97 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:17 PM UTC 24 |
| Peak memory | 250892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876094040 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_intg_err.2876094040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.25591478 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 1564221767 ps |
| CPU time | 3.88 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:53 PM UTC 24 |
| Peak memory | 250760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25591478 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_aliasing.25591478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.1686891020 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 686824374 ps |
| CPU time | 8.22 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:57 PM UTC 24 |
| Peak memory | 250564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686891020 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_bash.1686891020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.89046453 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 104751683 ps |
| CPU time | 2.68 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:51 PM UTC 24 |
| Peak memory | 250648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89046453 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_reset.89046453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.2861916293 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 281974512 ps |
| CPU time | 2.22 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:51 PM UTC 24 |
| Peak memory | 254792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2861916293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_cs r_mem_rw_with_rand_reset.2861916293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1415517290 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 88260894 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:50 PM UTC 24 |
| Peak memory | 250488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415517290 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.1415517290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.1776944963 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 66835726 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:50 PM UTC 24 |
| Peak memory | 237236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776944963 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.1776944963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.4272052627 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 72706499 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:50 PM UTC 24 |
| Peak memory | 238844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272052627 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_partial_access.4272052627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2733273337 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 40398001 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:50 PM UTC 24 |
| Peak memory | 237452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733273337 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.2733273337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2675491458 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 77262720 ps |
| CPU time | 2.28 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:51 PM UTC 24 |
| Peak memory | 250720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675491458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_same_csr_outstanding.2675491458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3601114904 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 100941148 ps |
| CPU time | 3.7 seconds |
| Started | Oct 12 05:45:46 PM UTC 24 |
| Finished | Oct 12 05:45:50 PM UTC 24 |
| Peak memory | 257180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601114904 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3601114904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.1633254831 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 85978127 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:02 PM UTC 24 |
| Peak memory | 240460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633254831 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.1633254831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/20.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.1007742356 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 128943087 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:02 PM UTC 24 |
| Peak memory | 240520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007742356 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.1007742356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/21.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.2147531394 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 41360640 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:03 PM UTC 24 |
| Peak memory | 240520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147531394 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.2147531394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/22.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.592319205 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 611375002 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:02 PM UTC 24 |
| Peak memory | 238512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592319205 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.592319205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/23.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.3900191619 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 41741165 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:02 PM UTC 24 |
| Peak memory | 240460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900191619 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.3900191619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/24.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.404138536 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 50930607 ps |
| CPU time | 1.56 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:03 PM UTC 24 |
| Peak memory | 238776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404138536 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.404138536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/25.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.2238520697 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 581144868 ps |
| CPU time | 1.65 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:03 PM UTC 24 |
| Peak memory | 240520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238520697 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.2238520697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/26.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.155868347 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 39179091 ps |
| CPU time | 1.74 seconds |
| Started | Oct 12 05:46:00 PM UTC 24 |
| Finished | Oct 12 05:46:03 PM UTC 24 |
| Peak memory | 238512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155868347 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.155868347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/27.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.2830355766 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 56597824 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 05:46:02 PM UTC 24 |
| Finished | Oct 12 05:46:05 PM UTC 24 |
| Peak memory | 240520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830355766 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.2830355766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/28.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.4166455020 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 557597542 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 05:46:02 PM UTC 24 |
| Finished | Oct 12 05:46:05 PM UTC 24 |
| Peak memory | 240460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166455020 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.4166455020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/29.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2168258139 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 386424642 ps |
| CPU time | 3.79 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:53 PM UTC 24 |
| Peak memory | 250752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168258139 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_aliasing.2168258139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.935086928 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 563952324 ps |
| CPU time | 9.18 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:59 PM UTC 24 |
| Peak memory | 240508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935086928 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_bash.935086928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.1144589945 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 103430692 ps |
| CPU time | 2.55 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:52 PM UTC 24 |
| Peak memory | 250560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144589945 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_reset.1144589945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.3901393144 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 117701822 ps |
| CPU time | 3.67 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:53 PM UTC 24 |
| Peak memory | 256880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3901393144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_cs r_mem_rw_with_rand_reset.3901393144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.810578388 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 43776089 ps |
| CPU time | 1.57 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:51 PM UTC 24 |
| Peak memory | 250684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810578388 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.810578388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.774284295 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 58965895 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:51 PM UTC 24 |
| Peak memory | 238772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774284295 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.774284295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1505730495 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 76813628 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:50 PM UTC 24 |
| Peak memory | 238844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505730495 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_partial_access.1505730495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3533081950 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 37691938 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:50 PM UTC 24 |
| Peak memory | 238920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533081950 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.3533081950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.334133745 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 91610303 ps |
| CPU time | 2.89 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:52 PM UTC 24 |
| Peak memory | 250696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334133745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_same_csr_outstanding.334133745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1332690578 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 157232017 ps |
| CPU time | 4.87 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:54 PM UTC 24 |
| Peak memory | 250848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332690578 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.1332690578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.3247670369 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 700227209 ps |
| CPU time | 9.56 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:59 PM UTC 24 |
| Peak memory | 254920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247670369 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_intg_err.3247670369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.391464921 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 49383813 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 05:46:02 PM UTC 24 |
| Finished | Oct 12 05:46:05 PM UTC 24 |
| Peak memory | 240456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391464921 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.391464921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/30.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.1482300835 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 37673815 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 05:46:02 PM UTC 24 |
| Finished | Oct 12 05:46:05 PM UTC 24 |
| Peak memory | 238840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482300835 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.1482300835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/31.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.3604024871 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 76329254 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 05:46:02 PM UTC 24 |
| Finished | Oct 12 05:46:05 PM UTC 24 |
| Peak memory | 238516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604024871 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.3604024871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/32.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.2993686528 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 526260813 ps |
| CPU time | 1.67 seconds |
| Started | Oct 12 05:46:02 PM UTC 24 |
| Finished | Oct 12 05:46:06 PM UTC 24 |
| Peak memory | 240460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993686528 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.2993686528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/33.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.3634439230 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 48394923 ps |
| CPU time | 1.6 seconds |
| Started | Oct 12 05:46:02 PM UTC 24 |
| Finished | Oct 12 05:46:06 PM UTC 24 |
| Peak memory | 238516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634439230 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.3634439230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/34.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.655147826 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 35916695 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 05:46:02 PM UTC 24 |
| Finished | Oct 12 05:46:05 PM UTC 24 |
| Peak memory | 238692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655147826 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.655147826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/35.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.606447865 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 38300232 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 05:46:02 PM UTC 24 |
| Finished | Oct 12 05:46:05 PM UTC 24 |
| Peak memory | 238836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606447865 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.606447865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/36.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.3523090396 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 144379571 ps |
| CPU time | 1.59 seconds |
| Started | Oct 12 05:46:02 PM UTC 24 |
| Finished | Oct 12 05:46:06 PM UTC 24 |
| Peak memory | 238780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523090396 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.3523090396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/37.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.2797661893 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 41869551 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 05:46:03 PM UTC 24 |
| Finished | Oct 12 05:46:05 PM UTC 24 |
| Peak memory | 238516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797661893 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.2797661893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/38.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.2319338472 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 70106548 ps |
| CPU time | 1.56 seconds |
| Started | Oct 12 05:46:03 PM UTC 24 |
| Finished | Oct 12 05:46:06 PM UTC 24 |
| Peak memory | 238516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319338472 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.2319338472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/39.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.627584831 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 3006991891 ps |
| CPU time | 9.58 seconds |
| Started | Oct 12 05:45:50 PM UTC 24 |
| Finished | Oct 12 05:46:01 PM UTC 24 |
| Peak memory | 250712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627584831 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_aliasing.627584831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.4097858443 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 163290589 ps |
| CPU time | 3.63 seconds |
| Started | Oct 12 05:45:50 PM UTC 24 |
| Finished | Oct 12 05:45:55 PM UTC 24 |
| Peak memory | 250684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097858443 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_bash.4097858443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.2253748390 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 177105855 ps |
| CPU time | 2.42 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:52 PM UTC 24 |
| Peak memory | 250648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253748390 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_reset.2253748390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.601385597 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 74803418 ps |
| CPU time | 2.13 seconds |
| Started | Oct 12 05:45:50 PM UTC 24 |
| Finished | Oct 12 05:45:53 PM UTC 24 |
| Peak memory | 256928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=601385597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr _mem_rw_with_rand_reset.601385597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.456827425 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 541229409 ps |
| CPU time | 1.83 seconds |
| Started | Oct 12 05:45:50 PM UTC 24 |
| Finished | Oct 12 05:45:53 PM UTC 24 |
| Peak memory | 250464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456827425 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.456827425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.3178211041 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 129050337 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:51 PM UTC 24 |
| Peak memory | 238776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178211041 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.3178211041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.2948955339 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 74657614 ps |
| CPU time | 1.65 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:51 PM UTC 24 |
| Peak memory | 238580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948955339 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_partial_access.2948955339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2940386363 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 40625650 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:51 PM UTC 24 |
| Peak memory | 238908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940386363 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.2940386363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.778110117 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 101471588 ps |
| CPU time | 2.21 seconds |
| Started | Oct 12 05:45:50 PM UTC 24 |
| Finished | Oct 12 05:45:53 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778110117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_same_csr_outstanding.778110117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.4032956376 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 91526929 ps |
| CPU time | 3.11 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:45:53 PM UTC 24 |
| Peak memory | 257032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032956376 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.4032956376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.2018020164 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 18826582795 ps |
| CPU time | 29.58 seconds |
| Started | Oct 12 05:45:48 PM UTC 24 |
| Finished | Oct 12 05:46:19 PM UTC 24 |
| Peak memory | 254944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018020164 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg_err.2018020164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.2809931358 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 143127615 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 05:46:03 PM UTC 24 |
| Finished | Oct 12 05:46:06 PM UTC 24 |
| Peak memory | 238840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809931358 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.2809931358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/40.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.4257106490 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 42337119 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 05:46:03 PM UTC 24 |
| Finished | Oct 12 05:46:06 PM UTC 24 |
| Peak memory | 238516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257106490 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.4257106490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/41.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.40030977 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 584832086 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 05:46:03 PM UTC 24 |
| Finished | Oct 12 05:46:06 PM UTC 24 |
| Peak memory | 238508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40030977 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.40030977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/42.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.2895439929 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 146579399 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 05:46:03 PM UTC 24 |
| Finished | Oct 12 05:46:06 PM UTC 24 |
| Peak memory | 238516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895439929 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.2895439929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/43.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.2836771706 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 99154671 ps |
| CPU time | 1.64 seconds |
| Started | Oct 12 05:46:03 PM UTC 24 |
| Finished | Oct 12 05:46:06 PM UTC 24 |
| Peak memory | 240460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836771706 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.2836771706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/44.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.2277303420 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 87745380 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 05:46:03 PM UTC 24 |
| Finished | Oct 12 05:46:06 PM UTC 24 |
| Peak memory | 240520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277303420 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.2277303420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/45.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.3236451093 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 47514364 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 05:46:03 PM UTC 24 |
| Finished | Oct 12 05:46:06 PM UTC 24 |
| Peak memory | 239992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236451093 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.3236451093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/46.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.1888868151 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 132366689 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 05:46:04 PM UTC 24 |
| Finished | Oct 12 05:46:07 PM UTC 24 |
| Peak memory | 238516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888868151 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.1888868151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/47.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.2058953180 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 134467904 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 05:46:04 PM UTC 24 |
| Finished | Oct 12 05:46:07 PM UTC 24 |
| Peak memory | 240520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058953180 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.2058953180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/48.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.2686287557 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 565682361 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 05:46:04 PM UTC 24 |
| Finished | Oct 12 05:46:07 PM UTC 24 |
| Peak memory | 238720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686287557 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.2686287557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/49.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.712180085 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 75604620 ps |
| CPU time | 2.34 seconds |
| Started | Oct 12 05:45:50 PM UTC 24 |
| Finished | Oct 12 05:45:54 PM UTC 24 |
| Peak memory | 256908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=712180085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr _mem_rw_with_rand_reset.712180085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.4150425866 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 71480992 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 05:45:50 PM UTC 24 |
| Finished | Oct 12 05:45:53 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150425866 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.4150425866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.1746992784 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 111630799 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 05:45:50 PM UTC 24 |
| Finished | Oct 12 05:45:53 PM UTC 24 |
| Peak memory | 238776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746992784 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.1746992784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.40976181 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 97393664 ps |
| CPU time | 2.24 seconds |
| Started | Oct 12 05:45:50 PM UTC 24 |
| Finished | Oct 12 05:45:54 PM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40976181 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_same_csr_outstanding.40976181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3622473675 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 327105147 ps |
| CPU time | 5.28 seconds |
| Started | Oct 12 05:45:50 PM UTC 24 |
| Finished | Oct 12 05:45:56 PM UTC 24 |
| Peak memory | 250916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622473675 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.3622473675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.4279354423 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1848602784 ps |
| CPU time | 9.51 seconds |
| Started | Oct 12 05:45:50 PM UTC 24 |
| Finished | Oct 12 05:46:01 PM UTC 24 |
| Peak memory | 250780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279354423 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_intg_err.4279354423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.3840427745 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 227602202 ps |
| CPU time | 2.67 seconds |
| Started | Oct 12 05:45:50 PM UTC 24 |
| Finished | Oct 12 05:45:54 PM UTC 24 |
| Peak memory | 256924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3840427745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_cs r_mem_rw_with_rand_reset.3840427745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.4037844343 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 83565434 ps |
| CPU time | 1.56 seconds |
| Started | Oct 12 05:45:50 PM UTC 24 |
| Finished | Oct 12 05:45:53 PM UTC 24 |
| Peak memory | 250580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037844343 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.4037844343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.395499764 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 629437622 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 05:45:50 PM UTC 24 |
| Finished | Oct 12 05:45:53 PM UTC 24 |
| Peak memory | 238832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395499764 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.395499764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1620217760 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 234926720 ps |
| CPU time | 3.28 seconds |
| Started | Oct 12 05:45:50 PM UTC 24 |
| Finished | Oct 12 05:45:55 PM UTC 24 |
| Peak memory | 250832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620217760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_same_csr_outstanding.1620217760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.483240757 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 777699762 ps |
| CPU time | 2.74 seconds |
| Started | Oct 12 05:45:50 PM UTC 24 |
| Finished | Oct 12 05:45:54 PM UTC 24 |
| Peak memory | 256964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483240757 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.483240757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1641016440 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 414128023 ps |
| CPU time | 2.96 seconds |
| Started | Oct 12 05:45:52 PM UTC 24 |
| Finished | Oct 12 05:45:56 PM UTC 24 |
| Peak memory | 256820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1641016440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_cs r_mem_rw_with_rand_reset.1641016440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.4031684447 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 110307423 ps |
| CPU time | 1.87 seconds |
| Started | Oct 12 05:45:52 PM UTC 24 |
| Finished | Oct 12 05:45:55 PM UTC 24 |
| Peak memory | 250500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031684447 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.4031684447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.1680152444 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 51001349 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 05:45:52 PM UTC 24 |
| Finished | Oct 12 05:45:54 PM UTC 24 |
| Peak memory | 238488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680152444 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.1680152444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.37514771 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 45635662 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 05:45:52 PM UTC 24 |
| Finished | Oct 12 05:45:55 PM UTC 24 |
| Peak memory | 250436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37514771 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_same_csr_outstanding.37514771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3585121095 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 75218963 ps |
| CPU time | 4.54 seconds |
| Started | Oct 12 05:45:51 PM UTC 24 |
| Finished | Oct 12 05:45:56 PM UTC 24 |
| Peak memory | 256996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585121095 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3585121095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.307423910 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 398652040 ps |
| CPU time | 3.47 seconds |
| Started | Oct 12 05:45:52 PM UTC 24 |
| Finished | Oct 12 05:45:57 PM UTC 24 |
| Peak memory | 256964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=307423910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr _mem_rw_with_rand_reset.307423910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.4179721516 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 76755405 ps |
| CPU time | 1.71 seconds |
| Started | Oct 12 05:45:52 PM UTC 24 |
| Finished | Oct 12 05:45:55 PM UTC 24 |
| Peak memory | 252604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179721516 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.4179721516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.888235285 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 43118595 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 05:45:52 PM UTC 24 |
| Finished | Oct 12 05:45:55 PM UTC 24 |
| Peak memory | 240452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888235285 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.888235285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.1539277534 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 70983305 ps |
| CPU time | 2.14 seconds |
| Started | Oct 12 05:45:52 PM UTC 24 |
| Finished | Oct 12 05:45:55 PM UTC 24 |
| Peak memory | 252732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539277534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_same_csr_outstanding.1539277534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3591138006 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 158769063 ps |
| CPU time | 4.49 seconds |
| Started | Oct 12 05:45:52 PM UTC 24 |
| Finished | Oct 12 05:45:58 PM UTC 24 |
| Peak memory | 257004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591138006 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.3591138006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3947709978 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 5148754978 ps |
| CPU time | 19.77 seconds |
| Started | Oct 12 05:45:52 PM UTC 24 |
| Finished | Oct 12 05:46:13 PM UTC 24 |
| Peak memory | 254912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947709978 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_intg_err.3947709978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1847432365 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 178544373 ps |
| CPU time | 2.09 seconds |
| Started | Oct 12 05:45:53 PM UTC 24 |
| Finished | Oct 12 05:45:56 PM UTC 24 |
| Peak memory | 254792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1847432365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_cs r_mem_rw_with_rand_reset.1847432365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3498766283 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 613228658 ps |
| CPU time | 2.07 seconds |
| Started | Oct 12 05:45:52 PM UTC 24 |
| Finished | Oct 12 05:45:56 PM UTC 24 |
| Peak memory | 252612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498766283 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.3498766283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.981684676 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 94725932 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 05:45:52 PM UTC 24 |
| Finished | Oct 12 05:45:55 PM UTC 24 |
| Peak memory | 240452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981684676 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.981684676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.1127560480 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 2201605862 ps |
| CPU time | 5.61 seconds |
| Started | Oct 12 05:45:52 PM UTC 24 |
| Finished | Oct 12 05:45:59 PM UTC 24 |
| Peak memory | 250792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127560480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_same_csr_outstanding.1127560480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.925412534 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 123420539 ps |
| CPU time | 4.89 seconds |
| Started | Oct 12 05:45:52 PM UTC 24 |
| Finished | Oct 12 05:45:58 PM UTC 24 |
| Peak memory | 256980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925412534 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.925412534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1709618120 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 926490213 ps |
| CPU time | 9.81 seconds |
| Started | Oct 12 05:45:52 PM UTC 24 |
| Finished | Oct 12 05:46:03 PM UTC 24 |
| Peak memory | 254956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709618120 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_intg_err.1709618120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_errs.3756052557 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4557923182 ps |
| CPU time | 18.96 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:37:31 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756052557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.3756052557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_lock.953076698 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 4217556276 ps |
| CPU time | 26.27 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:37:38 PM UTC 24 |
| Peak memory | 254856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953076698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.953076698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_low_freq_read.2891889418 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 7518449092 ps |
| CPU time | 15.57 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:27 PM UTC 24 |
| Peak memory | 252964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891889418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.2891889418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_macro_errs.1118111821 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 3551752164 ps |
| CPU time | 33 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:37:45 PM UTC 24 |
| Peak memory | 254912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118111821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.1118111821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_esc.3431022147 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 134304612 ps |
| CPU time | 3.47 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:37:15 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431022147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.3431022147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_partition_walk.3590134107 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1564719737 ps |
| CPU time | 20.14 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:32 PM UTC 24 |
| Peak memory | 252928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590134107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.3590134107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_regwen.3497622654 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 140853635 ps |
| CPU time | 3.76 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:37:16 PM UTC 24 |
| Peak memory | 258852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497622654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.3497622654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_sec_cm.4119079844 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 41636543159 ps |
| CPU time | 192.58 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:40:27 PM UTC 24 |
| Peak memory | 299408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119079844 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.4119079844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_smoke.4236753773 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 152111374 ps |
| CPU time | 4.99 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:17 PM UTC 24 |
| Peak memory | 252976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236753773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.4236753773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all.1407869234 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 69748861788 ps |
| CPU time | 287.9 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:42:03 PM UTC 24 |
| Peak memory | 291800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407869234 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.1407869234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_test_access.1457527544 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1981557403 ps |
| CPU time | 5.21 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:37:17 PM UTC 24 |
| Peak memory | 253004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457527544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.1457527544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_alert_test.1754679331 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 920792766 ps |
| CPU time | 1.89 seconds |
| Started | Oct 12 05:37:16 PM UTC 24 |
| Finished | Oct 12 05:37:19 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754679331 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.1754679331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_req.2532953484 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1034009380 ps |
| CPU time | 18.46 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:37:31 PM UTC 24 |
| Peak memory | 252752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532953484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.2532953484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_regwen.1206630917 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1781589091 ps |
| CPU time | 4.6 seconds |
| Started | Oct 12 05:37:15 PM UTC 24 |
| Finished | Oct 12 05:37:21 PM UTC 24 |
| Peak memory | 252616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206630917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.1206630917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_sec_cm.4179986517 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 173292907156 ps |
| CPU time | 247.33 seconds |
| Started | Oct 12 05:37:16 PM UTC 24 |
| Finished | Oct 12 05:41:28 PM UTC 24 |
| Peak memory | 291168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179986517 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.4179986517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_smoke.3855237667 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 650670493 ps |
| CPU time | 7.6 seconds |
| Started | Oct 12 05:37:11 PM UTC 24 |
| Finished | Oct 12 05:37:20 PM UTC 24 |
| Peak memory | 252792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855237667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.3855237667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all.2164445562 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 16611806426 ps |
| CPU time | 133.75 seconds |
| Started | Oct 12 05:37:16 PM UTC 24 |
| Finished | Oct 12 05:39:33 PM UTC 24 |
| Peak memory | 324772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164445562 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.2164445562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_alert_test.2198072144 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 90841975 ps |
| CPU time | 2.21 seconds |
| Started | Oct 12 05:38:00 PM UTC 24 |
| Finished | Oct 12 05:38:04 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198072144 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.2198072144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_errs.1594368683 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 505356513 ps |
| CPU time | 16.43 seconds |
| Started | Oct 12 05:37:57 PM UTC 24 |
| Finished | Oct 12 05:38:15 PM UTC 24 |
| Peak memory | 252672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594368683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.1594368683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_lock.2403955925 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 1725217711 ps |
| CPU time | 9.95 seconds |
| Started | Oct 12 05:37:57 PM UTC 24 |
| Finished | Oct 12 05:38:09 PM UTC 24 |
| Peak memory | 252816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403955925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.2403955925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_init_fail.1086816302 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 572727403 ps |
| CPU time | 4.77 seconds |
| Started | Oct 12 05:37:57 PM UTC 24 |
| Finished | Oct 12 05:38:03 PM UTC 24 |
| Peak memory | 252788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086816302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.1086816302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_key_req.144508163 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1458141005 ps |
| CPU time | 33.8 seconds |
| Started | Oct 12 05:37:57 PM UTC 24 |
| Finished | Oct 12 05:38:33 PM UTC 24 |
| Peak memory | 252764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144508163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.144508163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_esc.1361216005 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 547299264 ps |
| CPU time | 10.07 seconds |
| Started | Oct 12 05:37:57 PM UTC 24 |
| Finished | Oct 12 05:38:08 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361216005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.1361216005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_req.11449419 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 284696126 ps |
| CPU time | 8.91 seconds |
| Started | Oct 12 05:37:57 PM UTC 24 |
| Finished | Oct 12 05:38:08 PM UTC 24 |
| Peak memory | 252616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11449419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.11449419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_regwen.3853472106 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 164800963 ps |
| CPU time | 5.15 seconds |
| Started | Oct 12 05:37:57 PM UTC 24 |
| Finished | Oct 12 05:38:04 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853472106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.3853472106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_smoke.1340255705 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 894903139 ps |
| CPU time | 5.65 seconds |
| Started | Oct 12 05:37:57 PM UTC 24 |
| Finished | Oct 12 05:38:04 PM UTC 24 |
| Peak memory | 254760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340255705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.1340255705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.2997762730 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 16245358274 ps |
| CPU time | 177.49 seconds |
| Started | Oct 12 05:38:00 PM UTC 24 |
| Finished | Oct 12 05:41:01 PM UTC 24 |
| Peak memory | 275496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2997762730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.otp_ctrl_stress_all_with_rand_reset.2997762730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_test_access.1612313682 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 7196165511 ps |
| CPU time | 17.91 seconds |
| Started | Oct 12 05:38:00 PM UTC 24 |
| Finished | Oct 12 05:38:20 PM UTC 24 |
| Peak memory | 259056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612313682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.1612313682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/10.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_init_fail.2258892510 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 249582820 ps |
| CPU time | 5.34 seconds |
| Started | Oct 12 05:44:03 PM UTC 24 |
| Finished | Oct 12 05:44:09 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258892510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.2258892510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/100.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_parallel_lc_esc.214123098 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 822923633 ps |
| CPU time | 6.67 seconds |
| Started | Oct 12 05:44:08 PM UTC 24 |
| Finished | Oct 12 05:44:16 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214123098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.214123098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/100.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_init_fail.547511957 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 201163391 ps |
| CPU time | 5.4 seconds |
| Started | Oct 12 05:44:10 PM UTC 24 |
| Finished | Oct 12 05:44:17 PM UTC 24 |
| Peak memory | 252676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547511957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.547511957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/101.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_parallel_lc_esc.12518394 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 3620521820 ps |
| CPU time | 26.95 seconds |
| Started | Oct 12 05:44:10 PM UTC 24 |
| Finished | Oct 12 05:44:39 PM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12518394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.12518394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/101.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_init_fail.1963421779 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 847099128 ps |
| CPU time | 7.88 seconds |
| Started | Oct 12 05:44:11 PM UTC 24 |
| Finished | Oct 12 05:44:19 PM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963421779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.1963421779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/102.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_parallel_lc_esc.2343812041 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 4631600888 ps |
| CPU time | 30.3 seconds |
| Started | Oct 12 05:44:11 PM UTC 24 |
| Finished | Oct 12 05:44:42 PM UTC 24 |
| Peak memory | 255144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343812041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.2343812041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/102.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_init_fail.1025095465 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 2211314853 ps |
| CPU time | 5.4 seconds |
| Started | Oct 12 05:44:11 PM UTC 24 |
| Finished | Oct 12 05:44:17 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025095465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.1025095465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/103.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_parallel_lc_esc.3643669684 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 273813321 ps |
| CPU time | 8.49 seconds |
| Started | Oct 12 05:44:11 PM UTC 24 |
| Finished | Oct 12 05:44:20 PM UTC 24 |
| Peak memory | 252592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643669684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.3643669684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/103.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_init_fail.486911920 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 321060740 ps |
| CPU time | 6.01 seconds |
| Started | Oct 12 05:44:11 PM UTC 24 |
| Finished | Oct 12 05:44:18 PM UTC 24 |
| Peak memory | 254796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486911920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.486911920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/104.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_parallel_lc_esc.1236477572 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 2607311953 ps |
| CPU time | 25.47 seconds |
| Started | Oct 12 05:44:14 PM UTC 24 |
| Finished | Oct 12 05:44:41 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236477572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.1236477572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/104.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_init_fail.1540652814 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 204712617 ps |
| CPU time | 3.37 seconds |
| Started | Oct 12 05:44:14 PM UTC 24 |
| Finished | Oct 12 05:44:18 PM UTC 24 |
| Peak memory | 254888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540652814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.1540652814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/105.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_parallel_lc_esc.2778152882 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 6924607680 ps |
| CPU time | 18.88 seconds |
| Started | Oct 12 05:44:14 PM UTC 24 |
| Finished | Oct 12 05:44:34 PM UTC 24 |
| Peak memory | 253032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778152882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.2778152882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/105.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_init_fail.995847067 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 333831661 ps |
| CPU time | 6.74 seconds |
| Started | Oct 12 05:44:14 PM UTC 24 |
| Finished | Oct 12 05:44:22 PM UTC 24 |
| Peak memory | 255052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995847067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.995847067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/106.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_parallel_lc_esc.2378324781 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 287225197 ps |
| CPU time | 11.94 seconds |
| Started | Oct 12 05:44:14 PM UTC 24 |
| Finished | Oct 12 05:44:27 PM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378324781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.2378324781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/106.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_parallel_lc_esc.4110013277 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 831116131 ps |
| CPU time | 9.73 seconds |
| Started | Oct 12 05:44:16 PM UTC 24 |
| Finished | Oct 12 05:44:27 PM UTC 24 |
| Peak memory | 252908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110013277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.4110013277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/107.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_parallel_lc_esc.854202922 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 5219715443 ps |
| CPU time | 15.22 seconds |
| Started | Oct 12 05:44:17 PM UTC 24 |
| Finished | Oct 12 05:44:34 PM UTC 24 |
| Peak memory | 253028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854202922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.854202922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/108.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_init_fail.3579125595 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 389170512 ps |
| CPU time | 6.24 seconds |
| Started | Oct 12 05:44:18 PM UTC 24 |
| Finished | Oct 12 05:44:26 PM UTC 24 |
| Peak memory | 252656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579125595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.3579125595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/109.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_parallel_lc_esc.4164889 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 518565448 ps |
| CPU time | 8.56 seconds |
| Started | Oct 12 05:44:18 PM UTC 24 |
| Finished | Oct 12 05:44:28 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.4164889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/109.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_alert_test.644464161 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 168229451 ps |
| CPU time | 1.76 seconds |
| Started | Oct 12 05:38:13 PM UTC 24 |
| Finished | Oct 12 05:38:16 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644464161 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.644464161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_check_fail.16637999 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 339942885 ps |
| CPU time | 5.99 seconds |
| Started | Oct 12 05:38:05 PM UTC 24 |
| Finished | Oct 12 05:38:12 PM UTC 24 |
| Peak memory | 258852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16637999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.16637999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_errs.3446412682 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 709841937 ps |
| CPU time | 21.48 seconds |
| Started | Oct 12 05:38:05 PM UTC 24 |
| Finished | Oct 12 05:38:28 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446412682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.3446412682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_lock.3802396975 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 134639704 ps |
| CPU time | 5.04 seconds |
| Started | Oct 12 05:38:05 PM UTC 24 |
| Finished | Oct 12 05:38:11 PM UTC 24 |
| Peak memory | 252876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802396975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.3802396975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_init_fail.914084505 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 2356436290 ps |
| CPU time | 6.48 seconds |
| Started | Oct 12 05:38:05 PM UTC 24 |
| Finished | Oct 12 05:38:12 PM UTC 24 |
| Peak memory | 252760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914084505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.914084505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_macro_errs.2519990598 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 15700334453 ps |
| CPU time | 21.2 seconds |
| Started | Oct 12 05:38:07 PM UTC 24 |
| Finished | Oct 12 05:38:29 PM UTC 24 |
| Peak memory | 269284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519990598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.2519990598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_key_req.3325468786 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 209981563 ps |
| CPU time | 5.01 seconds |
| Started | Oct 12 05:38:07 PM UTC 24 |
| Finished | Oct 12 05:38:13 PM UTC 24 |
| Peak memory | 252996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325468786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.3325468786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_esc.946867053 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 295535937 ps |
| CPU time | 6.79 seconds |
| Started | Oct 12 05:38:05 PM UTC 24 |
| Finished | Oct 12 05:38:13 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946867053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.946867053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_req.2628971272 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 981409261 ps |
| CPU time | 10.52 seconds |
| Started | Oct 12 05:38:05 PM UTC 24 |
| Finished | Oct 12 05:38:17 PM UTC 24 |
| Peak memory | 258860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628971272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.2628971272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_regwen.1876513915 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 362707092 ps |
| CPU time | 6.48 seconds |
| Started | Oct 12 05:38:07 PM UTC 24 |
| Finished | Oct 12 05:38:15 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876513915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.1876513915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_smoke.2507458460 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 189169991 ps |
| CPU time | 5.22 seconds |
| Started | Oct 12 05:38:04 PM UTC 24 |
| Finished | Oct 12 05:38:10 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507458460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.2507458460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.3719379900 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5446270157 ps |
| CPU time | 71.83 seconds |
| Started | Oct 12 05:38:07 PM UTC 24 |
| Finished | Oct 12 05:39:21 PM UTC 24 |
| Peak memory | 259144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3719379900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.otp_ctrl_stress_all_with_rand_reset.3719379900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_test_access.2396425646 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 4513354771 ps |
| CPU time | 41.86 seconds |
| Started | Oct 12 05:38:07 PM UTC 24 |
| Finished | Oct 12 05:38:50 PM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396425646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.2396425646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/11.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_init_fail.2909866141 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 137984649 ps |
| CPU time | 4.43 seconds |
| Started | Oct 12 05:44:18 PM UTC 24 |
| Finished | Oct 12 05:44:24 PM UTC 24 |
| Peak memory | 252972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909866141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.2909866141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/110.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_parallel_lc_esc.1485242208 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 495411903 ps |
| CPU time | 11 seconds |
| Started | Oct 12 05:44:21 PM UTC 24 |
| Finished | Oct 12 05:44:33 PM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485242208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.1485242208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/110.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_init_fail.2407989288 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 1375389595 ps |
| CPU time | 5.92 seconds |
| Started | Oct 12 05:44:21 PM UTC 24 |
| Finished | Oct 12 05:44:28 PM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407989288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.2407989288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/111.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_parallel_lc_esc.1401683647 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 455946422 ps |
| CPU time | 12.29 seconds |
| Started | Oct 12 05:44:21 PM UTC 24 |
| Finished | Oct 12 05:44:35 PM UTC 24 |
| Peak memory | 252912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401683647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.1401683647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/111.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_parallel_lc_esc.3974458316 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 4372918709 ps |
| CPU time | 11.32 seconds |
| Started | Oct 12 05:44:22 PM UTC 24 |
| Finished | Oct 12 05:44:34 PM UTC 24 |
| Peak memory | 253168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974458316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.3974458316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/112.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_init_fail.3396348425 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 2208128950 ps |
| CPU time | 8.09 seconds |
| Started | Oct 12 05:44:22 PM UTC 24 |
| Finished | Oct 12 05:44:31 PM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396348425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.3396348425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/113.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_parallel_lc_esc.2285454295 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 5531702892 ps |
| CPU time | 11.52 seconds |
| Started | Oct 12 05:44:23 PM UTC 24 |
| Finished | Oct 12 05:44:35 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285454295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.2285454295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/113.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_init_fail.2053637211 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 255455348 ps |
| CPU time | 3.87 seconds |
| Started | Oct 12 05:44:24 PM UTC 24 |
| Finished | Oct 12 05:44:29 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053637211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.2053637211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/114.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_parallel_lc_esc.558325394 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 1731997533 ps |
| CPU time | 18.14 seconds |
| Started | Oct 12 05:44:25 PM UTC 24 |
| Finished | Oct 12 05:44:44 PM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558325394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.558325394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/114.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_init_fail.3703633061 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 1601704631 ps |
| CPU time | 4.74 seconds |
| Started | Oct 12 05:44:29 PM UTC 24 |
| Finished | Oct 12 05:44:35 PM UTC 24 |
| Peak memory | 254740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703633061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.3703633061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/115.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_parallel_lc_esc.1478734972 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 1509302648 ps |
| CPU time | 3.88 seconds |
| Started | Oct 12 05:44:29 PM UTC 24 |
| Finished | Oct 12 05:44:34 PM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478734972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.1478734972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/115.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_parallel_lc_esc.814119066 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 661148743 ps |
| CPU time | 13.87 seconds |
| Started | Oct 12 05:44:29 PM UTC 24 |
| Finished | Oct 12 05:44:44 PM UTC 24 |
| Peak memory | 252900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814119066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.814119066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/116.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_init_fail.603432656 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 187651204 ps |
| CPU time | 3.33 seconds |
| Started | Oct 12 05:44:33 PM UTC 24 |
| Finished | Oct 12 05:44:37 PM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603432656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.603432656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/117.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_parallel_lc_esc.3263960306 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 223052101 ps |
| CPU time | 6.71 seconds |
| Started | Oct 12 05:44:33 PM UTC 24 |
| Finished | Oct 12 05:44:41 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263960306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.3263960306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/117.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_init_fail.808258502 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 1778576904 ps |
| CPU time | 3.79 seconds |
| Started | Oct 12 05:44:33 PM UTC 24 |
| Finished | Oct 12 05:44:38 PM UTC 24 |
| Peak memory | 252656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808258502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.808258502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/118.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_parallel_lc_esc.717445154 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 11240383495 ps |
| CPU time | 24.98 seconds |
| Started | Oct 12 05:44:33 PM UTC 24 |
| Finished | Oct 12 05:44:59 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717445154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.717445154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/118.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_init_fail.3588250925 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 582774344 ps |
| CPU time | 3.62 seconds |
| Started | Oct 12 05:44:33 PM UTC 24 |
| Finished | Oct 12 05:44:38 PM UTC 24 |
| Peak memory | 254956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588250925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.3588250925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/119.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_parallel_lc_esc.2310467544 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 6365434693 ps |
| CPU time | 20.1 seconds |
| Started | Oct 12 05:44:33 PM UTC 24 |
| Finished | Oct 12 05:44:54 PM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310467544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.2310467544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/119.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_alert_test.3247737757 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 68251962 ps |
| CPU time | 2.29 seconds |
| Started | Oct 12 05:38:13 PM UTC 24 |
| Finished | Oct 12 05:38:17 PM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247737757 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.3247737757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_check_fail.3862895610 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 327328074 ps |
| CPU time | 10.38 seconds |
| Started | Oct 12 05:38:13 PM UTC 24 |
| Finished | Oct 12 05:38:25 PM UTC 24 |
| Peak memory | 252816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862895610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.3862895610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_errs.2694747547 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 2688922164 ps |
| CPU time | 21.05 seconds |
| Started | Oct 12 05:38:13 PM UTC 24 |
| Finished | Oct 12 05:38:35 PM UTC 24 |
| Peak memory | 254992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694747547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.2694747547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_lock.2292913695 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 6613542718 ps |
| CPU time | 50.58 seconds |
| Started | Oct 12 05:38:13 PM UTC 24 |
| Finished | Oct 12 05:39:05 PM UTC 24 |
| Peak memory | 254928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292913695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.2292913695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_macro_errs.508285246 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 2099655427 ps |
| CPU time | 44.69 seconds |
| Started | Oct 12 05:38:13 PM UTC 24 |
| Finished | Oct 12 05:38:59 PM UTC 24 |
| Peak memory | 269180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508285246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.508285246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_key_req.3695032883 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 126640865 ps |
| CPU time | 4.94 seconds |
| Started | Oct 12 05:38:13 PM UTC 24 |
| Finished | Oct 12 05:38:19 PM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695032883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.3695032883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_esc.1465946403 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 9844251489 ps |
| CPU time | 21.18 seconds |
| Started | Oct 12 05:38:13 PM UTC 24 |
| Finished | Oct 12 05:38:35 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465946403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.1465946403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_regwen.1679974102 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 568146669 ps |
| CPU time | 5.07 seconds |
| Started | Oct 12 05:38:13 PM UTC 24 |
| Finished | Oct 12 05:38:19 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679974102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.1679974102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_smoke.3797120554 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 513263923 ps |
| CPU time | 9.89 seconds |
| Started | Oct 12 05:38:13 PM UTC 24 |
| Finished | Oct 12 05:38:24 PM UTC 24 |
| Peak memory | 252792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797120554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.3797120554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all.3202586325 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 5775870650 ps |
| CPU time | 47.31 seconds |
| Started | Oct 12 05:38:13 PM UTC 24 |
| Finished | Oct 12 05:39:02 PM UTC 24 |
| Peak memory | 257196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202586325 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.3202586325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_test_access.65684695 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 939850104 ps |
| CPU time | 21.56 seconds |
| Started | Oct 12 05:38:13 PM UTC 24 |
| Finished | Oct 12 05:38:36 PM UTC 24 |
| Peak memory | 259208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65684695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.65684695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/12.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_init_fail.3337708312 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 164315927 ps |
| CPU time | 5.19 seconds |
| Started | Oct 12 05:44:33 PM UTC 24 |
| Finished | Oct 12 05:44:39 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337708312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.3337708312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/120.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_parallel_lc_esc.4054592605 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 656239990 ps |
| CPU time | 7.45 seconds |
| Started | Oct 12 05:44:33 PM UTC 24 |
| Finished | Oct 12 05:44:42 PM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054592605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.4054592605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/120.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_init_fail.3273016308 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 166421555 ps |
| CPU time | 3.03 seconds |
| Started | Oct 12 05:44:33 PM UTC 24 |
| Finished | Oct 12 05:44:37 PM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273016308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.3273016308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/121.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_parallel_lc_esc.1638015663 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 3867300608 ps |
| CPU time | 11.58 seconds |
| Started | Oct 12 05:44:33 PM UTC 24 |
| Finished | Oct 12 05:44:46 PM UTC 24 |
| Peak memory | 253104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638015663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.1638015663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/121.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_init_fail.2425650070 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 1607941547 ps |
| CPU time | 6.59 seconds |
| Started | Oct 12 05:44:33 PM UTC 24 |
| Finished | Oct 12 05:44:41 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425650070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.2425650070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/122.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_parallel_lc_esc.2168517389 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 416257489 ps |
| CPU time | 3.61 seconds |
| Started | Oct 12 05:44:36 PM UTC 24 |
| Finished | Oct 12 05:44:41 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168517389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.2168517389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/122.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_init_fail.3805617794 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 1667293471 ps |
| CPU time | 5.97 seconds |
| Started | Oct 12 05:44:36 PM UTC 24 |
| Finished | Oct 12 05:44:44 PM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805617794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.3805617794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/123.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_parallel_lc_esc.889726150 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 339615262 ps |
| CPU time | 9.04 seconds |
| Started | Oct 12 05:44:36 PM UTC 24 |
| Finished | Oct 12 05:44:47 PM UTC 24 |
| Peak memory | 253004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889726150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.889726150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/123.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_init_fail.742034170 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 95772214 ps |
| CPU time | 3.09 seconds |
| Started | Oct 12 05:44:36 PM UTC 24 |
| Finished | Oct 12 05:44:41 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742034170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.742034170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/124.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_parallel_lc_esc.1702225054 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 1352971692 ps |
| CPU time | 16.38 seconds |
| Started | Oct 12 05:44:36 PM UTC 24 |
| Finished | Oct 12 05:44:54 PM UTC 24 |
| Peak memory | 252524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702225054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.1702225054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/124.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_init_fail.2614528340 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 526497234 ps |
| CPU time | 4.98 seconds |
| Started | Oct 12 05:44:36 PM UTC 24 |
| Finished | Oct 12 05:44:43 PM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614528340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.2614528340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/125.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_parallel_lc_esc.1826023112 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 911865553 ps |
| CPU time | 6.55 seconds |
| Started | Oct 12 05:44:36 PM UTC 24 |
| Finished | Oct 12 05:44:45 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826023112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.1826023112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/125.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_init_fail.360592385 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 261692085 ps |
| CPU time | 3.73 seconds |
| Started | Oct 12 05:44:36 PM UTC 24 |
| Finished | Oct 12 05:44:42 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360592385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.360592385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/126.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_parallel_lc_esc.3623727852 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 210821011 ps |
| CPU time | 7.41 seconds |
| Started | Oct 12 05:44:36 PM UTC 24 |
| Finished | Oct 12 05:44:45 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623727852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.3623727852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/126.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_init_fail.3003165883 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 330513522 ps |
| CPU time | 5.76 seconds |
| Started | Oct 12 05:44:38 PM UTC 24 |
| Finished | Oct 12 05:44:46 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003165883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.3003165883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/127.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_parallel_lc_esc.2618412627 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 97935930 ps |
| CPU time | 4.05 seconds |
| Started | Oct 12 05:44:39 PM UTC 24 |
| Finished | Oct 12 05:44:44 PM UTC 24 |
| Peak memory | 252876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618412627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.2618412627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/127.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_init_fail.1119436605 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 326007814 ps |
| CPU time | 4.92 seconds |
| Started | Oct 12 05:44:39 PM UTC 24 |
| Finished | Oct 12 05:44:45 PM UTC 24 |
| Peak memory | 255096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119436605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.1119436605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/128.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_parallel_lc_esc.1441365387 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 585125706 ps |
| CPU time | 16.07 seconds |
| Started | Oct 12 05:44:39 PM UTC 24 |
| Finished | Oct 12 05:44:56 PM UTC 24 |
| Peak memory | 252908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441365387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.1441365387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/128.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_init_fail.686771213 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1809015739 ps |
| CPU time | 4.74 seconds |
| Started | Oct 12 05:44:39 PM UTC 24 |
| Finished | Oct 12 05:44:45 PM UTC 24 |
| Peak memory | 253024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686771213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.686771213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/129.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_parallel_lc_esc.1286869435 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1270833670 ps |
| CPU time | 8.91 seconds |
| Started | Oct 12 05:44:39 PM UTC 24 |
| Finished | Oct 12 05:44:49 PM UTC 24 |
| Peak memory | 252972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286869435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.1286869435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/129.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_alert_test.2453749734 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 78050917 ps |
| CPU time | 2.43 seconds |
| Started | Oct 12 05:38:21 PM UTC 24 |
| Finished | Oct 12 05:38:24 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453749734 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.2453749734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_check_fail.3542206659 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 1220871398 ps |
| CPU time | 6.78 seconds |
| Started | Oct 12 05:38:17 PM UTC 24 |
| Finished | Oct 12 05:38:25 PM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542206659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.3542206659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_errs.984925482 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 395757540 ps |
| CPU time | 24.16 seconds |
| Started | Oct 12 05:38:15 PM UTC 24 |
| Finished | Oct 12 05:38:41 PM UTC 24 |
| Peak memory | 254796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984925482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.984925482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_lock.1607816706 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2584777805 ps |
| CPU time | 27.98 seconds |
| Started | Oct 12 05:38:15 PM UTC 24 |
| Finished | Oct 12 05:38:45 PM UTC 24 |
| Peak memory | 252912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607816706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.1607816706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_init_fail.513701850 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2028685876 ps |
| CPU time | 5.38 seconds |
| Started | Oct 12 05:38:15 PM UTC 24 |
| Finished | Oct 12 05:38:21 PM UTC 24 |
| Peak memory | 252952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513701850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.513701850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_macro_errs.2221289225 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1526561557 ps |
| CPU time | 29.33 seconds |
| Started | Oct 12 05:38:17 PM UTC 24 |
| Finished | Oct 12 05:38:47 PM UTC 24 |
| Peak memory | 256876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221289225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.2221289225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_key_req.3608769893 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 807306056 ps |
| CPU time | 10.17 seconds |
| Started | Oct 12 05:38:17 PM UTC 24 |
| Finished | Oct 12 05:38:28 PM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608769893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.3608769893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_esc.3117196880 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 193152066 ps |
| CPU time | 9.44 seconds |
| Started | Oct 12 05:38:15 PM UTC 24 |
| Finished | Oct 12 05:38:26 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117196880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.3117196880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_req.2673160293 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 698329130 ps |
| CPU time | 11.64 seconds |
| Started | Oct 12 05:38:15 PM UTC 24 |
| Finished | Oct 12 05:38:28 PM UTC 24 |
| Peak memory | 252740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673160293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.2673160293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_regwen.1891743380 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 424716841 ps |
| CPU time | 7.93 seconds |
| Started | Oct 12 05:38:18 PM UTC 24 |
| Finished | Oct 12 05:38:27 PM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891743380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.1891743380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_smoke.1272583113 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 409365684 ps |
| CPU time | 10.15 seconds |
| Started | Oct 12 05:38:15 PM UTC 24 |
| Finished | Oct 12 05:38:26 PM UTC 24 |
| Peak memory | 252792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272583113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.1272583113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all.2791626119 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 13945270624 ps |
| CPU time | 100.62 seconds |
| Started | Oct 12 05:38:21 PM UTC 24 |
| Finished | Oct 12 05:40:04 PM UTC 24 |
| Peak memory | 259048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791626119 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.2791626119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.199548415 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3443411002 ps |
| CPU time | 82.51 seconds |
| Started | Oct 12 05:38:19 PM UTC 24 |
| Finished | Oct 12 05:39:43 PM UTC 24 |
| Peak memory | 259048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=199548415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.199548415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_test_access.1309347287 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 17167819702 ps |
| CPU time | 32.25 seconds |
| Started | Oct 12 05:38:19 PM UTC 24 |
| Finished | Oct 12 05:38:52 PM UTC 24 |
| Peak memory | 254896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309347287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.1309347287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/13.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_init_fail.4014075075 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 161544053 ps |
| CPU time | 4.12 seconds |
| Started | Oct 12 05:44:39 PM UTC 24 |
| Finished | Oct 12 05:44:44 PM UTC 24 |
| Peak memory | 253096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014075075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.4014075075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/130.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_parallel_lc_esc.121609620 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 789480634 ps |
| CPU time | 5.42 seconds |
| Started | Oct 12 05:44:39 PM UTC 24 |
| Finished | Oct 12 05:44:46 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121609620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.121609620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/130.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_init_fail.2903083357 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 342124415 ps |
| CPU time | 3.39 seconds |
| Started | Oct 12 05:44:41 PM UTC 24 |
| Finished | Oct 12 05:44:46 PM UTC 24 |
| Peak memory | 252192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903083357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.2903083357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/131.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_parallel_lc_esc.253814227 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 227220053 ps |
| CPU time | 3.89 seconds |
| Started | Oct 12 05:44:41 PM UTC 24 |
| Finished | Oct 12 05:44:47 PM UTC 24 |
| Peak memory | 252872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253814227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.253814227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/131.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_init_fail.3963305348 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 1737671879 ps |
| CPU time | 4.67 seconds |
| Started | Oct 12 05:44:41 PM UTC 24 |
| Finished | Oct 12 05:44:47 PM UTC 24 |
| Peak memory | 252080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963305348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.3963305348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/132.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_parallel_lc_esc.1804065657 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 344772034 ps |
| CPU time | 3.14 seconds |
| Started | Oct 12 05:44:42 PM UTC 24 |
| Finished | Oct 12 05:44:46 PM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804065657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.1804065657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/132.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_init_fail.4268788801 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 138060968 ps |
| CPU time | 3.8 seconds |
| Started | Oct 12 05:44:42 PM UTC 24 |
| Finished | Oct 12 05:44:47 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268788801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.4268788801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/133.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_parallel_lc_esc.2027631295 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 254293529 ps |
| CPU time | 7.33 seconds |
| Started | Oct 12 05:44:42 PM UTC 24 |
| Finished | Oct 12 05:44:50 PM UTC 24 |
| Peak memory | 252684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027631295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.2027631295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/133.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_init_fail.306489409 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 195068943 ps |
| CPU time | 4.51 seconds |
| Started | Oct 12 05:44:42 PM UTC 24 |
| Finished | Oct 12 05:44:47 PM UTC 24 |
| Peak memory | 252944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306489409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.306489409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/134.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_parallel_lc_esc.4213689026 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 611568921 ps |
| CPU time | 14.63 seconds |
| Started | Oct 12 05:44:46 PM UTC 24 |
| Finished | Oct 12 05:45:02 PM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213689026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.4213689026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/134.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_init_fail.1325132602 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 261307465 ps |
| CPU time | 5.34 seconds |
| Started | Oct 12 05:44:46 PM UTC 24 |
| Finished | Oct 12 05:44:52 PM UTC 24 |
| Peak memory | 253032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325132602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.1325132602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/135.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_parallel_lc_esc.3632352494 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 422296544 ps |
| CPU time | 7.65 seconds |
| Started | Oct 12 05:44:46 PM UTC 24 |
| Finished | Oct 12 05:44:55 PM UTC 24 |
| Peak memory | 253008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632352494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.3632352494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/135.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_init_fail.910375266 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 339875782 ps |
| CPU time | 3.93 seconds |
| Started | Oct 12 05:44:46 PM UTC 24 |
| Finished | Oct 12 05:44:51 PM UTC 24 |
| Peak memory | 254856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910375266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.910375266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/136.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_parallel_lc_esc.3070237833 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 1945770120 ps |
| CPU time | 21.67 seconds |
| Started | Oct 12 05:44:46 PM UTC 24 |
| Finished | Oct 12 05:45:09 PM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070237833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.3070237833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/136.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_init_fail.1362218873 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 546208917 ps |
| CPU time | 4.16 seconds |
| Started | Oct 12 05:44:46 PM UTC 24 |
| Finished | Oct 12 05:44:51 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362218873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.1362218873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/137.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_parallel_lc_esc.1129983432 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 299795362 ps |
| CPU time | 9.18 seconds |
| Started | Oct 12 05:44:46 PM UTC 24 |
| Finished | Oct 12 05:44:56 PM UTC 24 |
| Peak memory | 258800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129983432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.1129983432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/137.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_init_fail.2769412658 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 120132523 ps |
| CPU time | 4.4 seconds |
| Started | Oct 12 05:44:46 PM UTC 24 |
| Finished | Oct 12 05:44:52 PM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769412658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.2769412658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/138.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_parallel_lc_esc.281824075 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 277522159 ps |
| CPU time | 4.12 seconds |
| Started | Oct 12 05:44:46 PM UTC 24 |
| Finished | Oct 12 05:44:51 PM UTC 24 |
| Peak memory | 252556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281824075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.281824075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/138.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_init_fail.884930086 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 231804042 ps |
| CPU time | 3.64 seconds |
| Started | Oct 12 05:44:46 PM UTC 24 |
| Finished | Oct 12 05:44:51 PM UTC 24 |
| Peak memory | 254788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884930086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.884930086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/139.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_parallel_lc_esc.4030076493 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 381017179 ps |
| CPU time | 3.25 seconds |
| Started | Oct 12 05:44:46 PM UTC 24 |
| Finished | Oct 12 05:44:51 PM UTC 24 |
| Peak memory | 252904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030076493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.4030076493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/139.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_alert_test.4105194729 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 179482354 ps |
| CPU time | 1.72 seconds |
| Started | Oct 12 05:38:26 PM UTC 24 |
| Finished | Oct 12 05:38:29 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105194729 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.4105194729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_errs.4152932028 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1024803264 ps |
| CPU time | 13.23 seconds |
| Started | Oct 12 05:38:22 PM UTC 24 |
| Finished | Oct 12 05:38:37 PM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152932028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.4152932028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_lock.2901592699 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1677380990 ps |
| CPU time | 23.72 seconds |
| Started | Oct 12 05:38:21 PM UTC 24 |
| Finished | Oct 12 05:38:46 PM UTC 24 |
| Peak memory | 252876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901592699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.2901592699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_init_fail.4147025984 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1945523697 ps |
| CPU time | 7.88 seconds |
| Started | Oct 12 05:38:21 PM UTC 24 |
| Finished | Oct 12 05:38:30 PM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147025984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.4147025984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_macro_errs.2209248402 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 623707424 ps |
| CPU time | 10.24 seconds |
| Started | Oct 12 05:38:26 PM UTC 24 |
| Finished | Oct 12 05:38:37 PM UTC 24 |
| Peak memory | 254832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209248402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.2209248402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_key_req.4271692764 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1181013175 ps |
| CPU time | 12.74 seconds |
| Started | Oct 12 05:38:26 PM UTC 24 |
| Finished | Oct 12 05:38:40 PM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271692764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.4271692764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_esc.3313948144 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 723218714 ps |
| CPU time | 11.02 seconds |
| Started | Oct 12 05:38:21 PM UTC 24 |
| Finished | Oct 12 05:38:33 PM UTC 24 |
| Peak memory | 258788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313948144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.3313948144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_req.3906957136 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 653095076 ps |
| CPU time | 6.49 seconds |
| Started | Oct 12 05:38:21 PM UTC 24 |
| Finished | Oct 12 05:38:29 PM UTC 24 |
| Peak memory | 258860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906957136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.3906957136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_regwen.212804519 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 239869486 ps |
| CPU time | 4.54 seconds |
| Started | Oct 12 05:38:26 PM UTC 24 |
| Finished | Oct 12 05:38:31 PM UTC 24 |
| Peak memory | 259040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212804519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.212804519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_smoke.2508825910 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 2991338528 ps |
| CPU time | 11.39 seconds |
| Started | Oct 12 05:38:21 PM UTC 24 |
| Finished | Oct 12 05:38:33 PM UTC 24 |
| Peak memory | 253112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508825910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.2508825910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.2699092403 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2414783858 ps |
| CPU time | 20.61 seconds |
| Started | Oct 12 05:38:26 PM UTC 24 |
| Finished | Oct 12 05:38:48 PM UTC 24 |
| Peak memory | 259140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2699092403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.otp_ctrl_stress_all_with_rand_reset.2699092403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_test_access.56728740 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1556777113 ps |
| CPU time | 14.58 seconds |
| Started | Oct 12 05:38:26 PM UTC 24 |
| Finished | Oct 12 05:38:42 PM UTC 24 |
| Peak memory | 253136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56728740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.56728740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/14.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_init_fail.4106822506 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 218366425 ps |
| CPU time | 4.29 seconds |
| Started | Oct 12 05:44:46 PM UTC 24 |
| Finished | Oct 12 05:44:52 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106822506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.4106822506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/140.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_parallel_lc_esc.1405003606 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 133945356 ps |
| CPU time | 5.44 seconds |
| Started | Oct 12 05:44:46 PM UTC 24 |
| Finished | Oct 12 05:44:53 PM UTC 24 |
| Peak memory | 252560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405003606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.1405003606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/140.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_init_fail.2046807451 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 444945383 ps |
| CPU time | 4.1 seconds |
| Started | Oct 12 05:44:46 PM UTC 24 |
| Finished | Oct 12 05:44:52 PM UTC 24 |
| Peak memory | 254692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046807451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.2046807451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/141.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_parallel_lc_esc.941124745 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 888955217 ps |
| CPU time | 12.27 seconds |
| Started | Oct 12 05:44:46 PM UTC 24 |
| Finished | Oct 12 05:45:00 PM UTC 24 |
| Peak memory | 252872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941124745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.941124745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/141.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_init_fail.1541545018 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 2270055227 ps |
| CPU time | 6.51 seconds |
| Started | Oct 12 05:44:46 PM UTC 24 |
| Finished | Oct 12 05:44:54 PM UTC 24 |
| Peak memory | 253032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541545018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.1541545018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/142.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_parallel_lc_esc.2939187165 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 3093477556 ps |
| CPU time | 9.02 seconds |
| Started | Oct 12 05:44:48 PM UTC 24 |
| Finished | Oct 12 05:44:59 PM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939187165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.2939187165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/142.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_init_fail.3141424338 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 458377713 ps |
| CPU time | 5.02 seconds |
| Started | Oct 12 05:44:48 PM UTC 24 |
| Finished | Oct 12 05:44:55 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141424338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.3141424338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/143.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_parallel_lc_esc.1096677313 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 665861948 ps |
| CPU time | 10.27 seconds |
| Started | Oct 12 05:44:48 PM UTC 24 |
| Finished | Oct 12 05:45:00 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096677313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.1096677313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/143.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_init_fail.1952892978 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 266366669 ps |
| CPU time | 4.73 seconds |
| Started | Oct 12 05:44:48 PM UTC 24 |
| Finished | Oct 12 05:44:54 PM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952892978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.1952892978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/144.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_parallel_lc_esc.2878659287 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 765051444 ps |
| CPU time | 19.81 seconds |
| Started | Oct 12 05:44:48 PM UTC 24 |
| Finished | Oct 12 05:45:10 PM UTC 24 |
| Peak memory | 252464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878659287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.2878659287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/144.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_init_fail.340514437 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 658668860 ps |
| CPU time | 4.76 seconds |
| Started | Oct 12 05:44:48 PM UTC 24 |
| Finished | Oct 12 05:44:54 PM UTC 24 |
| Peak memory | 254736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340514437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.340514437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/145.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_parallel_lc_esc.3007323797 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 139150263 ps |
| CPU time | 5.08 seconds |
| Started | Oct 12 05:44:49 PM UTC 24 |
| Finished | Oct 12 05:44:55 PM UTC 24 |
| Peak memory | 252344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007323797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.3007323797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/145.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_init_fail.3871626955 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 241766127 ps |
| CPU time | 5.87 seconds |
| Started | Oct 12 05:44:49 PM UTC 24 |
| Finished | Oct 12 05:44:56 PM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871626955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.3871626955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/146.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_parallel_lc_esc.671472780 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 1040965775 ps |
| CPU time | 7.98 seconds |
| Started | Oct 12 05:44:49 PM UTC 24 |
| Finished | Oct 12 05:44:58 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671472780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.671472780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/146.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_init_fail.1077899098 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 2071769883 ps |
| CPU time | 4.95 seconds |
| Started | Oct 12 05:44:49 PM UTC 24 |
| Finished | Oct 12 05:44:55 PM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077899098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.1077899098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/147.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_parallel_lc_esc.1687894391 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 565174024 ps |
| CPU time | 11.5 seconds |
| Started | Oct 12 05:44:49 PM UTC 24 |
| Finished | Oct 12 05:45:01 PM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687894391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.1687894391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/147.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_init_fail.604633036 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 267010941 ps |
| CPU time | 4.88 seconds |
| Started | Oct 12 05:44:49 PM UTC 24 |
| Finished | Oct 12 05:44:55 PM UTC 24 |
| Peak memory | 252736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604633036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.604633036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/148.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_parallel_lc_esc.2815586042 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 2588443364 ps |
| CPU time | 22.94 seconds |
| Started | Oct 12 05:44:50 PM UTC 24 |
| Finished | Oct 12 05:45:15 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815586042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.2815586042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/148.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_init_fail.786768818 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 149407633 ps |
| CPU time | 4.34 seconds |
| Started | Oct 12 05:44:52 PM UTC 24 |
| Finished | Oct 12 05:44:58 PM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786768818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.786768818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/149.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_parallel_lc_esc.1631228023 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 404590447 ps |
| CPU time | 3.05 seconds |
| Started | Oct 12 05:44:52 PM UTC 24 |
| Finished | Oct 12 05:44:56 PM UTC 24 |
| Peak memory | 252908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631228023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.1631228023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/149.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_alert_test.3684696834 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 69584827 ps |
| CPU time | 2.63 seconds |
| Started | Oct 12 05:38:35 PM UTC 24 |
| Finished | Oct 12 05:38:39 PM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684696834 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.3684696834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_check_fail.3996547521 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 946009761 ps |
| CPU time | 19.22 seconds |
| Started | Oct 12 05:38:31 PM UTC 24 |
| Finished | Oct 12 05:38:51 PM UTC 24 |
| Peak memory | 258924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996547521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.3996547521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_errs.222464378 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 1858352289 ps |
| CPU time | 31.59 seconds |
| Started | Oct 12 05:38:31 PM UTC 24 |
| Finished | Oct 12 05:39:04 PM UTC 24 |
| Peak memory | 254856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222464378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.222464378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_lock.2285077558 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2084125663 ps |
| CPU time | 18.04 seconds |
| Started | Oct 12 05:38:31 PM UTC 24 |
| Finished | Oct 12 05:38:50 PM UTC 24 |
| Peak memory | 252880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285077558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.2285077558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_macro_errs.2889066107 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 604722799 ps |
| CPU time | 6.2 seconds |
| Started | Oct 12 05:38:31 PM UTC 24 |
| Finished | Oct 12 05:38:38 PM UTC 24 |
| Peak memory | 253100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889066107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.2889066107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_key_req.2966498857 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 1555251072 ps |
| CPU time | 41.25 seconds |
| Started | Oct 12 05:38:31 PM UTC 24 |
| Finished | Oct 12 05:39:14 PM UTC 24 |
| Peak memory | 254772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966498857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.2966498857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_esc.1867201966 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 657202404 ps |
| CPU time | 6.88 seconds |
| Started | Oct 12 05:38:31 PM UTC 24 |
| Finished | Oct 12 05:38:39 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867201966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.1867201966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_req.345695623 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 652893940 ps |
| CPU time | 17.42 seconds |
| Started | Oct 12 05:38:31 PM UTC 24 |
| Finished | Oct 12 05:38:49 PM UTC 24 |
| Peak memory | 258896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345695623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.345695623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_regwen.724540135 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 638317869 ps |
| CPU time | 7.29 seconds |
| Started | Oct 12 05:38:31 PM UTC 24 |
| Finished | Oct 12 05:38:40 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724540135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.724540135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_smoke.3007219195 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 2600936105 ps |
| CPU time | 6.47 seconds |
| Started | Oct 12 05:38:28 PM UTC 24 |
| Finished | Oct 12 05:38:35 PM UTC 24 |
| Peak memory | 252908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007219195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.3007219195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all.3926340463 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 11111262593 ps |
| CPU time | 120.94 seconds |
| Started | Oct 12 05:38:33 PM UTC 24 |
| Finished | Oct 12 05:40:36 PM UTC 24 |
| Peak memory | 257180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926340463 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.3926340463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_test_access.1438802238 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 13020436596 ps |
| CPU time | 27.9 seconds |
| Started | Oct 12 05:38:31 PM UTC 24 |
| Finished | Oct 12 05:39:00 PM UTC 24 |
| Peak memory | 254888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438802238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.1438802238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/15.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_init_fail.1151002105 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 141552968 ps |
| CPU time | 4.08 seconds |
| Started | Oct 12 05:44:52 PM UTC 24 |
| Finished | Oct 12 05:44:57 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151002105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.1151002105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/150.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_parallel_lc_esc.4249010974 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 91188936 ps |
| CPU time | 3.34 seconds |
| Started | Oct 12 05:44:52 PM UTC 24 |
| Finished | Oct 12 05:44:57 PM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249010974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.4249010974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/150.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_init_fail.138914660 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 130240741 ps |
| CPU time | 4.91 seconds |
| Started | Oct 12 05:44:52 PM UTC 24 |
| Finished | Oct 12 05:44:58 PM UTC 24 |
| Peak memory | 252732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138914660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.138914660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/151.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_parallel_lc_esc.296252951 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 337121166 ps |
| CPU time | 9.6 seconds |
| Started | Oct 12 05:44:52 PM UTC 24 |
| Finished | Oct 12 05:45:03 PM UTC 24 |
| Peak memory | 252612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296252951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.296252951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/151.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_init_fail.3893229981 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 115256128 ps |
| CPU time | 3.22 seconds |
| Started | Oct 12 05:44:52 PM UTC 24 |
| Finished | Oct 12 05:44:57 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893229981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.3893229981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/152.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_parallel_lc_esc.478289118 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 4832841469 ps |
| CPU time | 7.46 seconds |
| Started | Oct 12 05:44:54 PM UTC 24 |
| Finished | Oct 12 05:45:03 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478289118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.478289118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/152.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_init_fail.3691973403 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 595025389 ps |
| CPU time | 4.31 seconds |
| Started | Oct 12 05:44:54 PM UTC 24 |
| Finished | Oct 12 05:44:59 PM UTC 24 |
| Peak memory | 254700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691973403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.3691973403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/153.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_parallel_lc_esc.351269459 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 577549336 ps |
| CPU time | 4.66 seconds |
| Started | Oct 12 05:44:54 PM UTC 24 |
| Finished | Oct 12 05:45:00 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351269459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.351269459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/153.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_init_fail.982987758 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 172949230 ps |
| CPU time | 4.06 seconds |
| Started | Oct 12 05:44:54 PM UTC 24 |
| Finished | Oct 12 05:44:59 PM UTC 24 |
| Peak memory | 253004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982987758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.982987758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/154.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_parallel_lc_esc.1105836495 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 314917813 ps |
| CPU time | 6.13 seconds |
| Started | Oct 12 05:44:54 PM UTC 24 |
| Finished | Oct 12 05:45:01 PM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105836495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.1105836495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/154.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_init_fail.2508927244 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 389622781 ps |
| CPU time | 3.07 seconds |
| Started | Oct 12 05:44:59 PM UTC 24 |
| Finished | Oct 12 05:45:03 PM UTC 24 |
| Peak memory | 254756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508927244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.2508927244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/155.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_parallel_lc_esc.3453443964 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 384073998 ps |
| CPU time | 5.07 seconds |
| Started | Oct 12 05:44:59 PM UTC 24 |
| Finished | Oct 12 05:45:05 PM UTC 24 |
| Peak memory | 252972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453443964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.3453443964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/155.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_init_fail.3125763189 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 465331143 ps |
| CPU time | 4.72 seconds |
| Started | Oct 12 05:44:59 PM UTC 24 |
| Finished | Oct 12 05:45:04 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125763189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.3125763189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/156.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_parallel_lc_esc.1358184117 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 171986115 ps |
| CPU time | 4.32 seconds |
| Started | Oct 12 05:44:59 PM UTC 24 |
| Finished | Oct 12 05:45:04 PM UTC 24 |
| Peak memory | 252972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358184117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.1358184117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/156.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_init_fail.2711513510 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 424913276 ps |
| CPU time | 4.35 seconds |
| Started | Oct 12 05:44:59 PM UTC 24 |
| Finished | Oct 12 05:45:04 PM UTC 24 |
| Peak memory | 252904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711513510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.2711513510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/157.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_parallel_lc_esc.2729816012 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 773852505 ps |
| CPU time | 5.63 seconds |
| Started | Oct 12 05:44:59 PM UTC 24 |
| Finished | Oct 12 05:45:05 PM UTC 24 |
| Peak memory | 252588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729816012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.2729816012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/157.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_init_fail.411660226 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 422182444 ps |
| CPU time | 3.08 seconds |
| Started | Oct 12 05:44:59 PM UTC 24 |
| Finished | Oct 12 05:45:03 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411660226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.411660226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/158.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_parallel_lc_esc.406255028 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 1008462616 ps |
| CPU time | 15.61 seconds |
| Started | Oct 12 05:44:59 PM UTC 24 |
| Finished | Oct 12 05:45:16 PM UTC 24 |
| Peak memory | 252936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406255028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.406255028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/158.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_parallel_lc_esc.2973464249 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 827354447 ps |
| CPU time | 5.25 seconds |
| Started | Oct 12 05:44:59 PM UTC 24 |
| Finished | Oct 12 05:45:05 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973464249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.2973464249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/159.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_alert_test.388667430 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 244245342 ps |
| CPU time | 5.5 seconds |
| Started | Oct 12 05:38:40 PM UTC 24 |
| Finished | Oct 12 05:38:46 PM UTC 24 |
| Peak memory | 252552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388667430 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.388667430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_check_fail.514095158 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 4240706636 ps |
| CPU time | 11.13 seconds |
| Started | Oct 12 05:38:37 PM UTC 24 |
| Finished | Oct 12 05:38:50 PM UTC 24 |
| Peak memory | 252864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514095158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.514095158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_errs.3111333954 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 4198161835 ps |
| CPU time | 18.18 seconds |
| Started | Oct 12 05:38:37 PM UTC 24 |
| Finished | Oct 12 05:38:57 PM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111333954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.3111333954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_lock.2315484418 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 2999266530 ps |
| CPU time | 30.34 seconds |
| Started | Oct 12 05:38:37 PM UTC 24 |
| Finished | Oct 12 05:39:09 PM UTC 24 |
| Peak memory | 252876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315484418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.2315484418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_macro_errs.3382851664 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 5237326701 ps |
| CPU time | 10.91 seconds |
| Started | Oct 12 05:38:37 PM UTC 24 |
| Finished | Oct 12 05:38:49 PM UTC 24 |
| Peak memory | 259000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382851664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.3382851664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_key_req.2945590698 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 11748778870 ps |
| CPU time | 56.2 seconds |
| Started | Oct 12 05:38:38 PM UTC 24 |
| Finished | Oct 12 05:39:35 PM UTC 24 |
| Peak memory | 254892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945590698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.2945590698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_esc.990884154 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 1019107963 ps |
| CPU time | 7.99 seconds |
| Started | Oct 12 05:38:35 PM UTC 24 |
| Finished | Oct 12 05:38:44 PM UTC 24 |
| Peak memory | 252964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990884154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.990884154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_smoke.3198532 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 177997270 ps |
| CPU time | 4.3 seconds |
| Started | Oct 12 05:38:35 PM UTC 24 |
| Finished | Oct 12 05:38:40 PM UTC 24 |
| Peak memory | 252796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.3198532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_test_access.3160523278 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 13005820000 ps |
| CPU time | 40.2 seconds |
| Started | Oct 12 05:38:38 PM UTC 24 |
| Finished | Oct 12 05:39:19 PM UTC 24 |
| Peak memory | 255212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160523278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.3160523278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/16.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_init_fail.741571158 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 353767648 ps |
| CPU time | 5.51 seconds |
| Started | Oct 12 05:44:59 PM UTC 24 |
| Finished | Oct 12 05:45:06 PM UTC 24 |
| Peak memory | 255052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741571158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.741571158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/160.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_parallel_lc_esc.3788016862 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 312868575 ps |
| CPU time | 6.53 seconds |
| Started | Oct 12 05:44:59 PM UTC 24 |
| Finished | Oct 12 05:45:07 PM UTC 24 |
| Peak memory | 258868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788016862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.3788016862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/160.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_init_fail.995463224 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 123359177 ps |
| CPU time | 3.19 seconds |
| Started | Oct 12 05:44:59 PM UTC 24 |
| Finished | Oct 12 05:45:03 PM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995463224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.995463224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/161.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_parallel_lc_esc.2652824824 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 592195667 ps |
| CPU time | 15.86 seconds |
| Started | Oct 12 05:45:01 PM UTC 24 |
| Finished | Oct 12 05:45:18 PM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652824824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.2652824824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/161.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_init_fail.490474455 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 228478788 ps |
| CPU time | 4.15 seconds |
| Started | Oct 12 05:45:01 PM UTC 24 |
| Finished | Oct 12 05:45:07 PM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490474455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.490474455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/162.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_parallel_lc_esc.2026722467 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 783863790 ps |
| CPU time | 10.48 seconds |
| Started | Oct 12 05:45:01 PM UTC 24 |
| Finished | Oct 12 05:45:13 PM UTC 24 |
| Peak memory | 252656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026722467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.2026722467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/162.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_init_fail.4232174937 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 139592928 ps |
| CPU time | 3.4 seconds |
| Started | Oct 12 05:45:02 PM UTC 24 |
| Finished | Oct 12 05:45:06 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232174937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.4232174937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/163.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_parallel_lc_esc.1050420773 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 228694470 ps |
| CPU time | 6.1 seconds |
| Started | Oct 12 05:45:02 PM UTC 24 |
| Finished | Oct 12 05:45:09 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050420773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.1050420773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/163.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_init_fail.199256274 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 127321062 ps |
| CPU time | 3.97 seconds |
| Started | Oct 12 05:45:02 PM UTC 24 |
| Finished | Oct 12 05:45:07 PM UTC 24 |
| Peak memory | 252992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199256274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.199256274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/164.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_parallel_lc_esc.2441647907 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 2821477727 ps |
| CPU time | 18.33 seconds |
| Started | Oct 12 05:45:02 PM UTC 24 |
| Finished | Oct 12 05:45:21 PM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441647907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.2441647907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/164.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_init_fail.2063008173 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 262981829 ps |
| CPU time | 3.13 seconds |
| Started | Oct 12 05:45:02 PM UTC 24 |
| Finished | Oct 12 05:45:06 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063008173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.2063008173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/165.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_parallel_lc_esc.574636824 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 310477986 ps |
| CPU time | 7.33 seconds |
| Started | Oct 12 05:45:02 PM UTC 24 |
| Finished | Oct 12 05:45:10 PM UTC 24 |
| Peak memory | 252872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574636824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.574636824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/165.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_init_fail.2755788551 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 137602525 ps |
| CPU time | 4.09 seconds |
| Started | Oct 12 05:45:02 PM UTC 24 |
| Finished | Oct 12 05:45:07 PM UTC 24 |
| Peak memory | 253032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755788551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.2755788551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/166.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_parallel_lc_esc.2556427591 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 356803412 ps |
| CPU time | 9.18 seconds |
| Started | Oct 12 05:45:02 PM UTC 24 |
| Finished | Oct 12 05:45:12 PM UTC 24 |
| Peak memory | 252536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556427591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.2556427591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/166.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_init_fail.2908756163 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 221935587 ps |
| CPU time | 3.6 seconds |
| Started | Oct 12 05:45:02 PM UTC 24 |
| Finished | Oct 12 05:45:07 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908756163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.2908756163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/167.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_parallel_lc_esc.3168132919 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 2018238419 ps |
| CPU time | 5.75 seconds |
| Started | Oct 12 05:45:02 PM UTC 24 |
| Finished | Oct 12 05:45:09 PM UTC 24 |
| Peak memory | 252532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168132919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.3168132919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/167.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_init_fail.1188576989 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 220361984 ps |
| CPU time | 4.16 seconds |
| Started | Oct 12 05:45:02 PM UTC 24 |
| Finished | Oct 12 05:45:07 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188576989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.1188576989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/168.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_parallel_lc_esc.290329808 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 787070609 ps |
| CPU time | 9.81 seconds |
| Started | Oct 12 05:45:02 PM UTC 24 |
| Finished | Oct 12 05:45:13 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290329808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.290329808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/168.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_init_fail.922855471 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 184644301 ps |
| CPU time | 3.4 seconds |
| Started | Oct 12 05:45:02 PM UTC 24 |
| Finished | Oct 12 05:45:07 PM UTC 24 |
| Peak memory | 253068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922855471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.922855471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/169.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_parallel_lc_esc.2948101139 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 10129519424 ps |
| CPU time | 16.59 seconds |
| Started | Oct 12 05:45:02 PM UTC 24 |
| Finished | Oct 12 05:45:20 PM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948101139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.2948101139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/169.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_alert_test.2258072636 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 150418157 ps |
| CPU time | 2.16 seconds |
| Started | Oct 12 05:38:49 PM UTC 24 |
| Finished | Oct 12 05:38:52 PM UTC 24 |
| Peak memory | 252452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258072636 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.2258072636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_check_fail.1879378717 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 3779907739 ps |
| CPU time | 41.54 seconds |
| Started | Oct 12 05:38:43 PM UTC 24 |
| Finished | Oct 12 05:39:26 PM UTC 24 |
| Peak memory | 256940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879378717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.1879378717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_errs.1783212196 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 4608720402 ps |
| CPU time | 31.69 seconds |
| Started | Oct 12 05:38:43 PM UTC 24 |
| Finished | Oct 12 05:39:16 PM UTC 24 |
| Peak memory | 252940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783212196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.1783212196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_lock.4218009489 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 435440235 ps |
| CPU time | 6.63 seconds |
| Started | Oct 12 05:38:43 PM UTC 24 |
| Finished | Oct 12 05:38:50 PM UTC 24 |
| Peak memory | 252876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218009489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.4218009489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_init_fail.1436486839 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 599201050 ps |
| CPU time | 6.31 seconds |
| Started | Oct 12 05:38:40 PM UTC 24 |
| Finished | Oct 12 05:38:47 PM UTC 24 |
| Peak memory | 254968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436486839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.1436486839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_macro_errs.1753586429 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 4646919235 ps |
| CPU time | 30.25 seconds |
| Started | Oct 12 05:38:43 PM UTC 24 |
| Finished | Oct 12 05:39:15 PM UTC 24 |
| Peak memory | 259020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753586429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.1753586429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_key_req.782332398 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 10327021679 ps |
| CPU time | 32.69 seconds |
| Started | Oct 12 05:38:46 PM UTC 24 |
| Finished | Oct 12 05:39:20 PM UTC 24 |
| Peak memory | 253104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782332398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.782332398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_esc.3846241245 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 462699852 ps |
| CPU time | 7.86 seconds |
| Started | Oct 12 05:38:43 PM UTC 24 |
| Finished | Oct 12 05:38:52 PM UTC 24 |
| Peak memory | 253032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846241245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.3846241245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_req.3291595997 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1141523896 ps |
| CPU time | 13.63 seconds |
| Started | Oct 12 05:38:43 PM UTC 24 |
| Finished | Oct 12 05:38:57 PM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291595997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.3291595997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_regwen.969413050 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 419758960 ps |
| CPU time | 6.76 seconds |
| Started | Oct 12 05:38:46 PM UTC 24 |
| Finished | Oct 12 05:38:54 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969413050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.969413050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_smoke.3144615253 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2406506454 ps |
| CPU time | 7.29 seconds |
| Started | Oct 12 05:38:40 PM UTC 24 |
| Finished | Oct 12 05:38:48 PM UTC 24 |
| Peak memory | 252852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144615253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.3144615253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all.693079143 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 982650574 ps |
| CPU time | 20.93 seconds |
| Started | Oct 12 05:38:49 PM UTC 24 |
| Finished | Oct 12 05:39:11 PM UTC 24 |
| Peak memory | 254780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693079143 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.693079143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.3353887317 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3902331907 ps |
| CPU time | 111.59 seconds |
| Started | Oct 12 05:38:49 PM UTC 24 |
| Finished | Oct 12 05:40:43 PM UTC 24 |
| Peak memory | 263496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3353887317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.otp_ctrl_stress_all_with_rand_reset.3353887317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_init_fail.1572614077 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 126385533 ps |
| CPU time | 3.48 seconds |
| Started | Oct 12 05:45:05 PM UTC 24 |
| Finished | Oct 12 05:45:09 PM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572614077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.1572614077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/170.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_parallel_lc_esc.1462629878 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 818948637 ps |
| CPU time | 10.86 seconds |
| Started | Oct 12 05:45:05 PM UTC 24 |
| Finished | Oct 12 05:45:17 PM UTC 24 |
| Peak memory | 252620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462629878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.1462629878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/170.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_init_fail.2185582573 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 593920359 ps |
| CPU time | 4.2 seconds |
| Started | Oct 12 05:45:05 PM UTC 24 |
| Finished | Oct 12 05:45:10 PM UTC 24 |
| Peak memory | 255016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185582573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.2185582573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/171.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_parallel_lc_esc.1563463975 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 1662409356 ps |
| CPU time | 3.45 seconds |
| Started | Oct 12 05:45:05 PM UTC 24 |
| Finished | Oct 12 05:45:09 PM UTC 24 |
| Peak memory | 253008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563463975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.1563463975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/171.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_init_fail.2013882729 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 157566194 ps |
| CPU time | 4.05 seconds |
| Started | Oct 12 05:45:05 PM UTC 24 |
| Finished | Oct 12 05:45:10 PM UTC 24 |
| Peak memory | 254700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013882729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.2013882729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/172.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_parallel_lc_esc.3365110128 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 453772533 ps |
| CPU time | 10.71 seconds |
| Started | Oct 12 05:45:05 PM UTC 24 |
| Finished | Oct 12 05:45:17 PM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365110128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.3365110128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/172.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_init_fail.3158833471 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 140556743 ps |
| CPU time | 3.89 seconds |
| Started | Oct 12 05:45:05 PM UTC 24 |
| Finished | Oct 12 05:45:10 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158833471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.3158833471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/173.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_parallel_lc_esc.532029752 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 1291091711 ps |
| CPU time | 13.72 seconds |
| Started | Oct 12 05:45:05 PM UTC 24 |
| Finished | Oct 12 05:45:20 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532029752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.532029752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/173.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_init_fail.3452773941 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 195625369 ps |
| CPU time | 4.06 seconds |
| Started | Oct 12 05:45:05 PM UTC 24 |
| Finished | Oct 12 05:45:10 PM UTC 24 |
| Peak memory | 254748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452773941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.3452773941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/174.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_parallel_lc_esc.4198998615 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 93742717 ps |
| CPU time | 5.55 seconds |
| Started | Oct 12 05:45:05 PM UTC 24 |
| Finished | Oct 12 05:45:12 PM UTC 24 |
| Peak memory | 252624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198998615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.4198998615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/174.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_init_fail.1821691441 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 170900625 ps |
| CPU time | 4.07 seconds |
| Started | Oct 12 05:45:05 PM UTC 24 |
| Finished | Oct 12 05:45:10 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821691441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.1821691441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/175.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_parallel_lc_esc.4190860952 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 1037726005 ps |
| CPU time | 7.41 seconds |
| Started | Oct 12 05:45:05 PM UTC 24 |
| Finished | Oct 12 05:45:14 PM UTC 24 |
| Peak memory | 252908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190860952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.4190860952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/175.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_init_fail.1381859781 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 365785008 ps |
| CPU time | 3.96 seconds |
| Started | Oct 12 05:45:07 PM UTC 24 |
| Finished | Oct 12 05:45:12 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381859781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.1381859781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/176.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_parallel_lc_esc.2503273782 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 944557192 ps |
| CPU time | 10.68 seconds |
| Started | Oct 12 05:45:07 PM UTC 24 |
| Finished | Oct 12 05:45:19 PM UTC 24 |
| Peak memory | 252492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503273782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.2503273782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/176.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_init_fail.1573734104 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 534374285 ps |
| CPU time | 4.69 seconds |
| Started | Oct 12 05:45:07 PM UTC 24 |
| Finished | Oct 12 05:45:13 PM UTC 24 |
| Peak memory | 254776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573734104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.1573734104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/177.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_parallel_lc_esc.2871989420 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 535503817 ps |
| CPU time | 6.02 seconds |
| Started | Oct 12 05:45:07 PM UTC 24 |
| Finished | Oct 12 05:45:14 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871989420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.2871989420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/177.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_init_fail.36816208 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 372285799 ps |
| CPU time | 5.38 seconds |
| Started | Oct 12 05:45:07 PM UTC 24 |
| Finished | Oct 12 05:45:14 PM UTC 24 |
| Peak memory | 252948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36816208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.36816208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/178.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_parallel_lc_esc.288581546 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 161829879 ps |
| CPU time | 3.62 seconds |
| Started | Oct 12 05:45:07 PM UTC 24 |
| Finished | Oct 12 05:45:12 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288581546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.288581546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/178.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_init_fail.2479754005 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 196756481 ps |
| CPU time | 2.88 seconds |
| Started | Oct 12 05:45:07 PM UTC 24 |
| Finished | Oct 12 05:45:11 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479754005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.2479754005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/179.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_parallel_lc_esc.1556101498 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 287802367 ps |
| CPU time | 6.54 seconds |
| Started | Oct 12 05:45:07 PM UTC 24 |
| Finished | Oct 12 05:45:15 PM UTC 24 |
| Peak memory | 252940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556101498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.1556101498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/179.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_alert_test.4257011807 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 52441877 ps |
| CPU time | 2.4 seconds |
| Started | Oct 12 05:38:54 PM UTC 24 |
| Finished | Oct 12 05:38:58 PM UTC 24 |
| Peak memory | 252808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257011807 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.4257011807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_check_fail.4153707593 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 526258583 ps |
| CPU time | 10.06 seconds |
| Started | Oct 12 05:38:51 PM UTC 24 |
| Finished | Oct 12 05:39:02 PM UTC 24 |
| Peak memory | 254824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153707593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.4153707593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_errs.4065736457 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 1398765986 ps |
| CPU time | 20.95 seconds |
| Started | Oct 12 05:38:51 PM UTC 24 |
| Finished | Oct 12 05:39:13 PM UTC 24 |
| Peak memory | 252876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065736457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.4065736457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_lock.869127800 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 10298301963 ps |
| CPU time | 103.77 seconds |
| Started | Oct 12 05:38:51 PM UTC 24 |
| Finished | Oct 12 05:40:37 PM UTC 24 |
| Peak memory | 252876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869127800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.869127800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_init_fail.2635200580 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 2047509208 ps |
| CPU time | 7.99 seconds |
| Started | Oct 12 05:38:49 PM UTC 24 |
| Finished | Oct 12 05:38:58 PM UTC 24 |
| Peak memory | 252920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635200580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.2635200580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_macro_errs.1898978923 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 13195565445 ps |
| CPU time | 35.53 seconds |
| Started | Oct 12 05:38:51 PM UTC 24 |
| Finished | Oct 12 05:39:28 PM UTC 24 |
| Peak memory | 257260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898978923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.1898978923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_key_req.788079049 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 5706896570 ps |
| CPU time | 15.69 seconds |
| Started | Oct 12 05:38:51 PM UTC 24 |
| Finished | Oct 12 05:39:08 PM UTC 24 |
| Peak memory | 254884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788079049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.788079049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_esc.2412750307 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 544371030 ps |
| CPU time | 10.05 seconds |
| Started | Oct 12 05:38:49 PM UTC 24 |
| Finished | Oct 12 05:39:00 PM UTC 24 |
| Peak memory | 252964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412750307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.2412750307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_req.1262687119 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 3218202066 ps |
| CPU time | 24.65 seconds |
| Started | Oct 12 05:38:49 PM UTC 24 |
| Finished | Oct 12 05:39:15 PM UTC 24 |
| Peak memory | 252808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262687119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.1262687119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_smoke.2499076872 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 475487973 ps |
| CPU time | 4.93 seconds |
| Started | Oct 12 05:38:49 PM UTC 24 |
| Finished | Oct 12 05:38:55 PM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499076872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.2499076872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_test_access.3395191379 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1209481258 ps |
| CPU time | 12.98 seconds |
| Started | Oct 12 05:38:54 PM UTC 24 |
| Finished | Oct 12 05:39:08 PM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395191379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.3395191379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/18.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_init_fail.3503037516 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 474019069 ps |
| CPU time | 4.44 seconds |
| Started | Oct 12 05:45:07 PM UTC 24 |
| Finished | Oct 12 05:45:13 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503037516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.3503037516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/180.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_parallel_lc_esc.665250132 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 9211173541 ps |
| CPU time | 17.86 seconds |
| Started | Oct 12 05:45:07 PM UTC 24 |
| Finished | Oct 12 05:45:27 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665250132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.665250132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_init_fail.3809556378 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 121775349 ps |
| CPU time | 3.74 seconds |
| Started | Oct 12 05:45:09 PM UTC 24 |
| Finished | Oct 12 05:45:14 PM UTC 24 |
| Peak memory | 252964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809556378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.3809556378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/181.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_parallel_lc_esc.2027556664 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 1846530781 ps |
| CPU time | 6.76 seconds |
| Started | Oct 12 05:45:09 PM UTC 24 |
| Finished | Oct 12 05:45:17 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027556664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.2027556664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/181.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_init_fail.2615780104 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 2970653675 ps |
| CPU time | 5.32 seconds |
| Started | Oct 12 05:45:09 PM UTC 24 |
| Finished | Oct 12 05:45:15 PM UTC 24 |
| Peak memory | 255080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615780104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.2615780104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/182.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_parallel_lc_esc.1330789161 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 598759534 ps |
| CPU time | 8.74 seconds |
| Started | Oct 12 05:45:09 PM UTC 24 |
| Finished | Oct 12 05:45:19 PM UTC 24 |
| Peak memory | 253036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330789161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.1330789161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/182.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_init_fail.2469782511 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 109901283 ps |
| CPU time | 3.64 seconds |
| Started | Oct 12 05:45:09 PM UTC 24 |
| Finished | Oct 12 05:45:14 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469782511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.2469782511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/183.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_parallel_lc_esc.2179416641 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 640532150 ps |
| CPU time | 3.97 seconds |
| Started | Oct 12 05:45:14 PM UTC 24 |
| Finished | Oct 12 05:45:19 PM UTC 24 |
| Peak memory | 253040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179416641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.2179416641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/183.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_init_fail.3482582378 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 257414319 ps |
| CPU time | 3.04 seconds |
| Started | Oct 12 05:45:14 PM UTC 24 |
| Finished | Oct 12 05:45:18 PM UTC 24 |
| Peak memory | 254692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482582378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.3482582378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/184.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_parallel_lc_esc.4079111437 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 882141932 ps |
| CPU time | 6.87 seconds |
| Started | Oct 12 05:45:14 PM UTC 24 |
| Finished | Oct 12 05:45:22 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079111437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.4079111437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/184.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_init_fail.1056429156 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 95586754 ps |
| CPU time | 3.19 seconds |
| Started | Oct 12 05:45:14 PM UTC 24 |
| Finished | Oct 12 05:45:18 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056429156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.1056429156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/185.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.568213209 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 1031909509 ps |
| CPU time | 2.52 seconds |
| Started | Oct 12 05:45:14 PM UTC 24 |
| Finished | Oct 12 05:45:17 PM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568213209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.568213209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/185.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_init_fail.2304498419 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 122175005 ps |
| CPU time | 3.5 seconds |
| Started | Oct 12 05:45:14 PM UTC 24 |
| Finished | Oct 12 05:45:18 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304498419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.2304498419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/186.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.304244919 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 140532878 ps |
| CPU time | 2.4 seconds |
| Started | Oct 12 05:45:14 PM UTC 24 |
| Finished | Oct 12 05:45:17 PM UTC 24 |
| Peak memory | 252612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304244919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.304244919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/186.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_init_fail.1008054165 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 410120806 ps |
| CPU time | 3.04 seconds |
| Started | Oct 12 05:45:14 PM UTC 24 |
| Finished | Oct 12 05:45:18 PM UTC 24 |
| Peak memory | 252612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008054165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.1008054165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/187.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.859821621 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 919200640 ps |
| CPU time | 5.73 seconds |
| Started | Oct 12 05:45:14 PM UTC 24 |
| Finished | Oct 12 05:45:21 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859821621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.859821621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/187.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_init_fail.1082899336 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 411079294 ps |
| CPU time | 3.16 seconds |
| Started | Oct 12 05:45:14 PM UTC 24 |
| Finished | Oct 12 05:45:18 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082899336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.1082899336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/188.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.3754297713 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 2691669594 ps |
| CPU time | 5.33 seconds |
| Started | Oct 12 05:45:14 PM UTC 24 |
| Finished | Oct 12 05:45:20 PM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754297713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.3754297713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/188.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_init_fail.77112337 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 136491010 ps |
| CPU time | 3.37 seconds |
| Started | Oct 12 05:45:14 PM UTC 24 |
| Finished | Oct 12 05:45:19 PM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77112337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.77112337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/189.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_alert_test.12466091 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 571843822 ps |
| CPU time | 2.7 seconds |
| Started | Oct 12 05:39:03 PM UTC 24 |
| Finished | Oct 12 05:39:07 PM UTC 24 |
| Peak memory | 252460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12466091 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.12466091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_check_fail.3564594989 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 347080908 ps |
| CPU time | 4 seconds |
| Started | Oct 12 05:39:03 PM UTC 24 |
| Finished | Oct 12 05:39:08 PM UTC 24 |
| Peak memory | 252620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564594989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.3564594989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_errs.2728595758 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 3481875556 ps |
| CPU time | 34.64 seconds |
| Started | Oct 12 05:39:03 PM UTC 24 |
| Finished | Oct 12 05:39:39 PM UTC 24 |
| Peak memory | 258924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728595758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.2728595758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_lock.4176750148 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 540602047 ps |
| CPU time | 17.39 seconds |
| Started | Oct 12 05:39:03 PM UTC 24 |
| Finished | Oct 12 05:39:21 PM UTC 24 |
| Peak memory | 255184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176750148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.4176750148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_init_fail.565517120 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 572610475 ps |
| CPU time | 5.22 seconds |
| Started | Oct 12 05:38:56 PM UTC 24 |
| Finished | Oct 12 05:39:02 PM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565517120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.565517120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_macro_errs.380931957 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 137528797 ps |
| CPU time | 4.72 seconds |
| Started | Oct 12 05:39:03 PM UTC 24 |
| Finished | Oct 12 05:39:09 PM UTC 24 |
| Peak memory | 252620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380931957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.380931957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_key_req.2386877137 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 273033487 ps |
| CPU time | 6.79 seconds |
| Started | Oct 12 05:39:03 PM UTC 24 |
| Finished | Oct 12 05:39:11 PM UTC 24 |
| Peak memory | 258928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386877137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.2386877137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_esc.2661743628 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1067928196 ps |
| CPU time | 18.28 seconds |
| Started | Oct 12 05:38:57 PM UTC 24 |
| Finished | Oct 12 05:39:17 PM UTC 24 |
| Peak memory | 253092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661743628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.2661743628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_req.165307284 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 133969896 ps |
| CPU time | 4.36 seconds |
| Started | Oct 12 05:38:56 PM UTC 24 |
| Finished | Oct 12 05:39:01 PM UTC 24 |
| Peak memory | 252880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165307284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.165307284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_regwen.2190152623 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 376433746 ps |
| CPU time | 4.61 seconds |
| Started | Oct 12 05:39:03 PM UTC 24 |
| Finished | Oct 12 05:39:09 PM UTC 24 |
| Peak memory | 258852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190152623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.2190152623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_smoke.3135054641 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1342600719 ps |
| CPU time | 8.4 seconds |
| Started | Oct 12 05:38:54 PM UTC 24 |
| Finished | Oct 12 05:39:04 PM UTC 24 |
| Peak memory | 253112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135054641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.3135054641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all.4180075223 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 29380651651 ps |
| CPU time | 235.23 seconds |
| Started | Oct 12 05:39:03 PM UTC 24 |
| Finished | Oct 12 05:43:02 PM UTC 24 |
| Peak memory | 259180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180075223 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.4180075223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.1664927962 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3205893637 ps |
| CPU time | 43.76 seconds |
| Started | Oct 12 05:39:03 PM UTC 24 |
| Finished | Oct 12 05:39:48 PM UTC 24 |
| Peak memory | 259096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1664927962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.otp_ctrl_stress_all_with_rand_reset.1664927962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_test_access.494042427 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 1052390331 ps |
| CPU time | 10.15 seconds |
| Started | Oct 12 05:39:03 PM UTC 24 |
| Finished | Oct 12 05:39:14 PM UTC 24 |
| Peak memory | 252876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494042427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.494042427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/19.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.3939105029 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 318152582 ps |
| CPU time | 4.71 seconds |
| Started | Oct 12 05:45:22 PM UTC 24 |
| Finished | Oct 12 05:45:28 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939105029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.3939105029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/190.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.1114793066 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 8871156168 ps |
| CPU time | 15.37 seconds |
| Started | Oct 12 05:45:22 PM UTC 24 |
| Finished | Oct 12 05:45:39 PM UTC 24 |
| Peak memory | 253040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114793066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.1114793066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/190.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_init_fail.2907267131 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 103897918 ps |
| CPU time | 3.21 seconds |
| Started | Oct 12 05:45:22 PM UTC 24 |
| Finished | Oct 12 05:45:27 PM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907267131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.2907267131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/191.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.787683094 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 7778941640 ps |
| CPU time | 10.9 seconds |
| Started | Oct 12 05:45:22 PM UTC 24 |
| Finished | Oct 12 05:45:35 PM UTC 24 |
| Peak memory | 253096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787683094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.787683094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/191.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_init_fail.1859871578 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 594937248 ps |
| CPU time | 3.95 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:28 PM UTC 24 |
| Peak memory | 254756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859871578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.1859871578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/192.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.2240375038 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 416471726 ps |
| CPU time | 3.05 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:27 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240375038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.2240375038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/192.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.2355682947 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 487849898 ps |
| CPU time | 4.66 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:28 PM UTC 24 |
| Peak memory | 254820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355682947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.2355682947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/193.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.309881217 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 710999018 ps |
| CPU time | 10.79 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:35 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309881217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.309881217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/193.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_init_fail.3944452988 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 680464258 ps |
| CPU time | 5.16 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:29 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944452988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.3944452988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/194.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.92947790 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 542350210 ps |
| CPU time | 4.17 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:28 PM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92947790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.92947790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/194.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.2714046203 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 323996696 ps |
| CPU time | 3.97 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:28 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714046203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.2714046203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/195.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.3893758825 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 427801397 ps |
| CPU time | 4.17 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:28 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893758825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.3893758825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/195.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.2684717791 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 163259813 ps |
| CPU time | 4.52 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:28 PM UTC 24 |
| Peak memory | 252656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684717791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.2684717791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/196.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.371185130 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 730710027 ps |
| CPU time | 7.95 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:32 PM UTC 24 |
| Peak memory | 252896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371185130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.371185130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/196.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.2511673115 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 2045290473 ps |
| CPU time | 4.37 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:28 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511673115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.2511673115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/197.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.1949844253 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 684654514 ps |
| CPU time | 6.31 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:30 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949844253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.1949844253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/197.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.1030697317 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 439092247 ps |
| CPU time | 3.68 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:28 PM UTC 24 |
| Peak memory | 254740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030697317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.1030697317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/198.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.2849149031 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 250469407 ps |
| CPU time | 5.77 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:30 PM UTC 24 |
| Peak memory | 252624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849149031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2849149031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/198.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.5096766 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 122323002 ps |
| CPU time | 3.35 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:27 PM UTC 24 |
| Peak memory | 252656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5096766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.5096766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/199.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.742125163 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 618422200 ps |
| CPU time | 14.51 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:39 PM UTC 24 |
| Peak memory | 252612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742125163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.742125163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/199.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_alert_test.305860462 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 49119952 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:20 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305860462 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.305860462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_check_fail.2574629566 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 7927402762 ps |
| CPU time | 10.21 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:28 PM UTC 24 |
| Peak memory | 254896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574629566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.2574629566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_errs.2752711807 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 706752828 ps |
| CPU time | 18.26 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:36 PM UTC 24 |
| Peak memory | 254644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752711807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.2752711807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_lock.3819170988 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 4022147753 ps |
| CPU time | 27.18 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:45 PM UTC 24 |
| Peak memory | 252788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819170988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.3819170988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_init_fail.884379990 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1865720631 ps |
| CPU time | 5.35 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:23 PM UTC 24 |
| Peak memory | 252976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884379990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.884379990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_macro_errs.1937720478 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 905223701 ps |
| CPU time | 20.92 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:39 PM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937720478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.1937720478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_esc.3478642088 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1228091787 ps |
| CPU time | 12.91 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:31 PM UTC 24 |
| Peak memory | 259044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478642088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.3478642088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_sec_cm.2218764881 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 11290163254 ps |
| CPU time | 181.63 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:40:22 PM UTC 24 |
| Peak memory | 297504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218764881 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.2218764881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_smoke.1812867528 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 287932502 ps |
| CPU time | 6.27 seconds |
| Started | Oct 12 05:37:16 PM UTC 24 |
| Finished | Oct 12 05:37:24 PM UTC 24 |
| Peak memory | 252592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812867528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.1812867528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/2.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_alert_test.3288017599 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 45555476 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 05:39:11 PM UTC 24 |
| Finished | Oct 12 05:39:14 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288017599 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.3288017599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/20.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_check_fail.2453787099 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 9647049519 ps |
| CPU time | 18.3 seconds |
| Started | Oct 12 05:39:08 PM UTC 24 |
| Finished | Oct 12 05:39:27 PM UTC 24 |
| Peak memory | 255212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453787099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.2453787099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_errs.579583466 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 7014844749 ps |
| CPU time | 13.25 seconds |
| Started | Oct 12 05:39:06 PM UTC 24 |
| Finished | Oct 12 05:39:21 PM UTC 24 |
| Peak memory | 252864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579583466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.579583466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/20.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_lock.2628521475 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 672885183 ps |
| CPU time | 18.2 seconds |
| Started | Oct 12 05:39:06 PM UTC 24 |
| Finished | Oct 12 05:39:26 PM UTC 24 |
| Peak memory | 255120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628521475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.2628521475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/20.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_macro_errs.891120978 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 380155311 ps |
| CPU time | 7.19 seconds |
| Started | Oct 12 05:39:08 PM UTC 24 |
| Finished | Oct 12 05:39:16 PM UTC 24 |
| Peak memory | 254876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891120978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.891120978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/20.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_key_req.2109207471 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 3223535902 ps |
| CPU time | 29.94 seconds |
| Started | Oct 12 05:39:11 PM UTC 24 |
| Finished | Oct 12 05:39:43 PM UTC 24 |
| Peak memory | 253104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109207471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.2109207471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_esc.2425172310 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 367680443 ps |
| CPU time | 8.75 seconds |
| Started | Oct 12 05:39:06 PM UTC 24 |
| Finished | Oct 12 05:39:16 PM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425172310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.2425172310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_req.3615257563 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 635652405 ps |
| CPU time | 16.1 seconds |
| Started | Oct 12 05:39:06 PM UTC 24 |
| Finished | Oct 12 05:39:24 PM UTC 24 |
| Peak memory | 252940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615257563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.3615257563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_regwen.788652768 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 299432037 ps |
| CPU time | 10.91 seconds |
| Started | Oct 12 05:39:11 PM UTC 24 |
| Finished | Oct 12 05:39:23 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788652768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.788652768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/20.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_smoke.270640229 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 357710482 ps |
| CPU time | 7.06 seconds |
| Started | Oct 12 05:39:03 PM UTC 24 |
| Finished | Oct 12 05:39:11 PM UTC 24 |
| Peak memory | 252980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270640229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.270640229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/20.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all.1859674747 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 67845825176 ps |
| CPU time | 135.7 seconds |
| Started | Oct 12 05:39:11 PM UTC 24 |
| Finished | Oct 12 05:41:30 PM UTC 24 |
| Peak memory | 259064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859674747 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.1859674747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.2729178122 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 2802823005 ps |
| CPU time | 50.54 seconds |
| Started | Oct 12 05:39:11 PM UTC 24 |
| Finished | Oct 12 05:40:03 PM UTC 24 |
| Peak memory | 259140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2729178122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 20.otp_ctrl_stress_all_with_rand_reset.2729178122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_test_access.3411874929 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1614415553 ps |
| CPU time | 16.61 seconds |
| Started | Oct 12 05:39:11 PM UTC 24 |
| Finished | Oct 12 05:39:29 PM UTC 24 |
| Peak memory | 254892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411874929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.3411874929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/20.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.2713141153 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 130865840 ps |
| CPU time | 3.15 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:27 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713141153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.2713141153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/200.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.1296979010 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 115505082 ps |
| CPU time | 2.91 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:27 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296979010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.1296979010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/201.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.3660643951 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 94329831 ps |
| CPU time | 3.9 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:28 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660643951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.3660643951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/202.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.2491621472 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 213839323 ps |
| CPU time | 3.46 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:28 PM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491621472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.2491621472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/203.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.2816291766 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 387831434 ps |
| CPU time | 4.73 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:29 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816291766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.2816291766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/204.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.2328652761 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 125980315 ps |
| CPU time | 4.27 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:29 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328652761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.2328652761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/205.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.2060015753 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 408412624 ps |
| CPU time | 4.8 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:29 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060015753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.2060015753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/206.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.2634485633 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 2088509169 ps |
| CPU time | 5.99 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:30 PM UTC 24 |
| Peak memory | 252268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634485633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.2634485633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/207.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.1870531743 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 234144082 ps |
| CPU time | 4.01 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:28 PM UTC 24 |
| Peak memory | 252596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870531743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.1870531743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/208.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_alert_test.1296754179 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 87328671 ps |
| CPU time | 2.39 seconds |
| Started | Oct 12 05:39:19 PM UTC 24 |
| Finished | Oct 12 05:39:23 PM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296754179 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.1296754179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/21.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_check_fail.1160470139 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 812629471 ps |
| CPU time | 23.95 seconds |
| Started | Oct 12 05:39:15 PM UTC 24 |
| Finished | Oct 12 05:39:41 PM UTC 24 |
| Peak memory | 254920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160470139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.1160470139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/21.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_errs.1780498784 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 483965984 ps |
| CPU time | 13.12 seconds |
| Started | Oct 12 05:39:13 PM UTC 24 |
| Finished | Oct 12 05:39:27 PM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780498784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.1780498784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/21.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_lock.7091632 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 117108132 ps |
| CPU time | 4.12 seconds |
| Started | Oct 12 05:39:13 PM UTC 24 |
| Finished | Oct 12 05:39:18 PM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7091632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.7091632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/21.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_init_fail.676273906 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 406780546 ps |
| CPU time | 4.53 seconds |
| Started | Oct 12 05:39:11 PM UTC 24 |
| Finished | Oct 12 05:39:17 PM UTC 24 |
| Peak memory | 254868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676273906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.676273906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/21.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_macro_errs.3896710376 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1361950954 ps |
| CPU time | 16.2 seconds |
| Started | Oct 12 05:39:15 PM UTC 24 |
| Finished | Oct 12 05:39:33 PM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896710376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.3896710376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/21.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_key_req.1600228811 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 10110279071 ps |
| CPU time | 18.61 seconds |
| Started | Oct 12 05:39:15 PM UTC 24 |
| Finished | Oct 12 05:39:35 PM UTC 24 |
| Peak memory | 254896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600228811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.1600228811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_esc.1079140856 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 4846794570 ps |
| CPU time | 14.34 seconds |
| Started | Oct 12 05:39:13 PM UTC 24 |
| Finished | Oct 12 05:39:29 PM UTC 24 |
| Peak memory | 253060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079140856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.1079140856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_req.2860162 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 12296242180 ps |
| CPU time | 36.84 seconds |
| Started | Oct 12 05:39:12 PM UTC 24 |
| Finished | Oct 12 05:39:50 PM UTC 24 |
| Peak memory | 259052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_t est +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.2860162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_regwen.934260356 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 4239779415 ps |
| CPU time | 12.03 seconds |
| Started | Oct 12 05:39:19 PM UTC 24 |
| Finished | Oct 12 05:39:32 PM UTC 24 |
| Peak memory | 252768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934260356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.934260356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/21.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_smoke.645562763 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 221221621 ps |
| CPU time | 7.08 seconds |
| Started | Oct 12 05:39:11 PM UTC 24 |
| Finished | Oct 12 05:39:20 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645562763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.645562763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/21.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all.2717287163 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1527695942 ps |
| CPU time | 22.3 seconds |
| Started | Oct 12 05:39:19 PM UTC 24 |
| Finished | Oct 12 05:39:42 PM UTC 24 |
| Peak memory | 252824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717287163 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.2717287163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.3728818334 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3444488277 ps |
| CPU time | 114.01 seconds |
| Started | Oct 12 05:39:19 PM UTC 24 |
| Finished | Oct 12 05:41:15 PM UTC 24 |
| Peak memory | 259048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3728818334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 21.otp_ctrl_stress_all_with_rand_reset.3728818334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_test_access.3894184482 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 1241840625 ps |
| CPU time | 16.84 seconds |
| Started | Oct 12 05:39:19 PM UTC 24 |
| Finished | Oct 12 05:39:37 PM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894184482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.3894184482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/21.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.3635863358 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 540679008 ps |
| CPU time | 3.68 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:28 PM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635863358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.3635863358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/210.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.2841388476 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 401370791 ps |
| CPU time | 4.03 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:29 PM UTC 24 |
| Peak memory | 252288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841388476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.2841388476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/211.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.3081041872 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 127605767 ps |
| CPU time | 4.65 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:29 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081041872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.3081041872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/212.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.934250302 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 374842805 ps |
| CPU time | 4.02 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:29 PM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934250302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.934250302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/213.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.3048083497 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 392735599 ps |
| CPU time | 3.95 seconds |
| Started | Oct 12 05:45:23 PM UTC 24 |
| Finished | Oct 12 05:45:29 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048083497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.3048083497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/214.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.845864058 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 276267661 ps |
| CPU time | 4.3 seconds |
| Started | Oct 12 05:45:24 PM UTC 24 |
| Finished | Oct 12 05:45:29 PM UTC 24 |
| Peak memory | 255056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845864058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.845864058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/215.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.3411542333 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 1759217106 ps |
| CPU time | 5.91 seconds |
| Started | Oct 12 05:45:24 PM UTC 24 |
| Finished | Oct 12 05:45:31 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411542333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.3411542333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/216.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.257415886 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 299912610 ps |
| CPU time | 4.25 seconds |
| Started | Oct 12 05:45:24 PM UTC 24 |
| Finished | Oct 12 05:45:29 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257415886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.257415886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/217.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.3872486271 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 309322060 ps |
| CPU time | 3.86 seconds |
| Started | Oct 12 05:45:24 PM UTC 24 |
| Finished | Oct 12 05:45:29 PM UTC 24 |
| Peak memory | 255016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872486271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.3872486271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/218.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.516767616 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 211962564 ps |
| CPU time | 4.66 seconds |
| Started | Oct 12 05:45:24 PM UTC 24 |
| Finished | Oct 12 05:45:30 PM UTC 24 |
| Peak memory | 252848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516767616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.516767616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/219.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_alert_test.432423035 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 116151184 ps |
| CPU time | 3.12 seconds |
| Started | Oct 12 05:39:25 PM UTC 24 |
| Finished | Oct 12 05:39:30 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432423035 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.432423035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/22.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_check_fail.3436003784 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 151520121 ps |
| CPU time | 5.55 seconds |
| Started | Oct 12 05:39:22 PM UTC 24 |
| Finished | Oct 12 05:39:29 PM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436003784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.3436003784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/22.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_errs.4012473330 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 405493366 ps |
| CPU time | 13 seconds |
| Started | Oct 12 05:39:22 PM UTC 24 |
| Finished | Oct 12 05:39:36 PM UTC 24 |
| Peak memory | 252668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012473330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.4012473330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/22.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_lock.461775936 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 465139947 ps |
| CPU time | 7.74 seconds |
| Started | Oct 12 05:39:19 PM UTC 24 |
| Finished | Oct 12 05:39:28 PM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461775936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.461775936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/22.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_init_fail.3463382827 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1652357928 ps |
| CPU time | 6.07 seconds |
| Started | Oct 12 05:39:19 PM UTC 24 |
| Finished | Oct 12 05:39:26 PM UTC 24 |
| Peak memory | 253028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463382827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.3463382827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/22.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_macro_errs.2840769347 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 2298457632 ps |
| CPU time | 37.41 seconds |
| Started | Oct 12 05:39:22 PM UTC 24 |
| Finished | Oct 12 05:40:01 PM UTC 24 |
| Peak memory | 253040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840769347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.2840769347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/22.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_key_req.1040139545 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 2312089766 ps |
| CPU time | 27.37 seconds |
| Started | Oct 12 05:39:22 PM UTC 24 |
| Finished | Oct 12 05:39:51 PM UTC 24 |
| Peak memory | 253076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040139545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.1040139545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_esc.3507315343 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 2861518761 ps |
| CPU time | 22.38 seconds |
| Started | Oct 12 05:39:19 PM UTC 24 |
| Finished | Oct 12 05:39:43 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507315343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.3507315343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_req.1129845485 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 756355912 ps |
| CPU time | 29.89 seconds |
| Started | Oct 12 05:39:19 PM UTC 24 |
| Finished | Oct 12 05:39:51 PM UTC 24 |
| Peak memory | 255052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129845485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.1129845485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_regwen.1003026668 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 156954043 ps |
| CPU time | 5.02 seconds |
| Started | Oct 12 05:39:24 PM UTC 24 |
| Finished | Oct 12 05:39:30 PM UTC 24 |
| Peak memory | 252740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003026668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.1003026668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/22.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_smoke.3172212938 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 507917447 ps |
| CPU time | 5.01 seconds |
| Started | Oct 12 05:39:19 PM UTC 24 |
| Finished | Oct 12 05:39:25 PM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172212938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.3172212938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/22.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all.958733116 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 4853798180 ps |
| CPU time | 96.76 seconds |
| Started | Oct 12 05:39:25 PM UTC 24 |
| Finished | Oct 12 05:41:04 PM UTC 24 |
| Peak memory | 258968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958733116 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.958733116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_test_access.2769356889 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 3236938759 ps |
| CPU time | 29.88 seconds |
| Started | Oct 12 05:39:24 PM UTC 24 |
| Finished | Oct 12 05:39:55 PM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769356889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.2769356889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/22.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.2905060678 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 288658105 ps |
| CPU time | 4.3 seconds |
| Started | Oct 12 05:45:24 PM UTC 24 |
| Finished | Oct 12 05:45:29 PM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905060678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.2905060678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/220.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.1691282779 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 1411527248 ps |
| CPU time | 3.75 seconds |
| Started | Oct 12 05:45:24 PM UTC 24 |
| Finished | Oct 12 05:45:29 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691282779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.1691282779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/221.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.2128170219 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 98960988 ps |
| CPU time | 3.83 seconds |
| Started | Oct 12 05:45:24 PM UTC 24 |
| Finished | Oct 12 05:45:29 PM UTC 24 |
| Peak memory | 254828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128170219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.2128170219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/222.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.185649018 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 152705260 ps |
| CPU time | 4.08 seconds |
| Started | Oct 12 05:45:24 PM UTC 24 |
| Finished | Oct 12 05:45:29 PM UTC 24 |
| Peak memory | 252912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185649018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.185649018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/223.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.2176179325 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 326367939 ps |
| CPU time | 4.73 seconds |
| Started | Oct 12 05:45:24 PM UTC 24 |
| Finished | Oct 12 05:45:30 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176179325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.2176179325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/224.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.4021608655 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 260321253 ps |
| CPU time | 4.61 seconds |
| Started | Oct 12 05:45:24 PM UTC 24 |
| Finished | Oct 12 05:45:30 PM UTC 24 |
| Peak memory | 254952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021608655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.4021608655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/225.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.2612365352 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 328914818 ps |
| CPU time | 5.18 seconds |
| Started | Oct 12 05:45:24 PM UTC 24 |
| Finished | Oct 12 05:45:30 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612365352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.2612365352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/226.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.2131266364 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 2169457111 ps |
| CPU time | 5.35 seconds |
| Started | Oct 12 05:45:28 PM UTC 24 |
| Finished | Oct 12 05:45:35 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131266364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.2131266364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/227.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.1955137111 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 2421344132 ps |
| CPU time | 3.73 seconds |
| Started | Oct 12 05:45:28 PM UTC 24 |
| Finished | Oct 12 05:45:33 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955137111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.1955137111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/228.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.1326318192 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 338392933 ps |
| CPU time | 2.78 seconds |
| Started | Oct 12 05:45:28 PM UTC 24 |
| Finished | Oct 12 05:45:32 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326318192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.1326318192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/229.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_alert_test.569657979 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 325374438 ps |
| CPU time | 2.7 seconds |
| Started | Oct 12 05:39:32 PM UTC 24 |
| Finished | Oct 12 05:39:37 PM UTC 24 |
| Peak memory | 252552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569657979 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.569657979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/23.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_check_fail.3525464182 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 650959708 ps |
| CPU time | 19.18 seconds |
| Started | Oct 12 05:39:31 PM UTC 24 |
| Finished | Oct 12 05:39:51 PM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525464182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.3525464182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/23.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_errs.1462763340 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 938607052 ps |
| CPU time | 27.18 seconds |
| Started | Oct 12 05:39:31 PM UTC 24 |
| Finished | Oct 12 05:40:00 PM UTC 24 |
| Peak memory | 250716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462763340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.1462763340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/23.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_lock.1329326829 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 4066100366 ps |
| CPU time | 22.49 seconds |
| Started | Oct 12 05:39:31 PM UTC 24 |
| Finished | Oct 12 05:39:55 PM UTC 24 |
| Peak memory | 259344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329326829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.1329326829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/23.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_init_fail.207735037 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 200265279 ps |
| CPU time | 4.52 seconds |
| Started | Oct 12 05:39:28 PM UTC 24 |
| Finished | Oct 12 05:39:33 PM UTC 24 |
| Peak memory | 254744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207735037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.207735037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/23.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_macro_errs.2683403988 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 911410301 ps |
| CPU time | 14.94 seconds |
| Started | Oct 12 05:39:31 PM UTC 24 |
| Finished | Oct 12 05:39:47 PM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683403988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.2683403988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/23.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_key_req.3061044358 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 3446942317 ps |
| CPU time | 18.55 seconds |
| Started | Oct 12 05:39:31 PM UTC 24 |
| Finished | Oct 12 05:39:51 PM UTC 24 |
| Peak memory | 255024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061044358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.3061044358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_esc.1541374752 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 321901656 ps |
| CPU time | 6.94 seconds |
| Started | Oct 12 05:39:28 PM UTC 24 |
| Finished | Oct 12 05:39:36 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541374752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.1541374752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_req.2209914498 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 625521516 ps |
| CPU time | 17.18 seconds |
| Started | Oct 12 05:39:28 PM UTC 24 |
| Finished | Oct 12 05:39:46 PM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209914498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.2209914498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_regwen.1523245549 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1267892842 ps |
| CPU time | 13.32 seconds |
| Started | Oct 12 05:39:31 PM UTC 24 |
| Finished | Oct 12 05:39:46 PM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523245549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.1523245549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/23.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_smoke.3382186377 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 101204833 ps |
| CPU time | 4.43 seconds |
| Started | Oct 12 05:39:28 PM UTC 24 |
| Finished | Oct 12 05:39:33 PM UTC 24 |
| Peak memory | 252632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382186377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.3382186377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/23.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all.2764787722 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 8440447508 ps |
| CPU time | 93.82 seconds |
| Started | Oct 12 05:39:31 PM UTC 24 |
| Finished | Oct 12 05:41:07 PM UTC 24 |
| Peak memory | 259164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764787722 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.2764787722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.3870406480 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 49415527000 ps |
| CPU time | 191.92 seconds |
| Started | Oct 12 05:39:31 PM UTC 24 |
| Finished | Oct 12 05:42:46 PM UTC 24 |
| Peak memory | 259108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3870406480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 23.otp_ctrl_stress_all_with_rand_reset.3870406480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_test_access.1817958648 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 1326790175 ps |
| CPU time | 16.84 seconds |
| Started | Oct 12 05:39:31 PM UTC 24 |
| Finished | Oct 12 05:39:49 PM UTC 24 |
| Peak memory | 254772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817958648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.1817958648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/23.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.3960724249 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 106737686 ps |
| CPU time | 3.29 seconds |
| Started | Oct 12 05:45:28 PM UTC 24 |
| Finished | Oct 12 05:45:33 PM UTC 24 |
| Peak memory | 255016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960724249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.3960724249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/230.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.3733076799 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 116661366 ps |
| CPU time | 3.07 seconds |
| Started | Oct 12 05:45:28 PM UTC 24 |
| Finished | Oct 12 05:45:33 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733076799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.3733076799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/231.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.1908735835 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 387089790 ps |
| CPU time | 3.07 seconds |
| Started | Oct 12 05:45:28 PM UTC 24 |
| Finished | Oct 12 05:45:33 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908735835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.1908735835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/232.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.2449003133 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 110204101 ps |
| CPU time | 2.97 seconds |
| Started | Oct 12 05:45:29 PM UTC 24 |
| Finished | Oct 12 05:45:33 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449003133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.2449003133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/233.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.3270743424 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 171579404 ps |
| CPU time | 3.62 seconds |
| Started | Oct 12 05:45:29 PM UTC 24 |
| Finished | Oct 12 05:45:33 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270743424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.3270743424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/234.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.892392100 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 170701751 ps |
| CPU time | 4.07 seconds |
| Started | Oct 12 05:45:29 PM UTC 24 |
| Finished | Oct 12 05:45:34 PM UTC 24 |
| Peak memory | 252948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892392100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.892392100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/235.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.569383993 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 226199086 ps |
| CPU time | 3.15 seconds |
| Started | Oct 12 05:45:29 PM UTC 24 |
| Finished | Oct 12 05:45:33 PM UTC 24 |
| Peak memory | 253036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569383993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.569383993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/236.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.393097055 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 114517717 ps |
| CPU time | 3.26 seconds |
| Started | Oct 12 05:45:29 PM UTC 24 |
| Finished | Oct 12 05:45:33 PM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393097055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.393097055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/237.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.1140681454 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 144913976 ps |
| CPU time | 3.92 seconds |
| Started | Oct 12 05:45:29 PM UTC 24 |
| Finished | Oct 12 05:45:34 PM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140681454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.1140681454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/238.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.3873019541 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 101108942 ps |
| CPU time | 3.13 seconds |
| Started | Oct 12 05:45:29 PM UTC 24 |
| Finished | Oct 12 05:45:33 PM UTC 24 |
| Peak memory | 255016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873019541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.3873019541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/239.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_alert_test.3098560102 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 135833397 ps |
| CPU time | 2.35 seconds |
| Started | Oct 12 05:39:43 PM UTC 24 |
| Finished | Oct 12 05:39:47 PM UTC 24 |
| Peak memory | 252488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098560102 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.3098560102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/24.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_check_fail.3514431845 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 2199737485 ps |
| CPU time | 21.18 seconds |
| Started | Oct 12 05:39:39 PM UTC 24 |
| Finished | Oct 12 05:40:02 PM UTC 24 |
| Peak memory | 252940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514431845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.3514431845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/24.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_errs.1533515961 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 452103736 ps |
| CPU time | 11.56 seconds |
| Started | Oct 12 05:39:39 PM UTC 24 |
| Finished | Oct 12 05:39:52 PM UTC 24 |
| Peak memory | 252668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533515961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.1533515961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/24.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_lock.2606151822 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 345727561 ps |
| CPU time | 6.7 seconds |
| Started | Oct 12 05:39:39 PM UTC 24 |
| Finished | Oct 12 05:39:47 PM UTC 24 |
| Peak memory | 252864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606151822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.2606151822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/24.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_init_fail.2686422861 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 226931412 ps |
| CPU time | 4.08 seconds |
| Started | Oct 12 05:39:35 PM UTC 24 |
| Finished | Oct 12 05:39:41 PM UTC 24 |
| Peak memory | 253044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686422861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.2686422861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/24.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_macro_errs.2908215400 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 537725334 ps |
| CPU time | 6.09 seconds |
| Started | Oct 12 05:39:39 PM UTC 24 |
| Finished | Oct 12 05:39:46 PM UTC 24 |
| Peak memory | 252792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908215400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.2908215400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/24.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_key_req.2399286981 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 5771476444 ps |
| CPU time | 43.02 seconds |
| Started | Oct 12 05:39:39 PM UTC 24 |
| Finished | Oct 12 05:40:24 PM UTC 24 |
| Peak memory | 258992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399286981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.2399286981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_esc.1136324857 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 235723145 ps |
| CPU time | 11.15 seconds |
| Started | Oct 12 05:39:39 PM UTC 24 |
| Finished | Oct 12 05:39:51 PM UTC 24 |
| Peak memory | 252604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136324857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.1136324857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_req.3633329129 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 172322907 ps |
| CPU time | 7.15 seconds |
| Started | Oct 12 05:39:36 PM UTC 24 |
| Finished | Oct 12 05:39:44 PM UTC 24 |
| Peak memory | 258892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633329129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.3633329129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_regwen.426565326 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 297663292 ps |
| CPU time | 5.12 seconds |
| Started | Oct 12 05:39:39 PM UTC 24 |
| Finished | Oct 12 05:39:46 PM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426565326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.426565326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/24.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_smoke.231938162 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 492521584 ps |
| CPU time | 8.9 seconds |
| Started | Oct 12 05:39:35 PM UTC 24 |
| Finished | Oct 12 05:39:46 PM UTC 24 |
| Peak memory | 252728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231938162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.231938162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/24.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all.3311408847 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 24879884985 ps |
| CPU time | 184.56 seconds |
| Started | Oct 12 05:39:43 PM UTC 24 |
| Finished | Oct 12 05:42:51 PM UTC 24 |
| Peak memory | 287712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311408847 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all.3311408847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.2793737328 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 7119431204 ps |
| CPU time | 126.17 seconds |
| Started | Oct 12 05:39:43 PM UTC 24 |
| Finished | Oct 12 05:41:51 PM UTC 24 |
| Peak memory | 269332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2793737328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 24.otp_ctrl_stress_all_with_rand_reset.2793737328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_test_access.3298749684 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 3371681206 ps |
| CPU time | 26.33 seconds |
| Started | Oct 12 05:39:43 PM UTC 24 |
| Finished | Oct 12 05:40:11 PM UTC 24 |
| Peak memory | 253040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298749684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.3298749684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/24.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.2492057503 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 152543727 ps |
| CPU time | 3.73 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:36 PM UTC 24 |
| Peak memory | 252964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492057503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.2492057503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/240.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.2097697166 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 160901936 ps |
| CPU time | 3.6 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:36 PM UTC 24 |
| Peak memory | 254820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097697166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.2097697166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/241.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.2930652347 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 367243391 ps |
| CPU time | 3.23 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:35 PM UTC 24 |
| Peak memory | 252656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930652347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.2930652347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/242.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.3134700459 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 116695197 ps |
| CPU time | 3.65 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:36 PM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134700459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.3134700459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/243.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.3335578094 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 331278107 ps |
| CPU time | 4.42 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:37 PM UTC 24 |
| Peak memory | 254952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335578094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.3335578094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/244.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.2936794990 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 174835751 ps |
| CPU time | 2.9 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:35 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936794990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.2936794990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/245.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.2660260569 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 137029968 ps |
| CPU time | 3.72 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:36 PM UTC 24 |
| Peak memory | 254824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660260569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.2660260569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/246.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.1628889413 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 93088474 ps |
| CPU time | 3.02 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:35 PM UTC 24 |
| Peak memory | 254816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628889413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.1628889413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/247.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.1041270153 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 389049985 ps |
| CPU time | 3.54 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:36 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041270153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.1041270153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/248.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.1392099681 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 150141628 ps |
| CPU time | 3.19 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:36 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392099681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.1392099681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/249.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_alert_test.1451759670 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 177237093 ps |
| CPU time | 1.99 seconds |
| Started | Oct 12 05:39:50 PM UTC 24 |
| Finished | Oct 12 05:39:53 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451759670 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.1451759670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/25.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_check_fail.1435345109 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 2652654321 ps |
| CPU time | 10.68 seconds |
| Started | Oct 12 05:39:47 PM UTC 24 |
| Finished | Oct 12 05:39:59 PM UTC 24 |
| Peak memory | 258984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435345109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.1435345109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/25.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_errs.611523981 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 6009103287 ps |
| CPU time | 29.57 seconds |
| Started | Oct 12 05:39:47 PM UTC 24 |
| Finished | Oct 12 05:40:18 PM UTC 24 |
| Peak memory | 252816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611523981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.611523981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/25.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_lock.4171389311 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 2866905599 ps |
| CPU time | 25.26 seconds |
| Started | Oct 12 05:39:45 PM UTC 24 |
| Finished | Oct 12 05:40:12 PM UTC 24 |
| Peak memory | 253044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171389311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.4171389311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/25.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_init_fail.1929236024 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1768398043 ps |
| CPU time | 6.46 seconds |
| Started | Oct 12 05:39:45 PM UTC 24 |
| Finished | Oct 12 05:39:53 PM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929236024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.1929236024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/25.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_macro_errs.3788661921 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2365946158 ps |
| CPU time | 24.36 seconds |
| Started | Oct 12 05:39:47 PM UTC 24 |
| Finished | Oct 12 05:40:12 PM UTC 24 |
| Peak memory | 257196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788661921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.3788661921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/25.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_key_req.729541407 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1259712500 ps |
| CPU time | 34.41 seconds |
| Started | Oct 12 05:39:48 PM UTC 24 |
| Finished | Oct 12 05:40:24 PM UTC 24 |
| Peak memory | 254820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729541407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.729541407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_esc.4067747906 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 151711443 ps |
| CPU time | 6.95 seconds |
| Started | Oct 12 05:39:45 PM UTC 24 |
| Finished | Oct 12 05:39:53 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067747906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.4067747906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_req.2490455751 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 900065212 ps |
| CPU time | 13.34 seconds |
| Started | Oct 12 05:39:45 PM UTC 24 |
| Finished | Oct 12 05:40:00 PM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490455751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.2490455751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_regwen.224418009 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 134350805 ps |
| CPU time | 5.04 seconds |
| Started | Oct 12 05:39:48 PM UTC 24 |
| Finished | Oct 12 05:39:55 PM UTC 24 |
| Peak memory | 252728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224418009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.224418009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/25.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_smoke.1843339887 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 674839333 ps |
| CPU time | 7.87 seconds |
| Started | Oct 12 05:39:45 PM UTC 24 |
| Finished | Oct 12 05:39:54 PM UTC 24 |
| Peak memory | 252792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843339887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.1843339887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/25.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all.3253821117 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2051629201 ps |
| CPU time | 54.44 seconds |
| Started | Oct 12 05:39:49 PM UTC 24 |
| Finished | Oct 12 05:40:45 PM UTC 24 |
| Peak memory | 256788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253821117 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.3253821117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_test_access.1162395398 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 3012522523 ps |
| CPU time | 21.59 seconds |
| Started | Oct 12 05:39:49 PM UTC 24 |
| Finished | Oct 12 05:40:11 PM UTC 24 |
| Peak memory | 252904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162395398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.1162395398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/25.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.1952622697 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 318167525 ps |
| CPU time | 3.64 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:36 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952622697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.1952622697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/250.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.847865005 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 188872254 ps |
| CPU time | 3.61 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:36 PM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847865005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.847865005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/252.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.1026155881 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 2512402295 ps |
| CPU time | 5.08 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:38 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026155881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.1026155881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/253.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.476820326 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 530107363 ps |
| CPU time | 4.13 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:37 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476820326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.476820326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/254.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.92169844 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1557737376 ps |
| CPU time | 4.05 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:37 PM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92169844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.92169844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/255.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.1855750565 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 496463906 ps |
| CPU time | 3.7 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:36 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855750565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.1855750565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/256.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.2889961542 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 577764354 ps |
| CPU time | 4.09 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:37 PM UTC 24 |
| Peak memory | 252972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889961542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.2889961542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/257.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.3905497898 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 2734056062 ps |
| CPU time | 4.5 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:37 PM UTC 24 |
| Peak memory | 252836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905497898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.3905497898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/258.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.3503157694 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 174130209 ps |
| CPU time | 4.09 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:37 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503157694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.3503157694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/259.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_alert_test.4076619433 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 228014244 ps |
| CPU time | 3.25 seconds |
| Started | Oct 12 05:39:57 PM UTC 24 |
| Finished | Oct 12 05:40:01 PM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076619433 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.4076619433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/26.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_check_fail.3870698144 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 763831468 ps |
| CPU time | 10.51 seconds |
| Started | Oct 12 05:39:54 PM UTC 24 |
| Finished | Oct 12 05:40:06 PM UTC 24 |
| Peak memory | 253036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870698144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.3870698144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_errs.3492600833 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 2054334675 ps |
| CPU time | 32.83 seconds |
| Started | Oct 12 05:39:54 PM UTC 24 |
| Finished | Oct 12 05:40:28 PM UTC 24 |
| Peak memory | 258796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492600833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.3492600833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/26.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_lock.670721243 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 919006272 ps |
| CPU time | 15.27 seconds |
| Started | Oct 12 05:39:54 PM UTC 24 |
| Finished | Oct 12 05:40:11 PM UTC 24 |
| Peak memory | 253012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670721243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.670721243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/26.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_init_fail.2589088214 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 117869648 ps |
| CPU time | 3.17 seconds |
| Started | Oct 12 05:39:50 PM UTC 24 |
| Finished | Oct 12 05:39:55 PM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589088214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.2589088214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_macro_errs.792087135 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 305315719 ps |
| CPU time | 9.81 seconds |
| Started | Oct 12 05:39:54 PM UTC 24 |
| Finished | Oct 12 05:40:05 PM UTC 24 |
| Peak memory | 253008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792087135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.792087135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/26.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_key_req.1150888512 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 8961575307 ps |
| CPU time | 19.8 seconds |
| Started | Oct 12 05:39:54 PM UTC 24 |
| Finished | Oct 12 05:40:15 PM UTC 24 |
| Peak memory | 254868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150888512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.1150888512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_esc.1403878001 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1141697300 ps |
| CPU time | 10.52 seconds |
| Started | Oct 12 05:39:54 PM UTC 24 |
| Finished | Oct 12 05:40:06 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403878001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.1403878001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_req.3531661182 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 1066941215 ps |
| CPU time | 10.97 seconds |
| Started | Oct 12 05:39:54 PM UTC 24 |
| Finished | Oct 12 05:40:06 PM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531661182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.3531661182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_regwen.3050796904 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 191712475 ps |
| CPU time | 6.62 seconds |
| Started | Oct 12 05:39:55 PM UTC 24 |
| Finished | Oct 12 05:40:02 PM UTC 24 |
| Peak memory | 252740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050796904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.3050796904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/26.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_smoke.1467631347 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 933577858 ps |
| CPU time | 8.67 seconds |
| Started | Oct 12 05:39:50 PM UTC 24 |
| Finished | Oct 12 05:40:00 PM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467631347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.1467631347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/26.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_test_access.2585347199 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 1090403621 ps |
| CPU time | 23.91 seconds |
| Started | Oct 12 05:39:55 PM UTC 24 |
| Finished | Oct 12 05:40:20 PM UTC 24 |
| Peak memory | 253036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585347199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.2585347199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/26.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.750262099 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 119558949 ps |
| CPU time | 3.05 seconds |
| Started | Oct 12 05:45:31 PM UTC 24 |
| Finished | Oct 12 05:45:36 PM UTC 24 |
| Peak memory | 254728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750262099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.750262099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/260.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.2776272968 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 291601417 ps |
| CPU time | 3.74 seconds |
| Started | Oct 12 05:45:32 PM UTC 24 |
| Finished | Oct 12 05:45:37 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776272968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.2776272968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/261.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.920298875 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 645826703 ps |
| CPU time | 4.36 seconds |
| Started | Oct 12 05:45:32 PM UTC 24 |
| Finished | Oct 12 05:45:37 PM UTC 24 |
| Peak memory | 252564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920298875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.920298875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/263.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.2606656221 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 154826012 ps |
| CPU time | 3.96 seconds |
| Started | Oct 12 05:45:32 PM UTC 24 |
| Finished | Oct 12 05:45:37 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606656221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.2606656221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/264.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.99008221 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 108619715 ps |
| CPU time | 3.44 seconds |
| Started | Oct 12 05:45:32 PM UTC 24 |
| Finished | Oct 12 05:45:36 PM UTC 24 |
| Peak memory | 252740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99008221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.99008221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/265.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.240970902 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 1273124192 ps |
| CPU time | 4.81 seconds |
| Started | Oct 12 05:45:32 PM UTC 24 |
| Finished | Oct 12 05:45:38 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240970902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.240970902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/266.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.290191254 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 2355053833 ps |
| CPU time | 5.64 seconds |
| Started | Oct 12 05:45:32 PM UTC 24 |
| Finished | Oct 12 05:45:39 PM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290191254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.290191254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/267.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.537649580 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 209533927 ps |
| CPU time | 3.42 seconds |
| Started | Oct 12 05:45:32 PM UTC 24 |
| Finished | Oct 12 05:45:36 PM UTC 24 |
| Peak memory | 254740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537649580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.537649580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/268.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.2529474614 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 307075508 ps |
| CPU time | 3.44 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:45 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529474614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.2529474614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/269.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_alert_test.1038347166 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 73385305 ps |
| CPU time | 2.45 seconds |
| Started | Oct 12 05:40:05 PM UTC 24 |
| Finished | Oct 12 05:40:08 PM UTC 24 |
| Peak memory | 252468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038347166 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.1038347166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/27.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_check_fail.3891702715 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2200253238 ps |
| CPU time | 25.16 seconds |
| Started | Oct 12 05:40:04 PM UTC 24 |
| Finished | Oct 12 05:40:31 PM UTC 24 |
| Peak memory | 254924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891702715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.3891702715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/27.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_errs.379459880 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 922340738 ps |
| CPU time | 30.1 seconds |
| Started | Oct 12 05:40:04 PM UTC 24 |
| Finished | Oct 12 05:40:36 PM UTC 24 |
| Peak memory | 257296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379459880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.379459880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/27.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_lock.1488328257 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 984717597 ps |
| CPU time | 16.89 seconds |
| Started | Oct 12 05:40:04 PM UTC 24 |
| Finished | Oct 12 05:40:23 PM UTC 24 |
| Peak memory | 252880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488328257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.1488328257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/27.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_init_fail.1246510353 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 417576368 ps |
| CPU time | 4.01 seconds |
| Started | Oct 12 05:39:57 PM UTC 24 |
| Finished | Oct 12 05:40:02 PM UTC 24 |
| Peak memory | 254828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246510353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.1246510353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/27.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_macro_errs.436967559 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 540148157 ps |
| CPU time | 12.47 seconds |
| Started | Oct 12 05:40:05 PM UTC 24 |
| Finished | Oct 12 05:40:18 PM UTC 24 |
| Peak memory | 256904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436967559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.436967559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/27.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_key_req.2861349706 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 1620778581 ps |
| CPU time | 41.55 seconds |
| Started | Oct 12 05:40:05 PM UTC 24 |
| Finished | Oct 12 05:40:48 PM UTC 24 |
| Peak memory | 258864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861349706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.2861349706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_esc.2434609154 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 368755846 ps |
| CPU time | 15.43 seconds |
| Started | Oct 12 05:39:59 PM UTC 24 |
| Finished | Oct 12 05:40:15 PM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434609154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.2434609154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_req.1378043001 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 1019821579 ps |
| CPU time | 16.72 seconds |
| Started | Oct 12 05:39:57 PM UTC 24 |
| Finished | Oct 12 05:40:15 PM UTC 24 |
| Peak memory | 254764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378043001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.1378043001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_regwen.418202459 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 474722324 ps |
| CPU time | 6.12 seconds |
| Started | Oct 12 05:40:05 PM UTC 24 |
| Finished | Oct 12 05:40:12 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418202459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.418202459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/27.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_smoke.2550070713 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 4683346428 ps |
| CPU time | 7.13 seconds |
| Started | Oct 12 05:39:57 PM UTC 24 |
| Finished | Oct 12 05:40:05 PM UTC 24 |
| Peak memory | 252852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550070713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.2550070713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/27.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all.2271434928 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 99837374159 ps |
| CPU time | 486.97 seconds |
| Started | Oct 12 05:40:05 PM UTC 24 |
| Finished | Oct 12 05:48:18 PM UTC 24 |
| Peak memory | 285656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271434928 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.2271434928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.918276305 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 21488942788 ps |
| CPU time | 186.19 seconds |
| Started | Oct 12 05:40:05 PM UTC 24 |
| Finished | Oct 12 05:43:14 PM UTC 24 |
| Peak memory | 271408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=918276305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.918276305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_test_access.1879247712 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1261218913 ps |
| CPU time | 13.72 seconds |
| Started | Oct 12 05:40:05 PM UTC 24 |
| Finished | Oct 12 05:40:20 PM UTC 24 |
| Peak memory | 253164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879247712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.1879247712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/27.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.3965127821 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 351847397 ps |
| CPU time | 3.89 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965127821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.3965127821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/270.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.3976505466 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 369230721 ps |
| CPU time | 4.28 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 252904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976505466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.3976505466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/271.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.3618044318 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 185750638 ps |
| CPU time | 3.83 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 252908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618044318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.3618044318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/272.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.129959057 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 2182893357 ps |
| CPU time | 4.33 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129959057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.129959057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/273.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.2520339551 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 442243659 ps |
| CPU time | 3.91 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520339551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.2520339551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/274.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.1920126460 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 1460481081 ps |
| CPU time | 4.18 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 254748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920126460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.1920126460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/275.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.2209490241 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 2142955990 ps |
| CPU time | 4.79 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:47 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209490241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.2209490241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/276.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.4178504187 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 2118509278 ps |
| CPU time | 3.5 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178504187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.4178504187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/277.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.2031688039 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 565761312 ps |
| CPU time | 4.39 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:47 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031688039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.2031688039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/278.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.600437182 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 1699550918 ps |
| CPU time | 5.34 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:48 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600437182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.600437182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/279.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_alert_test.303130545 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 220657388 ps |
| CPU time | 3.38 seconds |
| Started | Oct 12 05:40:13 PM UTC 24 |
| Finished | Oct 12 05:40:18 PM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303130545 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.303130545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/28.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_check_fail.3862178869 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1997623118 ps |
| CPU time | 31.34 seconds |
| Started | Oct 12 05:40:08 PM UTC 24 |
| Finished | Oct 12 05:40:40 PM UTC 24 |
| Peak memory | 259120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862178869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.3862178869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/28.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_errs.1716337007 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 537527523 ps |
| CPU time | 16.65 seconds |
| Started | Oct 12 05:40:07 PM UTC 24 |
| Finished | Oct 12 05:40:25 PM UTC 24 |
| Peak memory | 252676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716337007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.1716337007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/28.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_lock.2364858975 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 3272710358 ps |
| CPU time | 25.05 seconds |
| Started | Oct 12 05:40:07 PM UTC 24 |
| Finished | Oct 12 05:40:34 PM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364858975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.2364858975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/28.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_init_fail.1978299831 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 100473454 ps |
| CPU time | 4.52 seconds |
| Started | Oct 12 05:40:07 PM UTC 24 |
| Finished | Oct 12 05:40:13 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978299831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.1978299831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/28.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_macro_errs.3172959349 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 3187038308 ps |
| CPU time | 24.43 seconds |
| Started | Oct 12 05:40:09 PM UTC 24 |
| Finished | Oct 12 05:40:34 PM UTC 24 |
| Peak memory | 257136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172959349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.3172959349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/28.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_key_req.3957111610 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 3778081541 ps |
| CPU time | 29.52 seconds |
| Started | Oct 12 05:40:09 PM UTC 24 |
| Finished | Oct 12 05:40:40 PM UTC 24 |
| Peak memory | 254896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957111610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.3957111610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_esc.3756973268 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 751530565 ps |
| CPU time | 12.39 seconds |
| Started | Oct 12 05:40:07 PM UTC 24 |
| Finished | Oct 12 05:40:21 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756973268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.3756973268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_req.1504176483 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 2382542969 ps |
| CPU time | 19.72 seconds |
| Started | Oct 12 05:40:07 PM UTC 24 |
| Finished | Oct 12 05:40:28 PM UTC 24 |
| Peak memory | 252804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504176483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.1504176483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_regwen.3424776223 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1003372021 ps |
| CPU time | 12.6 seconds |
| Started | Oct 12 05:40:13 PM UTC 24 |
| Finished | Oct 12 05:40:27 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424776223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.3424776223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/28.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_smoke.2669834411 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 492151018 ps |
| CPU time | 3.15 seconds |
| Started | Oct 12 05:40:07 PM UTC 24 |
| Finished | Oct 12 05:40:12 PM UTC 24 |
| Peak memory | 258808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669834411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.2669834411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/28.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all.4095565321 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 5700875025 ps |
| CPU time | 32.32 seconds |
| Started | Oct 12 05:40:13 PM UTC 24 |
| Finished | Oct 12 05:40:47 PM UTC 24 |
| Peak memory | 256924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095565321 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.4095565321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.1065958143 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 5278244570 ps |
| CPU time | 103.58 seconds |
| Started | Oct 12 05:40:13 PM UTC 24 |
| Finished | Oct 12 05:41:59 PM UTC 24 |
| Peak memory | 259364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1065958143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.otp_ctrl_stress_all_with_rand_reset.1065958143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_test_access.1842551429 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 957945334 ps |
| CPU time | 8.37 seconds |
| Started | Oct 12 05:40:13 PM UTC 24 |
| Finished | Oct 12 05:40:22 PM UTC 24 |
| Peak memory | 258928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842551429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.1842551429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/28.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.2156765939 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 546106721 ps |
| CPU time | 3.41 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 254700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156765939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.2156765939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/280.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.3447770559 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 210644402 ps |
| CPU time | 4.01 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 252956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447770559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.3447770559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/281.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.559865017 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 2715853221 ps |
| CPU time | 5.32 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:48 PM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559865017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.559865017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/282.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.3903190686 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 305177139 ps |
| CPU time | 3.67 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 254696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903190686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.3903190686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/283.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.62223716 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 2550496570 ps |
| CPU time | 5.91 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:48 PM UTC 24 |
| Peak memory | 253000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62223716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.62223716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/284.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.2704459508 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 187243547 ps |
| CPU time | 3.3 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 255016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704459508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.2704459508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/285.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.1337096667 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 181186879 ps |
| CPU time | 4.07 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:47 PM UTC 24 |
| Peak memory | 252800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337096667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.1337096667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/286.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.2829671412 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 127647229 ps |
| CPU time | 3.67 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829671412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.2829671412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/287.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.3892030915 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 1462460208 ps |
| CPU time | 3.09 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 254760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892030915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.3892030915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/288.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.2072312588 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 2151342760 ps |
| CPU time | 3.39 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072312588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.2072312588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/289.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_alert_test.760977954 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 104955838 ps |
| CPU time | 2.63 seconds |
| Started | Oct 12 05:40:23 PM UTC 24 |
| Finished | Oct 12 05:40:26 PM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760977954 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.760977954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/29.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_check_fail.3276736166 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1041419361 ps |
| CPU time | 26.59 seconds |
| Started | Oct 12 05:40:19 PM UTC 24 |
| Finished | Oct 12 05:40:47 PM UTC 24 |
| Peak memory | 254884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276736166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.3276736166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_errs.3812777856 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 2643136765 ps |
| CPU time | 39.62 seconds |
| Started | Oct 12 05:40:17 PM UTC 24 |
| Finished | Oct 12 05:40:59 PM UTC 24 |
| Peak memory | 259084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812777856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.3812777856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/29.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_lock.3302655244 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 10761988919 ps |
| CPU time | 13.64 seconds |
| Started | Oct 12 05:40:17 PM UTC 24 |
| Finished | Oct 12 05:40:32 PM UTC 24 |
| Peak memory | 255068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302655244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.3302655244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/29.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_macro_errs.3852633471 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 187612197 ps |
| CPU time | 6.7 seconds |
| Started | Oct 12 05:40:19 PM UTC 24 |
| Finished | Oct 12 05:40:27 PM UTC 24 |
| Peak memory | 254800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852633471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.3852633471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/29.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_key_req.3559804424 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 4933196016 ps |
| CPU time | 36.02 seconds |
| Started | Oct 12 05:40:20 PM UTC 24 |
| Finished | Oct 12 05:40:57 PM UTC 24 |
| Peak memory | 253044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559804424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.3559804424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_req.843635079 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 9651720035 ps |
| CPU time | 22.18 seconds |
| Started | Oct 12 05:40:15 PM UTC 24 |
| Finished | Oct 12 05:40:38 PM UTC 24 |
| Peak memory | 259280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843635079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.843635079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_regwen.3915324854 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 378869178 ps |
| CPU time | 9.71 seconds |
| Started | Oct 12 05:40:21 PM UTC 24 |
| Finished | Oct 12 05:40:32 PM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915324854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.3915324854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/29.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_smoke.4185516653 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 493379243 ps |
| CPU time | 8.61 seconds |
| Started | Oct 12 05:40:13 PM UTC 24 |
| Finished | Oct 12 05:40:23 PM UTC 24 |
| Peak memory | 252792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185516653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.4185516653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/29.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_test_access.87503105 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 1337137898 ps |
| CPU time | 13.89 seconds |
| Started | Oct 12 05:40:21 PM UTC 24 |
| Finished | Oct 12 05:40:36 PM UTC 24 |
| Peak memory | 252868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87503105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.87503105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/29.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.3466115282 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 154174424 ps |
| CPU time | 3.45 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466115282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.3466115282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/290.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.1747703250 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 120073464 ps |
| CPU time | 3.48 seconds |
| Started | Oct 12 05:45:41 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747703250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.1747703250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/291.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.2739450095 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 91609442 ps |
| CPU time | 2.97 seconds |
| Started | Oct 12 05:45:42 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739450095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.2739450095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/292.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.512092860 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 132859341 ps |
| CPU time | 3.06 seconds |
| Started | Oct 12 05:45:42 PM UTC 24 |
| Finished | Oct 12 05:45:46 PM UTC 24 |
| Peak memory | 252684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512092860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.512092860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/293.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.1014482448 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 1542142886 ps |
| CPU time | 4.22 seconds |
| Started | Oct 12 05:45:42 PM UTC 24 |
| Finished | Oct 12 05:45:47 PM UTC 24 |
| Peak memory | 254760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014482448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.1014482448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/294.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.1166950398 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 282395277 ps |
| CPU time | 3.72 seconds |
| Started | Oct 12 05:45:44 PM UTC 24 |
| Finished | Oct 12 05:45:49 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166950398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.1166950398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/295.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.854589506 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 419974897 ps |
| CPU time | 4.02 seconds |
| Started | Oct 12 05:45:44 PM UTC 24 |
| Finished | Oct 12 05:45:49 PM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854589506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.854589506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/296.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.446216608 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 173869846 ps |
| CPU time | 3.68 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:49 PM UTC 24 |
| Peak memory | 252684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446216608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.446216608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/297.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.2785765019 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 220414450 ps |
| CPU time | 3.48 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:49 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785765019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.2785765019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/298.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.941270873 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 1781690539 ps |
| CPU time | 4.85 seconds |
| Started | Oct 12 05:45:45 PM UTC 24 |
| Finished | Oct 12 05:45:50 PM UTC 24 |
| Peak memory | 254796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941270873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.941270873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/299.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_alert_test.317036571 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 964918605 ps |
| CPU time | 3.54 seconds |
| Started | Oct 12 05:37:19 PM UTC 24 |
| Finished | Oct 12 05:37:24 PM UTC 24 |
| Peak memory | 252524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317036571 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.317036571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_background_chks.563323476 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 3070536925 ps |
| CPU time | 16.09 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:34 PM UTC 24 |
| Peak memory | 254952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563323476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.563323476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_check_fail.1184517073 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 435994904 ps |
| CPU time | 13.97 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:32 PM UTC 24 |
| Peak memory | 254772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184517073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.1184517073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_errs.128606882 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1274365645 ps |
| CPU time | 16.09 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:35 PM UTC 24 |
| Peak memory | 254716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128606882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.128606882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_lock.1194905803 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 5685754023 ps |
| CPU time | 16.49 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:35 PM UTC 24 |
| Peak memory | 255216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194905803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.1194905803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_macro_errs.4197590486 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1297496555 ps |
| CPU time | 19.78 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:38 PM UTC 24 |
| Peak memory | 256944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197590486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.4197590486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_key_req.2017497441 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 676832616 ps |
| CPU time | 10.71 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:29 PM UTC 24 |
| Peak memory | 258924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017497441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.2017497441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_esc.3867552033 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 286609489 ps |
| CPU time | 7.05 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:25 PM UTC 24 |
| Peak memory | 252624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867552033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.3867552033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_req.3082471916 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1406394343 ps |
| CPU time | 16.57 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:35 PM UTC 24 |
| Peak memory | 252752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082471916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.3082471916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_regwen.4032874728 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 282885066 ps |
| CPU time | 3.32 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:22 PM UTC 24 |
| Peak memory | 252612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032874728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.4032874728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_sec_cm.3237687636 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 32216743291 ps |
| CPU time | 210.18 seconds |
| Started | Oct 12 05:37:19 PM UTC 24 |
| Finished | Oct 12 05:40:52 PM UTC 24 |
| Peak memory | 305600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237687636 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.3237687636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_smoke.1895924474 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1463284476 ps |
| CPU time | 9.14 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:37:27 PM UTC 24 |
| Peak memory | 253116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895924474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.1895924474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.3303327045 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 35160233326 ps |
| CPU time | 73.07 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:38:32 PM UTC 24 |
| Peak memory | 275548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3303327045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.otp_ctrl_stress_all_with_rand_reset.3303327045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_test_access.3076488527 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 49363668010 ps |
| CPU time | 247.22 seconds |
| Started | Oct 12 05:37:17 PM UTC 24 |
| Finished | Oct 12 05:41:29 PM UTC 24 |
| Peak memory | 254920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076488527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.3076488527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_alert_test.2710105300 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 121859006 ps |
| CPU time | 2.9 seconds |
| Started | Oct 12 05:40:37 PM UTC 24 |
| Finished | Oct 12 05:40:41 PM UTC 24 |
| Peak memory | 252552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710105300 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.2710105300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/30.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_check_fail.525711603 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 6962592367 ps |
| CPU time | 36.71 seconds |
| Started | Oct 12 05:40:28 PM UTC 24 |
| Finished | Oct 12 05:41:06 PM UTC 24 |
| Peak memory | 256968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525711603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.525711603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/30.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_errs.613262425 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 5260335377 ps |
| CPU time | 23.93 seconds |
| Started | Oct 12 05:40:28 PM UTC 24 |
| Finished | Oct 12 05:40:53 PM UTC 24 |
| Peak memory | 252752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613262425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.613262425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/30.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_lock.2959805259 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 976064310 ps |
| CPU time | 34.31 seconds |
| Started | Oct 12 05:40:28 PM UTC 24 |
| Finished | Oct 12 05:41:04 PM UTC 24 |
| Peak memory | 254928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959805259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.2959805259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/30.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_init_fail.2451393622 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 119817404 ps |
| CPU time | 5.98 seconds |
| Started | Oct 12 05:40:25 PM UTC 24 |
| Finished | Oct 12 05:40:32 PM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451393622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.2451393622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/30.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_macro_errs.3897396247 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 2304695919 ps |
| CPU time | 13.8 seconds |
| Started | Oct 12 05:40:28 PM UTC 24 |
| Finished | Oct 12 05:40:43 PM UTC 24 |
| Peak memory | 256936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897396247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.3897396247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/30.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_key_req.24529982 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 460576324 ps |
| CPU time | 11.51 seconds |
| Started | Oct 12 05:40:28 PM UTC 24 |
| Finished | Oct 12 05:40:41 PM UTC 24 |
| Peak memory | 258952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24529982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.24529982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_esc.2341725978 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 558183698 ps |
| CPU time | 7.31 seconds |
| Started | Oct 12 05:40:28 PM UTC 24 |
| Finished | Oct 12 05:40:36 PM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341725978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.2341725978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_req.595277220 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 554246485 ps |
| CPU time | 11.08 seconds |
| Started | Oct 12 05:40:25 PM UTC 24 |
| Finished | Oct 12 05:40:37 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595277220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.595277220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_regwen.3733530456 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 349921626 ps |
| CPU time | 8.6 seconds |
| Started | Oct 12 05:40:30 PM UTC 24 |
| Finished | Oct 12 05:40:40 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733530456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.3733530456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/30.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_smoke.1377326911 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 191663818 ps |
| CPU time | 4.9 seconds |
| Started | Oct 12 05:40:25 PM UTC 24 |
| Finished | Oct 12 05:40:31 PM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377326911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.1377326911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/30.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all.3564806904 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1851901317 ps |
| CPU time | 25.59 seconds |
| Started | Oct 12 05:40:37 PM UTC 24 |
| Finished | Oct 12 05:41:04 PM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564806904 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.3564806904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.547541291 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 5613940898 ps |
| CPU time | 76.78 seconds |
| Started | Oct 12 05:40:31 PM UTC 24 |
| Finished | Oct 12 05:41:49 PM UTC 24 |
| Peak memory | 269648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=547541291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.547541291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_test_access.3477092957 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 251888949 ps |
| CPU time | 4.95 seconds |
| Started | Oct 12 05:40:30 PM UTC 24 |
| Finished | Oct 12 05:40:36 PM UTC 24 |
| Peak memory | 252848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477092957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.3477092957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/30.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_alert_test.92095782 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 44886663 ps |
| CPU time | 2.41 seconds |
| Started | Oct 12 05:40:43 PM UTC 24 |
| Finished | Oct 12 05:40:46 PM UTC 24 |
| Peak memory | 252460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92095782 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.92095782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/31.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_check_fail.3215098763 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 956462702 ps |
| CPU time | 12.71 seconds |
| Started | Oct 12 05:40:38 PM UTC 24 |
| Finished | Oct 12 05:40:51 PM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215098763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.3215098763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/31.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_errs.1593706637 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 1825702594 ps |
| CPU time | 39.06 seconds |
| Started | Oct 12 05:40:38 PM UTC 24 |
| Finished | Oct 12 05:41:18 PM UTC 24 |
| Peak memory | 264912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593706637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.1593706637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/31.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_lock.235820280 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2487331482 ps |
| CPU time | 42.7 seconds |
| Started | Oct 12 05:40:37 PM UTC 24 |
| Finished | Oct 12 05:41:22 PM UTC 24 |
| Peak memory | 254924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235820280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.235820280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/31.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_init_fail.3176667271 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 170946650 ps |
| CPU time | 4.75 seconds |
| Started | Oct 12 05:40:37 PM UTC 24 |
| Finished | Oct 12 05:40:43 PM UTC 24 |
| Peak memory | 253044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176667271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.3176667271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/31.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_macro_errs.236604980 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 999819213 ps |
| CPU time | 25.31 seconds |
| Started | Oct 12 05:40:38 PM UTC 24 |
| Finished | Oct 12 05:41:04 PM UTC 24 |
| Peak memory | 255056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236604980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.236604980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/31.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_key_req.3334124505 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 1805274337 ps |
| CPU time | 21.33 seconds |
| Started | Oct 12 05:40:38 PM UTC 24 |
| Finished | Oct 12 05:41:00 PM UTC 24 |
| Peak memory | 254768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334124505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.3334124505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_esc.1886039839 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 415427377 ps |
| CPU time | 7.1 seconds |
| Started | Oct 12 05:40:37 PM UTC 24 |
| Finished | Oct 12 05:40:46 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886039839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.1886039839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_req.2528824208 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 405564955 ps |
| CPU time | 16.44 seconds |
| Started | Oct 12 05:40:37 PM UTC 24 |
| Finished | Oct 12 05:40:55 PM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528824208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.2528824208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_smoke.3944652097 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 8873601939 ps |
| CPU time | 15.76 seconds |
| Started | Oct 12 05:40:37 PM UTC 24 |
| Finished | Oct 12 05:40:54 PM UTC 24 |
| Peak memory | 252856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944652097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.3944652097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/31.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_test_access.1227583390 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 1080921809 ps |
| CPU time | 22.57 seconds |
| Started | Oct 12 05:40:38 PM UTC 24 |
| Finished | Oct 12 05:41:02 PM UTC 24 |
| Peak memory | 253104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227583390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.1227583390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/31.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_alert_test.2613739077 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 750281169 ps |
| CPU time | 4.27 seconds |
| Started | Oct 12 05:40:48 PM UTC 24 |
| Finished | Oct 12 05:40:54 PM UTC 24 |
| Peak memory | 252388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613739077 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.2613739077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/32.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_check_fail.3306991083 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 3566387298 ps |
| CPU time | 27.62 seconds |
| Started | Oct 12 05:40:43 PM UTC 24 |
| Finished | Oct 12 05:41:12 PM UTC 24 |
| Peak memory | 254892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306991083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.3306991083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/32.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_errs.1025254787 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 309254097 ps |
| CPU time | 17.58 seconds |
| Started | Oct 12 05:40:43 PM UTC 24 |
| Finished | Oct 12 05:41:02 PM UTC 24 |
| Peak memory | 252796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025254787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.1025254787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/32.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_lock.2285555835 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 5016389346 ps |
| CPU time | 12.99 seconds |
| Started | Oct 12 05:40:43 PM UTC 24 |
| Finished | Oct 12 05:40:57 PM UTC 24 |
| Peak memory | 254764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285555835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.2285555835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/32.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_macro_errs.1317083265 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 330434163 ps |
| CPU time | 7.93 seconds |
| Started | Oct 12 05:40:48 PM UTC 24 |
| Finished | Oct 12 05:40:57 PM UTC 24 |
| Peak memory | 258664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317083265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.1317083265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/32.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_key_req.3698422258 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 1056470827 ps |
| CPU time | 12.69 seconds |
| Started | Oct 12 05:40:48 PM UTC 24 |
| Finished | Oct 12 05:41:02 PM UTC 24 |
| Peak memory | 252740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698422258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.3698422258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_esc.3319056213 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 376786945 ps |
| CPU time | 5.42 seconds |
| Started | Oct 12 05:40:43 PM UTC 24 |
| Finished | Oct 12 05:40:49 PM UTC 24 |
| Peak memory | 252248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319056213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.3319056213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_req.1454784718 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 12397630756 ps |
| CPU time | 31.34 seconds |
| Started | Oct 12 05:40:43 PM UTC 24 |
| Finished | Oct 12 05:41:15 PM UTC 24 |
| Peak memory | 259224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454784718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.1454784718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_regwen.1824801378 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 1052657340 ps |
| CPU time | 9.67 seconds |
| Started | Oct 12 05:40:48 PM UTC 24 |
| Finished | Oct 12 05:40:59 PM UTC 24 |
| Peak memory | 258852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824801378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.1824801378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/32.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_smoke.3222789448 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 530680116 ps |
| CPU time | 6.91 seconds |
| Started | Oct 12 05:40:43 PM UTC 24 |
| Finished | Oct 12 05:40:51 PM UTC 24 |
| Peak memory | 252792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222789448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.3222789448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/32.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.400769954 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4054958605 ps |
| CPU time | 27.83 seconds |
| Started | Oct 12 05:40:48 PM UTC 24 |
| Finished | Oct 12 05:41:17 PM UTC 24 |
| Peak memory | 259084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=400769954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.400769954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_test_access.2532488923 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 2799697933 ps |
| CPU time | 12.07 seconds |
| Started | Oct 12 05:40:48 PM UTC 24 |
| Finished | Oct 12 05:41:01 PM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532488923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.2532488923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/32.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_alert_test.2175624851 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 726170062 ps |
| CPU time | 2.61 seconds |
| Started | Oct 12 05:40:56 PM UTC 24 |
| Finished | Oct 12 05:40:59 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175624851 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.2175624851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/33.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_check_fail.2111726356 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 314788718 ps |
| CPU time | 8.59 seconds |
| Started | Oct 12 05:40:53 PM UTC 24 |
| Finished | Oct 12 05:41:03 PM UTC 24 |
| Peak memory | 258924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111726356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.2111726356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/33.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_errs.3212370575 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 1329784334 ps |
| CPU time | 32.55 seconds |
| Started | Oct 12 05:40:53 PM UTC 24 |
| Finished | Oct 12 05:41:27 PM UTC 24 |
| Peak memory | 258992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212370575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.3212370575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/33.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_lock.3760609267 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 1944875293 ps |
| CPU time | 5.51 seconds |
| Started | Oct 12 05:40:53 PM UTC 24 |
| Finished | Oct 12 05:41:00 PM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760609267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.3760609267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/33.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_init_fail.3633852940 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 200878181 ps |
| CPU time | 4.44 seconds |
| Started | Oct 12 05:40:53 PM UTC 24 |
| Finished | Oct 12 05:40:59 PM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633852940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.3633852940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/33.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_macro_errs.2071984811 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 579617525 ps |
| CPU time | 9.5 seconds |
| Started | Oct 12 05:40:53 PM UTC 24 |
| Finished | Oct 12 05:41:04 PM UTC 24 |
| Peak memory | 252792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071984811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.2071984811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/33.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_key_req.677375719 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 1674113746 ps |
| CPU time | 23.33 seconds |
| Started | Oct 12 05:40:54 PM UTC 24 |
| Finished | Oct 12 05:41:18 PM UTC 24 |
| Peak memory | 258920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677375719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.677375719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_esc.713345147 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 125183038 ps |
| CPU time | 4 seconds |
| Started | Oct 12 05:40:53 PM UTC 24 |
| Finished | Oct 12 05:40:58 PM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713345147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.713345147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_req.3159353386 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 3885050848 ps |
| CPU time | 10.72 seconds |
| Started | Oct 12 05:40:53 PM UTC 24 |
| Finished | Oct 12 05:41:05 PM UTC 24 |
| Peak memory | 252892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159353386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.3159353386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_regwen.2301370707 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 89227326 ps |
| CPU time | 4.46 seconds |
| Started | Oct 12 05:40:54 PM UTC 24 |
| Finished | Oct 12 05:40:59 PM UTC 24 |
| Peak memory | 252676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301370707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.2301370707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/33.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_smoke.2271358752 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 453450154 ps |
| CPU time | 7.15 seconds |
| Started | Oct 12 05:40:48 PM UTC 24 |
| Finished | Oct 12 05:40:57 PM UTC 24 |
| Peak memory | 258920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271358752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.2271358752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/33.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all.188249784 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 52374749768 ps |
| CPU time | 92.29 seconds |
| Started | Oct 12 05:40:56 PM UTC 24 |
| Finished | Oct 12 05:42:30 PM UTC 24 |
| Peak memory | 269292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188249784 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all.188249784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_test_access.1054253523 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 580106019 ps |
| CPU time | 11.04 seconds |
| Started | Oct 12 05:40:55 PM UTC 24 |
| Finished | Oct 12 05:41:08 PM UTC 24 |
| Peak memory | 253036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054253523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.1054253523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/33.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_alert_test.4288286781 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 115411952 ps |
| CPU time | 2.61 seconds |
| Started | Oct 12 05:41:02 PM UTC 24 |
| Finished | Oct 12 05:41:05 PM UTC 24 |
| Peak memory | 252808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288286781 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.4288286781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/34.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_check_fail.1213915034 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1020012959 ps |
| CPU time | 16.96 seconds |
| Started | Oct 12 05:40:59 PM UTC 24 |
| Finished | Oct 12 05:41:17 PM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213915034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.1213915034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/34.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_errs.3589054205 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 206389368 ps |
| CPU time | 10.02 seconds |
| Started | Oct 12 05:40:59 PM UTC 24 |
| Finished | Oct 12 05:41:10 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589054205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.3589054205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/34.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_lock.599948629 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 5355501035 ps |
| CPU time | 24.31 seconds |
| Started | Oct 12 05:40:59 PM UTC 24 |
| Finished | Oct 12 05:41:25 PM UTC 24 |
| Peak memory | 254920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599948629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.599948629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/34.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_init_fail.1636830613 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1643880713 ps |
| CPU time | 5.18 seconds |
| Started | Oct 12 05:40:59 PM UTC 24 |
| Finished | Oct 12 05:41:05 PM UTC 24 |
| Peak memory | 252788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636830613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.1636830613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/34.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_macro_errs.4094198108 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 2886170133 ps |
| CPU time | 18.16 seconds |
| Started | Oct 12 05:41:01 PM UTC 24 |
| Finished | Oct 12 05:41:20 PM UTC 24 |
| Peak memory | 254932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094198108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.4094198108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/34.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_key_req.900935903 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 5317047885 ps |
| CPU time | 17.6 seconds |
| Started | Oct 12 05:41:01 PM UTC 24 |
| Finished | Oct 12 05:41:20 PM UTC 24 |
| Peak memory | 258812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900935903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.900935903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_esc.1982670586 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 336801745 ps |
| CPU time | 6.05 seconds |
| Started | Oct 12 05:40:59 PM UTC 24 |
| Finished | Oct 12 05:41:06 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982670586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.1982670586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_req.1296646284 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 754008088 ps |
| CPU time | 21.29 seconds |
| Started | Oct 12 05:40:59 PM UTC 24 |
| Finished | Oct 12 05:41:22 PM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296646284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.1296646284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_regwen.258905548 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 172195562 ps |
| CPU time | 6.83 seconds |
| Started | Oct 12 05:41:01 PM UTC 24 |
| Finished | Oct 12 05:41:09 PM UTC 24 |
| Peak memory | 252740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258905548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.258905548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/34.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_smoke.2409801023 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 910478076 ps |
| CPU time | 5.54 seconds |
| Started | Oct 12 05:40:56 PM UTC 24 |
| Finished | Oct 12 05:41:02 PM UTC 24 |
| Peak memory | 253112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409801023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.2409801023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/34.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all.3862734548 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 4747476948 ps |
| CPU time | 88.64 seconds |
| Started | Oct 12 05:41:01 PM UTC 24 |
| Finished | Oct 12 05:42:32 PM UTC 24 |
| Peak memory | 269352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862734548 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.3862734548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.1202722081 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 3009169474 ps |
| CPU time | 59.48 seconds |
| Started | Oct 12 05:41:01 PM UTC 24 |
| Finished | Oct 12 05:42:02 PM UTC 24 |
| Peak memory | 259140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1202722081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 34.otp_ctrl_stress_all_with_rand_reset.1202722081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_test_access.409163043 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 10206289198 ps |
| CPU time | 23.94 seconds |
| Started | Oct 12 05:41:01 PM UTC 24 |
| Finished | Oct 12 05:41:26 PM UTC 24 |
| Peak memory | 254992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409163043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.409163043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/34.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_alert_test.1805810438 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 50011545 ps |
| CPU time | 1.99 seconds |
| Started | Oct 12 05:41:09 PM UTC 24 |
| Finished | Oct 12 05:41:12 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805810438 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.1805810438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/35.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_check_fail.1995949366 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 323371988 ps |
| CPU time | 6.98 seconds |
| Started | Oct 12 05:41:05 PM UTC 24 |
| Finished | Oct 12 05:41:13 PM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995949366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.1995949366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/35.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_errs.4114312843 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 16033166985 ps |
| CPU time | 34.23 seconds |
| Started | Oct 12 05:41:05 PM UTC 24 |
| Finished | Oct 12 05:41:41 PM UTC 24 |
| Peak memory | 258896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114312843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.4114312843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/35.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_lock.3468233221 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 2218858957 ps |
| CPU time | 21.96 seconds |
| Started | Oct 12 05:41:05 PM UTC 24 |
| Finished | Oct 12 05:41:28 PM UTC 24 |
| Peak memory | 254992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468233221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.3468233221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/35.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_init_fail.3854838125 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 389555586 ps |
| CPU time | 4.88 seconds |
| Started | Oct 12 05:41:05 PM UTC 24 |
| Finished | Oct 12 05:41:11 PM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854838125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.3854838125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/35.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_macro_errs.1842787022 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 5120866234 ps |
| CPU time | 34.12 seconds |
| Started | Oct 12 05:41:05 PM UTC 24 |
| Finished | Oct 12 05:41:41 PM UTC 24 |
| Peak memory | 258932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842787022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.1842787022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/35.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_key_req.1876974466 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 15794750025 ps |
| CPU time | 39.53 seconds |
| Started | Oct 12 05:41:09 PM UTC 24 |
| Finished | Oct 12 05:41:50 PM UTC 24 |
| Peak memory | 255088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876974466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1876974466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_esc.1433792341 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 1056423802 ps |
| CPU time | 9.57 seconds |
| Started | Oct 12 05:41:05 PM UTC 24 |
| Finished | Oct 12 05:41:16 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433792341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.1433792341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_req.4161074770 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 926477587 ps |
| CPU time | 14.99 seconds |
| Started | Oct 12 05:41:05 PM UTC 24 |
| Finished | Oct 12 05:41:21 PM UTC 24 |
| Peak memory | 259148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161074770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.4161074770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_regwen.1001560706 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 164967097 ps |
| CPU time | 6.97 seconds |
| Started | Oct 12 05:41:09 PM UTC 24 |
| Finished | Oct 12 05:41:17 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001560706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.1001560706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/35.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_smoke.3354465966 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 487387419 ps |
| CPU time | 9.2 seconds |
| Started | Oct 12 05:41:05 PM UTC 24 |
| Finished | Oct 12 05:41:15 PM UTC 24 |
| Peak memory | 252972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354465966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.3354465966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/35.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_test_access.2228113286 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 12876047188 ps |
| CPU time | 42.39 seconds |
| Started | Oct 12 05:41:09 PM UTC 24 |
| Finished | Oct 12 05:41:53 PM UTC 24 |
| Peak memory | 259308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228113286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.2228113286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/35.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_alert_test.4293925097 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 74575644 ps |
| CPU time | 2.75 seconds |
| Started | Oct 12 05:41:19 PM UTC 24 |
| Finished | Oct 12 05:41:22 PM UTC 24 |
| Peak memory | 252824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293925097 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.4293925097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/36.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_check_fail.2846248439 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1380249950 ps |
| CPU time | 35.98 seconds |
| Started | Oct 12 05:41:13 PM UTC 24 |
| Finished | Oct 12 05:41:51 PM UTC 24 |
| Peak memory | 258948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846248439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.2846248439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/36.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_errs.273851458 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 305065453 ps |
| CPU time | 15.13 seconds |
| Started | Oct 12 05:41:13 PM UTC 24 |
| Finished | Oct 12 05:41:30 PM UTC 24 |
| Peak memory | 252880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273851458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.273851458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/36.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_lock.3493730877 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 7978209983 ps |
| CPU time | 20.08 seconds |
| Started | Oct 12 05:41:13 PM UTC 24 |
| Finished | Oct 12 05:41:35 PM UTC 24 |
| Peak memory | 253200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493730877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.3493730877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/36.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_init_fail.853906153 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 159293362 ps |
| CPU time | 4.95 seconds |
| Started | Oct 12 05:41:09 PM UTC 24 |
| Finished | Oct 12 05:41:15 PM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853906153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.853906153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/36.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_macro_errs.2252310390 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 2240165662 ps |
| CPU time | 22.71 seconds |
| Started | Oct 12 05:41:13 PM UTC 24 |
| Finished | Oct 12 05:41:38 PM UTC 24 |
| Peak memory | 256876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252310390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.2252310390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/36.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_key_req.1484743431 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 496821962 ps |
| CPU time | 14.62 seconds |
| Started | Oct 12 05:41:13 PM UTC 24 |
| Finished | Oct 12 05:41:30 PM UTC 24 |
| Peak memory | 252948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484743431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.1484743431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_esc.2138700664 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 572086368 ps |
| CPU time | 19.51 seconds |
| Started | Oct 12 05:41:09 PM UTC 24 |
| Finished | Oct 12 05:41:30 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138700664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.2138700664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_req.1162480422 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 666810175 ps |
| CPU time | 12.46 seconds |
| Started | Oct 12 05:41:09 PM UTC 24 |
| Finished | Oct 12 05:41:23 PM UTC 24 |
| Peak memory | 254796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162480422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.1162480422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_regwen.2850706164 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 1392457006 ps |
| CPU time | 6.1 seconds |
| Started | Oct 12 05:41:14 PM UTC 24 |
| Finished | Oct 12 05:41:21 PM UTC 24 |
| Peak memory | 259144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850706164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.2850706164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/36.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_smoke.2712969547 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 272354948 ps |
| CPU time | 8.33 seconds |
| Started | Oct 12 05:41:09 PM UTC 24 |
| Finished | Oct 12 05:41:19 PM UTC 24 |
| Peak memory | 252972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712969547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.2712969547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/36.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all.3117810732 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 24161583078 ps |
| CPU time | 186.77 seconds |
| Started | Oct 12 05:41:15 PM UTC 24 |
| Finished | Oct 12 05:44:25 PM UTC 24 |
| Peak memory | 269272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117810732 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.3117810732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_test_access.4224082454 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 481940984 ps |
| CPU time | 9.95 seconds |
| Started | Oct 12 05:41:14 PM UTC 24 |
| Finished | Oct 12 05:41:25 PM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224082454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.4224082454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/36.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_alert_test.4148160883 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 42341132 ps |
| CPU time | 1.98 seconds |
| Started | Oct 12 05:41:24 PM UTC 24 |
| Finished | Oct 12 05:41:27 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148160883 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.4148160883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/37.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_check_fail.3484341789 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 998595763 ps |
| CPU time | 24.83 seconds |
| Started | Oct 12 05:41:19 PM UTC 24 |
| Finished | Oct 12 05:41:45 PM UTC 24 |
| Peak memory | 255144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484341789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.3484341789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/37.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_errs.3771658648 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 26300305099 ps |
| CPU time | 70.67 seconds |
| Started | Oct 12 05:41:19 PM UTC 24 |
| Finished | Oct 12 05:42:31 PM UTC 24 |
| Peak memory | 267056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771658648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.3771658648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/37.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_lock.3944324931 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 5290896597 ps |
| CPU time | 32.87 seconds |
| Started | Oct 12 05:41:19 PM UTC 24 |
| Finished | Oct 12 05:41:53 PM UTC 24 |
| Peak memory | 254896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944324931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.3944324931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/37.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_init_fail.2286799455 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 456102147 ps |
| CPU time | 4.11 seconds |
| Started | Oct 12 05:41:19 PM UTC 24 |
| Finished | Oct 12 05:41:24 PM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286799455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.2286799455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/37.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_macro_errs.2861518875 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 806690469 ps |
| CPU time | 16.51 seconds |
| Started | Oct 12 05:41:21 PM UTC 24 |
| Finished | Oct 12 05:41:39 PM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861518875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.2861518875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/37.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_key_req.571408048 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 411622828 ps |
| CPU time | 5.63 seconds |
| Started | Oct 12 05:41:21 PM UTC 24 |
| Finished | Oct 12 05:41:28 PM UTC 24 |
| Peak memory | 258896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571408048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.571408048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_esc.1345242894 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 1123208467 ps |
| CPU time | 9.54 seconds |
| Started | Oct 12 05:41:19 PM UTC 24 |
| Finished | Oct 12 05:41:30 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345242894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.1345242894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_req.3722388738 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 317174699 ps |
| CPU time | 5.25 seconds |
| Started | Oct 12 05:41:19 PM UTC 24 |
| Finished | Oct 12 05:41:25 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722388738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.3722388738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_regwen.3255459912 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 979462378 ps |
| CPU time | 12.45 seconds |
| Started | Oct 12 05:41:21 PM UTC 24 |
| Finished | Oct 12 05:41:35 PM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255459912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.3255459912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/37.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_smoke.3447982305 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 863469216 ps |
| CPU time | 10.01 seconds |
| Started | Oct 12 05:41:19 PM UTC 24 |
| Finished | Oct 12 05:41:30 PM UTC 24 |
| Peak memory | 253048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447982305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.3447982305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/37.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.2186045877 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 43978305522 ps |
| CPU time | 250.12 seconds |
| Started | Oct 12 05:41:24 PM UTC 24 |
| Finished | Oct 12 05:45:38 PM UTC 24 |
| Peak memory | 275444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186045877 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.2186045877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_test_access.1052905343 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 134552651 ps |
| CPU time | 5.31 seconds |
| Started | Oct 12 05:41:21 PM UTC 24 |
| Finished | Oct 12 05:41:27 PM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052905343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.1052905343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/37.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_alert_test.566900060 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 46617053 ps |
| CPU time | 2.44 seconds |
| Started | Oct 12 05:41:29 PM UTC 24 |
| Finished | Oct 12 05:41:33 PM UTC 24 |
| Peak memory | 252460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566900060 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.566900060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/38.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_check_fail.1974632253 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 1366000255 ps |
| CPU time | 33.57 seconds |
| Started | Oct 12 05:41:27 PM UTC 24 |
| Finished | Oct 12 05:42:02 PM UTC 24 |
| Peak memory | 258948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974632253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.1974632253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/38.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_errs.1064978675 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 2614922905 ps |
| CPU time | 38.62 seconds |
| Started | Oct 12 05:41:25 PM UTC 24 |
| Finished | Oct 12 05:42:05 PM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064978675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.1064978675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/38.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_lock.3336692881 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 1688008775 ps |
| CPU time | 14.76 seconds |
| Started | Oct 12 05:41:25 PM UTC 24 |
| Finished | Oct 12 05:41:41 PM UTC 24 |
| Peak memory | 252820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336692881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.3336692881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/38.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_init_fail.4055979445 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 413060599 ps |
| CPU time | 4.48 seconds |
| Started | Oct 12 05:41:24 PM UTC 24 |
| Finished | Oct 12 05:41:30 PM UTC 24 |
| Peak memory | 252608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055979445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.4055979445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/38.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_macro_errs.2558133763 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 408536829 ps |
| CPU time | 9.1 seconds |
| Started | Oct 12 05:41:27 PM UTC 24 |
| Finished | Oct 12 05:41:37 PM UTC 24 |
| Peak memory | 259196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558133763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.2558133763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/38.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_key_req.630733929 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 771889448 ps |
| CPU time | 17.1 seconds |
| Started | Oct 12 05:41:27 PM UTC 24 |
| Finished | Oct 12 05:41:45 PM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630733929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.630733929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_esc.2297774746 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 353525894 ps |
| CPU time | 7.84 seconds |
| Started | Oct 12 05:41:24 PM UTC 24 |
| Finished | Oct 12 05:41:33 PM UTC 24 |
| Peak memory | 252616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297774746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.2297774746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_req.3964961855 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 400728552 ps |
| CPU time | 11.7 seconds |
| Started | Oct 12 05:41:24 PM UTC 24 |
| Finished | Oct 12 05:41:37 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964961855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.3964961855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_regwen.1005370410 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 626616538 ps |
| CPU time | 5.77 seconds |
| Started | Oct 12 05:41:29 PM UTC 24 |
| Finished | Oct 12 05:41:36 PM UTC 24 |
| Peak memory | 259116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005370410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.1005370410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/38.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_smoke.3304944551 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 5632042024 ps |
| CPU time | 14.9 seconds |
| Started | Oct 12 05:41:24 PM UTC 24 |
| Finished | Oct 12 05:41:40 PM UTC 24 |
| Peak memory | 255224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304944551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.3304944551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/38.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all.2991022319 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 22680045170 ps |
| CPU time | 113.23 seconds |
| Started | Oct 12 05:41:29 PM UTC 24 |
| Finished | Oct 12 05:43:25 PM UTC 24 |
| Peak memory | 273384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991022319 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.2991022319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.3861093618 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 7862241250 ps |
| CPU time | 66.18 seconds |
| Started | Oct 12 05:41:29 PM UTC 24 |
| Finished | Oct 12 05:42:37 PM UTC 24 |
| Peak memory | 259476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3861093618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 38.otp_ctrl_stress_all_with_rand_reset.3861093618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_test_access.2208351835 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 1050892071 ps |
| CPU time | 10.73 seconds |
| Started | Oct 12 05:41:29 PM UTC 24 |
| Finished | Oct 12 05:41:41 PM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208351835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.2208351835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/38.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_alert_test.2617570570 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 686210855 ps |
| CPU time | 2.79 seconds |
| Started | Oct 12 05:41:37 PM UTC 24 |
| Finished | Oct 12 05:41:41 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617570570 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.2617570570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/39.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_check_fail.2227935118 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 976661980 ps |
| CPU time | 7.29 seconds |
| Started | Oct 12 05:41:33 PM UTC 24 |
| Finished | Oct 12 05:41:42 PM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227935118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.2227935118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_errs.761245236 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 2710448935 ps |
| CPU time | 22.65 seconds |
| Started | Oct 12 05:41:33 PM UTC 24 |
| Finished | Oct 12 05:41:57 PM UTC 24 |
| Peak memory | 252820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761245236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.761245236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/39.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_lock.4262441904 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 852183378 ps |
| CPU time | 24.62 seconds |
| Started | Oct 12 05:41:33 PM UTC 24 |
| Finished | Oct 12 05:41:59 PM UTC 24 |
| Peak memory | 254804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262441904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.4262441904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/39.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_init_fail.1386143918 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 296129040 ps |
| CPU time | 4.58 seconds |
| Started | Oct 12 05:41:33 PM UTC 24 |
| Finished | Oct 12 05:41:39 PM UTC 24 |
| Peak memory | 252788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386143918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.1386143918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/39.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_macro_errs.3877519610 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 658676558 ps |
| CPU time | 15.7 seconds |
| Started | Oct 12 05:41:33 PM UTC 24 |
| Finished | Oct 12 05:41:50 PM UTC 24 |
| Peak memory | 257148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877519610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.3877519610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/39.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_key_req.1361989172 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 763326497 ps |
| CPU time | 26.59 seconds |
| Started | Oct 12 05:41:34 PM UTC 24 |
| Finished | Oct 12 05:42:01 PM UTC 24 |
| Peak memory | 258900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361989172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.1361989172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_esc.814172731 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 6582486902 ps |
| CPU time | 18.52 seconds |
| Started | Oct 12 05:41:33 PM UTC 24 |
| Finished | Oct 12 05:41:53 PM UTC 24 |
| Peak memory | 252836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814172731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.814172731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_req.1732860113 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 1153483859 ps |
| CPU time | 17.17 seconds |
| Started | Oct 12 05:41:33 PM UTC 24 |
| Finished | Oct 12 05:41:52 PM UTC 24 |
| Peak memory | 258892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732860113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.1732860113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_regwen.654596181 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 124254025 ps |
| CPU time | 6.79 seconds |
| Started | Oct 12 05:41:34 PM UTC 24 |
| Finished | Oct 12 05:41:41 PM UTC 24 |
| Peak memory | 252604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654596181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.654596181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/39.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_smoke.2873937982 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 4450903485 ps |
| CPU time | 10.98 seconds |
| Started | Oct 12 05:41:29 PM UTC 24 |
| Finished | Oct 12 05:41:41 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873937982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.2873937982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/39.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all.3438467798 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 1344841424 ps |
| CPU time | 22.38 seconds |
| Started | Oct 12 05:41:37 PM UTC 24 |
| Finished | Oct 12 05:42:01 PM UTC 24 |
| Peak memory | 254748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438467798 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.3438467798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_test_access.820584534 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 2584636335 ps |
| CPU time | 27.39 seconds |
| Started | Oct 12 05:41:34 PM UTC 24 |
| Finished | Oct 12 05:42:02 PM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820584534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.820584534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/39.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_alert_test.2787078869 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 198307526 ps |
| CPU time | 3.1 seconds |
| Started | Oct 12 05:37:25 PM UTC 24 |
| Finished | Oct 12 05:37:30 PM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787078869 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.2787078869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_background_chks.2052803737 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 492119946 ps |
| CPU time | 14.64 seconds |
| Started | Oct 12 05:37:19 PM UTC 24 |
| Finished | Oct 12 05:37:35 PM UTC 24 |
| Peak memory | 252904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052803737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.2052803737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_errs.3640271027 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 211092736 ps |
| CPU time | 10.48 seconds |
| Started | Oct 12 05:37:21 PM UTC 24 |
| Finished | Oct 12 05:37:33 PM UTC 24 |
| Peak memory | 254720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640271027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.3640271027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_lock.2258641901 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 726319299 ps |
| CPU time | 7.88 seconds |
| Started | Oct 12 05:37:21 PM UTC 24 |
| Finished | Oct 12 05:37:30 PM UTC 24 |
| Peak memory | 252656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258641901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.2258641901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_key_req.1179457116 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1616116563 ps |
| CPU time | 9.38 seconds |
| Started | Oct 12 05:37:25 PM UTC 24 |
| Finished | Oct 12 05:37:36 PM UTC 24 |
| Peak memory | 253008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179457116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.1179457116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_esc.956148749 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 305404384 ps |
| CPU time | 6.88 seconds |
| Started | Oct 12 05:37:21 PM UTC 24 |
| Finished | Oct 12 05:37:29 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956148749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.956148749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_req.1005526156 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 284098240 ps |
| CPU time | 7.44 seconds |
| Started | Oct 12 05:37:19 PM UTC 24 |
| Finished | Oct 12 05:37:28 PM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005526156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.1005526156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_smoke.3638192818 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 723438821 ps |
| CPU time | 10.84 seconds |
| Started | Oct 12 05:37:19 PM UTC 24 |
| Finished | Oct 12 05:37:31 PM UTC 24 |
| Peak memory | 252796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638192818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.3638192818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/4.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_alert_test.3813755233 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 220202767 ps |
| CPU time | 2.07 seconds |
| Started | Oct 12 05:41:45 PM UTC 24 |
| Finished | Oct 12 05:41:48 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813755233 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.3813755233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/40.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_check_fail.4249203783 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 1013167127 ps |
| CPU time | 13.9 seconds |
| Started | Oct 12 05:41:44 PM UTC 24 |
| Finished | Oct 12 05:42:00 PM UTC 24 |
| Peak memory | 254828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249203783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.4249203783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/40.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_errs.1137184409 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 729018798 ps |
| CPU time | 19.69 seconds |
| Started | Oct 12 05:41:44 PM UTC 24 |
| Finished | Oct 12 05:42:05 PM UTC 24 |
| Peak memory | 252788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137184409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.1137184409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/40.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_lock.163903477 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 826028815 ps |
| CPU time | 7.22 seconds |
| Started | Oct 12 05:41:44 PM UTC 24 |
| Finished | Oct 12 05:41:53 PM UTC 24 |
| Peak memory | 252944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163903477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.163903477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/40.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_init_fail.763361063 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 440613089 ps |
| CPU time | 4.89 seconds |
| Started | Oct 12 05:41:37 PM UTC 24 |
| Finished | Oct 12 05:41:43 PM UTC 24 |
| Peak memory | 253016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763361063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.763361063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/40.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_macro_errs.3599411706 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 1406707992 ps |
| CPU time | 19.39 seconds |
| Started | Oct 12 05:41:44 PM UTC 24 |
| Finished | Oct 12 05:42:05 PM UTC 24 |
| Peak memory | 254768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599411706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.3599411706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/40.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_key_req.4115739965 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 3517592184 ps |
| CPU time | 33.85 seconds |
| Started | Oct 12 05:41:45 PM UTC 24 |
| Finished | Oct 12 05:42:20 PM UTC 24 |
| Peak memory | 259248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115739965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.4115739965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_esc.4117079187 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 135538702 ps |
| CPU time | 2.2 seconds |
| Started | Oct 12 05:41:44 PM UTC 24 |
| Finished | Oct 12 05:41:48 PM UTC 24 |
| Peak memory | 252616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117079187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.4117079187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_req.2724567673 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 300641562 ps |
| CPU time | 7.88 seconds |
| Started | Oct 12 05:41:44 PM UTC 24 |
| Finished | Oct 12 05:41:53 PM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724567673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.2724567673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_regwen.3790897653 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 3430417971 ps |
| CPU time | 10.93 seconds |
| Started | Oct 12 05:41:45 PM UTC 24 |
| Finished | Oct 12 05:41:57 PM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790897653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.3790897653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/40.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_smoke.2708984289 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 292194782 ps |
| CPU time | 8.18 seconds |
| Started | Oct 12 05:41:37 PM UTC 24 |
| Finished | Oct 12 05:41:46 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708984289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.2708984289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/40.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all.3363707645 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 59405803351 ps |
| CPU time | 335.51 seconds |
| Started | Oct 12 05:41:45 PM UTC 24 |
| Finished | Oct 12 05:47:25 PM UTC 24 |
| Peak memory | 269228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363707645 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.3363707645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_test_access.2947851235 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 455097377 ps |
| CPU time | 15.47 seconds |
| Started | Oct 12 05:41:45 PM UTC 24 |
| Finished | Oct 12 05:42:01 PM UTC 24 |
| Peak memory | 254768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947851235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.2947851235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/40.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_alert_test.747867780 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 56368741 ps |
| CPU time | 2.78 seconds |
| Started | Oct 12 05:41:53 PM UTC 24 |
| Finished | Oct 12 05:41:57 PM UTC 24 |
| Peak memory | 252456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747867780 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.747867780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/41.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_check_fail.1007273744 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 1196297479 ps |
| CPU time | 8.97 seconds |
| Started | Oct 12 05:41:48 PM UTC 24 |
| Finished | Oct 12 05:41:58 PM UTC 24 |
| Peak memory | 258924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007273744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.1007273744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_errs.4112240378 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 269889608 ps |
| CPU time | 13.44 seconds |
| Started | Oct 12 05:41:47 PM UTC 24 |
| Finished | Oct 12 05:42:02 PM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112240378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.4112240378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/41.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_lock.2597321225 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 9021518895 ps |
| CPU time | 23.06 seconds |
| Started | Oct 12 05:41:45 PM UTC 24 |
| Finished | Oct 12 05:42:09 PM UTC 24 |
| Peak memory | 254868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597321225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.2597321225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/41.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_init_fail.1537067778 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 105857004 ps |
| CPU time | 4.32 seconds |
| Started | Oct 12 05:41:45 PM UTC 24 |
| Finished | Oct 12 05:41:50 PM UTC 24 |
| Peak memory | 252980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537067778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.1537067778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/41.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_macro_errs.3578865429 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 4204924899 ps |
| CPU time | 24.22 seconds |
| Started | Oct 12 05:41:48 PM UTC 24 |
| Finished | Oct 12 05:42:13 PM UTC 24 |
| Peak memory | 252856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578865429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.3578865429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/41.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_key_req.1018194089 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 568603507 ps |
| CPU time | 20.25 seconds |
| Started | Oct 12 05:41:49 PM UTC 24 |
| Finished | Oct 12 05:42:10 PM UTC 24 |
| Peak memory | 255060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018194089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.1018194089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_esc.3543695105 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 589474312 ps |
| CPU time | 17.31 seconds |
| Started | Oct 12 05:41:45 PM UTC 24 |
| Finished | Oct 12 05:42:04 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543695105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.3543695105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_req.1033249205 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 7652606005 ps |
| CPU time | 18.13 seconds |
| Started | Oct 12 05:41:45 PM UTC 24 |
| Finished | Oct 12 05:42:04 PM UTC 24 |
| Peak memory | 253068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033249205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.1033249205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_regwen.89941544 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 3678905345 ps |
| CPU time | 8.4 seconds |
| Started | Oct 12 05:41:49 PM UTC 24 |
| Finished | Oct 12 05:41:58 PM UTC 24 |
| Peak memory | 254956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89941544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ot p_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.89941544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/41.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_smoke.1401444212 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 482204347 ps |
| CPU time | 12.8 seconds |
| Started | Oct 12 05:41:45 PM UTC 24 |
| Finished | Oct 12 05:41:59 PM UTC 24 |
| Peak memory | 252920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401444212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.1401444212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/41.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all.2311142584 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 4178831511 ps |
| CPU time | 53.35 seconds |
| Started | Oct 12 05:41:53 PM UTC 24 |
| Finished | Oct 12 05:42:48 PM UTC 24 |
| Peak memory | 258968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311142584 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.2311142584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.4142429546 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2379402324 ps |
| CPU time | 40.61 seconds |
| Started | Oct 12 05:41:50 PM UTC 24 |
| Finished | Oct 12 05:42:32 PM UTC 24 |
| Peak memory | 259092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4142429546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 41.otp_ctrl_stress_all_with_rand_reset.4142429546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_test_access.3118296270 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 2046693416 ps |
| CPU time | 18.81 seconds |
| Started | Oct 12 05:41:50 PM UTC 24 |
| Finished | Oct 12 05:42:10 PM UTC 24 |
| Peak memory | 255208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118296270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.3118296270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/41.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_alert_test.2966250063 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 154630661 ps |
| CPU time | 2.31 seconds |
| Started | Oct 12 05:42:01 PM UTC 24 |
| Finished | Oct 12 05:42:04 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966250063 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.2966250063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/42.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_check_fail.1990194071 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 644426403 ps |
| CPU time | 10.78 seconds |
| Started | Oct 12 05:41:58 PM UTC 24 |
| Finished | Oct 12 05:42:10 PM UTC 24 |
| Peak memory | 259240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990194071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.1990194071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_errs.1626145125 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 1327056215 ps |
| CPU time | 19.95 seconds |
| Started | Oct 12 05:41:58 PM UTC 24 |
| Finished | Oct 12 05:42:19 PM UTC 24 |
| Peak memory | 254848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626145125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.1626145125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/42.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_lock.351309796 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 444277741 ps |
| CPU time | 5.18 seconds |
| Started | Oct 12 05:41:58 PM UTC 24 |
| Finished | Oct 12 05:42:04 PM UTC 24 |
| Peak memory | 258960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351309796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.351309796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/42.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_init_fail.1905277645 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 587389784 ps |
| CPU time | 5.33 seconds |
| Started | Oct 12 05:41:53 PM UTC 24 |
| Finished | Oct 12 05:41:59 PM UTC 24 |
| Peak memory | 254768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905277645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.1905277645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/42.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_macro_errs.3472483574 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 1050468536 ps |
| CPU time | 12.65 seconds |
| Started | Oct 12 05:41:58 PM UTC 24 |
| Finished | Oct 12 05:42:12 PM UTC 24 |
| Peak memory | 254892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472483574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.3472483574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/42.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_key_req.3866654661 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 28464224902 ps |
| CPU time | 51.17 seconds |
| Started | Oct 12 05:41:58 PM UTC 24 |
| Finished | Oct 12 05:42:51 PM UTC 24 |
| Peak memory | 254892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866654661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.3866654661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_esc.2758286295 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 292857343 ps |
| CPU time | 7.76 seconds |
| Started | Oct 12 05:41:58 PM UTC 24 |
| Finished | Oct 12 05:42:07 PM UTC 24 |
| Peak memory | 252740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758286295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.2758286295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_req.1529294879 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 900063141 ps |
| CPU time | 9.24 seconds |
| Started | Oct 12 05:41:53 PM UTC 24 |
| Finished | Oct 12 05:42:03 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529294879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.1529294879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_regwen.1887266728 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 533877059 ps |
| CPU time | 6.3 seconds |
| Started | Oct 12 05:41:58 PM UTC 24 |
| Finished | Oct 12 05:42:06 PM UTC 24 |
| Peak memory | 258732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887266728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.1887266728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/42.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_smoke.1023534172 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 353376039 ps |
| CPU time | 6.41 seconds |
| Started | Oct 12 05:41:53 PM UTC 24 |
| Finished | Oct 12 05:42:00 PM UTC 24 |
| Peak memory | 252984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023534172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.1023534172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/42.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all.477712068 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 5822928497 ps |
| CPU time | 38.27 seconds |
| Started | Oct 12 05:42:01 PM UTC 24 |
| Finished | Oct 12 05:42:41 PM UTC 24 |
| Peak memory | 254844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477712068 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.477712068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.3570278897 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1377513716 ps |
| CPU time | 54.29 seconds |
| Started | Oct 12 05:42:01 PM UTC 24 |
| Finished | Oct 12 05:42:57 PM UTC 24 |
| Peak memory | 259016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3570278897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.otp_ctrl_stress_all_with_rand_reset.3570278897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_test_access.249459084 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 482936662 ps |
| CPU time | 17.99 seconds |
| Started | Oct 12 05:42:01 PM UTC 24 |
| Finished | Oct 12 05:42:20 PM UTC 24 |
| Peak memory | 254912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249459084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.249459084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/42.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_alert_test.4109662194 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 755230411 ps |
| CPU time | 2.79 seconds |
| Started | Oct 12 05:42:07 PM UTC 24 |
| Finished | Oct 12 05:42:11 PM UTC 24 |
| Peak memory | 252552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109662194 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.4109662194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/43.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_check_fail.2903221246 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 2158777953 ps |
| CPU time | 24.63 seconds |
| Started | Oct 12 05:42:02 PM UTC 24 |
| Finished | Oct 12 05:42:27 PM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903221246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.2903221246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/43.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_errs.2961653673 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 2218657856 ps |
| CPU time | 25.31 seconds |
| Started | Oct 12 05:42:01 PM UTC 24 |
| Finished | Oct 12 05:42:28 PM UTC 24 |
| Peak memory | 252860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961653673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.2961653673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/43.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_lock.1448522403 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2350179921 ps |
| CPU time | 15.81 seconds |
| Started | Oct 12 05:42:01 PM UTC 24 |
| Finished | Oct 12 05:42:18 PM UTC 24 |
| Peak memory | 259280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448522403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.1448522403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/43.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_init_fail.3993065415 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 135190080 ps |
| CPU time | 4.07 seconds |
| Started | Oct 12 05:42:01 PM UTC 24 |
| Finished | Oct 12 05:42:06 PM UTC 24 |
| Peak memory | 255028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993065415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.3993065415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/43.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_macro_errs.2608315973 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 680705347 ps |
| CPU time | 13.65 seconds |
| Started | Oct 12 05:42:07 PM UTC 24 |
| Finished | Oct 12 05:42:21 PM UTC 24 |
| Peak memory | 258988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608315973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.2608315973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/43.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_key_req.4034792039 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 1582500819 ps |
| CPU time | 30.99 seconds |
| Started | Oct 12 05:42:07 PM UTC 24 |
| Finished | Oct 12 05:42:39 PM UTC 24 |
| Peak memory | 259124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034792039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.4034792039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_esc.3183349908 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 991312410 ps |
| CPU time | 15.31 seconds |
| Started | Oct 12 05:42:01 PM UTC 24 |
| Finished | Oct 12 05:42:18 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183349908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.3183349908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_req.1160181702 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 10507663821 ps |
| CPU time | 19.91 seconds |
| Started | Oct 12 05:42:01 PM UTC 24 |
| Finished | Oct 12 05:42:22 PM UTC 24 |
| Peak memory | 258956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160181702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.1160181702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_regwen.3791152574 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 2658999214 ps |
| CPU time | 12.44 seconds |
| Started | Oct 12 05:42:07 PM UTC 24 |
| Finished | Oct 12 05:42:20 PM UTC 24 |
| Peak memory | 253092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791152574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.3791152574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/43.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_smoke.3909443677 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 403649082 ps |
| CPU time | 9.53 seconds |
| Started | Oct 12 05:42:01 PM UTC 24 |
| Finished | Oct 12 05:42:12 PM UTC 24 |
| Peak memory | 252792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909443677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.3909443677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/43.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.3761343874 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 13758281034 ps |
| CPU time | 89.3 seconds |
| Started | Oct 12 05:42:07 PM UTC 24 |
| Finished | Oct 12 05:43:38 PM UTC 24 |
| Peak memory | 257116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761343874 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.3761343874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.2000620800 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 5958055855 ps |
| CPU time | 83.28 seconds |
| Started | Oct 12 05:42:07 PM UTC 24 |
| Finished | Oct 12 05:43:32 PM UTC 24 |
| Peak memory | 271384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2000620800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 43.otp_ctrl_stress_all_with_rand_reset.2000620800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_test_access.3245842666 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 8029734616 ps |
| CPU time | 20.53 seconds |
| Started | Oct 12 05:42:07 PM UTC 24 |
| Finished | Oct 12 05:42:28 PM UTC 24 |
| Peak memory | 252908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245842666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.3245842666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/43.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_alert_test.1220665861 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 909295211 ps |
| CPU time | 3.47 seconds |
| Started | Oct 12 05:42:11 PM UTC 24 |
| Finished | Oct 12 05:42:16 PM UTC 24 |
| Peak memory | 252532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220665861 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.1220665861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/44.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_check_fail.2307958734 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 2141937330 ps |
| CPU time | 19.35 seconds |
| Started | Oct 12 05:42:11 PM UTC 24 |
| Finished | Oct 12 05:42:31 PM UTC 24 |
| Peak memory | 255176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307958734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.2307958734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/44.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_errs.2925841233 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 19780052988 ps |
| CPU time | 38.65 seconds |
| Started | Oct 12 05:42:11 PM UTC 24 |
| Finished | Oct 12 05:42:51 PM UTC 24 |
| Peak memory | 258908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925841233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.2925841233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/44.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_lock.2489505026 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 3314788768 ps |
| CPU time | 24.95 seconds |
| Started | Oct 12 05:42:11 PM UTC 24 |
| Finished | Oct 12 05:42:37 PM UTC 24 |
| Peak memory | 254896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489505026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.2489505026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/44.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_init_fail.239121347 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 98548757 ps |
| CPU time | 4.35 seconds |
| Started | Oct 12 05:42:07 PM UTC 24 |
| Finished | Oct 12 05:42:12 PM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239121347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.239121347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/44.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_macro_errs.451447047 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 9370817993 ps |
| CPU time | 60.72 seconds |
| Started | Oct 12 05:42:11 PM UTC 24 |
| Finished | Oct 12 05:43:13 PM UTC 24 |
| Peak memory | 269260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451447047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.451447047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/44.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_key_req.3627910561 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 885074007 ps |
| CPU time | 19.12 seconds |
| Started | Oct 12 05:42:11 PM UTC 24 |
| Finished | Oct 12 05:42:31 PM UTC 24 |
| Peak memory | 254804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627910561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.3627910561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_esc.4040148210 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 1292955431 ps |
| CPU time | 20.42 seconds |
| Started | Oct 12 05:42:11 PM UTC 24 |
| Finished | Oct 12 05:42:32 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040148210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.4040148210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_req.3978569433 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1363125901 ps |
| CPU time | 9.49 seconds |
| Started | Oct 12 05:42:07 PM UTC 24 |
| Finished | Oct 12 05:42:18 PM UTC 24 |
| Peak memory | 253000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978569433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.3978569433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_regwen.4045358140 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 271153803 ps |
| CPU time | 8.76 seconds |
| Started | Oct 12 05:42:11 PM UTC 24 |
| Finished | Oct 12 05:42:21 PM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045358140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.4045358140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/44.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_smoke.2998339874 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 1277697702 ps |
| CPU time | 14.58 seconds |
| Started | Oct 12 05:42:07 PM UTC 24 |
| Finished | Oct 12 05:42:23 PM UTC 24 |
| Peak memory | 253112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998339874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.2998339874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/44.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.2556574632 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 43733468880 ps |
| CPU time | 103.24 seconds |
| Started | Oct 12 05:42:11 PM UTC 24 |
| Finished | Oct 12 05:43:56 PM UTC 24 |
| Peak memory | 258904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556574632 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.2556574632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_test_access.2046484738 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 2483872366 ps |
| CPU time | 16.6 seconds |
| Started | Oct 12 05:42:11 PM UTC 24 |
| Finished | Oct 12 05:42:29 PM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046484738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.2046484738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/44.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_alert_test.3870372463 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 273162415 ps |
| CPU time | 2.86 seconds |
| Started | Oct 12 05:42:23 PM UTC 24 |
| Finished | Oct 12 05:42:27 PM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870372463 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.3870372463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/45.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_check_fail.2903675943 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 1164344991 ps |
| CPU time | 18.25 seconds |
| Started | Oct 12 05:42:14 PM UTC 24 |
| Finished | Oct 12 05:42:33 PM UTC 24 |
| Peak memory | 253036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903675943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.2903675943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_errs.2149062159 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 1623421177 ps |
| CPU time | 35.33 seconds |
| Started | Oct 12 05:42:13 PM UTC 24 |
| Finished | Oct 12 05:42:50 PM UTC 24 |
| Peak memory | 258956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149062159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.2149062159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/45.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_lock.2588384202 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 1244021374 ps |
| CPU time | 14.38 seconds |
| Started | Oct 12 05:42:13 PM UTC 24 |
| Finished | Oct 12 05:42:29 PM UTC 24 |
| Peak memory | 253008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588384202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.2588384202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/45.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_init_fail.1274557232 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 221459014 ps |
| CPU time | 4.69 seconds |
| Started | Oct 12 05:42:13 PM UTC 24 |
| Finished | Oct 12 05:42:19 PM UTC 24 |
| Peak memory | 255016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274557232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.1274557232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/45.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_macro_errs.3593852187 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 982764378 ps |
| CPU time | 10.57 seconds |
| Started | Oct 12 05:42:14 PM UTC 24 |
| Finished | Oct 12 05:42:25 PM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593852187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.3593852187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/45.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_key_req.3975017741 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 750243680 ps |
| CPU time | 29.78 seconds |
| Started | Oct 12 05:42:15 PM UTC 24 |
| Finished | Oct 12 05:42:46 PM UTC 24 |
| Peak memory | 252948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975017741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.3975017741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_esc.3648380946 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 381427416 ps |
| CPU time | 7.23 seconds |
| Started | Oct 12 05:42:13 PM UTC 24 |
| Finished | Oct 12 05:42:22 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648380946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.3648380946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_req.46503379 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 836681888 ps |
| CPU time | 22.66 seconds |
| Started | Oct 12 05:42:13 PM UTC 24 |
| Finished | Oct 12 05:42:37 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46503379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.46503379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_regwen.3925360913 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 980474423 ps |
| CPU time | 11.28 seconds |
| Started | Oct 12 05:42:17 PM UTC 24 |
| Finished | Oct 12 05:42:29 PM UTC 24 |
| Peak memory | 252904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925360913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.3925360913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/45.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_smoke.3907938928 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 577970067 ps |
| CPU time | 7.11 seconds |
| Started | Oct 12 05:42:11 PM UTC 24 |
| Finished | Oct 12 05:42:19 PM UTC 24 |
| Peak memory | 258932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907938928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.3907938928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/45.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.3916218033 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 52638986627 ps |
| CPU time | 242.41 seconds |
| Started | Oct 12 05:42:20 PM UTC 24 |
| Finished | Oct 12 05:46:26 PM UTC 24 |
| Peak memory | 271272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916218033 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.3916218033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_test_access.4284965253 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 605018568 ps |
| CPU time | 20.96 seconds |
| Started | Oct 12 05:42:20 PM UTC 24 |
| Finished | Oct 12 05:42:42 PM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284965253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.4284965253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/45.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_alert_test.2608141081 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 84252699 ps |
| CPU time | 2.12 seconds |
| Started | Oct 12 05:42:30 PM UTC 24 |
| Finished | Oct 12 05:42:33 PM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608141081 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.2608141081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/46.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_check_fail.1306667482 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 5060954669 ps |
| CPU time | 29.23 seconds |
| Started | Oct 12 05:42:24 PM UTC 24 |
| Finished | Oct 12 05:42:54 PM UTC 24 |
| Peak memory | 259244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306667482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.1306667482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_errs.2553434381 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 2918513823 ps |
| CPU time | 18.65 seconds |
| Started | Oct 12 05:42:24 PM UTC 24 |
| Finished | Oct 12 05:42:43 PM UTC 24 |
| Peak memory | 252876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553434381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.2553434381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/46.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_lock.3019993616 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 1469876497 ps |
| CPU time | 19.96 seconds |
| Started | Oct 12 05:42:23 PM UTC 24 |
| Finished | Oct 12 05:42:45 PM UTC 24 |
| Peak memory | 254928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019993616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.3019993616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/46.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_init_fail.1518382639 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 524836670 ps |
| CPU time | 3.62 seconds |
| Started | Oct 12 05:42:23 PM UTC 24 |
| Finished | Oct 12 05:42:28 PM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518382639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.1518382639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/46.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_macro_errs.2367815574 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 3695735961 ps |
| CPU time | 49.12 seconds |
| Started | Oct 12 05:42:25 PM UTC 24 |
| Finished | Oct 12 05:43:16 PM UTC 24 |
| Peak memory | 258988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367815574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.2367815574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/46.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_key_req.3784451284 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 2221523907 ps |
| CPU time | 13.26 seconds |
| Started | Oct 12 05:42:25 PM UTC 24 |
| Finished | Oct 12 05:42:40 PM UTC 24 |
| Peak memory | 258928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784451284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.3784451284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_esc.70455008 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 137094963 ps |
| CPU time | 6.56 seconds |
| Started | Oct 12 05:42:23 PM UTC 24 |
| Finished | Oct 12 05:42:31 PM UTC 24 |
| Peak memory | 253000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70455008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.70455008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_req.3249022304 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2076338985 ps |
| CPU time | 13.82 seconds |
| Started | Oct 12 05:42:23 PM UTC 24 |
| Finished | Oct 12 05:42:38 PM UTC 24 |
| Peak memory | 258892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249022304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.3249022304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_regwen.2750848561 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 506983439 ps |
| CPU time | 5.92 seconds |
| Started | Oct 12 05:42:25 PM UTC 24 |
| Finished | Oct 12 05:42:32 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750848561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.2750848561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/46.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_smoke.1176065249 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 310745033 ps |
| CPU time | 8.43 seconds |
| Started | Oct 12 05:42:23 PM UTC 24 |
| Finished | Oct 12 05:42:33 PM UTC 24 |
| Peak memory | 253048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176065249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.1176065249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/46.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all.1571408695 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 25750133656 ps |
| CPU time | 170.12 seconds |
| Started | Oct 12 05:42:28 PM UTC 24 |
| Finished | Oct 12 05:45:21 PM UTC 24 |
| Peak memory | 271324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571408695 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.1571408695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.2125940378 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 1218846655 ps |
| CPU time | 36.48 seconds |
| Started | Oct 12 05:42:28 PM UTC 24 |
| Finished | Oct 12 05:43:06 PM UTC 24 |
| Peak memory | 259032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2125940378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 46.otp_ctrl_stress_all_with_rand_reset.2125940378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_test_access.3577841925 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 8868426201 ps |
| CPU time | 15.04 seconds |
| Started | Oct 12 05:42:27 PM UTC 24 |
| Finished | Oct 12 05:42:43 PM UTC 24 |
| Peak memory | 258992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577841925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.3577841925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/46.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_alert_test.175759399 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 73082206 ps |
| CPU time | 1.89 seconds |
| Started | Oct 12 05:42:42 PM UTC 24 |
| Finished | Oct 12 05:42:45 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175759399 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.175759399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/47.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_check_fail.1003478387 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 706093212 ps |
| CPU time | 13.93 seconds |
| Started | Oct 12 05:42:42 PM UTC 24 |
| Finished | Oct 12 05:42:57 PM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003478387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.1003478387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/47.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_errs.1262265880 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 602661158 ps |
| CPU time | 16.8 seconds |
| Started | Oct 12 05:42:42 PM UTC 24 |
| Finished | Oct 12 05:43:00 PM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262265880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.1262265880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/47.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_lock.283724996 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 606400845 ps |
| CPU time | 14.84 seconds |
| Started | Oct 12 05:42:42 PM UTC 24 |
| Finished | Oct 12 05:42:58 PM UTC 24 |
| Peak memory | 252816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283724996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.283724996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/47.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_init_fail.2252229173 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 246527444 ps |
| CPU time | 4.43 seconds |
| Started | Oct 12 05:42:30 PM UTC 24 |
| Finished | Oct 12 05:42:36 PM UTC 24 |
| Peak memory | 254708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252229173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.2252229173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/47.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_macro_errs.2906191879 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 766437307 ps |
| CPU time | 6.81 seconds |
| Started | Oct 12 05:42:42 PM UTC 24 |
| Finished | Oct 12 05:42:49 PM UTC 24 |
| Peak memory | 258988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906191879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.2906191879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/47.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_key_req.2401877760 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 621016067 ps |
| CPU time | 25.04 seconds |
| Started | Oct 12 05:42:42 PM UTC 24 |
| Finished | Oct 12 05:43:08 PM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401877760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.2401877760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_esc.2108259530 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 2446960711 ps |
| CPU time | 8.18 seconds |
| Started | Oct 12 05:42:30 PM UTC 24 |
| Finished | Oct 12 05:42:40 PM UTC 24 |
| Peak memory | 253000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108259530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.2108259530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_req.2999582315 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 1140299696 ps |
| CPU time | 14.25 seconds |
| Started | Oct 12 05:42:30 PM UTC 24 |
| Finished | Oct 12 05:42:46 PM UTC 24 |
| Peak memory | 252904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999582315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.2999582315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_regwen.1057684005 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3708630449 ps |
| CPU time | 9.42 seconds |
| Started | Oct 12 05:42:42 PM UTC 24 |
| Finished | Oct 12 05:42:52 PM UTC 24 |
| Peak memory | 253032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057684005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.1057684005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/47.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_smoke.2047263649 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 499423736 ps |
| CPU time | 6.66 seconds |
| Started | Oct 12 05:42:30 PM UTC 24 |
| Finished | Oct 12 05:42:38 PM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047263649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.2047263649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/47.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all.95243165 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 32892046533 ps |
| CPU time | 146.2 seconds |
| Started | Oct 12 05:42:42 PM UTC 24 |
| Finished | Oct 12 05:45:11 PM UTC 24 |
| Peak memory | 273616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95243165 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.95243165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.3737918401 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 4999050247 ps |
| CPU time | 16.11 seconds |
| Started | Oct 12 05:42:42 PM UTC 24 |
| Finished | Oct 12 05:42:59 PM UTC 24 |
| Peak memory | 259140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3737918401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 47.otp_ctrl_stress_all_with_rand_reset.3737918401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_test_access.1017174406 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 747387389 ps |
| CPU time | 16.96 seconds |
| Started | Oct 12 05:42:42 PM UTC 24 |
| Finished | Oct 12 05:43:00 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017174406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.1017174406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/47.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_alert_test.446387531 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 153983819 ps |
| CPU time | 2.83 seconds |
| Started | Oct 12 05:42:46 PM UTC 24 |
| Finished | Oct 12 05:42:50 PM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446387531 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.446387531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/48.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_check_fail.763966430 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 1496677643 ps |
| CPU time | 15.54 seconds |
| Started | Oct 12 05:42:46 PM UTC 24 |
| Finished | Oct 12 05:43:02 PM UTC 24 |
| Peak memory | 258956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763966430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.763966430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/48.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_errs.737120734 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 221755651 ps |
| CPU time | 12.75 seconds |
| Started | Oct 12 05:42:46 PM UTC 24 |
| Finished | Oct 12 05:42:59 PM UTC 24 |
| Peak memory | 252880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737120734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.737120734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/48.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_lock.2136479193 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 629267732 ps |
| CPU time | 8.3 seconds |
| Started | Oct 12 05:42:45 PM UTC 24 |
| Finished | Oct 12 05:42:55 PM UTC 24 |
| Peak memory | 253108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136479193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.2136479193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/48.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_init_fail.600962158 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 1975770196 ps |
| CPU time | 3.83 seconds |
| Started | Oct 12 05:42:42 PM UTC 24 |
| Finished | Oct 12 05:42:47 PM UTC 24 |
| Peak memory | 254736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600962158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.600962158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/48.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_macro_errs.79849195 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 261887029 ps |
| CPU time | 7.2 seconds |
| Started | Oct 12 05:42:46 PM UTC 24 |
| Finished | Oct 12 05:42:54 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79849195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.79849195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/48.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_key_req.4147540915 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 820097035 ps |
| CPU time | 18.07 seconds |
| Started | Oct 12 05:42:46 PM UTC 24 |
| Finished | Oct 12 05:43:05 PM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147540915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.4147540915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_esc.3415327995 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 520567566 ps |
| CPU time | 5.19 seconds |
| Started | Oct 12 05:42:45 PM UTC 24 |
| Finished | Oct 12 05:42:52 PM UTC 24 |
| Peak memory | 252620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415327995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.3415327995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_req.2556579172 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 1502116009 ps |
| CPU time | 14.79 seconds |
| Started | Oct 12 05:42:42 PM UTC 24 |
| Finished | Oct 12 05:42:58 PM UTC 24 |
| Peak memory | 252908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556579172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.2556579172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_regwen.1539050677 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 102977167 ps |
| CPU time | 3.41 seconds |
| Started | Oct 12 05:42:46 PM UTC 24 |
| Finished | Oct 12 05:42:50 PM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539050677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.1539050677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/48.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_smoke.1098477209 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 1291808512 ps |
| CPU time | 13.56 seconds |
| Started | Oct 12 05:42:42 PM UTC 24 |
| Finished | Oct 12 05:42:57 PM UTC 24 |
| Peak memory | 252788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098477209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.1098477209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/48.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.2235252653 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 6056658414 ps |
| CPU time | 33.76 seconds |
| Started | Oct 12 05:42:46 PM UTC 24 |
| Finished | Oct 12 05:43:21 PM UTC 24 |
| Peak memory | 257000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235252653 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.2235252653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.1404148542 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 27946540674 ps |
| CPU time | 95.48 seconds |
| Started | Oct 12 05:42:46 PM UTC 24 |
| Finished | Oct 12 05:44:23 PM UTC 24 |
| Peak memory | 259332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1404148542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.otp_ctrl_stress_all_with_rand_reset.1404148542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_test_access.4071664494 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 703581742 ps |
| CPU time | 11.57 seconds |
| Started | Oct 12 05:42:46 PM UTC 24 |
| Finished | Oct 12 05:42:59 PM UTC 24 |
| Peak memory | 258988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071664494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.4071664494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/48.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_alert_test.1878364408 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 141058247 ps |
| CPU time | 2.86 seconds |
| Started | Oct 12 05:42:50 PM UTC 24 |
| Finished | Oct 12 05:42:54 PM UTC 24 |
| Peak memory | 252836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878364408 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.1878364408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/49.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_check_fail.3714985899 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 350543571 ps |
| CPU time | 6.28 seconds |
| Started | Oct 12 05:42:46 PM UTC 24 |
| Finished | Oct 12 05:42:54 PM UTC 24 |
| Peak memory | 252836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714985899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.3714985899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/49.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_errs.1512948227 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 1428774147 ps |
| CPU time | 35.65 seconds |
| Started | Oct 12 05:42:46 PM UTC 24 |
| Finished | Oct 12 05:43:23 PM UTC 24 |
| Peak memory | 258976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512948227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.1512948227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/49.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_lock.1868211277 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 1075052628 ps |
| CPU time | 17.06 seconds |
| Started | Oct 12 05:42:46 PM UTC 24 |
| Finished | Oct 12 05:43:04 PM UTC 24 |
| Peak memory | 252800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868211277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.1868211277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/49.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_init_fail.1259678759 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1945150852 ps |
| CPU time | 5.37 seconds |
| Started | Oct 12 05:42:46 PM UTC 24 |
| Finished | Oct 12 05:42:52 PM UTC 24 |
| Peak memory | 252920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259678759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.1259678759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/49.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_macro_errs.2983860853 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 8077089914 ps |
| CPU time | 13.99 seconds |
| Started | Oct 12 05:42:49 PM UTC 24 |
| Finished | Oct 12 05:43:05 PM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983860853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.2983860853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/49.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_key_req.1678617999 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 1286881667 ps |
| CPU time | 23.57 seconds |
| Started | Oct 12 05:42:49 PM UTC 24 |
| Finished | Oct 12 05:43:14 PM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678617999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.1678617999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_esc.3954993288 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 254331084 ps |
| CPU time | 9.66 seconds |
| Started | Oct 12 05:42:46 PM UTC 24 |
| Finished | Oct 12 05:42:57 PM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954993288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.3954993288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_req.3378110845 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 855914412 ps |
| CPU time | 10.23 seconds |
| Started | Oct 12 05:42:46 PM UTC 24 |
| Finished | Oct 12 05:42:57 PM UTC 24 |
| Peak memory | 252972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378110845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.3378110845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_regwen.1335057619 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 348665123 ps |
| CPU time | 6.62 seconds |
| Started | Oct 12 05:42:49 PM UTC 24 |
| Finished | Oct 12 05:42:57 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335057619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.1335057619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/49.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_smoke.2308765584 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 279207978 ps |
| CPU time | 4.49 seconds |
| Started | Oct 12 05:42:46 PM UTC 24 |
| Finished | Oct 12 05:42:52 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308765584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.2308765584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/49.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all.68378710 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 18951405881 ps |
| CPU time | 157.75 seconds |
| Started | Oct 12 05:42:49 PM UTC 24 |
| Finished | Oct 12 05:45:30 PM UTC 24 |
| Peak memory | 259236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68378710 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.68378710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_test_access.608038171 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 3891066447 ps |
| CPU time | 49.46 seconds |
| Started | Oct 12 05:42:49 PM UTC 24 |
| Finished | Oct 12 05:43:41 PM UTC 24 |
| Peak memory | 252872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608038171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.608038171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/49.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_alert_test.1786174392 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 60313144 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 05:37:35 PM UTC 24 |
| Finished | Oct 12 05:37:37 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786174392 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.1786174392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_background_chks.2329342969 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 8143455963 ps |
| CPU time | 14.01 seconds |
| Started | Oct 12 05:37:29 PM UTC 24 |
| Finished | Oct 12 05:37:44 PM UTC 24 |
| Peak memory | 254700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329342969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.2329342969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_errs.2616869790 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 3361171909 ps |
| CPU time | 23.63 seconds |
| Started | Oct 12 05:37:29 PM UTC 24 |
| Finished | Oct 12 05:37:54 PM UTC 24 |
| Peak memory | 257328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616869790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.2616869790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_lock.2577361017 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 419810393 ps |
| CPU time | 5.31 seconds |
| Started | Oct 12 05:37:29 PM UTC 24 |
| Finished | Oct 12 05:37:36 PM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577361017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.2577361017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_init_fail.3767830325 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 146997073 ps |
| CPU time | 4.41 seconds |
| Started | Oct 12 05:37:29 PM UTC 24 |
| Finished | Oct 12 05:37:35 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767830325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.3767830325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_key_req.163243040 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 3999337185 ps |
| CPU time | 6.78 seconds |
| Started | Oct 12 05:37:34 PM UTC 24 |
| Finished | Oct 12 05:37:42 PM UTC 24 |
| Peak memory | 254884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163243040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.163243040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_esc.4026727353 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 314081180 ps |
| CPU time | 5.89 seconds |
| Started | Oct 12 05:37:29 PM UTC 24 |
| Finished | Oct 12 05:37:36 PM UTC 24 |
| Peak memory | 252620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026727353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.4026727353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_req.1784960444 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 439035378 ps |
| CPU time | 13.33 seconds |
| Started | Oct 12 05:37:29 PM UTC 24 |
| Finished | Oct 12 05:37:44 PM UTC 24 |
| Peak memory | 258892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784960444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.1784960444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_regwen.1130003107 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 2955607463 ps |
| CPU time | 8.11 seconds |
| Started | Oct 12 05:37:34 PM UTC 24 |
| Finished | Oct 12 05:37:44 PM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130003107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.1130003107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_smoke.657700858 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2043951738 ps |
| CPU time | 5.97 seconds |
| Started | Oct 12 05:37:29 PM UTC 24 |
| Finished | Oct 12 05:37:36 PM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657700858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.657700858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all.3930598288 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 967645232 ps |
| CPU time | 18.33 seconds |
| Started | Oct 12 05:37:35 PM UTC 24 |
| Finished | Oct 12 05:37:54 PM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930598288 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.3930598288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_test_access.236983017 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 889959049 ps |
| CPU time | 16.12 seconds |
| Started | Oct 12 05:37:34 PM UTC 24 |
| Finished | Oct 12 05:37:52 PM UTC 24 |
| Peak memory | 252872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236983017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.236983017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/5.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_init_fail.2171755544 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 154937355 ps |
| CPU time | 4.53 seconds |
| Started | Oct 12 05:42:51 PM UTC 24 |
| Finished | Oct 12 05:42:56 PM UTC 24 |
| Peak memory | 252920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171755544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.2171755544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/50.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_parallel_lc_esc.2417137330 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 327532190 ps |
| CPU time | 4.45 seconds |
| Started | Oct 12 05:42:55 PM UTC 24 |
| Finished | Oct 12 05:43:00 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417137330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.2417137330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/50.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.318381565 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 9483067517 ps |
| CPU time | 52.01 seconds |
| Started | Oct 12 05:42:55 PM UTC 24 |
| Finished | Oct 12 05:43:49 PM UTC 24 |
| Peak memory | 269420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=318381565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.318381565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_init_fail.1730358346 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 293949835 ps |
| CPU time | 5.76 seconds |
| Started | Oct 12 05:42:55 PM UTC 24 |
| Finished | Oct 12 05:43:02 PM UTC 24 |
| Peak memory | 254708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730358346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.1730358346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/51.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_parallel_lc_esc.2261662779 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 4475904503 ps |
| CPU time | 8.15 seconds |
| Started | Oct 12 05:42:55 PM UTC 24 |
| Finished | Oct 12 05:43:04 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261662779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.2261662779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/51.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.1806178004 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 13656705174 ps |
| CPU time | 96.98 seconds |
| Started | Oct 12 05:42:55 PM UTC 24 |
| Finished | Oct 12 05:44:34 PM UTC 24 |
| Peak memory | 269412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1806178004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 51.otp_ctrl_stress_all_with_rand_reset.1806178004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_init_fail.2811010726 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 181419349 ps |
| CPU time | 4.2 seconds |
| Started | Oct 12 05:42:55 PM UTC 24 |
| Finished | Oct 12 05:43:00 PM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811010726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.2811010726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/52.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_parallel_lc_esc.406971139 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 1620227465 ps |
| CPU time | 20.26 seconds |
| Started | Oct 12 05:42:55 PM UTC 24 |
| Finished | Oct 12 05:43:17 PM UTC 24 |
| Peak memory | 252636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406971139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.406971139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/52.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.4290136304 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 9507447947 ps |
| CPU time | 137.6 seconds |
| Started | Oct 12 05:42:55 PM UTC 24 |
| Finished | Oct 12 05:45:15 PM UTC 24 |
| Peak memory | 285796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4290136304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 52.otp_ctrl_stress_all_with_rand_reset.4290136304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_init_fail.786567841 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 131719497 ps |
| CPU time | 4.37 seconds |
| Started | Oct 12 05:42:55 PM UTC 24 |
| Finished | Oct 12 05:43:01 PM UTC 24 |
| Peak memory | 253036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786567841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.786567841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/53.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_parallel_lc_esc.777933445 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 129166183 ps |
| CPU time | 3.79 seconds |
| Started | Oct 12 05:42:56 PM UTC 24 |
| Finished | Oct 12 05:43:01 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777933445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.777933445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/53.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_init_fail.452666194 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 583888252 ps |
| CPU time | 5.59 seconds |
| Started | Oct 12 05:42:56 PM UTC 24 |
| Finished | Oct 12 05:43:03 PM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452666194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.452666194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/54.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_parallel_lc_esc.1269585670 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 292959676 ps |
| CPU time | 3.46 seconds |
| Started | Oct 12 05:42:56 PM UTC 24 |
| Finished | Oct 12 05:43:01 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269585670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.1269585670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/54.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_init_fail.2175379921 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 2044289015 ps |
| CPU time | 5.73 seconds |
| Started | Oct 12 05:42:57 PM UTC 24 |
| Finished | Oct 12 05:43:03 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175379921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.2175379921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/55.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_parallel_lc_esc.2587415458 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 365923364 ps |
| CPU time | 4.82 seconds |
| Started | Oct 12 05:42:59 PM UTC 24 |
| Finished | Oct 12 05:43:05 PM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587415458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.2587415458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/55.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.1939041621 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 37038035023 ps |
| CPU time | 113.29 seconds |
| Started | Oct 12 05:42:59 PM UTC 24 |
| Finished | Oct 12 05:44:54 PM UTC 24 |
| Peak memory | 269600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1939041621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 55.otp_ctrl_stress_all_with_rand_reset.1939041621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/55.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_init_fail.947429354 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 120274836 ps |
| CPU time | 3.89 seconds |
| Started | Oct 12 05:42:59 PM UTC 24 |
| Finished | Oct 12 05:43:04 PM UTC 24 |
| Peak memory | 255048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947429354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.947429354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/56.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_parallel_lc_esc.2374781292 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 722243629 ps |
| CPU time | 16.42 seconds |
| Started | Oct 12 05:42:59 PM UTC 24 |
| Finished | Oct 12 05:43:16 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374781292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.2374781292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/56.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_init_fail.3738051850 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 601058880 ps |
| CPU time | 4.89 seconds |
| Started | Oct 12 05:42:59 PM UTC 24 |
| Finished | Oct 12 05:43:05 PM UTC 24 |
| Peak memory | 252916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738051850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.3738051850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/57.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_parallel_lc_esc.3767771610 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 138709649 ps |
| CPU time | 5.52 seconds |
| Started | Oct 12 05:42:59 PM UTC 24 |
| Finished | Oct 12 05:43:05 PM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767771610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.3767771610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/57.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_init_fail.1316187753 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 106174702 ps |
| CPU time | 3.63 seconds |
| Started | Oct 12 05:43:01 PM UTC 24 |
| Finished | Oct 12 05:43:06 PM UTC 24 |
| Peak memory | 253044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316187753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.1316187753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/58.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_parallel_lc_esc.1727554524 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 459119559 ps |
| CPU time | 5.48 seconds |
| Started | Oct 12 05:43:02 PM UTC 24 |
| Finished | Oct 12 05:43:08 PM UTC 24 |
| Peak memory | 252552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727554524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.1727554524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/58.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.3127631284 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 3631974592 ps |
| CPU time | 67.55 seconds |
| Started | Oct 12 05:43:02 PM UTC 24 |
| Finished | Oct 12 05:44:11 PM UTC 24 |
| Peak memory | 259352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3127631284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 58.otp_ctrl_stress_all_with_rand_reset.3127631284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_parallel_lc_esc.1995813907 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 866080111 ps |
| CPU time | 6.04 seconds |
| Started | Oct 12 05:43:02 PM UTC 24 |
| Finished | Oct 12 05:43:09 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995813907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.1995813907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.2064691867 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 4963326985 ps |
| CPU time | 74.86 seconds |
| Started | Oct 12 05:43:02 PM UTC 24 |
| Finished | Oct 12 05:44:18 PM UTC 24 |
| Peak memory | 259096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2064691867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 59.otp_ctrl_stress_all_with_rand_reset.2064691867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/59.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_alert_test.2377176233 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 117237821 ps |
| CPU time | 2.99 seconds |
| Started | Oct 12 05:37:41 PM UTC 24 |
| Finished | Oct 12 05:37:45 PM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377176233 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.2377176233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_background_chks.698288430 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1384486429 ps |
| CPU time | 18.58 seconds |
| Started | Oct 12 05:37:35 PM UTC 24 |
| Finished | Oct 12 05:37:55 PM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698288430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.698288430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_errs.4107976734 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 287106826 ps |
| CPU time | 14.23 seconds |
| Started | Oct 12 05:37:40 PM UTC 24 |
| Finished | Oct 12 05:37:56 PM UTC 24 |
| Peak memory | 254900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107976734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.4107976734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_init_fail.1429319901 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 188084866 ps |
| CPU time | 3.45 seconds |
| Started | Oct 12 05:37:35 PM UTC 24 |
| Finished | Oct 12 05:37:39 PM UTC 24 |
| Peak memory | 255012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429319901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.1429319901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_macro_errs.473964659 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1077610706 ps |
| CPU time | 19.39 seconds |
| Started | Oct 12 05:37:40 PM UTC 24 |
| Finished | Oct 12 05:38:01 PM UTC 24 |
| Peak memory | 254840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473964659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.473964659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_key_req.2363302615 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 228764521 ps |
| CPU time | 6.47 seconds |
| Started | Oct 12 05:37:40 PM UTC 24 |
| Finished | Oct 12 05:37:48 PM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363302615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.2363302615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_esc.3704294337 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1437216718 ps |
| CPU time | 3.49 seconds |
| Started | Oct 12 05:37:35 PM UTC 24 |
| Finished | Oct 12 05:37:39 PM UTC 24 |
| Peak memory | 252620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704294337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.3704294337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_req.3084786757 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 2717004704 ps |
| CPU time | 26.21 seconds |
| Started | Oct 12 05:37:35 PM UTC 24 |
| Finished | Oct 12 05:38:02 PM UTC 24 |
| Peak memory | 253072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084786757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.3084786757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_regwen.2523212964 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1131871277 ps |
| CPU time | 8.37 seconds |
| Started | Oct 12 05:37:40 PM UTC 24 |
| Finished | Oct 12 05:37:50 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523212964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.2523212964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_smoke.20976582 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 5080770824 ps |
| CPU time | 7.81 seconds |
| Started | Oct 12 05:37:35 PM UTC 24 |
| Finished | Oct 12 05:37:43 PM UTC 24 |
| Peak memory | 252856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20976582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.20976582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_test_access.556286865 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 386135772 ps |
| CPU time | 5.78 seconds |
| Started | Oct 12 05:37:40 PM UTC 24 |
| Finished | Oct 12 05:37:47 PM UTC 24 |
| Peak memory | 253072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556286865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.556286865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/6.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_init_fail.385166828 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 1797245290 ps |
| CPU time | 6.42 seconds |
| Started | Oct 12 05:43:02 PM UTC 24 |
| Finished | Oct 12 05:43:09 PM UTC 24 |
| Peak memory | 252740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385166828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.385166828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/60.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_parallel_lc_esc.2106187057 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 1636888444 ps |
| CPU time | 4.29 seconds |
| Started | Oct 12 05:43:02 PM UTC 24 |
| Finished | Oct 12 05:43:07 PM UTC 24 |
| Peak memory | 252964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106187057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.2106187057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/60.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_init_fail.940639451 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 433369043 ps |
| CPU time | 4.44 seconds |
| Started | Oct 12 05:43:06 PM UTC 24 |
| Finished | Oct 12 05:43:12 PM UTC 24 |
| Peak memory | 255056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940639451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.940639451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/61.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_parallel_lc_esc.3104141498 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 2238825541 ps |
| CPU time | 7.74 seconds |
| Started | Oct 12 05:43:06 PM UTC 24 |
| Finished | Oct 12 05:43:15 PM UTC 24 |
| Peak memory | 252808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104141498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.3104141498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/61.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_init_fail.3477474452 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 658877850 ps |
| CPU time | 4.69 seconds |
| Started | Oct 12 05:43:06 PM UTC 24 |
| Finished | Oct 12 05:43:12 PM UTC 24 |
| Peak memory | 252920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477474452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.3477474452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/62.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_parallel_lc_esc.2999177357 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 2809410212 ps |
| CPU time | 14.42 seconds |
| Started | Oct 12 05:43:06 PM UTC 24 |
| Finished | Oct 12 05:43:22 PM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999177357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.2999177357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/62.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.2644762810 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3757563313 ps |
| CPU time | 87.15 seconds |
| Started | Oct 12 05:43:06 PM UTC 24 |
| Finished | Oct 12 05:44:36 PM UTC 24 |
| Peak memory | 269384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2644762810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 62.otp_ctrl_stress_all_with_rand_reset.2644762810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_init_fail.1964123926 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 139271197 ps |
| CPU time | 2.76 seconds |
| Started | Oct 12 05:43:06 PM UTC 24 |
| Finished | Oct 12 05:43:10 PM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964123926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.1964123926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/63.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_parallel_lc_esc.2992214085 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 8126619868 ps |
| CPU time | 22.41 seconds |
| Started | Oct 12 05:43:09 PM UTC 24 |
| Finished | Oct 12 05:43:33 PM UTC 24 |
| Peak memory | 252700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992214085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.2992214085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/63.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.720432926 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 8352229695 ps |
| CPU time | 29.66 seconds |
| Started | Oct 12 05:43:09 PM UTC 24 |
| Finished | Oct 12 05:43:40 PM UTC 24 |
| Peak memory | 259420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=720432926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.720432926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_init_fail.3287184521 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 140894322 ps |
| CPU time | 4.25 seconds |
| Started | Oct 12 05:43:09 PM UTC 24 |
| Finished | Oct 12 05:43:15 PM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287184521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.3287184521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/64.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_parallel_lc_esc.4084131152 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 275682223 ps |
| CPU time | 7.82 seconds |
| Started | Oct 12 05:43:09 PM UTC 24 |
| Finished | Oct 12 05:43:18 PM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084131152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.4084131152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/64.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_init_fail.344164442 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 633944046 ps |
| CPU time | 4.87 seconds |
| Started | Oct 12 05:43:09 PM UTC 24 |
| Finished | Oct 12 05:43:16 PM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344164442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.344164442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/65.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_parallel_lc_esc.591381357 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 1025058919 ps |
| CPU time | 19 seconds |
| Started | Oct 12 05:43:09 PM UTC 24 |
| Finished | Oct 12 05:43:30 PM UTC 24 |
| Peak memory | 252676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591381357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.591381357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/65.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.3598031626 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 24854477095 ps |
| CPU time | 58.49 seconds |
| Started | Oct 12 05:43:09 PM UTC 24 |
| Finished | Oct 12 05:44:10 PM UTC 24 |
| Peak memory | 269412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3598031626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 65.otp_ctrl_stress_all_with_rand_reset.3598031626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_init_fail.3042166025 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 493254336 ps |
| CPU time | 5.21 seconds |
| Started | Oct 12 05:43:09 PM UTC 24 |
| Finished | Oct 12 05:43:16 PM UTC 24 |
| Peak memory | 254964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042166025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.3042166025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/66.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_parallel_lc_esc.2370331023 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 242174587 ps |
| CPU time | 13.55 seconds |
| Started | Oct 12 05:43:10 PM UTC 24 |
| Finished | Oct 12 05:43:24 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370331023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.2370331023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/66.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.3280803538 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 37652885719 ps |
| CPU time | 77.19 seconds |
| Started | Oct 12 05:43:10 PM UTC 24 |
| Finished | Oct 12 05:44:29 PM UTC 24 |
| Peak memory | 269408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3280803538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 66.otp_ctrl_stress_all_with_rand_reset.3280803538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_init_fail.713648770 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 2049542094 ps |
| CPU time | 4.63 seconds |
| Started | Oct 12 05:43:10 PM UTC 24 |
| Finished | Oct 12 05:43:16 PM UTC 24 |
| Peak memory | 252928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713648770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.713648770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/67.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_parallel_lc_esc.22549569 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 2376597330 ps |
| CPU time | 22.11 seconds |
| Started | Oct 12 05:43:10 PM UTC 24 |
| Finished | Oct 12 05:43:34 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22549569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.22549569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/67.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_init_fail.4176044801 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 185977085 ps |
| CPU time | 6 seconds |
| Started | Oct 12 05:43:10 PM UTC 24 |
| Finished | Oct 12 05:43:17 PM UTC 24 |
| Peak memory | 254680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176044801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.4176044801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/68.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.436041474 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 21955762778 ps |
| CPU time | 103.44 seconds |
| Started | Oct 12 05:43:12 PM UTC 24 |
| Finished | Oct 12 05:44:57 PM UTC 24 |
| Peak memory | 269420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=436041474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.436041474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_init_fail.875183089 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 518698270 ps |
| CPU time | 6.65 seconds |
| Started | Oct 12 05:43:12 PM UTC 24 |
| Finished | Oct 12 05:43:20 PM UTC 24 |
| Peak memory | 252572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875183089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.875183089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/69.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_alert_test.2720113286 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 158462749 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 05:37:44 PM UTC 24 |
| Finished | Oct 12 05:37:47 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720113286 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.2720113286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_background_chks.3411253300 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 2471601576 ps |
| CPU time | 25.83 seconds |
| Started | Oct 12 05:37:41 PM UTC 24 |
| Finished | Oct 12 05:38:08 PM UTC 24 |
| Peak memory | 259108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411253300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.3411253300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_errs.3852444627 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1622330292 ps |
| CPU time | 40.42 seconds |
| Started | Oct 12 05:37:41 PM UTC 24 |
| Finished | Oct 12 05:38:23 PM UTC 24 |
| Peak memory | 258940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852444627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.3852444627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_lock.3869291459 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 443885134 ps |
| CPU time | 8.15 seconds |
| Started | Oct 12 05:37:41 PM UTC 24 |
| Finished | Oct 12 05:37:50 PM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869291459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.3869291459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_init_fail.1804280641 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 294087854 ps |
| CPU time | 5.03 seconds |
| Started | Oct 12 05:37:41 PM UTC 24 |
| Finished | Oct 12 05:37:47 PM UTC 24 |
| Peak memory | 254692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804280641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.1804280641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_macro_errs.1565637742 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 775925344 ps |
| CPU time | 8.77 seconds |
| Started | Oct 12 05:37:41 PM UTC 24 |
| Finished | Oct 12 05:37:51 PM UTC 24 |
| Peak memory | 254844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565637742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.1565637742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_key_req.57916694 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2575093685 ps |
| CPU time | 15.31 seconds |
| Started | Oct 12 05:37:41 PM UTC 24 |
| Finished | Oct 12 05:37:57 PM UTC 24 |
| Peak memory | 255140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57916694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.57916694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_esc.3358622964 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 8005406837 ps |
| CPU time | 25.38 seconds |
| Started | Oct 12 05:37:41 PM UTC 24 |
| Finished | Oct 12 05:38:07 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358622964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.3358622964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_req.2841354762 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 288732829 ps |
| CPU time | 9.99 seconds |
| Started | Oct 12 05:37:41 PM UTC 24 |
| Finished | Oct 12 05:37:52 PM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841354762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.2841354762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_regwen.1158512275 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 516566959 ps |
| CPU time | 8.92 seconds |
| Started | Oct 12 05:37:41 PM UTC 24 |
| Finished | Oct 12 05:37:51 PM UTC 24 |
| Peak memory | 253028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158512275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.1158512275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_smoke.1964407473 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 537645574 ps |
| CPU time | 5.37 seconds |
| Started | Oct 12 05:37:41 PM UTC 24 |
| Finished | Oct 12 05:37:47 PM UTC 24 |
| Peak memory | 252924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964407473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.1964407473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_test_access.1571102690 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 9071469470 ps |
| CPU time | 12.2 seconds |
| Started | Oct 12 05:37:41 PM UTC 24 |
| Finished | Oct 12 05:37:54 PM UTC 24 |
| Peak memory | 253132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571102690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.1571102690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/7.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_init_fail.3389046527 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2025120247 ps |
| CPU time | 5.77 seconds |
| Started | Oct 12 05:43:12 PM UTC 24 |
| Finished | Oct 12 05:43:19 PM UTC 24 |
| Peak memory | 254712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389046527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.3389046527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/70.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_parallel_lc_esc.1026757520 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 602514103 ps |
| CPU time | 8.17 seconds |
| Started | Oct 12 05:43:13 PM UTC 24 |
| Finished | Oct 12 05:43:22 PM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026757520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.1026757520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/70.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_init_fail.2695790523 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 136609286 ps |
| CPU time | 5.49 seconds |
| Started | Oct 12 05:43:17 PM UTC 24 |
| Finished | Oct 12 05:43:23 PM UTC 24 |
| Peak memory | 252920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695790523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.2695790523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/71.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_parallel_lc_esc.1378901169 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 433278040 ps |
| CPU time | 8.74 seconds |
| Started | Oct 12 05:43:17 PM UTC 24 |
| Finished | Oct 12 05:43:27 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378901169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.1378901169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/71.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.2677339317 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 8694283715 ps |
| CPU time | 116.37 seconds |
| Started | Oct 12 05:43:17 PM UTC 24 |
| Finished | Oct 12 05:45:16 PM UTC 24 |
| Peak memory | 269592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2677339317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 71.otp_ctrl_stress_all_with_rand_reset.2677339317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_parallel_lc_esc.744341367 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 1475848986 ps |
| CPU time | 4.38 seconds |
| Started | Oct 12 05:43:17 PM UTC 24 |
| Finished | Oct 12 05:43:22 PM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744341367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.744341367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/72.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_init_fail.90628861 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 111523569 ps |
| CPU time | 5.3 seconds |
| Started | Oct 12 05:43:19 PM UTC 24 |
| Finished | Oct 12 05:43:26 PM UTC 24 |
| Peak memory | 253064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90628861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.90628861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/73.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_parallel_lc_esc.3416064632 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 286455492 ps |
| CPU time | 7.49 seconds |
| Started | Oct 12 05:43:19 PM UTC 24 |
| Finished | Oct 12 05:43:28 PM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416064632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.3416064632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/73.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_init_fail.3616532864 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 102200173 ps |
| CPU time | 5.09 seconds |
| Started | Oct 12 05:43:19 PM UTC 24 |
| Finished | Oct 12 05:43:26 PM UTC 24 |
| Peak memory | 255008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616532864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.3616532864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/74.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_parallel_lc_esc.2105011609 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 244915600 ps |
| CPU time | 4.04 seconds |
| Started | Oct 12 05:43:20 PM UTC 24 |
| Finished | Oct 12 05:43:25 PM UTC 24 |
| Peak memory | 252552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105011609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.2105011609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/74.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.3910453883 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 21131938881 ps |
| CPU time | 52.53 seconds |
| Started | Oct 12 05:43:20 PM UTC 24 |
| Finished | Oct 12 05:44:14 PM UTC 24 |
| Peak memory | 269412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3910453883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 74.otp_ctrl_stress_all_with_rand_reset.3910453883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/74.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_init_fail.3049676358 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 534551078 ps |
| CPU time | 6.32 seconds |
| Started | Oct 12 05:43:20 PM UTC 24 |
| Finished | Oct 12 05:43:27 PM UTC 24 |
| Peak memory | 253044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049676358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.3049676358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/75.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_parallel_lc_esc.1499554533 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 249920022 ps |
| CPU time | 6.13 seconds |
| Started | Oct 12 05:43:20 PM UTC 24 |
| Finished | Oct 12 05:43:27 PM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499554533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.1499554533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/75.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_init_fail.809744224 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 443098527 ps |
| CPU time | 3.83 seconds |
| Started | Oct 12 05:43:21 PM UTC 24 |
| Finished | Oct 12 05:43:26 PM UTC 24 |
| Peak memory | 253040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809744224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.809744224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/76.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_parallel_lc_esc.1776848582 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 2169901430 ps |
| CPU time | 21.34 seconds |
| Started | Oct 12 05:43:23 PM UTC 24 |
| Finished | Oct 12 05:43:45 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776848582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.1776848582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/76.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.446251320 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 34367924049 ps |
| CPU time | 79.75 seconds |
| Started | Oct 12 05:43:23 PM UTC 24 |
| Finished | Oct 12 05:44:44 PM UTC 24 |
| Peak memory | 269420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=446251320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.446251320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/76.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_init_fail.3352021195 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 225992696 ps |
| CPU time | 6.16 seconds |
| Started | Oct 12 05:43:23 PM UTC 24 |
| Finished | Oct 12 05:43:30 PM UTC 24 |
| Peak memory | 252980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352021195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.3352021195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/77.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_parallel_lc_esc.309524599 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 365641318 ps |
| CPU time | 17.35 seconds |
| Started | Oct 12 05:43:25 PM UTC 24 |
| Finished | Oct 12 05:43:43 PM UTC 24 |
| Peak memory | 252940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309524599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.309524599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/77.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_init_fail.3648561752 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 2194764659 ps |
| CPU time | 5.85 seconds |
| Started | Oct 12 05:43:25 PM UTC 24 |
| Finished | Oct 12 05:43:32 PM UTC 24 |
| Peak memory | 252788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648561752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.3648561752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/78.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_parallel_lc_esc.1840578117 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 211258264 ps |
| CPU time | 5.39 seconds |
| Started | Oct 12 05:43:25 PM UTC 24 |
| Finished | Oct 12 05:43:32 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840578117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.1840578117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/78.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.1060127872 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 7628720479 ps |
| CPU time | 97.05 seconds |
| Started | Oct 12 05:43:25 PM UTC 24 |
| Finished | Oct 12 05:45:04 PM UTC 24 |
| Peak memory | 259144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1060127872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 78.otp_ctrl_stress_all_with_rand_reset.1060127872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/78.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_parallel_lc_esc.174685775 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 14179948549 ps |
| CPU time | 24.33 seconds |
| Started | Oct 12 05:43:29 PM UTC 24 |
| Finished | Oct 12 05:43:54 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174685775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.174685775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/79.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_alert_test.244734994 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 109955333 ps |
| CPU time | 2.88 seconds |
| Started | Oct 12 05:37:48 PM UTC 24 |
| Finished | Oct 12 05:37:52 PM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244734994 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.244734994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_background_chks.1682662348 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 661965941 ps |
| CPU time | 18.49 seconds |
| Started | Oct 12 05:37:44 PM UTC 24 |
| Finished | Oct 12 05:38:04 PM UTC 24 |
| Peak memory | 252876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682662348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.1682662348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_check_fail.1290236898 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1880435876 ps |
| CPU time | 20.95 seconds |
| Started | Oct 12 05:37:48 PM UTC 24 |
| Finished | Oct 12 05:38:10 PM UTC 24 |
| Peak memory | 254828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290236898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.1290236898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_errs.2774065554 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 825863578 ps |
| CPU time | 14 seconds |
| Started | Oct 12 05:37:48 PM UTC 24 |
| Finished | Oct 12 05:38:03 PM UTC 24 |
| Peak memory | 252608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774065554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.2774065554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_lock.1835361739 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 11300127641 ps |
| CPU time | 37.17 seconds |
| Started | Oct 12 05:37:48 PM UTC 24 |
| Finished | Oct 12 05:38:27 PM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835361739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.1835361739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_macro_errs.992391495 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 1795903809 ps |
| CPU time | 37.02 seconds |
| Started | Oct 12 05:37:48 PM UTC 24 |
| Finished | Oct 12 05:38:27 PM UTC 24 |
| Peak memory | 269196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992391495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.992391495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_key_req.1174048134 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 271047323 ps |
| CPU time | 7.05 seconds |
| Started | Oct 12 05:37:48 PM UTC 24 |
| Finished | Oct 12 05:37:57 PM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174048134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.1174048134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_req.1953345134 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1324953719 ps |
| CPU time | 13.24 seconds |
| Started | Oct 12 05:37:44 PM UTC 24 |
| Finished | Oct 12 05:37:59 PM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953345134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.1953345134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_regwen.288042847 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 141874867 ps |
| CPU time | 5.56 seconds |
| Started | Oct 12 05:37:48 PM UTC 24 |
| Finished | Oct 12 05:37:55 PM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288042847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.288042847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_test_access.3356036369 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 5859142324 ps |
| CPU time | 32.71 seconds |
| Started | Oct 12 05:37:48 PM UTC 24 |
| Finished | Oct 12 05:38:23 PM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356036369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.3356036369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/8.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_init_fail.398053135 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 128735413 ps |
| CPU time | 5.93 seconds |
| Started | Oct 12 05:43:29 PM UTC 24 |
| Finished | Oct 12 05:43:36 PM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398053135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.398053135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/80.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_parallel_lc_esc.1409363495 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 606555499 ps |
| CPU time | 8.93 seconds |
| Started | Oct 12 05:43:29 PM UTC 24 |
| Finished | Oct 12 05:43:39 PM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409363495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.1409363495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/80.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_init_fail.3669077604 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 1547632185 ps |
| CPU time | 5.33 seconds |
| Started | Oct 12 05:43:34 PM UTC 24 |
| Finished | Oct 12 05:43:41 PM UTC 24 |
| Peak memory | 252920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669077604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.3669077604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/81.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_parallel_lc_esc.814631025 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 282748989 ps |
| CPU time | 9.23 seconds |
| Started | Oct 12 05:43:34 PM UTC 24 |
| Finished | Oct 12 05:43:45 PM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814631025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.814631025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/81.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_init_fail.4226704129 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 255225639 ps |
| CPU time | 5.62 seconds |
| Started | Oct 12 05:43:34 PM UTC 24 |
| Finished | Oct 12 05:43:41 PM UTC 24 |
| Peak memory | 254968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226704129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.4226704129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/82.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_parallel_lc_esc.3691381793 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 226004993 ps |
| CPU time | 6.48 seconds |
| Started | Oct 12 05:43:34 PM UTC 24 |
| Finished | Oct 12 05:43:42 PM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691381793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.3691381793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/82.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_init_fail.3094527949 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 166129177 ps |
| CPU time | 6.05 seconds |
| Started | Oct 12 05:43:35 PM UTC 24 |
| Finished | Oct 12 05:43:42 PM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094527949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.3094527949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/83.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_parallel_lc_esc.2689881801 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 215212763 ps |
| CPU time | 7.61 seconds |
| Started | Oct 12 05:43:37 PM UTC 24 |
| Finished | Oct 12 05:43:46 PM UTC 24 |
| Peak memory | 252648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689881801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.2689881801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/83.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_init_fail.3563580103 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 220498665 ps |
| CPU time | 6.27 seconds |
| Started | Oct 12 05:43:37 PM UTC 24 |
| Finished | Oct 12 05:43:45 PM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563580103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.3563580103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/84.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_parallel_lc_esc.2459896309 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 5574827743 ps |
| CPU time | 15.16 seconds |
| Started | Oct 12 05:43:37 PM UTC 24 |
| Finished | Oct 12 05:43:54 PM UTC 24 |
| Peak memory | 252836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459896309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.2459896309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/84.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_init_fail.3424788866 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 1604854334 ps |
| CPU time | 4.69 seconds |
| Started | Oct 12 05:43:37 PM UTC 24 |
| Finished | Oct 12 05:43:43 PM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424788866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.3424788866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/85.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_parallel_lc_esc.2676258009 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 457062023 ps |
| CPU time | 9.23 seconds |
| Started | Oct 12 05:43:37 PM UTC 24 |
| Finished | Oct 12 05:43:48 PM UTC 24 |
| Peak memory | 252620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676258009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.2676258009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.1048692237 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 3354563669 ps |
| CPU time | 56.65 seconds |
| Started | Oct 12 05:43:38 PM UTC 24 |
| Finished | Oct 12 05:44:36 PM UTC 24 |
| Peak memory | 259096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1048692237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 85.otp_ctrl_stress_all_with_rand_reset.1048692237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_parallel_lc_esc.31063868 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 590442296 ps |
| CPU time | 8.62 seconds |
| Started | Oct 12 05:43:42 PM UTC 24 |
| Finished | Oct 12 05:43:52 PM UTC 24 |
| Peak memory | 253028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31063868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.31063868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/86.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_init_fail.3670438532 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 339286276 ps |
| CPU time | 6.53 seconds |
| Started | Oct 12 05:43:43 PM UTC 24 |
| Finished | Oct 12 05:43:50 PM UTC 24 |
| Peak memory | 253044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670438532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.3670438532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/87.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_parallel_lc_esc.3990393719 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 1910380794 ps |
| CPU time | 7.98 seconds |
| Started | Oct 12 05:43:43 PM UTC 24 |
| Finished | Oct 12 05:43:52 PM UTC 24 |
| Peak memory | 252620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990393719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.3990393719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/87.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_init_fail.1361368225 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 529921889 ps |
| CPU time | 4.91 seconds |
| Started | Oct 12 05:43:43 PM UTC 24 |
| Finished | Oct 12 05:43:49 PM UTC 24 |
| Peak memory | 254772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361368225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.1361368225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/88.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_parallel_lc_esc.1441200517 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 589224167 ps |
| CPU time | 11.55 seconds |
| Started | Oct 12 05:43:43 PM UTC 24 |
| Finished | Oct 12 05:43:55 PM UTC 24 |
| Peak memory | 252044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441200517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.1441200517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/88.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_init_fail.1770680737 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 106361692 ps |
| CPU time | 5.41 seconds |
| Started | Oct 12 05:43:44 PM UTC 24 |
| Finished | Oct 12 05:43:51 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770680737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.1770680737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/89.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_parallel_lc_esc.166924324 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 526598987 ps |
| CPU time | 4.68 seconds |
| Started | Oct 12 05:43:44 PM UTC 24 |
| Finished | Oct 12 05:43:50 PM UTC 24 |
| Peak memory | 252964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166924324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.166924324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/89.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_alert_test.1763533195 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 78724414 ps |
| CPU time | 2.15 seconds |
| Started | Oct 12 05:37:57 PM UTC 24 |
| Finished | Oct 12 05:38:00 PM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763533195 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.1763533195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_background_chks.525440203 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1234472624 ps |
| CPU time | 26.45 seconds |
| Started | Oct 12 05:37:51 PM UTC 24 |
| Finished | Oct 12 05:38:19 PM UTC 24 |
| Peak memory | 254832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525440203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.525440203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_check_fail.2808652701 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 9378160162 ps |
| CPU time | 25.32 seconds |
| Started | Oct 12 05:37:52 PM UTC 24 |
| Finished | Oct 12 05:38:18 PM UTC 24 |
| Peak memory | 253104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808652701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.2808652701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_errs.1118776888 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 953198107 ps |
| CPU time | 15.28 seconds |
| Started | Oct 12 05:37:52 PM UTC 24 |
| Finished | Oct 12 05:38:08 PM UTC 24 |
| Peak memory | 252884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118776888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.1118776888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_lock.3717011614 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 23545513304 ps |
| CPU time | 40.32 seconds |
| Started | Oct 12 05:37:52 PM UTC 24 |
| Finished | Oct 12 05:38:34 PM UTC 24 |
| Peak memory | 253104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717011614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.3717011614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_init_fail.2615101712 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1461026868 ps |
| CPU time | 5.64 seconds |
| Started | Oct 12 05:37:49 PM UTC 24 |
| Finished | Oct 12 05:37:55 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615101712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.2615101712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_macro_errs.1588107226 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 905702715 ps |
| CPU time | 14.24 seconds |
| Started | Oct 12 05:37:52 PM UTC 24 |
| Finished | Oct 12 05:38:07 PM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588107226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.1588107226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_key_req.695943559 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 4836541933 ps |
| CPU time | 8.55 seconds |
| Started | Oct 12 05:37:57 PM UTC 24 |
| Finished | Oct 12 05:38:07 PM UTC 24 |
| Peak memory | 253092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695943559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.695943559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_esc.2713241008 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 101200115 ps |
| CPU time | 3.17 seconds |
| Started | Oct 12 05:37:52 PM UTC 24 |
| Finished | Oct 12 05:37:56 PM UTC 24 |
| Peak memory | 252940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713241008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.2713241008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_regwen.1910398045 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 144546850 ps |
| CPU time | 5.21 seconds |
| Started | Oct 12 05:37:57 PM UTC 24 |
| Finished | Oct 12 05:38:03 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910398045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.1910398045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_smoke.2477970672 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 251490569 ps |
| CPU time | 5.52 seconds |
| Started | Oct 12 05:37:49 PM UTC 24 |
| Finished | Oct 12 05:37:55 PM UTC 24 |
| Peak memory | 258844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477970672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.2477970672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_test_access.2406899427 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 3540431159 ps |
| CPU time | 18.06 seconds |
| Started | Oct 12 05:37:57 PM UTC 24 |
| Finished | Oct 12 05:38:16 PM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406899427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.2406899427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/9.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_init_fail.1420451671 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 195991652 ps |
| CPU time | 4.49 seconds |
| Started | Oct 12 05:43:46 PM UTC 24 |
| Finished | Oct 12 05:43:51 PM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420451671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.1420451671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/90.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_parallel_lc_esc.3133665118 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 6243337648 ps |
| CPU time | 13 seconds |
| Started | Oct 12 05:43:47 PM UTC 24 |
| Finished | Oct 12 05:44:02 PM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133665118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.3133665118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/90.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_init_fail.2071618865 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 506744154 ps |
| CPU time | 5.02 seconds |
| Started | Oct 12 05:43:48 PM UTC 24 |
| Finished | Oct 12 05:43:54 PM UTC 24 |
| Peak memory | 254712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071618865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.2071618865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/91.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_parallel_lc_esc.3202554328 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 1121250957 ps |
| CPU time | 18.77 seconds |
| Started | Oct 12 05:43:49 PM UTC 24 |
| Finished | Oct 12 05:44:09 PM UTC 24 |
| Peak memory | 252596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202554328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.3202554328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/91.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.1885620242 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 11069551939 ps |
| CPU time | 85.75 seconds |
| Started | Oct 12 05:43:49 PM UTC 24 |
| Finished | Oct 12 05:45:16 PM UTC 24 |
| Peak memory | 269432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1885620242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 91.otp_ctrl_stress_all_with_rand_reset.1885620242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_init_fail.2188926134 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 235086808 ps |
| CPU time | 4.9 seconds |
| Started | Oct 12 05:43:51 PM UTC 24 |
| Finished | Oct 12 05:43:57 PM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188926134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.2188926134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/92.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_parallel_lc_esc.3239464949 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 111020737 ps |
| CPU time | 4.15 seconds |
| Started | Oct 12 05:43:51 PM UTC 24 |
| Finished | Oct 12 05:43:56 PM UTC 24 |
| Peak memory | 252612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239464949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.3239464949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/92.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.1280717432 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 8137966364 ps |
| CPU time | 68.87 seconds |
| Started | Oct 12 05:43:51 PM UTC 24 |
| Finished | Oct 12 05:45:02 PM UTC 24 |
| Peak memory | 259400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1280717432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 92.otp_ctrl_stress_all_with_rand_reset.1280717432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/92.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_init_fail.4165826955 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 464754669 ps |
| CPU time | 3.98 seconds |
| Started | Oct 12 05:43:51 PM UTC 24 |
| Finished | Oct 12 05:43:56 PM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165826955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.4165826955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/93.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_parallel_lc_esc.3994740758 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 2103752458 ps |
| CPU time | 19.14 seconds |
| Started | Oct 12 05:43:51 PM UTC 24 |
| Finished | Oct 12 05:44:11 PM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994740758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.3994740758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/93.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_init_fail.3707085849 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 2130777821 ps |
| CPU time | 7.34 seconds |
| Started | Oct 12 05:43:53 PM UTC 24 |
| Finished | Oct 12 05:44:01 PM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707085849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.3707085849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/94.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_parallel_lc_esc.2350274190 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 603789495 ps |
| CPU time | 17.98 seconds |
| Started | Oct 12 05:43:53 PM UTC 24 |
| Finished | Oct 12 05:44:12 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350274190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.2350274190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/94.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_parallel_lc_esc.2391166601 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 1029735331 ps |
| CPU time | 21.67 seconds |
| Started | Oct 12 05:43:56 PM UTC 24 |
| Finished | Oct 12 05:44:19 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391166601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.2391166601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_init_fail.301476602 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 135694569 ps |
| CPU time | 4.67 seconds |
| Started | Oct 12 05:43:56 PM UTC 24 |
| Finished | Oct 12 05:44:01 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301476602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.301476602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/96.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_parallel_lc_esc.2696554792 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 424557398 ps |
| CPU time | 7.05 seconds |
| Started | Oct 12 05:44:01 PM UTC 24 |
| Finished | Oct 12 05:44:09 PM UTC 24 |
| Peak memory | 252896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696554792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.2696554792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/96.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_init_fail.465459103 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 190958084 ps |
| CPU time | 4.85 seconds |
| Started | Oct 12 05:44:01 PM UTC 24 |
| Finished | Oct 12 05:44:07 PM UTC 24 |
| Peak memory | 252740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465459103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.465459103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/97.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_parallel_lc_esc.3722884491 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 1267006310 ps |
| CPU time | 13.6 seconds |
| Started | Oct 12 05:44:01 PM UTC 24 |
| Finished | Oct 12 05:44:16 PM UTC 24 |
| Peak memory | 253028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722884491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.3722884491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/97.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_init_fail.3714963326 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 293442507 ps |
| CPU time | 6.02 seconds |
| Started | Oct 12 05:44:01 PM UTC 24 |
| Finished | Oct 12 05:44:08 PM UTC 24 |
| Peak memory | 254832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714963326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.3714963326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/98.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_parallel_lc_esc.2615755286 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 328143392 ps |
| CPU time | 7.52 seconds |
| Started | Oct 12 05:44:01 PM UTC 24 |
| Finished | Oct 12 05:44:10 PM UTC 24 |
| Peak memory | 252964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615755286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.2615755286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/98.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.4134564283 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 11934516212 ps |
| CPU time | 98.93 seconds |
| Started | Oct 12 05:44:01 PM UTC 24 |
| Finished | Oct 12 05:45:42 PM UTC 24 |
| Peak memory | 269408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4134564283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 98.otp_ctrl_stress_all_with_rand_reset.4134564283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/98.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_init_fail.3350334857 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 453520131 ps |
| CPU time | 6.93 seconds |
| Started | Oct 12 05:44:01 PM UTC 24 |
| Finished | Oct 12 05:44:09 PM UTC 24 |
| Peak memory | 252972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350334857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.3350334857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/99.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_parallel_lc_esc.671141146 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 613599077 ps |
| CPU time | 6.88 seconds |
| Started | Oct 12 05:44:02 PM UTC 24 |
| Finished | Oct 12 05:44:10 PM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671141146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.671141146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/99.otp_ctrl_parallel_lc_esc/latest |
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