PATTGEN Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: 30db5a999

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2235272161

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 9.000s 715.261us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 2.000s 35.483us 5 5 100.00
V1 csr_rw pattgen_csr_rw 3.000s 43.162us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 6.000s 203.046us 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 3.000s 21.893us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 4.000s 20.207us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 3.000s 43.162us 20 20 100.00
pattgen_csr_aliasing 3.000s 21.893us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 1.850m 10.985ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.867m 5.371ms 50 50 100.00
V2 error pattgen_error 4.000s 70.535us 50 50 100.00
V2 stress_all pattgen_stress_all 3.450m 8.061ms 50 50 100.00
V2 alert_test pattgen_alert_test 6.000s 15.639us 50 50 100.00
V2 intr_test pattgen_intr_test 4.000s 20.419us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 6.000s 982.150us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 6.000s 982.150us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 2.000s 35.483us 5 5 100.00
pattgen_csr_rw 3.000s 43.162us 20 20 100.00
pattgen_csr_aliasing 3.000s 21.893us 5 5 100.00
pattgen_same_csr_outstanding 4.000s 31.090us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 2.000s 35.483us 5 5 100.00
pattgen_csr_rw 3.000s 43.162us 20 20 100.00
pattgen_csr_aliasing 3.000s 21.893us 5 5 100.00
pattgen_same_csr_outstanding 4.000s 31.090us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 4.000s 52.527us 20 20 100.00
pattgen_sec_cm 3.000s 664.335us 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 4.000s 52.527us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 27.400m 916.424ms 44 50 88.00
V3 TOTAL 44 50 88.00
TOTAL 514 520 98.85

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.83 100.00 100.00 100.00 99.06 96.13 -- 100.00 90.91

Failure Buckets

Past Results