PATTGEN Simulation Results

Sunday September 17 2023 19:02:18 UTC

GitHub Revision: 3451d3b85

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 266892513

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 15.000s 383.207us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 7.000s 14.766us 5 5 100.00
V1 csr_rw pattgen_csr_rw 7.000s 81.033us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 10.000s 431.294us 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 3.000s 55.957us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 12.000s 41.306us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 7.000s 81.033us 20 20 100.00
pattgen_csr_aliasing 3.000s 55.957us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 2.767m 23.209ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.567m 2.289ms 50 50 100.00
V2 error pattgen_error 12.000s 46.493us 50 50 100.00
V2 stress_all pattgen_stress_all 4.683m 6.680ms 50 50 100.00
V2 alert_test pattgen_alert_test 15.000s 96.154us 50 50 100.00
V2 intr_test pattgen_intr_test 7.000s 36.031us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 13.000s 50.801us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 13.000s 50.801us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 7.000s 14.766us 5 5 100.00
pattgen_csr_rw 7.000s 81.033us 20 20 100.00
pattgen_csr_aliasing 3.000s 55.957us 5 5 100.00
pattgen_same_csr_outstanding 7.000s 16.490us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 7.000s 14.766us 5 5 100.00
pattgen_csr_rw 7.000s 81.033us 20 20 100.00
pattgen_csr_aliasing 3.000s 55.957us 5 5 100.00
pattgen_same_csr_outstanding 7.000s 16.490us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 7.000s 48.509us 20 20 100.00
pattgen_sec_cm 3.000s 1.303ms 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 7.000s 48.509us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 37.750m 103.341ms 41 50 82.00
V3 TOTAL 41 50 82.00
TOTAL 511 520 98.27

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.79 100.00 100.00 100.00 99.06 96.13 -- 100.00 90.43

Failure Buckets

Past Results