PATTGEN Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: `1c75f24e99`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	165.718us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	46.687us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	13.641us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	284.066us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	65.934us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	339.026us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	13.641us	20	20	100.00
		pattgen_csr_aliasing	3.000s	65.934us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.967m	26.302ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.983m	7.736ms	50	50	100.00
V2	error	pattgen_error	7.000s	13.590us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.000m	2.764ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	46.563us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	41.122us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	112.764us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	112.764us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	46.687us	5	5	100.00
		pattgen_csr_rw	3.000s	13.641us	20	20	100.00
		pattgen_csr_aliasing	3.000s	65.934us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	25.861us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	46.687us	5	5	100.00
		pattgen_csr_rw	3.000s	13.641us	20	20	100.00
		pattgen_csr_aliasing	3.000s	65.934us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	25.861us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	110.301us	20	20	100.00
		pattgen_sec_cm	3.000s	492.155us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	110.301us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	30.567m	135.388ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			488	520	93.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 30 failures:

Test pattgen_stress_all_with_rand_reset has 30 failures.

0.pattgen_stress_all_with_rand_reset.110987980717926166883446694819179253260536562677901843639559791757129433394309
Line 916, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 121191388301 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 121191413089 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 121191413089 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 5/5
  UVM_INFO @ 121191573089 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.105457541998337691365610332293167421446206564131827544165575007718680052165842
Line 384, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5032830879 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 5032835256 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 5032835256 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 5032930998 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 28 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 9.pattgen_stress_all_with_rand_reset.93930389268513544322822489656121730042672940661351688146245048840320740612940
    Line 415, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7290897357 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - 33.pattgen_stress_all_with_rand_reset.10947389964327975672814099228257871599595721891334838389483691119262467304576
    Line 443, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/33.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29778226210 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```