PATTGEN Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: `9f20940d49`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	22.000s	318.897us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	97.207us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	45.949us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	118.573us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	57.172us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	5.000s	57.493us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	45.949us	20	20	100.00
		pattgen_csr_aliasing	3.000s	57.172us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.967m	5.651ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.783m	2.745ms	50	50	100.00
V2	error	pattgen_error	4.000s	41.964us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.817m	17.185ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	32.654us	50	50	100.00
V2	intr_test	pattgen_intr_test	4.000s	18.811us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	581.838us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	581.838us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	97.207us	5	5	100.00
		pattgen_csr_rw	3.000s	45.949us	20	20	100.00
		pattgen_csr_aliasing	3.000s	57.172us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	28.192us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	97.207us	5	5	100.00
		pattgen_csr_rw	3.000s	45.949us	20	20	100.00
		pattgen_csr_aliasing	3.000s	57.172us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	28.192us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	324.457us	20	20	100.00
		pattgen_sec_cm	3.000s	34.906us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	324.457us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	40.000m	92.308ms	16	50	32.00
V3		TOTAL			16	50	32.00
	Unmapped tests	pattgen_inactive_level	6.183m	10.004ms	43	50	86.00
		TOTAL			529	570	92.81

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:

Test pattgen_stress_all_with_rand_reset has 32 failures.

2.pattgen_stress_all_with_rand_reset.115100978739291656087604011247706303492916063542824058521067700870092140433570
Line 103, in log /workspaces/repo/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 225911310 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 225931829 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 225931829 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 225994328 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

3.pattgen_stress_all_with_rand_reset.87487238535062552608057847461872658217347051171070403007325064247736996158401
Line 103, in log /workspaces/repo/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 433659657 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 433678331 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 433678331 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 433758331 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 30 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 12.pattgen_stress_all_with_rand_reset.110714270838910755941728074210864630104481811489006542813437500102152356765482
    Line 713, in log /workspaces/repo/scratch/os_regression/pattgen-sim-xcelium/12.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 306421472567 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 47.pattgen_stress_all_with_rand_reset.19133765793278630752675883129762174005323255440444930485742396256291688141525
    Line 886, in log /workspaces/repo/scratch/os_regression/pattgen-sim-xcelium/47.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 53024853717 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 12.pattgen_inactive_level.85801348456095818440472823350689863503776304555013247975866664923217712816354
    Line 89, in log /workspaces/repo/scratch/os_regression/pattgen-sim-xcelium/12.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10145555826 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x84a62c90, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
  UVM_INFO @ 10145555826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=29) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 17.pattgen_inactive_level.100703583987596846987615553804805151327330485471694649182617064656250880839803
    Line 89, in log /workspaces/repo/scratch/os_regression/pattgen-sim-xcelium/17.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10319637581 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8d1f1ad0, Comparison=CompareOpEq, exp_data=0x0, call_count=29)
  UVM_INFO @ 10319637581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 23.pattgen_inactive_level.20609390132800695119801445208596044281932402695074771525822207548968099046955
    Line 89, in log /workspaces/repo/scratch/os_regression/pattgen-sim-xcelium/23.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10009060002 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x9b035510, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10009060002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 30.pattgen_inactive_level.26540919405467147513526098951340947825952134988702580178279759901789614742809
    Line 89, in log /workspaces/repo/scratch/os_regression/pattgen-sim-xcelium/30.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10010617009 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x20768c50, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10010617009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 33.pattgen_inactive_level.79072126996502327583749905085226595775332788852701486242940191375061432265099
    Line 89, in log /workspaces/repo/scratch/os_regression/pattgen-sim-xcelium/33.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10004233040 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x7d3cec90, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10004233040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 36.pattgen_inactive_level.54665383366862002149806543491266048936438620704067023085013247002380197065355
    Line 89, in log /workspaces/repo/scratch/os_regression/pattgen-sim-xcelium/36.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10022140510 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc4b05190, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
  UVM_INFO @ 10022140510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 41.pattgen_inactive_level.79399581722602589996077970298523985576669697981887360268965665465073819545256
    Line 89, in log /workspaces/repo/scratch/os_regression/pattgen-sim-xcelium/41.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10074599545 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc32eec10, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10074599545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```