PATTGEN Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: `12e3b8572e`

Branch: os_regression_2024_10_14

Simulator: XCELIUM

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	35.000s	288.608us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	13.201us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	53.000s	13.575us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	2.145ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	37.161us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.033m	76.733us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	53.000s	13.575us	20	20	100.00
		pattgen_csr_aliasing	4.000s	37.161us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.917m	15.493ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.867m	5.345ms	50	50	100.00
V2	error	pattgen_error	38.000s	99.862us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.767m	5.438ms	50	50	100.00
V2	alert_test	pattgen_alert_test	37.000s	86.228us	50	50	100.00
V2	intr_test	pattgen_intr_test	49.000s	36.432us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	1.100m	49.183us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	1.100m	49.183us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	13.201us	5	5	100.00
		pattgen_csr_rw	53.000s	13.575us	20	20	100.00
		pattgen_csr_aliasing	4.000s	37.161us	5	5	100.00
		pattgen_same_csr_outstanding	56.000s	36.336us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	13.201us	5	5	100.00
		pattgen_csr_rw	53.000s	13.575us	20	20	100.00
		pattgen_csr_aliasing	4.000s	37.161us	5	5	100.00
		pattgen_same_csr_outstanding	56.000s	36.336us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	1.067m	60.337us	20	20	100.00
		pattgen_sec_cm	3.000s	496.142us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	1.067m	60.337us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	3.317m	51.350ms	2	50	4.00
V3		TOTAL			2	50	4.00
	Unmapped tests	pattgen_inactive_level	1.283m	10.027ms	48	50	96.00
		TOTAL			520	570	91.23

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 45 failures:

Test pattgen_stress_all_with_rand_reset has 45 failures.

0.pattgen_stress_all_with_rand_reset.83348021052304164628219875822199694231980777849387139990118518417611761361014
Line 149, in log /workspaces/repo/scratch/os_regression_2024_10_14/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1395267049 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1395272797 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1395272797 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/5
  UVM_INFO @ 1395302797 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.88128472004178308874360352239538414205269852850209833482057825619317317709895
Line 105, in log /workspaces/repo/scratch/os_regression_2024_10_14/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1567147563 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1567155033 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1567155033 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 1567525403 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 43 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 9.pattgen_stress_all_with_rand_reset.45881964251029237396145654120980667843215734099437583122025109509510105024040
    Line 165, in log /workspaces/repo/scratch/os_regression_2024_10_14/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2198807730 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 28.pattgen_stress_all_with_rand_reset.51630144251052971967645597016345777414089259869324509856641385764274081095320
    Line 192, in log /workspaces/repo/scratch/os_regression_2024_10_14/pattgen-sim-xcelium/28.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3190799960 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 13.pattgen_inactive_level.54793250266928397174397744096380817742956901739532558970718560268792694765371
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_10_14/pattgen-sim-xcelium/13.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10127709454 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa5c67110, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
  UVM_INFO @ 10127709454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 24.pattgen_inactive_level.54303558140593657293487371434171475992568199364650533026460166514488876861685
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_10_14/pattgen-sim-xcelium/24.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10027037713 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc3e63fd0, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10027037713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```