f8b3c19a2
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pattgen_smoke | 8.000s | 354.792us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pattgen_csr_hw_reset | 4.000s | 19.201us | 5 | 5 | 100.00 |
V1 | csr_rw | pattgen_csr_rw | 5.000s | 30.061us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pattgen_csr_bit_bash | 4.000s | 106.459us | 5 | 5 | 100.00 |
V1 | csr_aliasing | pattgen_csr_aliasing | 3.000s | 47.672us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 4.000s | 92.636us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 5.000s | 30.061us | 20 | 20 | 100.00 |
pattgen_csr_aliasing | 3.000s | 47.672us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | perf | pattgen_perf | 2.750m | 4.113ms | 50 | 50 | 100.00 |
V2 | cnt_rollover | cnt_rollover | 1.900m | 2.635ms | 50 | 50 | 100.00 |
V2 | error | pattgen_error | 4.000s | 38.619us | 50 | 50 | 100.00 |
V2 | stress_all | pattgen_stress_all | 3.633m | 21.090ms | 50 | 50 | 100.00 |
V2 | alert_test | pattgen_alert_test | 4.000s | 14.998us | 50 | 50 | 100.00 |
V2 | intr_test | pattgen_intr_test | 4.000s | 24.256us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pattgen_tl_errors | 6.000s | 103.022us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pattgen_tl_errors | 6.000s | 103.022us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 4.000s | 19.201us | 5 | 5 | 100.00 |
pattgen_csr_rw | 5.000s | 30.061us | 20 | 20 | 100.00 | ||
pattgen_csr_aliasing | 3.000s | 47.672us | 5 | 5 | 100.00 | ||
pattgen_same_csr_outstanding | 5.000s | 96.056us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pattgen_csr_hw_reset | 4.000s | 19.201us | 5 | 5 | 100.00 |
pattgen_csr_rw | 5.000s | 30.061us | 20 | 20 | 100.00 | ||
pattgen_csr_aliasing | 3.000s | 47.672us | 5 | 5 | 100.00 | ||
pattgen_same_csr_outstanding | 5.000s | 96.056us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 340 | 340 | 100.00 | |||
V2S | tl_intg_err | pattgen_tl_intg_err | 5.000s | 178.344us | 20 | 20 | 100.00 |
pattgen_sec_cm | 3.000s | 60.781us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 5.000s | 178.344us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 31.333m | 486.091ms | 46 | 50 | 92.00 |
V3 | TOTAL | 46 | 50 | 92.00 | |||
TOTAL | 516 | 520 | 99.23 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 8 | 8 | 8 | 100.00 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.81 | 100.00 | 100.00 | 100.00 | 99.06 | 96.13 | -- | 100.00 | 90.43 |
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard]
has 4 failures:
0.pattgen_stress_all_with_rand_reset.1765135648
Line 710, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 90726411095 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
12.pattgen_stress_all_with_rand_reset.3676483998
Line 705, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/12.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 168572618769 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
... and 2 more failures.