PATTGEN Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 16.000s 862.741us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 8.000s 63.191us 5 5 100.00
V1 csr_rw pattgen_csr_rw 8.000s 41.891us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 16.000s 690.141us 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 6.000s 81.641us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 8.000s 86.991us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 8.000s 41.891us 20 20 100.00
pattgen_csr_aliasing 6.000s 81.641us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 42.000s 13.180ms 50 50 100.00
V2 cnt_rollover cnt_rollover 28.000s 6.603ms 50 50 100.00
V2 error pattgen_error 16.000s 132.391us 50 50 100.00
V2 stress_all pattgen_stress_all 17.000s 211.591us 50 50 100.00
V2 alert_test pattgen_alert_test 14.000s 42.241us 50 50 100.00
V2 intr_test pattgen_intr_test 12.000s 57.041us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 11.000s 364.691us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 11.000s 364.691us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 8.000s 63.191us 5 5 100.00
pattgen_csr_rw 8.000s 41.891us 20 20 100.00
pattgen_csr_aliasing 6.000s 81.641us 5 5 100.00
pattgen_same_csr_outstanding 11.000s 97.241us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 8.000s 63.191us 5 5 100.00
pattgen_csr_rw 8.000s 41.891us 20 20 100.00
pattgen_csr_aliasing 6.000s 81.641us 5 5 100.00
pattgen_same_csr_outstanding 11.000s 97.241us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 9.000s 226.541us 20 20 100.00
pattgen_sec_cm 16.000s 155.441us 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 9.000s 226.541us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 3.483m 67.654ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 520 520 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.20 100.00 100.00 100.00 99.06 92.74 -- 98.15 90.43

Past Results