| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.67 | 88.67 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 75.00 | 75.00 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/2.prim_async_alert.3396930593 |
| 91.80 | 3.13 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/13.prim_sync_alert.4250585302 |
| 93.66 | 1.86 | 100.00 | 0.00 | 97.92 | 4.17 | 100.00 | 0.00 | 82.14 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1629627110 |
| 94.85 | 1.19 | 100.00 | 0.00 | 97.92 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/18.prim_async_alert.392308502 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1417155385 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.3844236519 |
| /workspace/coverage/default/1.prim_async_alert.749876963 |
| /workspace/coverage/default/10.prim_async_alert.3343084801 |
| /workspace/coverage/default/11.prim_async_alert.3152406340 |
| /workspace/coverage/default/12.prim_async_alert.3063126882 |
| /workspace/coverage/default/13.prim_async_alert.3823342383 |
| /workspace/coverage/default/14.prim_async_alert.3836264990 |
| /workspace/coverage/default/15.prim_async_alert.1167432928 |
| /workspace/coverage/default/16.prim_async_alert.3627614476 |
| /workspace/coverage/default/17.prim_async_alert.781840395 |
| /workspace/coverage/default/19.prim_async_alert.4148436705 |
| /workspace/coverage/default/3.prim_async_alert.3040117486 |
| /workspace/coverage/default/4.prim_async_alert.1841896812 |
| /workspace/coverage/default/5.prim_async_alert.1265225214 |
| /workspace/coverage/default/6.prim_async_alert.1249667882 |
| /workspace/coverage/default/7.prim_async_alert.4193213586 |
| /workspace/coverage/default/8.prim_async_alert.443034840 |
| /workspace/coverage/default/9.prim_async_alert.2569972990 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2540892245 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3491159109 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2810906810 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3851490656 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1589948952 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.212188393 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1439408047 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2836665424 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4013195871 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.993144543 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.626017352 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1413243338 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.599094404 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.905788001 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.903526450 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2328794575 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3223646760 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.2685332602 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.3892658135 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.2291023182 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.540012021 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.2966816202 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.1395814613 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.261516971 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.165366409 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.2109836638 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.1707863328 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.2967447110 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.3687815381 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.1230498908 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.2423507944 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.4285164378 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.4117028628 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.1501130732 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.2948670289 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.274506123 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3735999027 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.210477577 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.694944741 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.322466722 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.615906759 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2151047640 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2878874825 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3817716344 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4149502310 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3362882482 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.846112133 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3361213822 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2301064074 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.918383268 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1344666790 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2162799091 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2304773133 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2910391386 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2375758941 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/12.prim_async_alert.3063126882 | May 23 12:25:17 AM PDT 23 | May 23 12:25:18 AM PDT 23 | 11355624 ps | ||
| T2 | /workspace/coverage/default/1.prim_async_alert.749876963 | May 23 12:25:39 AM PDT 23 | May 23 12:25:40 AM PDT 23 | 11075630 ps | ||
| T3 | /workspace/coverage/default/2.prim_async_alert.3396930593 | May 23 12:23:46 AM PDT 23 | May 23 12:23:46 AM PDT 23 | 12699225 ps | ||
| T15 | /workspace/coverage/default/7.prim_async_alert.4193213586 | May 23 12:25:46 AM PDT 23 | May 23 12:25:46 AM PDT 23 | 10715894 ps | ||
| T9 | /workspace/coverage/default/13.prim_async_alert.3823342383 | May 23 12:23:53 AM PDT 23 | May 23 12:23:54 AM PDT 23 | 10577794 ps | ||
| T10 | /workspace/coverage/default/10.prim_async_alert.3343084801 | May 23 12:25:17 AM PDT 23 | May 23 12:25:18 AM PDT 23 | 11796551 ps | ||
| T13 | /workspace/coverage/default/5.prim_async_alert.1265225214 | May 23 12:22:46 AM PDT 23 | May 23 12:22:47 AM PDT 23 | 12157730 ps | ||
| T23 | /workspace/coverage/default/0.prim_async_alert.3844236519 | May 23 12:22:47 AM PDT 23 | May 23 12:22:47 AM PDT 23 | 11139881 ps | ||
| T7 | /workspace/coverage/default/6.prim_async_alert.1249667882 | May 23 12:25:30 AM PDT 23 | May 23 12:25:31 AM PDT 23 | 10466608 ps | ||
| T24 | /workspace/coverage/default/15.prim_async_alert.1167432928 | May 23 12:19:54 AM PDT 23 | May 23 12:19:54 AM PDT 23 | 11338123 ps | ||
| T11 | /workspace/coverage/default/19.prim_async_alert.4148436705 | May 23 12:25:49 AM PDT 23 | May 23 12:25:50 AM PDT 23 | 10629569 ps | ||
| T14 | /workspace/coverage/default/9.prim_async_alert.2569972990 | May 23 12:25:56 AM PDT 23 | May 23 12:25:57 AM PDT 23 | 11930216 ps | ||
| T8 | /workspace/coverage/default/17.prim_async_alert.781840395 | May 23 12:25:59 AM PDT 23 | May 23 12:26:00 AM PDT 23 | 10373893 ps | ||
| T16 | /workspace/coverage/default/18.prim_async_alert.392308502 | May 23 12:25:59 AM PDT 23 | May 23 12:26:00 AM PDT 23 | 11353180 ps | ||
| T19 | /workspace/coverage/default/16.prim_async_alert.3627614476 | May 23 12:25:48 AM PDT 23 | May 23 12:25:50 AM PDT 23 | 11333823 ps | ||
| T45 | /workspace/coverage/default/3.prim_async_alert.3040117486 | May 23 12:25:42 AM PDT 23 | May 23 12:25:44 AM PDT 23 | 10989965 ps | ||
| T20 | /workspace/coverage/default/8.prim_async_alert.443034840 | May 23 12:25:17 AM PDT 23 | May 23 12:25:18 AM PDT 23 | 11058485 ps | ||
| T46 | /workspace/coverage/default/14.prim_async_alert.3836264990 | May 23 12:20:16 AM PDT 23 | May 23 12:20:17 AM PDT 23 | 10889607 ps | ||
| T25 | /workspace/coverage/default/11.prim_async_alert.3152406340 | May 23 12:25:17 AM PDT 23 | May 23 12:25:18 AM PDT 23 | 12193599 ps | ||
| T47 | /workspace/coverage/default/4.prim_async_alert.1841896812 | May 23 12:23:56 AM PDT 23 | May 23 12:23:57 AM PDT 23 | 11735243 ps | ||
| T26 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.626017352 | May 23 12:18:30 AM PDT 23 | May 23 12:18:30 AM PDT 23 | 29705268 ps | ||
| T40 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2836665424 | May 23 12:18:53 AM PDT 23 | May 23 12:18:54 AM PDT 23 | 30931062 ps | ||
| T41 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3851490656 | May 23 12:18:53 AM PDT 23 | May 23 12:18:53 AM PDT 23 | 29201214 ps | ||
| T21 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.905788001 | May 23 12:18:46 AM PDT 23 | May 23 12:18:47 AM PDT 23 | 30666002 ps | ||
| T42 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1589948952 | May 23 12:18:53 AM PDT 23 | May 23 12:18:53 AM PDT 23 | 30002859 ps | ||
| T22 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2328794575 | May 23 12:18:09 AM PDT 23 | May 23 12:18:10 AM PDT 23 | 29874120 ps | ||
| T38 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.993144543 | May 23 12:18:32 AM PDT 23 | May 23 12:18:32 AM PDT 23 | 29319107 ps | ||
| T4 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1629627110 | May 23 12:18:21 AM PDT 23 | May 23 12:18:22 AM PDT 23 | 30812150 ps | ||
| T43 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4013195871 | May 23 12:18:09 AM PDT 23 | May 23 12:18:10 AM PDT 23 | 29757836 ps | ||
| T44 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1413243338 | May 23 12:18:53 AM PDT 23 | May 23 12:18:53 AM PDT 23 | 27842772 ps | ||
| T48 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.599094404 | May 23 12:18:21 AM PDT 23 | May 23 12:18:21 AM PDT 23 | 28766064 ps | ||
| T49 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.903526450 | May 23 12:18:52 AM PDT 23 | May 23 12:18:53 AM PDT 23 | 32500592 ps | ||
| T50 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2810906810 | May 23 12:18:53 AM PDT 23 | May 23 12:18:53 AM PDT 23 | 30194295 ps | ||
| T51 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1439408047 | May 23 12:18:53 AM PDT 23 | May 23 12:18:53 AM PDT 23 | 30016015 ps | ||
| T39 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2540892245 | May 23 12:18:22 AM PDT 23 | May 23 12:18:22 AM PDT 23 | 31005129 ps | ||
| T52 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.212188393 | May 23 12:18:21 AM PDT 23 | May 23 12:18:22 AM PDT 23 | 31449797 ps | ||
| T53 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3491159109 | May 23 12:18:14 AM PDT 23 | May 23 12:18:14 AM PDT 23 | 30437433 ps | ||
| T17 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3223646760 | May 23 12:18:26 AM PDT 23 | May 23 12:18:26 AM PDT 23 | 29559618 ps | ||
| T36 | /workspace/coverage/sync_alert/14.prim_sync_alert.1395814613 | May 23 12:36:24 AM PDT 23 | May 23 12:36:26 AM PDT 23 | 9471995 ps | ||
| T37 | /workspace/coverage/sync_alert/8.prim_sync_alert.2948670289 | May 23 12:36:15 AM PDT 23 | May 23 12:36:15 AM PDT 23 | 8460691 ps | ||
| T27 | /workspace/coverage/sync_alert/7.prim_sync_alert.1501130732 | May 23 12:36:11 AM PDT 23 | May 23 12:36:12 AM PDT 23 | 8555972 ps | ||
| T28 | /workspace/coverage/sync_alert/19.prim_sync_alert.2967447110 | May 23 12:35:54 AM PDT 23 | May 23 12:35:55 AM PDT 23 | 8772464 ps | ||
| T29 | /workspace/coverage/sync_alert/16.prim_sync_alert.165366409 | May 23 12:36:20 AM PDT 23 | May 23 12:36:21 AM PDT 23 | 8477094 ps | ||
| T30 | /workspace/coverage/sync_alert/11.prim_sync_alert.540012021 | May 23 12:36:17 AM PDT 23 | May 23 12:36:17 AM PDT 23 | 8564800 ps | ||
| T31 | /workspace/coverage/sync_alert/0.prim_sync_alert.2685332602 | May 23 12:36:11 AM PDT 23 | May 23 12:36:12 AM PDT 23 | 9623670 ps | ||
| T32 | /workspace/coverage/sync_alert/6.prim_sync_alert.4117028628 | May 23 12:36:20 AM PDT 23 | May 23 12:36:21 AM PDT 23 | 10165833 ps | ||
| T33 | /workspace/coverage/sync_alert/4.prim_sync_alert.2423507944 | May 23 12:36:03 AM PDT 23 | May 23 12:36:03 AM PDT 23 | 9548606 ps | ||
| T34 | /workspace/coverage/sync_alert/13.prim_sync_alert.4250585302 | May 23 12:36:20 AM PDT 23 | May 23 12:36:21 AM PDT 23 | 8607884 ps | ||
| T35 | /workspace/coverage/sync_alert/1.prim_sync_alert.3892658135 | May 23 12:36:21 AM PDT 23 | May 23 12:36:21 AM PDT 23 | 8814492 ps | ||
| T54 | /workspace/coverage/sync_alert/3.prim_sync_alert.1230498908 | May 23 12:36:20 AM PDT 23 | May 23 12:36:21 AM PDT 23 | 8640363 ps | ||
| T55 | /workspace/coverage/sync_alert/10.prim_sync_alert.2291023182 | May 23 12:36:07 AM PDT 23 | May 23 12:36:08 AM PDT 23 | 9349702 ps | ||
| T56 | /workspace/coverage/sync_alert/18.prim_sync_alert.1707863328 | May 23 12:36:07 AM PDT 23 | May 23 12:36:08 AM PDT 23 | 8916197 ps | ||
| T57 | /workspace/coverage/sync_alert/12.prim_sync_alert.2966816202 | May 23 12:36:01 AM PDT 23 | May 23 12:36:01 AM PDT 23 | 9633052 ps | ||
| T58 | /workspace/coverage/sync_alert/17.prim_sync_alert.2109836638 | May 23 12:36:20 AM PDT 23 | May 23 12:36:21 AM PDT 23 | 10139162 ps | ||
| T59 | /workspace/coverage/sync_alert/5.prim_sync_alert.4285164378 | May 23 12:36:22 AM PDT 23 | May 23 12:36:22 AM PDT 23 | 8759102 ps | ||
| T60 | /workspace/coverage/sync_alert/9.prim_sync_alert.274506123 | May 23 12:36:06 AM PDT 23 | May 23 12:36:07 AM PDT 23 | 9271882 ps | ||
| T61 | /workspace/coverage/sync_alert/2.prim_sync_alert.3687815381 | May 23 12:36:08 AM PDT 23 | May 23 12:36:08 AM PDT 23 | 9271820 ps | ||
| T62 | /workspace/coverage/sync_alert/15.prim_sync_alert.261516971 | May 23 12:36:09 AM PDT 23 | May 23 12:36:10 AM PDT 23 | 10062815 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.918383268 | May 23 12:18:00 AM PDT 23 | May 23 12:18:01 AM PDT 23 | 26911092 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2878874825 | May 23 12:18:38 AM PDT 23 | May 23 12:18:39 AM PDT 23 | 27261085 ps | ||
| T18 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.694944741 | May 23 12:18:06 AM PDT 23 | May 23 12:18:06 AM PDT 23 | 28187305 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.210477577 | May 23 12:18:09 AM PDT 23 | May 23 12:18:10 AM PDT 23 | 27816081 ps | ||
| T12 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1417155385 | May 23 12:18:13 AM PDT 23 | May 23 12:18:14 AM PDT 23 | 27085184 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3735999027 | May 23 12:18:06 AM PDT 23 | May 23 12:18:07 AM PDT 23 | 27467682 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2375758941 | May 23 12:18:06 AM PDT 23 | May 23 12:18:07 AM PDT 23 | 30334942 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.322466722 | May 23 12:18:09 AM PDT 23 | May 23 12:18:10 AM PDT 23 | 26444794 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.615906759 | May 23 12:18:06 AM PDT 23 | May 23 12:18:07 AM PDT 23 | 28731335 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4149502310 | May 23 12:18:14 AM PDT 23 | May 23 12:18:15 AM PDT 23 | 26868420 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2151047640 | May 23 12:18:14 AM PDT 23 | May 23 12:18:14 AM PDT 23 | 28719085 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2301064074 | May 23 12:18:06 AM PDT 23 | May 23 12:18:07 AM PDT 23 | 26819916 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2910391386 | May 23 12:18:14 AM PDT 23 | May 23 12:18:14 AM PDT 23 | 27511413 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3361213822 | May 23 12:18:06 AM PDT 23 | May 23 12:18:06 AM PDT 23 | 28452787 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2162799091 | May 23 12:18:13 AM PDT 23 | May 23 12:18:14 AM PDT 23 | 29390373 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1344666790 | May 23 12:18:14 AM PDT 23 | May 23 12:18:15 AM PDT 23 | 28776629 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3817716344 | May 23 12:18:06 AM PDT 23 | May 23 12:18:07 AM PDT 23 | 27089273 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.846112133 | May 23 12:18:06 AM PDT 23 | May 23 12:18:07 AM PDT 23 | 27590320 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2304773133 | May 23 12:18:06 AM PDT 23 | May 23 12:18:06 AM PDT 23 | 27188515 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3362882482 | May 23 12:18:06 AM PDT 23 | May 23 12:18:07 AM PDT 23 | 28912042 ps |
| Test location | /workspace/coverage/default/2.prim_async_alert.3396930593 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12699225 ps |
| CPU time | 0.38 seconds |
| Started | May 23 12:23:46 AM PDT 23 |
| Finished | May 23 12:23:46 AM PDT 23 |
| Peak memory | 145636 kb |
| Host | smart-54edae52-914d-4a70-bb99-bdfec3f095c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3396930593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3396930593 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.4250585302 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8607884 ps |
| CPU time | 0.38 seconds |
| Started | May 23 12:36:20 AM PDT 23 |
| Finished | May 23 12:36:21 AM PDT 23 |
| Peak memory | 145392 kb |
| Host | smart-f2bc269a-3387-4914-9336-b5e698db056e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4250585302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.4250585302 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1629627110 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30812150 ps |
| CPU time | 0.41 seconds |
| Started | May 23 12:18:21 AM PDT 23 |
| Finished | May 23 12:18:22 AM PDT 23 |
| Peak memory | 145872 kb |
| Host | smart-b7cd3ccb-6a19-4743-8beb-523f899a5a04 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1629627110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1629627110 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.392308502 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11353180 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:25:59 AM PDT 23 |
| Finished | May 23 12:26:00 AM PDT 23 |
| Peak memory | 145180 kb |
| Host | smart-0fbe8f8b-1daf-499e-8ebc-714ae1767636 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=392308502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.392308502 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1417155385 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 27085184 ps |
| CPU time | 0.42 seconds |
| Started | May 23 12:18:13 AM PDT 23 |
| Finished | May 23 12:18:14 AM PDT 23 |
| Peak memory | 144516 kb |
| Host | smart-0fa35ede-2751-4637-a5b7-ecdf3b7ac6be |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1417155385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1417155385 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.3844236519 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11139881 ps |
| CPU time | 0.4 seconds |
| Started | May 23 12:22:47 AM PDT 23 |
| Finished | May 23 12:22:47 AM PDT 23 |
| Peak memory | 145660 kb |
| Host | smart-6a2867cb-19a6-4bdb-b8df-3699224166bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3844236519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3844236519 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.749876963 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11075630 ps |
| CPU time | 0.45 seconds |
| Started | May 23 12:25:39 AM PDT 23 |
| Finished | May 23 12:25:40 AM PDT 23 |
| Peak memory | 145320 kb |
| Host | smart-57d40d14-47ed-4e62-946b-5af6dc723fba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=749876963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.749876963 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.3343084801 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11796551 ps |
| CPU time | 0.51 seconds |
| Started | May 23 12:25:17 AM PDT 23 |
| Finished | May 23 12:25:18 AM PDT 23 |
| Peak memory | 144832 kb |
| Host | smart-eba9a448-5084-426e-9f54-e72d664bbfbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3343084801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3343084801 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.3152406340 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 12193599 ps |
| CPU time | 0.52 seconds |
| Started | May 23 12:25:17 AM PDT 23 |
| Finished | May 23 12:25:18 AM PDT 23 |
| Peak memory | 144340 kb |
| Host | smart-b86ee68b-c9a4-415a-9a04-b324bfc2e458 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3152406340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3152406340 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.3063126882 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11355624 ps |
| CPU time | 0.56 seconds |
| Started | May 23 12:25:17 AM PDT 23 |
| Finished | May 23 12:25:18 AM PDT 23 |
| Peak memory | 143996 kb |
| Host | smart-7383a1c2-4b1a-4fab-9682-e225378339fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3063126882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3063126882 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.3823342383 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10577794 ps |
| CPU time | 0.43 seconds |
| Started | May 23 12:23:53 AM PDT 23 |
| Finished | May 23 12:23:54 AM PDT 23 |
| Peak memory | 145316 kb |
| Host | smart-30df8460-5793-47a8-8c8c-e8ed7b52ae26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3823342383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3823342383 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.3836264990 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10889607 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:20:16 AM PDT 23 |
| Finished | May 23 12:20:17 AM PDT 23 |
| Peak memory | 145368 kb |
| Host | smart-4b78a297-ba0c-47b0-9be9-a5b623b3cffb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3836264990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3836264990 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.1167432928 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11338123 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:19:54 AM PDT 23 |
| Finished | May 23 12:19:54 AM PDT 23 |
| Peak memory | 145412 kb |
| Host | smart-1b26270e-d8f2-43b4-a100-495140d43c78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1167432928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1167432928 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.3627614476 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11333823 ps |
| CPU time | 0.46 seconds |
| Started | May 23 12:25:48 AM PDT 23 |
| Finished | May 23 12:25:50 AM PDT 23 |
| Peak memory | 145568 kb |
| Host | smart-8708ae5a-4ec7-417f-9232-51d2e49fe541 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3627614476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3627614476 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.781840395 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10373893 ps |
| CPU time | 0.41 seconds |
| Started | May 23 12:25:59 AM PDT 23 |
| Finished | May 23 12:26:00 AM PDT 23 |
| Peak memory | 145472 kb |
| Host | smart-f7cfe298-cc5d-4ddb-9472-387485e0328a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=781840395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.781840395 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.4148436705 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10629569 ps |
| CPU time | 0.4 seconds |
| Started | May 23 12:25:49 AM PDT 23 |
| Finished | May 23 12:25:50 AM PDT 23 |
| Peak memory | 145552 kb |
| Host | smart-8e36fcae-e623-4a43-8a36-c1a206fc8bac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4148436705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.4148436705 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.3040117486 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 10989965 ps |
| CPU time | 0.42 seconds |
| Started | May 23 12:25:42 AM PDT 23 |
| Finished | May 23 12:25:44 AM PDT 23 |
| Peak memory | 145392 kb |
| Host | smart-15eca6a3-d8d4-49c3-b999-e6e0157b635d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3040117486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3040117486 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.1841896812 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11735243 ps |
| CPU time | 0.4 seconds |
| Started | May 23 12:23:56 AM PDT 23 |
| Finished | May 23 12:23:57 AM PDT 23 |
| Peak memory | 145456 kb |
| Host | smart-d51c46d6-9ad5-45e6-ba20-9df0109ebf72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1841896812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1841896812 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.1265225214 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 12157730 ps |
| CPU time | 0.4 seconds |
| Started | May 23 12:22:46 AM PDT 23 |
| Finished | May 23 12:22:47 AM PDT 23 |
| Peak memory | 145800 kb |
| Host | smart-c4376991-69d6-44eb-909f-485dfa48e853 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1265225214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1265225214 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.1249667882 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10466608 ps |
| CPU time | 0.44 seconds |
| Started | May 23 12:25:30 AM PDT 23 |
| Finished | May 23 12:25:31 AM PDT 23 |
| Peak memory | 145328 kb |
| Host | smart-4deebfdc-8005-43b6-8492-de9c4da3ae06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249667882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1249667882 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.4193213586 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10715894 ps |
| CPU time | 0.38 seconds |
| Started | May 23 12:25:46 AM PDT 23 |
| Finished | May 23 12:25:46 AM PDT 23 |
| Peak memory | 145468 kb |
| Host | smart-ddf6b294-1fea-4803-a069-499b07a67327 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4193213586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.4193213586 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.443034840 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11058485 ps |
| CPU time | 0.57 seconds |
| Started | May 23 12:25:17 AM PDT 23 |
| Finished | May 23 12:25:18 AM PDT 23 |
| Peak memory | 144484 kb |
| Host | smart-710b388d-d153-48db-bed1-5ed0099c29d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=443034840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.443034840 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.2569972990 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11930216 ps |
| CPU time | 0.44 seconds |
| Started | May 23 12:25:56 AM PDT 23 |
| Finished | May 23 12:25:57 AM PDT 23 |
| Peak memory | 144792 kb |
| Host | smart-534f5628-db63-4b44-a703-1847b0bb9bb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2569972990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2569972990 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2540892245 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 31005129 ps |
| CPU time | 0.41 seconds |
| Started | May 23 12:18:22 AM PDT 23 |
| Finished | May 23 12:18:22 AM PDT 23 |
| Peak memory | 145872 kb |
| Host | smart-12201b3b-ff82-4b9c-b425-dad37204d55b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2540892245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2540892245 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3491159109 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 30437433 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:18:14 AM PDT 23 |
| Finished | May 23 12:18:14 AM PDT 23 |
| Peak memory | 146456 kb |
| Host | smart-6498ae73-cc93-4f64-9ae6-0c9219501564 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3491159109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3491159109 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2810906810 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 30194295 ps |
| CPU time | 0.45 seconds |
| Started | May 23 12:18:53 AM PDT 23 |
| Finished | May 23 12:18:53 AM PDT 23 |
| Peak memory | 145520 kb |
| Host | smart-7302edcf-e82d-4e1e-9085-cb37df10d980 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2810906810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2810906810 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3851490656 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29201214 ps |
| CPU time | 0.4 seconds |
| Started | May 23 12:18:53 AM PDT 23 |
| Finished | May 23 12:18:53 AM PDT 23 |
| Peak memory | 145520 kb |
| Host | smart-37b66d94-25f9-4738-ae67-54f305cecf82 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3851490656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3851490656 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1589948952 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 30002859 ps |
| CPU time | 0.4 seconds |
| Started | May 23 12:18:53 AM PDT 23 |
| Finished | May 23 12:18:53 AM PDT 23 |
| Peak memory | 145520 kb |
| Host | smart-5e31a171-2368-4794-b7d9-ecee0ab2f503 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1589948952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1589948952 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.212188393 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 31449797 ps |
| CPU time | 0.41 seconds |
| Started | May 23 12:18:21 AM PDT 23 |
| Finished | May 23 12:18:22 AM PDT 23 |
| Peak memory | 145872 kb |
| Host | smart-6f72ca06-d276-422a-99d6-a6d0cec615b9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=212188393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.212188393 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1439408047 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 30016015 ps |
| CPU time | 0.42 seconds |
| Started | May 23 12:18:53 AM PDT 23 |
| Finished | May 23 12:18:53 AM PDT 23 |
| Peak memory | 145520 kb |
| Host | smart-f1efb3d4-7e2a-4677-885c-78a169bbf2e7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1439408047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1439408047 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2836665424 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 30931062 ps |
| CPU time | 0.41 seconds |
| Started | May 23 12:18:53 AM PDT 23 |
| Finished | May 23 12:18:54 AM PDT 23 |
| Peak memory | 145520 kb |
| Host | smart-21f53957-0736-4ab8-bbc5-552ebc6728ac |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2836665424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2836665424 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4013195871 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 29757836 ps |
| CPU time | 0.41 seconds |
| Started | May 23 12:18:09 AM PDT 23 |
| Finished | May 23 12:18:10 AM PDT 23 |
| Peak memory | 145272 kb |
| Host | smart-f650209d-408a-4f17-b586-9b5c9f913d5f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4013195871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.4013195871 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.993144543 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 29319107 ps |
| CPU time | 0.41 seconds |
| Started | May 23 12:18:32 AM PDT 23 |
| Finished | May 23 12:18:32 AM PDT 23 |
| Peak memory | 145872 kb |
| Host | smart-dfb2b253-2cff-42f1-9c6f-50730ddc4d25 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=993144543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.993144543 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.626017352 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 29705268 ps |
| CPU time | 0.41 seconds |
| Started | May 23 12:18:30 AM PDT 23 |
| Finished | May 23 12:18:30 AM PDT 23 |
| Peak memory | 145940 kb |
| Host | smart-f78ebd27-d4c4-406c-a173-ff785215d24b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=626017352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.626017352 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1413243338 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 27842772 ps |
| CPU time | 0.43 seconds |
| Started | May 23 12:18:53 AM PDT 23 |
| Finished | May 23 12:18:53 AM PDT 23 |
| Peak memory | 145520 kb |
| Host | smart-0cd098da-4344-48dd-8dfd-35751b4e0ec1 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1413243338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1413243338 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.599094404 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 28766064 ps |
| CPU time | 0.41 seconds |
| Started | May 23 12:18:21 AM PDT 23 |
| Finished | May 23 12:18:21 AM PDT 23 |
| Peak memory | 145940 kb |
| Host | smart-454d7f9f-804f-49bc-b09d-1b07ed7734be |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=599094404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.599094404 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.905788001 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 30666002 ps |
| CPU time | 0.38 seconds |
| Started | May 23 12:18:46 AM PDT 23 |
| Finished | May 23 12:18:47 AM PDT 23 |
| Peak memory | 145468 kb |
| Host | smart-a1e7179d-0767-42e2-be9d-1afaab9edccd |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=905788001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.905788001 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.903526450 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 32500592 ps |
| CPU time | 0.4 seconds |
| Started | May 23 12:18:52 AM PDT 23 |
| Finished | May 23 12:18:53 AM PDT 23 |
| Peak memory | 145468 kb |
| Host | smart-8bc3e4b6-ce19-457b-b9a2-add933d63963 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=903526450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.903526450 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2328794575 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 29874120 ps |
| CPU time | 0.46 seconds |
| Started | May 23 12:18:09 AM PDT 23 |
| Finished | May 23 12:18:10 AM PDT 23 |
| Peak memory | 145456 kb |
| Host | smart-c8ed5950-8df5-4112-8433-1c6d861dcf0a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2328794575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2328794575 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3223646760 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 29559618 ps |
| CPU time | 0.42 seconds |
| Started | May 23 12:18:26 AM PDT 23 |
| Finished | May 23 12:18:26 AM PDT 23 |
| Peak memory | 145872 kb |
| Host | smart-b9a607b1-ac8c-42a8-b3db-f7a21f81f0ec |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3223646760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3223646760 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.2685332602 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9623670 ps |
| CPU time | 0.4 seconds |
| Started | May 23 12:36:11 AM PDT 23 |
| Finished | May 23 12:36:12 AM PDT 23 |
| Peak memory | 145364 kb |
| Host | smart-dd453b80-0d32-45c1-a21f-1c49fef34923 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2685332602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2685332602 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.3892658135 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8814492 ps |
| CPU time | 0.38 seconds |
| Started | May 23 12:36:21 AM PDT 23 |
| Finished | May 23 12:36:21 AM PDT 23 |
| Peak memory | 145392 kb |
| Host | smart-bfd68e6c-5341-437b-beb7-2d72565bddc0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3892658135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3892658135 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.2291023182 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 9349702 ps |
| CPU time | 0.42 seconds |
| Started | May 23 12:36:07 AM PDT 23 |
| Finished | May 23 12:36:08 AM PDT 23 |
| Peak memory | 145400 kb |
| Host | smart-4caa1563-c5b2-40f4-ad31-f5e12e46647d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2291023182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2291023182 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.540012021 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8564800 ps |
| CPU time | 0.38 seconds |
| Started | May 23 12:36:17 AM PDT 23 |
| Finished | May 23 12:36:17 AM PDT 23 |
| Peak memory | 145404 kb |
| Host | smart-1885a6e2-0eb0-4b39-9a21-1271b690f3d5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=540012021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.540012021 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.2966816202 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9633052 ps |
| CPU time | 0.37 seconds |
| Started | May 23 12:36:01 AM PDT 23 |
| Finished | May 23 12:36:01 AM PDT 23 |
| Peak memory | 145404 kb |
| Host | smart-98054641-4c1b-4e00-ad97-59746fcab2d1 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2966816202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2966816202 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.1395814613 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9471995 ps |
| CPU time | 0.38 seconds |
| Started | May 23 12:36:24 AM PDT 23 |
| Finished | May 23 12:36:26 AM PDT 23 |
| Peak memory | 145160 kb |
| Host | smart-6e4dfe84-7b3e-4c48-8eb6-4a19f569391b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1395814613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1395814613 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.261516971 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 10062815 ps |
| CPU time | 0.38 seconds |
| Started | May 23 12:36:09 AM PDT 23 |
| Finished | May 23 12:36:10 AM PDT 23 |
| Peak memory | 145492 kb |
| Host | smart-536f60c6-24bc-416c-9f4e-99aaf6c05e44 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=261516971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.261516971 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.165366409 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8477094 ps |
| CPU time | 0.38 seconds |
| Started | May 23 12:36:20 AM PDT 23 |
| Finished | May 23 12:36:21 AM PDT 23 |
| Peak memory | 145396 kb |
| Host | smart-d1cd6b57-41bd-4601-bbf8-7644d8f6ceed |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=165366409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.165366409 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.2109836638 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 10139162 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:36:20 AM PDT 23 |
| Finished | May 23 12:36:21 AM PDT 23 |
| Peak memory | 145288 kb |
| Host | smart-6f141d2b-75d9-4db9-8992-b2c5a6e85a0d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2109836638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2109836638 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.1707863328 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 8916197 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:36:07 AM PDT 23 |
| Finished | May 23 12:36:08 AM PDT 23 |
| Peak memory | 145400 kb |
| Host | smart-349b824b-a36c-41d5-9781-9c01ffc29039 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1707863328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1707863328 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.2967447110 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8772464 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:35:54 AM PDT 23 |
| Finished | May 23 12:35:55 AM PDT 23 |
| Peak memory | 145680 kb |
| Host | smart-288f7e86-dced-4096-80b3-b1c2dcb6ffb0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2967447110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2967447110 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.3687815381 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9271820 ps |
| CPU time | 0.42 seconds |
| Started | May 23 12:36:08 AM PDT 23 |
| Finished | May 23 12:36:08 AM PDT 23 |
| Peak memory | 145376 kb |
| Host | smart-1622890c-7ae9-4dc8-94df-b9622cdc1288 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3687815381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3687815381 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.1230498908 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 8640363 ps |
| CPU time | 0.38 seconds |
| Started | May 23 12:36:20 AM PDT 23 |
| Finished | May 23 12:36:21 AM PDT 23 |
| Peak memory | 145392 kb |
| Host | smart-8af2841e-6404-4ac9-a4c0-c9a1682e724a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1230498908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1230498908 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.2423507944 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9548606 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:36:03 AM PDT 23 |
| Finished | May 23 12:36:03 AM PDT 23 |
| Peak memory | 145404 kb |
| Host | smart-c56b7cfe-67d8-4020-a89d-92f023d49ac9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2423507944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2423507944 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.4285164378 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 8759102 ps |
| CPU time | 0.37 seconds |
| Started | May 23 12:36:22 AM PDT 23 |
| Finished | May 23 12:36:22 AM PDT 23 |
| Peak memory | 145488 kb |
| Host | smart-caf8f09b-e520-4443-a3cf-4c3495ffb9b9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4285164378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.4285164378 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.4117028628 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 10165833 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:36:20 AM PDT 23 |
| Finished | May 23 12:36:21 AM PDT 23 |
| Peak memory | 145392 kb |
| Host | smart-15569430-8836-4b06-b23d-63a03a00b605 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4117028628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.4117028628 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.1501130732 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8555972 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:36:11 AM PDT 23 |
| Finished | May 23 12:36:12 AM PDT 23 |
| Peak memory | 145364 kb |
| Host | smart-82e9bae7-947a-48a4-ad59-049caf66b8d9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1501130732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1501130732 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.2948670289 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8460691 ps |
| CPU time | 0.38 seconds |
| Started | May 23 12:36:15 AM PDT 23 |
| Finished | May 23 12:36:15 AM PDT 23 |
| Peak memory | 145388 kb |
| Host | smart-cbb44ac3-f488-4bfc-8382-43f4a5fc81a8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2948670289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2948670289 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.274506123 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9271882 ps |
| CPU time | 0.38 seconds |
| Started | May 23 12:36:06 AM PDT 23 |
| Finished | May 23 12:36:07 AM PDT 23 |
| Peak memory | 145404 kb |
| Host | smart-411596d9-6976-4707-b06f-fc36a4627a71 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=274506123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.274506123 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3735999027 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 27467682 ps |
| CPU time | 0.43 seconds |
| Started | May 23 12:18:06 AM PDT 23 |
| Finished | May 23 12:18:07 AM PDT 23 |
| Peak memory | 143936 kb |
| Host | smart-f0f28576-a330-4f1a-afbb-f9e33677f8df |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3735999027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3735999027 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.210477577 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 27816081 ps |
| CPU time | 0.4 seconds |
| Started | May 23 12:18:09 AM PDT 23 |
| Finished | May 23 12:18:10 AM PDT 23 |
| Peak memory | 144508 kb |
| Host | smart-ad13cb96-1574-4eac-86af-77f6a77d873d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=210477577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.210477577 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.694944741 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 28187305 ps |
| CPU time | 0.41 seconds |
| Started | May 23 12:18:06 AM PDT 23 |
| Finished | May 23 12:18:06 AM PDT 23 |
| Peak memory | 144464 kb |
| Host | smart-2841e9b5-5609-4cb5-a060-8ff7eb523654 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=694944741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.694944741 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.322466722 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 26444794 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:18:09 AM PDT 23 |
| Finished | May 23 12:18:10 AM PDT 23 |
| Peak memory | 144540 kb |
| Host | smart-439032b5-3ac3-40fb-a901-7480f4d5f388 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=322466722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.322466722 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.615906759 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 28731335 ps |
| CPU time | 0.45 seconds |
| Started | May 23 12:18:06 AM PDT 23 |
| Finished | May 23 12:18:07 AM PDT 23 |
| Peak memory | 143224 kb |
| Host | smart-7a2bc12f-d8e2-4074-8aeb-65f26ec1ee37 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=615906759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.615906759 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2151047640 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 28719085 ps |
| CPU time | 0.37 seconds |
| Started | May 23 12:18:14 AM PDT 23 |
| Finished | May 23 12:18:14 AM PDT 23 |
| Peak memory | 144328 kb |
| Host | smart-292917ab-f3b9-4540-8193-4c3b072de680 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2151047640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2151047640 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2878874825 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27261085 ps |
| CPU time | 0.43 seconds |
| Started | May 23 12:18:38 AM PDT 23 |
| Finished | May 23 12:18:39 AM PDT 23 |
| Peak memory | 144952 kb |
| Host | smart-eb6e4331-9146-4908-a106-45af22a92ece |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2878874825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2878874825 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3817716344 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27089273 ps |
| CPU time | 0.43 seconds |
| Started | May 23 12:18:06 AM PDT 23 |
| Finished | May 23 12:18:07 AM PDT 23 |
| Peak memory | 144028 kb |
| Host | smart-d31a4aa4-9ee8-4a4f-b956-8946c331dbb1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3817716344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3817716344 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4149502310 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 26868420 ps |
| CPU time | 0.4 seconds |
| Started | May 23 12:18:14 AM PDT 23 |
| Finished | May 23 12:18:15 AM PDT 23 |
| Peak memory | 145484 kb |
| Host | smart-6aadecbd-a8bc-47d0-9028-17b2bccbf1c3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4149502310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.4149502310 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3362882482 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 28912042 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:18:06 AM PDT 23 |
| Finished | May 23 12:18:07 AM PDT 23 |
| Peak memory | 144868 kb |
| Host | smart-c9a15edd-8ece-472a-a7cd-147df944e441 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3362882482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3362882482 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.846112133 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27590320 ps |
| CPU time | 0.44 seconds |
| Started | May 23 12:18:06 AM PDT 23 |
| Finished | May 23 12:18:07 AM PDT 23 |
| Peak memory | 143000 kb |
| Host | smart-60500033-39b2-4be3-b3aa-f8d4e9c66bf1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=846112133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.846112133 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3361213822 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 28452787 ps |
| CPU time | 0.44 seconds |
| Started | May 23 12:18:06 AM PDT 23 |
| Finished | May 23 12:18:06 AM PDT 23 |
| Peak memory | 143860 kb |
| Host | smart-8fbf977d-32cc-406e-873a-dd4df67b6b9e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3361213822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3361213822 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2301064074 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 26819916 ps |
| CPU time | 0.46 seconds |
| Started | May 23 12:18:06 AM PDT 23 |
| Finished | May 23 12:18:07 AM PDT 23 |
| Peak memory | 142996 kb |
| Host | smart-4db18bea-9602-4110-b436-b61a8d3d2326 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2301064074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2301064074 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.918383268 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 26911092 ps |
| CPU time | 0.42 seconds |
| Started | May 23 12:18:00 AM PDT 23 |
| Finished | May 23 12:18:01 AM PDT 23 |
| Peak memory | 144488 kb |
| Host | smart-ad93bf14-8b39-4458-9e01-f10dfa997c04 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=918383268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.918383268 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1344666790 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 28776629 ps |
| CPU time | 0.4 seconds |
| Started | May 23 12:18:14 AM PDT 23 |
| Finished | May 23 12:18:15 AM PDT 23 |
| Peak memory | 145688 kb |
| Host | smart-3d5202ae-ac90-4a92-9d59-7ac7b0fb2087 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1344666790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1344666790 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2162799091 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 29390373 ps |
| CPU time | 0.43 seconds |
| Started | May 23 12:18:13 AM PDT 23 |
| Finished | May 23 12:18:14 AM PDT 23 |
| Peak memory | 144604 kb |
| Host | smart-58bcea13-c530-49d4-b20f-d17432b61fa0 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2162799091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2162799091 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2304773133 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 27188515 ps |
| CPU time | 0.43 seconds |
| Started | May 23 12:18:06 AM PDT 23 |
| Finished | May 23 12:18:06 AM PDT 23 |
| Peak memory | 144116 kb |
| Host | smart-6604c117-bdce-4a53-9e62-3d35cb4f37d0 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2304773133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2304773133 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2910391386 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 27511413 ps |
| CPU time | 0.38 seconds |
| Started | May 23 12:18:14 AM PDT 23 |
| Finished | May 23 12:18:14 AM PDT 23 |
| Peak memory | 144468 kb |
| Host | smart-1a4b2b80-02cd-4910-b998-bbb2062dbbb4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2910391386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2910391386 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2375758941 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 30334942 ps |
| CPU time | 0.38 seconds |
| Started | May 23 12:18:06 AM PDT 23 |
| Finished | May 23 12:18:07 AM PDT 23 |
| Peak memory | 144920 kb |
| Host | smart-017f80f4-a8c5-4866-b49d-d19f231d222a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2375758941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2375758941 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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