Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.85	100.00	97.92	100.00	89.29	95.83	86.05

Total tests in report: 80

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
89.27	89.27	100.00	100.00	93.75	93.75	100.00	100.00	78.57	78.57	95.83	95.83	67.44	67.44	/workspace/coverage/default/11.prim_async_alert.1551946222
92.39	3.13	100.00	0.00	93.75	0.00	100.00	0.00	85.71	7.14	95.83	0.00	79.07	11.63	/workspace/coverage/sync_alert/18.prim_sync_alert.2719363412
94.25	1.86	100.00	0.00	97.92	4.17	100.00	0.00	85.71	0.00	95.83	0.00	86.05	6.98	/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4104466268
94.85	0.60	100.00	0.00	97.92	0.00	100.00	0.00	89.29	3.57	95.83	0.00	86.05	0.00	/workspace/coverage/default/13.prim_async_alert.2322319808

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.1177091568
/workspace/coverage/default/1.prim_async_alert.1913725389
/workspace/coverage/default/10.prim_async_alert.2551530912
/workspace/coverage/default/12.prim_async_alert.573985727
/workspace/coverage/default/14.prim_async_alert.3434037069
/workspace/coverage/default/15.prim_async_alert.1730527237
/workspace/coverage/default/16.prim_async_alert.336024694
/workspace/coverage/default/17.prim_async_alert.1705199722
/workspace/coverage/default/18.prim_async_alert.2368479371
/workspace/coverage/default/19.prim_async_alert.3378228753
/workspace/coverage/default/2.prim_async_alert.2632335790
/workspace/coverage/default/3.prim_async_alert.2924076859
/workspace/coverage/default/4.prim_async_alert.4005251326
/workspace/coverage/default/5.prim_async_alert.1983051138
/workspace/coverage/default/6.prim_async_alert.484856644
/workspace/coverage/default/7.prim_async_alert.15749270
/workspace/coverage/default/8.prim_async_alert.2086658880
/workspace/coverage/default/9.prim_async_alert.4067191303
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3958803103
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1910304594
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.898015356
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.120123258
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2206434268
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1678724822
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.670964189
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1799890479
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1691712773
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.351977951
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2436426380
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2034547338
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.4151461655
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.897565569
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2465834420
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1120467444
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3117851999
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1245758232
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.898732683
/workspace/coverage/sync_alert/0.prim_sync_alert.2477919047
/workspace/coverage/sync_alert/1.prim_sync_alert.2383334062
/workspace/coverage/sync_alert/10.prim_sync_alert.515957702
/workspace/coverage/sync_alert/11.prim_sync_alert.2132511669
/workspace/coverage/sync_alert/12.prim_sync_alert.2778263491
/workspace/coverage/sync_alert/13.prim_sync_alert.2838829171
/workspace/coverage/sync_alert/14.prim_sync_alert.3158502465
/workspace/coverage/sync_alert/15.prim_sync_alert.4199681142
/workspace/coverage/sync_alert/16.prim_sync_alert.2744597326
/workspace/coverage/sync_alert/17.prim_sync_alert.873141224
/workspace/coverage/sync_alert/19.prim_sync_alert.2703379529
/workspace/coverage/sync_alert/2.prim_sync_alert.4122468422
/workspace/coverage/sync_alert/3.prim_sync_alert.1637785463
/workspace/coverage/sync_alert/4.prim_sync_alert.3527538110
/workspace/coverage/sync_alert/5.prim_sync_alert.1027432718
/workspace/coverage/sync_alert/6.prim_sync_alert.878542415
/workspace/coverage/sync_alert/7.prim_sync_alert.2315211264
/workspace/coverage/sync_alert/8.prim_sync_alert.3719265601
/workspace/coverage/sync_alert/9.prim_sync_alert.121022258
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4147763116
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.591161661
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2851241792
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3410248350
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.364195584
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1092160173
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3984796384
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1386159985
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.476672714
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.230702931
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.963567387
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3785750620
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1600721644
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2021174674
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2153059721
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.654132618
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1947310027
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3492703391
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1826513153
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.457252810

Total test records in report: 80

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/17.prim_async_alert.1705199722	May 25 12:22:41 AM PDT 23	May 25 12:22:41 AM PDT 23	12160008 ps
T2	/workspace/coverage/default/3.prim_async_alert.2924076859	May 25 12:27:59 AM PDT 23	May 25 12:28:00 AM PDT 23	11038528 ps
T3	/workspace/coverage/default/6.prim_async_alert.484856644	May 25 12:22:36 AM PDT 23	May 25 12:22:36 AM PDT 23	10900318 ps
T7	/workspace/coverage/default/18.prim_async_alert.2368479371	May 25 12:26:20 AM PDT 23	May 25 12:26:22 AM PDT 23	11749694 ps
T9	/workspace/coverage/default/8.prim_async_alert.2086658880	May 25 12:26:27 AM PDT 23	May 25 12:26:28 AM PDT 23	11188197 ps
T10	/workspace/coverage/default/11.prim_async_alert.1551946222	May 25 12:27:33 AM PDT 23	May 25 12:27:34 AM PDT 23	12577332 ps
T19	/workspace/coverage/default/14.prim_async_alert.3434037069	May 25 12:24:13 AM PDT 23	May 25 12:24:13 AM PDT 23	11275884 ps
T20	/workspace/coverage/default/0.prim_async_alert.1177091568	May 25 12:24:13 AM PDT 23	May 25 12:24:15 AM PDT 23	11093378 ps
T11	/workspace/coverage/default/19.prim_async_alert.3378228753	May 25 12:24:38 AM PDT 23	May 25 12:24:38 AM PDT 23	11990809 ps
T21	/workspace/coverage/default/15.prim_async_alert.1730527237	May 25 12:22:58 AM PDT 23	May 25 12:22:59 AM PDT 23	11241107 ps
T15	/workspace/coverage/default/16.prim_async_alert.336024694	May 25 12:27:49 AM PDT 23	May 25 12:27:49 AM PDT 23	11436736 ps
T16	/workspace/coverage/default/1.prim_async_alert.1913725389	May 25 12:24:14 AM PDT 23	May 25 12:24:15 AM PDT 23	11853563 ps
T40	/workspace/coverage/default/12.prim_async_alert.573985727	May 25 12:24:14 AM PDT 23	May 25 12:24:15 AM PDT 23	10558729 ps
T12	/workspace/coverage/default/13.prim_async_alert.2322319808	May 25 12:28:13 AM PDT 23	May 25 12:28:14 AM PDT 23	12105763 ps
T41	/workspace/coverage/default/2.prim_async_alert.2632335790	May 25 12:27:04 AM PDT 23	May 25 12:27:05 AM PDT 23	11298281 ps
T8	/workspace/coverage/default/7.prim_async_alert.15749270	May 25 12:25:18 AM PDT 23	May 25 12:25:18 AM PDT 23	10632934 ps
T17	/workspace/coverage/default/5.prim_async_alert.1983051138	May 25 12:28:00 AM PDT 23	May 25 12:28:00 AM PDT 23	11275382 ps
T18	/workspace/coverage/default/9.prim_async_alert.4067191303	May 25 12:26:27 AM PDT 23	May 25 12:26:28 AM PDT 23	11255978 ps
T42	/workspace/coverage/default/4.prim_async_alert.4005251326	May 25 12:26:12 AM PDT 23	May 25 12:26:13 AM PDT 23	11148382 ps
T43	/workspace/coverage/default/10.prim_async_alert.2551530912	May 25 12:27:51 AM PDT 23	May 25 12:27:52 AM PDT 23	11553291 ps
T32	/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.120123258	May 25 12:23:29 AM PDT 23	May 25 12:23:30 AM PDT 23	29117447 ps
T4	/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.351977951	May 25 12:24:11 AM PDT 23	May 25 12:24:12 AM PDT 23	32008252 ps
T33	/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1678724822	May 25 12:28:03 AM PDT 23	May 25 12:28:04 AM PDT 23	31152094 ps
T5	/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4104466268	May 25 12:27:40 AM PDT 23	May 25 12:27:41 AM PDT 23	30760385 ps
T34	/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1799890479	May 25 12:27:10 AM PDT 23	May 25 12:27:11 AM PDT 23	27910870 ps
T35	/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1120467444	May 25 12:24:41 AM PDT 23	May 25 12:24:42 AM PDT 23	30099011 ps
T36	/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.4151461655	May 25 12:26:48 AM PDT 23	May 25 12:26:48 AM PDT 23	29670093 ps
T37	/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1691712773	May 25 12:24:59 AM PDT 23	May 25 12:24:59 AM PDT 23	30377646 ps
T38	/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.898015356	May 25 12:27:30 AM PDT 23	May 25 12:27:31 AM PDT 23	29870258 ps
T39	/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1910304594	May 25 12:28:03 AM PDT 23	May 25 12:28:03 AM PDT 23	29499848 ps
T13	/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.898732683	May 25 12:23:22 AM PDT 23	May 25 12:23:23 AM PDT 23	30412351 ps
T44	/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2465834420	May 25 12:23:22 AM PDT 23	May 25 12:23:23 AM PDT 23	29320716 ps
T45	/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3117851999	May 25 12:23:22 AM PDT 23	May 25 12:23:23 AM PDT 23	30265759 ps
T46	/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.670964189	May 25 12:28:04 AM PDT 23	May 25 12:28:04 AM PDT 23	28457358 ps
T47	/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2034547338	May 25 12:22:28 AM PDT 23	May 25 12:22:29 AM PDT 23	30449725 ps
T6	/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2436426380	May 25 12:27:51 AM PDT 23	May 25 12:27:52 AM PDT 23	29805154 ps
T48	/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3958803103	May 25 12:27:54 AM PDT 23	May 25 12:27:55 AM PDT 23	30281346 ps
T49	/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2206434268	May 25 12:25:24 AM PDT 23	May 25 12:25:24 AM PDT 23	29445496 ps
T50	/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.897565569	May 25 12:28:00 AM PDT 23	May 25 12:28:00 AM PDT 23	29358906 ps
T51	/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1245758232	May 25 12:27:16 AM PDT 23	May 25 12:27:16 AM PDT 23	31666971 ps
T22	/workspace/coverage/sync_alert/1.prim_sync_alert.2383334062	May 25 12:28:16 AM PDT 23	May 25 12:28:17 AM PDT 23	9081038 ps
T23	/workspace/coverage/sync_alert/3.prim_sync_alert.1637785463	May 25 12:28:07 AM PDT 23	May 25 12:28:08 AM PDT 23	8745949 ps
T24	/workspace/coverage/sync_alert/17.prim_sync_alert.873141224	May 25 12:57:19 AM PDT 23	May 25 12:57:19 AM PDT 23	8805937 ps
T25	/workspace/coverage/sync_alert/9.prim_sync_alert.121022258	May 25 12:48:00 AM PDT 23	May 25 12:48:00 AM PDT 23	8590581 ps
T26	/workspace/coverage/sync_alert/2.prim_sync_alert.4122468422	May 25 12:42:54 AM PDT 23	May 25 12:42:56 AM PDT 23	9301243 ps
T27	/workspace/coverage/sync_alert/0.prim_sync_alert.2477919047	May 25 12:26:25 AM PDT 23	May 25 12:26:26 AM PDT 23	9279871 ps
T28	/workspace/coverage/sync_alert/19.prim_sync_alert.2703379529	May 25 12:30:29 AM PDT 23	May 25 12:30:30 AM PDT 23	8873415 ps
T29	/workspace/coverage/sync_alert/18.prim_sync_alert.2719363412	May 25 12:23:21 AM PDT 23	May 25 12:23:22 AM PDT 23	9631511 ps
T30	/workspace/coverage/sync_alert/15.prim_sync_alert.4199681142	May 25 12:34:19 AM PDT 23	May 25 12:34:20 AM PDT 23	9985660 ps
T31	/workspace/coverage/sync_alert/14.prim_sync_alert.3158502465	May 25 12:48:02 AM PDT 23	May 25 12:48:03 AM PDT 23	8937518 ps
T52	/workspace/coverage/sync_alert/5.prim_sync_alert.1027432718	May 25 12:38:55 AM PDT 23	May 25 12:38:56 AM PDT 23	9616461 ps
T53	/workspace/coverage/sync_alert/8.prim_sync_alert.3719265601	May 25 12:51:04 AM PDT 23	May 25 12:51:05 AM PDT 23	9238054 ps
T54	/workspace/coverage/sync_alert/12.prim_sync_alert.2778263491	May 25 12:33:59 AM PDT 23	May 25 12:34:00 AM PDT 23	9091352 ps
T55	/workspace/coverage/sync_alert/6.prim_sync_alert.878542415	May 25 12:26:56 AM PDT 23	May 25 12:26:56 AM PDT 23	9456634 ps
T56	/workspace/coverage/sync_alert/13.prim_sync_alert.2838829171	May 25 12:54:11 AM PDT 23	May 25 12:54:12 AM PDT 23	10239417 ps
T57	/workspace/coverage/sync_alert/4.prim_sync_alert.3527538110	May 25 12:47:27 AM PDT 23	May 25 12:47:28 AM PDT 23	8731599 ps
T58	/workspace/coverage/sync_alert/10.prim_sync_alert.515957702	May 25 12:28:35 AM PDT 23	May 25 12:28:35 AM PDT 23	9186145 ps
T59	/workspace/coverage/sync_alert/11.prim_sync_alert.2132511669	May 25 12:30:15 AM PDT 23	May 25 12:30:16 AM PDT 23	9447063 ps
T60	/workspace/coverage/sync_alert/7.prim_sync_alert.2315211264	May 25 12:33:42 AM PDT 23	May 25 12:33:42 AM PDT 23	9379299 ps
T61	/workspace/coverage/sync_alert/16.prim_sync_alert.2744597326	May 25 12:34:19 AM PDT 23	May 25 12:34:20 AM PDT 23	8929602 ps
T62	/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3785750620	May 25 12:46:27 AM PDT 23	May 25 12:46:28 AM PDT 23	26792203 ps
T63	/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1386159985	May 25 12:46:27 AM PDT 23	May 25 12:46:27 AM PDT 23	26968444 ps
T14	/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.457252810	May 25 12:46:27 AM PDT 23	May 25 12:46:28 AM PDT 23	30362783 ps
T64	/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3984796384	May 25 12:46:39 AM PDT 23	May 25 12:46:39 AM PDT 23	27622494 ps
T65	/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2153059721	May 25 12:46:36 AM PDT 23	May 25 12:46:36 AM PDT 23	27837273 ps
T66	/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.476672714	May 25 12:46:27 AM PDT 23	May 25 12:46:28 AM PDT 23	28371751 ps
T67	/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2021174674	May 25 12:46:39 AM PDT 23	May 25 12:46:40 AM PDT 23	28113555 ps
T68	/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1826513153	May 25 12:46:39 AM PDT 23	May 25 12:46:39 AM PDT 23	27551219 ps
T69	/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.230702931	May 25 12:46:29 AM PDT 23	May 25 12:46:29 AM PDT 23	27710325 ps
T70	/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1092160173	May 25 12:46:27 AM PDT 23	May 25 12:46:28 AM PDT 23	26841053 ps
T71	/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2851241792	May 25 12:46:36 AM PDT 23	May 25 12:46:36 AM PDT 23	27389664 ps
T72	/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.591161661	May 25 12:46:26 AM PDT 23	May 25 12:46:27 AM PDT 23	27552528 ps
T73	/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.364195584	May 25 12:46:32 AM PDT 23	May 25 12:46:32 AM PDT 23	28160800 ps
T74	/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1947310027	May 25 12:46:27 AM PDT 23	May 25 12:46:28 AM PDT 23	26761789 ps
T75	/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3492703391	May 25 12:46:39 AM PDT 23	May 25 12:46:40 AM PDT 23	27117199 ps
T76	/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.654132618	May 25 12:46:39 AM PDT 23	May 25 12:46:40 AM PDT 23	27166089 ps
T77	/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3410248350	May 25 12:46:39 AM PDT 23	May 25 12:46:39 AM PDT 23	28930877 ps
T78	/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1600721644	May 25 12:46:28 AM PDT 23	May 25 12:46:29 AM PDT 23	28512666 ps
T79	/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.963567387	May 25 12:46:39 AM PDT 23	May 25 12:46:39 AM PDT 23	29240166 ps
T80	/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4147763116	May 25 12:46:38 AM PDT 23	May 25 12:46:39 AM PDT 23	27266841 ps

Test location	/workspace/coverage/default/11.prim_async_alert.1551946222
Short name	T10
Test name
Test status
Simulation time	12577332 ps
CPU time	0.37 seconds
Started	May 25 12:27:33 AM PDT 23
Finished	May 25 12:27:34 AM PDT 23
Peak memory	145548 kb
Host	smart-91ede43f-61f9-47a9-ab66-52e626c7ffe6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1551946222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1551946222
Directory	/workspace/11.prim_async_alert/latest

Test location	/workspace/coverage/sync_alert/18.prim_sync_alert.2719363412
Short name	T29
Test name
Test status
Simulation time	9631511 ps
CPU time	0.43 seconds
Started	May 25 12:23:21 AM PDT 23
Finished	May 25 12:23:22 AM PDT 23
Peak memory	144952 kb
Host	smart-3dd0b757-550f-4360-93ac-9df5405de89f
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2719363412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2719363412
Directory	/workspace/18.prim_sync_alert/latest

Test location	/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4104466268
Short name	T5
Test name
Test status
Simulation time	30760385 ps
CPU time	0.4 seconds
Started	May 25 12:27:40 AM PDT 23
Finished	May 25 12:27:41 AM PDT 23
Peak memory	144848 kb
Host	smart-ac9f5a0f-b769-401b-829c-1bf06dd0ba58
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4104466268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.4104466268
Directory	/workspace/0.prim_async_fatal_alert/latest

Test location	/workspace/coverage/default/13.prim_async_alert.2322319808
Short name	T12
Test name
Test status
Simulation time	12105763 ps
CPU time	0.36 seconds
Started	May 25 12:28:13 AM PDT 23
Finished	May 25 12:28:14 AM PDT 23
Peak memory	145548 kb
Host	smart-a3121662-9e52-4eb5-a2fb-6aad8a628ca3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2322319808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2322319808
Directory	/workspace/13.prim_async_alert/latest

Test location	/workspace/coverage/default/0.prim_async_alert.1177091568
Short name	T20
Test name
Test status
Simulation time	11093378 ps
CPU time	0.4 seconds
Started	May 25 12:24:13 AM PDT 23
Finished	May 25 12:24:15 AM PDT 23
Peak memory	145648 kb
Host	smart-85e38ba4-d81e-433e-879b-760098054c8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1177091568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1177091568
Directory	/workspace/0.prim_async_alert/latest

Test location	/workspace/coverage/default/1.prim_async_alert.1913725389
Short name	T16
Test name
Test status
Simulation time	11853563 ps
CPU time	0.4 seconds
Started	May 25 12:24:14 AM PDT 23
Finished	May 25 12:24:15 AM PDT 23
Peak memory	145648 kb
Host	smart-653109bf-4c29-4ae6-8ec2-bd10e6b7ac29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1913725389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1913725389
Directory	/workspace/1.prim_async_alert/latest

Test location	/workspace/coverage/default/10.prim_async_alert.2551530912
Short name	T43
Test name
Test status
Simulation time	11553291 ps
CPU time	0.48 seconds
Started	May 25 12:27:51 AM PDT 23
Finished	May 25 12:27:52 AM PDT 23
Peak memory	144732 kb
Host	smart-10c6e6f8-9d79-4a1c-994d-e57c44a4603c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2551530912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2551530912
Directory	/workspace/10.prim_async_alert/latest

Test location	/workspace/coverage/default/12.prim_async_alert.573985727
Short name	T40
Test name
Test status
Simulation time	10558729 ps
CPU time	0.39 seconds
Started	May 25 12:24:14 AM PDT 23
Finished	May 25 12:24:15 AM PDT 23
Peak memory	145644 kb
Host	smart-be748b58-6965-44f0-a0f4-2eb33667b0e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=573985727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.573985727
Directory	/workspace/12.prim_async_alert/latest

Test location	/workspace/coverage/default/14.prim_async_alert.3434037069
Short name	T19
Test name
Test status
Simulation time	11275884 ps
CPU time	0.4 seconds
Started	May 25 12:24:13 AM PDT 23
Finished	May 25 12:24:13 AM PDT 23
Peak memory	145512 kb
Host	smart-228b1490-9a23-41a9-9491-37e5ce017e5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3434037069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3434037069
Directory	/workspace/14.prim_async_alert/latest

Test location	/workspace/coverage/default/15.prim_async_alert.1730527237
Short name	T21
Test name
Test status
Simulation time	11241107 ps
CPU time	0.43 seconds
Started	May 25 12:22:58 AM PDT 23
Finished	May 25 12:22:59 AM PDT 23
Peak memory	145536 kb
Host	smart-1cd36dc1-4af1-4b13-8ff4-ae54f4767e88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1730527237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1730527237
Directory	/workspace/15.prim_async_alert/latest

Test location	/workspace/coverage/default/16.prim_async_alert.336024694
Short name	T15
Test name
Test status
Simulation time	11436736 ps
CPU time	0.37 seconds
Started	May 25 12:27:49 AM PDT 23
Finished	May 25 12:27:49 AM PDT 23
Peak memory	145392 kb
Host	smart-0a2b4f0e-836c-4383-ad0d-b67f9dcb9961
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=336024694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.336024694
Directory	/workspace/16.prim_async_alert/latest

Test location	/workspace/coverage/default/17.prim_async_alert.1705199722
Short name	T1
Test name
Test status
Simulation time	12160008 ps
CPU time	0.39 seconds
Started	May 25 12:22:41 AM PDT 23
Finished	May 25 12:22:41 AM PDT 23
Peak memory	145512 kb
Host	smart-9aea7331-e27f-47ca-9d51-2c6bf06a6e85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1705199722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1705199722
Directory	/workspace/17.prim_async_alert/latest

Test location	/workspace/coverage/default/18.prim_async_alert.2368479371
Short name	T7
Test name
Test status
Simulation time	11749694 ps
CPU time	0.39 seconds
Started	May 25 12:26:20 AM PDT 23
Finished	May 25 12:26:22 AM PDT 23
Peak memory	145576 kb
Host	smart-cb0203b4-1425-4378-8900-7320f3bfe1da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2368479371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2368479371
Directory	/workspace/18.prim_async_alert/latest

Test location	/workspace/coverage/default/19.prim_async_alert.3378228753
Short name	T11
Test name
Test status
Simulation time	11990809 ps
CPU time	0.37 seconds
Started	May 25 12:24:38 AM PDT 23
Finished	May 25 12:24:38 AM PDT 23
Peak memory	145564 kb
Host	smart-9569ec4e-d3a3-44e4-af1c-108d0ab0e2d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3378228753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3378228753
Directory	/workspace/19.prim_async_alert/latest

Test location	/workspace/coverage/default/2.prim_async_alert.2632335790
Short name	T41
Test name
Test status
Simulation time	11298281 ps
CPU time	0.38 seconds
Started	May 25 12:27:04 AM PDT 23
Finished	May 25 12:27:05 AM PDT 23
Peak memory	145608 kb
Host	smart-feb32395-43cd-4835-9442-08d66b7615f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2632335790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2632335790
Directory	/workspace/2.prim_async_alert/latest

Test location	/workspace/coverage/default/3.prim_async_alert.2924076859
Short name	T2
Test name
Test status
Simulation time	11038528 ps
CPU time	0.39 seconds
Started	May 25 12:27:59 AM PDT 23
Finished	May 25 12:28:00 AM PDT 23
Peak memory	145552 kb
Host	smart-72e9f894-ef15-4c96-9356-44ba8354aa22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924076859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2924076859
Directory	/workspace/3.prim_async_alert/latest

Test location	/workspace/coverage/default/4.prim_async_alert.4005251326
Short name	T42
Test name
Test status
Simulation time	11148382 ps
CPU time	0.38 seconds
Started	May 25 12:26:12 AM PDT 23
Finished	May 25 12:26:13 AM PDT 23
Peak memory	145600 kb
Host	smart-3560810d-f73f-4d9d-b55e-47325cad1c4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4005251326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.4005251326
Directory	/workspace/4.prim_async_alert/latest

Test location	/workspace/coverage/default/5.prim_async_alert.1983051138
Short name	T17
Test name
Test status
Simulation time	11275382 ps
CPU time	0.39 seconds
Started	May 25 12:28:00 AM PDT 23
Finished	May 25 12:28:00 AM PDT 23
Peak memory	145564 kb
Host	smart-d808c8a6-8f62-403e-bb32-ea93db503df7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1983051138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1983051138
Directory	/workspace/5.prim_async_alert/latest

Test location	/workspace/coverage/default/6.prim_async_alert.484856644
Short name	T3
Test name
Test status
Simulation time	10900318 ps
CPU time	0.4 seconds
Started	May 25 12:22:36 AM PDT 23
Finished	May 25 12:22:36 AM PDT 23
Peak memory	145556 kb
Host	smart-fda62961-0596-4ab7-acad-acd441e85ad9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=484856644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.484856644
Directory	/workspace/6.prim_async_alert/latest

Test location	/workspace/coverage/default/7.prim_async_alert.15749270
Short name	T8
Test name
Test status
Simulation time	10632934 ps
CPU time	0.38 seconds
Started	May 25 12:25:18 AM PDT 23
Finished	May 25 12:25:18 AM PDT 23
Peak memory	145592 kb
Host	smart-11128b8f-2cf5-4d17-9e48-2717cacc0aa1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=15749270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.15749270
Directory	/workspace/7.prim_async_alert/latest

Test location	/workspace/coverage/default/8.prim_async_alert.2086658880
Short name	T9
Test name
Test status
Simulation time	11188197 ps
CPU time	0.38 seconds
Started	May 25 12:26:27 AM PDT 23
Finished	May 25 12:26:28 AM PDT 23
Peak memory	145608 kb
Host	smart-1386aa08-4802-41b5-9278-639baa295761
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2086658880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2086658880
Directory	/workspace/8.prim_async_alert/latest

Test location	/workspace/coverage/default/9.prim_async_alert.4067191303
Short name	T18
Test name
Test status
Simulation time	11255978 ps
CPU time	0.4 seconds
Started	May 25 12:26:27 AM PDT 23
Finished	May 25 12:26:28 AM PDT 23
Peak memory	145736 kb
Host	smart-f6a05f53-81ad-4509-9b19-6279eb281537
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4067191303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.4067191303
Directory	/workspace/9.prim_async_alert/latest

Test location	/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3958803103
Short name	T48
Test name
Test status
Simulation time	30281346 ps
CPU time	0.45 seconds
Started	May 25 12:27:54 AM PDT 23
Finished	May 25 12:27:55 AM PDT 23
Peak memory	145388 kb
Host	smart-69047fcc-e262-4dc9-a74e-c3d0e0754a2e
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3958803103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3958803103
Directory	/workspace/1.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1910304594
Short name	T39
Test name
Test status
Simulation time	29499848 ps
CPU time	0.39 seconds
Started	May 25 12:28:03 AM PDT 23
Finished	May 25 12:28:03 AM PDT 23
Peak memory	145664 kb
Host	smart-ff0774ce-a5af-4d11-9806-fd5f9bff40f8
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1910304594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1910304594
Directory	/workspace/10.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.898015356
Short name	T38
Test name
Test status
Simulation time	29870258 ps
CPU time	0.41 seconds
Started	May 25 12:27:30 AM PDT 23
Finished	May 25 12:27:31 AM PDT 23
Peak memory	145464 kb
Host	smart-45e50fc0-7381-4598-964f-cf6e0f326a7d
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=898015356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.898015356
Directory	/workspace/11.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.120123258
Short name	T32
Test name
Test status
Simulation time	29117447 ps
CPU time	0.4 seconds
Started	May 25 12:23:29 AM PDT 23
Finished	May 25 12:23:30 AM PDT 23
Peak memory	145684 kb
Host	smart-ebdbcc38-5173-48d8-b13b-a08d04917f40
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=120123258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.120123258
Directory	/workspace/12.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2206434268
Short name	T49
Test name
Test status
Simulation time	29445496 ps
CPU time	0.43 seconds
Started	May 25 12:25:24 AM PDT 23
Finished	May 25 12:25:24 AM PDT 23
Peak memory	145724 kb
Host	smart-c614c96d-f62f-40c7-896b-0bfb3176b042
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2206434268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2206434268
Directory	/workspace/13.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1678724822
Short name	T33
Test name
Test status
Simulation time	31152094 ps
CPU time	0.41 seconds
Started	May 25 12:28:03 AM PDT 23
Finished	May 25 12:28:04 AM PDT 23
Peak memory	145768 kb
Host	smart-8160fd45-0c2d-4a76-99ff-2624623fe116
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1678724822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1678724822
Directory	/workspace/14.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.670964189
Short name	T46
Test name
Test status
Simulation time	28457358 ps
CPU time	0.38 seconds
Started	May 25 12:28:04 AM PDT 23
Finished	May 25 12:28:04 AM PDT 23
Peak memory	145676 kb
Host	smart-47d0fe9c-e318-4291-a53b-a7348f6345da
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=670964189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.670964189
Directory	/workspace/15.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1799890479
Short name	T34
Test name
Test status
Simulation time	27910870 ps
CPU time	0.39 seconds
Started	May 25 12:27:10 AM PDT 23
Finished	May 25 12:27:11 AM PDT 23
Peak memory	145728 kb
Host	smart-827a94ab-0a0f-46f6-bb3b-db0a5f2f6929
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1799890479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1799890479
Directory	/workspace/16.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1691712773
Short name	T37
Test name
Test status
Simulation time	30377646 ps
CPU time	0.4 seconds
Started	May 25 12:24:59 AM PDT 23
Finished	May 25 12:24:59 AM PDT 23
Peak memory	145676 kb
Host	smart-9ee5e881-711b-4ac4-998b-70689455ee3a
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1691712773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1691712773
Directory	/workspace/17.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.351977951
Short name	T4
Test name
Test status
Simulation time	32008252 ps
CPU time	0.41 seconds
Started	May 25 12:24:11 AM PDT 23
Finished	May 25 12:24:12 AM PDT 23
Peak memory	145648 kb
Host	smart-060e0d3b-6174-4ebf-b091-4968e6a9ba8f
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=351977951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.351977951
Directory	/workspace/18.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2436426380
Short name	T6
Test name
Test status
Simulation time	29805154 ps
CPU time	0.41 seconds
Started	May 25 12:27:51 AM PDT 23
Finished	May 25 12:27:52 AM PDT 23
Peak memory	144800 kb
Host	smart-30c79d15-deed-489b-a41e-9757be0d182f
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2436426380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2436426380
Directory	/workspace/19.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2034547338
Short name	T47
Test name
Test status
Simulation time	30449725 ps
CPU time	0.41 seconds
Started	May 25 12:22:28 AM PDT 23
Finished	May 25 12:22:29 AM PDT 23
Peak memory	145556 kb
Host	smart-a57b5564-e3d4-4510-8995-21f8862693b1
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2034547338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2034547338
Directory	/workspace/2.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.4151461655
Short name	T36
Test name
Test status
Simulation time	29670093 ps
CPU time	0.41 seconds
Started	May 25 12:26:48 AM PDT 23
Finished	May 25 12:26:48 AM PDT 23
Peak memory	145680 kb
Host	smart-8d090563-9a11-42af-9123-262366a36aca
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4151461655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.4151461655
Directory	/workspace/3.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.897565569
Short name	T50
Test name
Test status
Simulation time	29358906 ps
CPU time	0.41 seconds
Started	May 25 12:28:00 AM PDT 23
Finished	May 25 12:28:00 AM PDT 23
Peak memory	145700 kb
Host	smart-62c4ee22-38d8-42da-b66b-b16779ab4448
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=897565569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.897565569
Directory	/workspace/4.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2465834420
Short name	T44
Test name
Test status
Simulation time	29320716 ps
CPU time	0.56 seconds
Started	May 25 12:23:22 AM PDT 23
Finished	May 25 12:23:23 AM PDT 23
Peak memory	143548 kb
Host	smart-8369f3f6-5236-428d-b90b-95e15997e8db
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2465834420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2465834420
Directory	/workspace/5.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1120467444
Short name	T35
Test name
Test status
Simulation time	30099011 ps
CPU time	0.4 seconds
Started	May 25 12:24:41 AM PDT 23
Finished	May 25 12:24:42 AM PDT 23
Peak memory	145604 kb
Host	smart-1debb4a9-5800-4db2-b5c8-5ba69fa24e51
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1120467444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1120467444
Directory	/workspace/6.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3117851999
Short name	T45
Test name
Test status
Simulation time	30265759 ps
CPU time	0.53 seconds
Started	May 25 12:23:22 AM PDT 23
Finished	May 25 12:23:23 AM PDT 23
Peak memory	143504 kb
Host	smart-66cc699c-41f0-47ec-bd8e-523589c854a2
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3117851999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3117851999
Directory	/workspace/7.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1245758232
Short name	T51
Test name
Test status
Simulation time	31666971 ps
CPU time	0.41 seconds
Started	May 25 12:27:16 AM PDT 23
Finished	May 25 12:27:16 AM PDT 23
Peak memory	145700 kb
Host	smart-9e120b4e-995b-4740-9e4e-69efdc00a681
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1245758232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1245758232
Directory	/workspace/8.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.898732683
Short name	T13
Test name
Test status
Simulation time	30412351 ps
CPU time	0.56 seconds
Started	May 25 12:23:22 AM PDT 23
Finished	May 25 12:23:23 AM PDT 23
Peak memory	143912 kb
Host	smart-7b1374df-481c-4363-900d-d1ef296a86f5
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=898732683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.898732683
Directory	/workspace/9.prim_async_fatal_alert/latest

Test location	/workspace/coverage/sync_alert/0.prim_sync_alert.2477919047
Short name	T27
Test name
Test status
Simulation time	9279871 ps
CPU time	0.38 seconds
Started	May 25 12:26:25 AM PDT 23
Finished	May 25 12:26:26 AM PDT 23
Peak memory	145376 kb
Host	smart-25c5075e-9926-4f9a-bacf-0df0023d3dbe
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2477919047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2477919047
Directory	/workspace/0.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/1.prim_sync_alert.2383334062
Short name	T22
Test name
Test status
Simulation time	9081038 ps
CPU time	0.37 seconds
Started	May 25 12:28:16 AM PDT 23
Finished	May 25 12:28:17 AM PDT 23
Peak memory	144512 kb
Host	smart-e7a2be29-2313-4f89-942f-9621bd9bb6a3
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2383334062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2383334062
Directory	/workspace/1.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/10.prim_sync_alert.515957702
Short name	T58
Test name
Test status
Simulation time	9186145 ps
CPU time	0.37 seconds
Started	May 25 12:28:35 AM PDT 23
Finished	May 25 12:28:35 AM PDT 23
Peak memory	145352 kb
Host	smart-20f00e6f-39d4-4a76-8a3f-8658cfcfce01
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=515957702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.515957702
Directory	/workspace/10.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/11.prim_sync_alert.2132511669
Short name	T59
Test name
Test status
Simulation time	9447063 ps
CPU time	0.38 seconds
Started	May 25 12:30:15 AM PDT 23
Finished	May 25 12:30:16 AM PDT 23
Peak memory	145364 kb
Host	smart-fe8162b1-6d02-4c83-a170-4a8d99c19d84
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2132511669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2132511669
Directory	/workspace/11.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/12.prim_sync_alert.2778263491
Short name	T54
Test name
Test status
Simulation time	9091352 ps
CPU time	0.37 seconds
Started	May 25 12:33:59 AM PDT 23
Finished	May 25 12:34:00 AM PDT 23
Peak memory	145116 kb
Host	smart-bbae3a5d-35d9-4515-bc1c-6405809909cc
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2778263491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2778263491
Directory	/workspace/12.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/13.prim_sync_alert.2838829171
Short name	T56
Test name
Test status
Simulation time	10239417 ps
CPU time	0.38 seconds
Started	May 25 12:54:11 AM PDT 23
Finished	May 25 12:54:12 AM PDT 23
Peak memory	145384 kb
Host	smart-3f4dc43f-04d5-4fdc-b8c2-7e0cefcf647a
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2838829171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2838829171
Directory	/workspace/13.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/14.prim_sync_alert.3158502465
Short name	T31
Test name
Test status
Simulation time	8937518 ps
CPU time	0.42 seconds
Started	May 25 12:48:02 AM PDT 23
Finished	May 25 12:48:03 AM PDT 23
Peak memory	145544 kb
Host	smart-6c444bfb-9fbe-4a24-9392-3cbaec1151a6
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3158502465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3158502465
Directory	/workspace/14.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/15.prim_sync_alert.4199681142
Short name	T30
Test name
Test status
Simulation time	9985660 ps
CPU time	0.38 seconds
Started	May 25 12:34:19 AM PDT 23
Finished	May 25 12:34:20 AM PDT 23
Peak memory	145436 kb
Host	smart-7b49d597-4c37-4f51-9dcc-e0408d40b35e
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4199681142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.4199681142
Directory	/workspace/15.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/16.prim_sync_alert.2744597326
Short name	T61
Test name
Test status
Simulation time	8929602 ps
CPU time	0.39 seconds
Started	May 25 12:34:19 AM PDT 23
Finished	May 25 12:34:20 AM PDT 23
Peak memory	145420 kb
Host	smart-33360ff8-62cc-46c3-9b30-61d8913e7dec
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2744597326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2744597326
Directory	/workspace/16.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/17.prim_sync_alert.873141224
Short name	T24
Test name
Test status
Simulation time	8805937 ps
CPU time	0.39 seconds
Started	May 25 12:57:19 AM PDT 23
Finished	May 25 12:57:19 AM PDT 23
Peak memory	145380 kb
Host	smart-db57e754-cb9e-4456-8f2f-ced969337c28
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=873141224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.873141224
Directory	/workspace/17.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/19.prim_sync_alert.2703379529
Short name	T28
Test name
Test status
Simulation time	8873415 ps
CPU time	0.38 seconds
Started	May 25 12:30:29 AM PDT 23
Finished	May 25 12:30:30 AM PDT 23
Peak memory	145372 kb
Host	smart-1de43800-c2a5-4c9f-995d-22cdd7a912db
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2703379529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2703379529
Directory	/workspace/19.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/2.prim_sync_alert.4122468422
Short name	T26
Test name
Test status
Simulation time	9301243 ps
CPU time	0.37 seconds
Started	May 25 12:42:54 AM PDT 23
Finished	May 25 12:42:56 AM PDT 23
Peak memory	145408 kb
Host	smart-d942520c-7369-475a-a97a-e75f44b757c0
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4122468422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.4122468422
Directory	/workspace/2.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/3.prim_sync_alert.1637785463
Short name	T23
Test name
Test status
Simulation time	8745949 ps
CPU time	0.36 seconds
Started	May 25 12:28:07 AM PDT 23
Finished	May 25 12:28:08 AM PDT 23
Peak memory	145320 kb
Host	smart-337ecc80-6ae5-445b-9b75-b607db7e00f2
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1637785463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1637785463
Directory	/workspace/3.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/4.prim_sync_alert.3527538110
Short name	T57
Test name
Test status
Simulation time	8731599 ps
CPU time	0.44 seconds
Started	May 25 12:47:27 AM PDT 23
Finished	May 25 12:47:28 AM PDT 23
Peak memory	145444 kb
Host	smart-618304c9-8e13-47b6-bced-b395101ed3f0
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3527538110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3527538110
Directory	/workspace/4.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/5.prim_sync_alert.1027432718
Short name	T52
Test name
Test status
Simulation time	9616461 ps
CPU time	0.37 seconds
Started	May 25 12:38:55 AM PDT 23
Finished	May 25 12:38:56 AM PDT 23
Peak memory	145364 kb
Host	smart-57b5ecf0-160d-4209-a984-2b256f45d5fc
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1027432718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1027432718
Directory	/workspace/5.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/6.prim_sync_alert.878542415
Short name	T55
Test name
Test status
Simulation time	9456634 ps
CPU time	0.37 seconds
Started	May 25 12:26:56 AM PDT 23
Finished	May 25 12:26:56 AM PDT 23
Peak memory	145424 kb
Host	smart-7f70eb98-d9a5-4815-8f70-cbdca58d731f
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=878542415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.878542415
Directory	/workspace/6.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/7.prim_sync_alert.2315211264
Short name	T60
Test name
Test status
Simulation time	9379299 ps
CPU time	0.41 seconds
Started	May 25 12:33:42 AM PDT 23
Finished	May 25 12:33:42 AM PDT 23
Peak memory	145388 kb
Host	smart-e57e1f2c-9c40-4379-a6cc-20db7a95b8ae
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2315211264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2315211264
Directory	/workspace/7.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/8.prim_sync_alert.3719265601
Short name	T53
Test name
Test status
Simulation time	9238054 ps
CPU time	0.45 seconds
Started	May 25 12:51:04 AM PDT 23
Finished	May 25 12:51:05 AM PDT 23
Peak memory	145420 kb
Host	smart-cca2f850-8e73-40be-aff2-7235e513cd8e
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3719265601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3719265601
Directory	/workspace/8.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/9.prim_sync_alert.121022258
Short name	T25
Test name
Test status
Simulation time	8590581 ps
CPU time	0.38 seconds
Started	May 25 12:48:00 AM PDT 23
Finished	May 25 12:48:00 AM PDT 23
Peak memory	145384 kb
Host	smart-ef73639a-b071-4a1d-b982-135c5d303c94
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=121022258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.121022258
Directory	/workspace/9.prim_sync_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4147763116
Short name	T80
Test name
Test status
Simulation time	27266841 ps
CPU time	0.39 seconds
Started	May 25 12:46:38 AM PDT 23
Finished	May 25 12:46:39 AM PDT 23
Peak memory	145084 kb
Host	smart-c6b69591-414a-4d12-b583-cc6b8538f5f1
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4147763116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.4147763116
Directory	/workspace/0.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.591161661
Short name	T72
Test name
Test status
Simulation time	27552528 ps
CPU time	0.39 seconds
Started	May 25 12:46:26 AM PDT 23
Finished	May 25 12:46:27 AM PDT 23
Peak memory	145064 kb
Host	smart-8865ef18-4754-496e-a6af-dd9c5bf293be
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=591161661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.591161661
Directory	/workspace/1.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2851241792
Short name	T71
Test name
Test status
Simulation time	27389664 ps
CPU time	0.39 seconds
Started	May 25 12:46:36 AM PDT 23
Finished	May 25 12:46:36 AM PDT 23
Peak memory	144560 kb
Host	smart-a67e36dc-92c7-4b3e-8306-f72f9861bea7
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2851241792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2851241792
Directory	/workspace/10.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3410248350
Short name	T77
Test name
Test status
Simulation time	28930877 ps
CPU time	0.43 seconds
Started	May 25 12:46:39 AM PDT 23
Finished	May 25 12:46:39 AM PDT 23
Peak memory	144988 kb
Host	smart-a170a1b5-1e92-48d3-9062-06e92beb3105
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3410248350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3410248350
Directory	/workspace/11.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.364195584
Short name	T73
Test name
Test status
Simulation time	28160800 ps
CPU time	0.4 seconds
Started	May 25 12:46:32 AM PDT 23
Finished	May 25 12:46:32 AM PDT 23
Peak memory	145080 kb
Host	smart-aafb1d2b-f6df-4c45-b2a5-d1e017716b83
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=364195584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.364195584
Directory	/workspace/12.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1092160173
Short name	T70
Test name
Test status
Simulation time	26841053 ps
CPU time	0.39 seconds
Started	May 25 12:46:27 AM PDT 23
Finished	May 25 12:46:28 AM PDT 23
Peak memory	145084 kb
Host	smart-3c066ec7-09cf-4373-a0b3-4b752a113e6b
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1092160173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1092160173
Directory	/workspace/13.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3984796384
Short name	T64
Test name
Test status
Simulation time	27622494 ps
CPU time	0.38 seconds
Started	May 25 12:46:39 AM PDT 23
Finished	May 25 12:46:39 AM PDT 23
Peak memory	144988 kb
Host	smart-f05451ac-7dec-47ab-9026-a1568dc95ff0
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3984796384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3984796384
Directory	/workspace/14.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1386159985
Short name	T63
Test name
Test status
Simulation time	26968444 ps
CPU time	0.42 seconds
Started	May 25 12:46:27 AM PDT 23
Finished	May 25 12:46:27 AM PDT 23
Peak memory	145084 kb
Host	smart-204b74c4-29e3-400e-b4fb-fb706ba8a94b
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1386159985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1386159985
Directory	/workspace/15.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.476672714
Short name	T66
Test name
Test status
Simulation time	28371751 ps
CPU time	0.4 seconds
Started	May 25 12:46:27 AM PDT 23
Finished	May 25 12:46:28 AM PDT 23
Peak memory	145964 kb
Host	smart-770e4c69-7174-4df8-9678-ee3e1b7ff5ad
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=476672714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.476672714
Directory	/workspace/16.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.230702931
Short name	T69
Test name
Test status
Simulation time	27710325 ps
CPU time	0.39 seconds
Started	May 25 12:46:29 AM PDT 23
Finished	May 25 12:46:29 AM PDT 23
Peak memory	145044 kb
Host	smart-d0ee5e41-e47e-417d-be63-8fa136f75e15
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=230702931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.230702931
Directory	/workspace/17.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.963567387
Short name	T79
Test name
Test status
Simulation time	29240166 ps
CPU time	0.41 seconds
Started	May 25 12:46:39 AM PDT 23
Finished	May 25 12:46:39 AM PDT 23
Peak memory	144984 kb
Host	smart-0d264b1f-a50d-49a0-ae90-8eaf65959c71
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=963567387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.963567387
Directory	/workspace/18.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3785750620
Short name	T62
Test name
Test status
Simulation time	26792203 ps
CPU time	0.39 seconds
Started	May 25 12:46:27 AM PDT 23
Finished	May 25 12:46:28 AM PDT 23
Peak memory	145084 kb
Host	smart-05c12722-2001-4d49-8342-f20f1f44b5d1
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3785750620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3785750620
Directory	/workspace/19.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1600721644
Short name	T78
Test name
Test status
Simulation time	28512666 ps
CPU time	0.4 seconds
Started	May 25 12:46:28 AM PDT 23
Finished	May 25 12:46:29 AM PDT 23
Peak memory	145048 kb
Host	smart-24ca38e8-18f2-4454-992d-409114503d24
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1600721644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1600721644
Directory	/workspace/2.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2021174674
Short name	T67
Test name
Test status
Simulation time	28113555 ps
CPU time	0.39 seconds
Started	May 25 12:46:39 AM PDT 23
Finished	May 25 12:46:40 AM PDT 23
Peak memory	144960 kb
Host	smart-24a7e801-560f-402f-963b-b84ebb36161b
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2021174674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2021174674
Directory	/workspace/3.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2153059721
Short name	T65
Test name
Test status
Simulation time	27837273 ps
CPU time	0.39 seconds
Started	May 25 12:46:36 AM PDT 23
Finished	May 25 12:46:36 AM PDT 23
Peak memory	144552 kb
Host	smart-464e2295-2a1c-4a04-b407-f37953787982
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2153059721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2153059721
Directory	/workspace/4.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.654132618
Short name	T76
Test name
Test status
Simulation time	27166089 ps
CPU time	0.39 seconds
Started	May 25 12:46:39 AM PDT 23
Finished	May 25 12:46:40 AM PDT 23
Peak memory	144976 kb
Host	smart-dd968618-50f2-4d73-8650-a8bd718b1002
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=654132618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.654132618
Directory	/workspace/5.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1947310027
Short name	T74
Test name
Test status
Simulation time	26761789 ps
CPU time	0.4 seconds
Started	May 25 12:46:27 AM PDT 23
Finished	May 25 12:46:28 AM PDT 23
Peak memory	145084 kb
Host	smart-49403b88-6c95-49be-9e42-2904b61340a2
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1947310027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1947310027
Directory	/workspace/6.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3492703391
Short name	T75
Test name
Test status
Simulation time	27117199 ps
CPU time	0.4 seconds
Started	May 25 12:46:39 AM PDT 23
Finished	May 25 12:46:40 AM PDT 23
Peak memory	145084 kb
Host	smart-dc51559c-4642-4d22-a0ba-4bb94a12fbc5
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3492703391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3492703391
Directory	/workspace/7.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1826513153
Short name	T68
Test name
Test status
Simulation time	27551219 ps
CPU time	0.41 seconds
Started	May 25 12:46:39 AM PDT 23
Finished	May 25 12:46:39 AM PDT 23
Peak memory	144976 kb
Host	smart-ad14dcad-c830-49e4-a1ff-e678e6d93610
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1826513153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1826513153
Directory	/workspace/8.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.457252810
Short name	T14
Test name
Test status
Simulation time	30362783 ps
CPU time	0.4 seconds
Started	May 25 12:46:27 AM PDT 23
Finished	May 25 12:46:28 AM PDT 23
Peak memory	144880 kb
Host	smart-10c7d91c-1778-403c-b4db-7f13c3dad4d5
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=457252810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.457252810
Directory	/workspace/9.prim_sync_fatal_alert/latest