| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 89.02 | 89.02 | 100.00 | 100.00 | 95.83 | 95.83 | 100.00 | 100.00 | 75.00 | 75.00 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/17.prim_async_alert.2893005965 |
| 92.74 | 3.72 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/6.prim_sync_alert.1115063909 |
| 93.90 | 1.16 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.782569571 |
| 94.50 | 0.60 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/16.prim_async_alert.3574002398 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1196793897 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_alert/5.prim_sync_alert.610634259 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.1401042049 |
| /workspace/coverage/default/1.prim_async_alert.1861269885 |
| /workspace/coverage/default/10.prim_async_alert.2695508957 |
| /workspace/coverage/default/11.prim_async_alert.623785970 |
| /workspace/coverage/default/12.prim_async_alert.3084511179 |
| /workspace/coverage/default/13.prim_async_alert.358249635 |
| /workspace/coverage/default/14.prim_async_alert.3314028005 |
| /workspace/coverage/default/15.prim_async_alert.2483582365 |
| /workspace/coverage/default/18.prim_async_alert.1115167177 |
| /workspace/coverage/default/19.prim_async_alert.843606549 |
| /workspace/coverage/default/2.prim_async_alert.3766656263 |
| /workspace/coverage/default/3.prim_async_alert.4228715634 |
| /workspace/coverage/default/4.prim_async_alert.983745346 |
| /workspace/coverage/default/5.prim_async_alert.3262008233 |
| /workspace/coverage/default/6.prim_async_alert.1044280661 |
| /workspace/coverage/default/7.prim_async_alert.1320512654 |
| /workspace/coverage/default/8.prim_async_alert.3756232333 |
| /workspace/coverage/default/9.prim_async_alert.429443343 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.567545344 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.100388542 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3329661277 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2296250290 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4187452346 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3047148674 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2878665699 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.829052439 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1235445800 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2483917108 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.801921592 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2009033624 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2568306863 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1588380956 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3008724936 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1402527109 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4218039710 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.227052963 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.1532464004 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.3168606087 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.1046337811 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3154547203 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.146445081 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.898636321 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.4110273314 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.2413218235 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.3821937944 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.517005002 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.4244995065 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.2924442946 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.919555716 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.3599949821 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.3916317087 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.3813353248 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.3676454609 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3368740173 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2231344294 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.821811809 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2004307216 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.43541934 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.73020018 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2045559588 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.493638524 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1582313342 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3914291615 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1410792804 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2156659989 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4265434583 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.4037470860 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2466583643 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1574305985 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.163564867 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1001984105 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.391960181 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2035336927 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/13.prim_async_alert.358249635 | May 26 12:39:00 AM PDT 23 | May 26 12:39:01 AM PDT 23 | 10939900 ps | ||
| T2 | /workspace/coverage/default/4.prim_async_alert.983745346 | May 26 12:38:59 AM PDT 23 | May 26 12:38:59 AM PDT 23 | 10912285 ps | ||
| T3 | /workspace/coverage/default/14.prim_async_alert.3314028005 | May 26 12:38:59 AM PDT 23 | May 26 12:39:00 AM PDT 23 | 11040175 ps | ||
| T20 | /workspace/coverage/default/18.prim_async_alert.1115167177 | May 26 12:38:59 AM PDT 23 | May 26 12:39:00 AM PDT 23 | 11602970 ps | ||
| T21 | /workspace/coverage/default/7.prim_async_alert.1320512654 | May 26 12:38:58 AM PDT 23 | May 26 12:38:59 AM PDT 23 | 10686925 ps | ||
| T12 | /workspace/coverage/default/16.prim_async_alert.3574002398 | May 26 12:38:58 AM PDT 23 | May 26 12:38:59 AM PDT 23 | 11781737 ps | ||
| T13 | /workspace/coverage/default/8.prim_async_alert.3756232333 | May 26 12:39:00 AM PDT 23 | May 26 12:39:01 AM PDT 23 | 10691139 ps | ||
| T7 | /workspace/coverage/default/17.prim_async_alert.2893005965 | May 26 12:38:59 AM PDT 23 | May 26 12:39:00 AM PDT 23 | 11669858 ps | ||
| T22 | /workspace/coverage/default/0.prim_async_alert.1401042049 | May 26 12:38:55 AM PDT 23 | May 26 12:38:56 AM PDT 23 | 10943315 ps | ||
| T23 | /workspace/coverage/default/10.prim_async_alert.2695508957 | May 26 12:38:59 AM PDT 23 | May 26 12:39:00 AM PDT 23 | 11166088 ps | ||
| T24 | /workspace/coverage/default/3.prim_async_alert.4228715634 | May 26 12:39:07 AM PDT 23 | May 26 12:39:08 AM PDT 23 | 10568615 ps | ||
| T25 | /workspace/coverage/default/2.prim_async_alert.3766656263 | May 26 12:39:00 AM PDT 23 | May 26 12:39:01 AM PDT 23 | 10748038 ps | ||
| T26 | /workspace/coverage/default/19.prim_async_alert.843606549 | May 26 12:39:00 AM PDT 23 | May 26 12:39:01 AM PDT 23 | 11001516 ps | ||
| T49 | /workspace/coverage/default/9.prim_async_alert.429443343 | May 26 12:38:59 AM PDT 23 | May 26 12:39:00 AM PDT 23 | 10911785 ps | ||
| T27 | /workspace/coverage/default/11.prim_async_alert.623785970 | May 26 12:38:58 AM PDT 23 | May 26 12:38:59 AM PDT 23 | 9979669 ps | ||
| T10 | /workspace/coverage/default/6.prim_async_alert.1044280661 | May 26 12:38:59 AM PDT 23 | May 26 12:38:59 AM PDT 23 | 11353090 ps | ||
| T8 | /workspace/coverage/default/5.prim_async_alert.3262008233 | May 26 12:38:58 AM PDT 23 | May 26 12:38:59 AM PDT 23 | 11026360 ps | ||
| T28 | /workspace/coverage/default/15.prim_async_alert.2483582365 | May 26 12:38:59 AM PDT 23 | May 26 12:39:00 AM PDT 23 | 10238289 ps | ||
| T9 | /workspace/coverage/default/12.prim_async_alert.3084511179 | May 26 12:38:59 AM PDT 23 | May 26 12:39:00 AM PDT 23 | 11987809 ps | ||
| T17 | /workspace/coverage/default/1.prim_async_alert.1861269885 | May 26 12:39:10 AM PDT 23 | May 26 12:39:11 AM PDT 23 | 11420756 ps | ||
| T29 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2009033624 | May 26 12:24:41 AM PDT 23 | May 26 12:24:41 AM PDT 23 | 30350865 ps | ||
| T42 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2568306863 | May 26 12:24:47 AM PDT 23 | May 26 12:24:47 AM PDT 23 | 30064111 ps | ||
| T43 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2483917108 | May 26 12:29:36 AM PDT 23 | May 26 12:29:37 AM PDT 23 | 32363189 ps | ||
| T44 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1588380956 | May 26 12:24:42 AM PDT 23 | May 26 12:24:43 AM PDT 23 | 30028363 ps | ||
| T45 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.829052439 | May 26 12:30:06 AM PDT 23 | May 26 12:30:07 AM PDT 23 | 30746336 ps | ||
| T41 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3047148674 | May 26 12:27:34 AM PDT 23 | May 26 12:27:36 AM PDT 23 | 29324803 ps | ||
| T18 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.782569571 | May 26 12:24:44 AM PDT 23 | May 26 12:24:44 AM PDT 23 | 30808464 ps | ||
| T46 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1402527109 | May 26 12:24:42 AM PDT 23 | May 26 12:24:43 AM PDT 23 | 29793349 ps | ||
| T47 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3008724936 | May 26 12:24:42 AM PDT 23 | May 26 12:24:42 AM PDT 23 | 27558064 ps | ||
| T48 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.100388542 | May 26 12:24:40 AM PDT 23 | May 26 12:24:41 AM PDT 23 | 30365100 ps | ||
| T4 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1196793897 | May 26 12:24:42 AM PDT 23 | May 26 12:24:42 AM PDT 23 | 30182721 ps | ||
| T50 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.567545344 | May 26 12:24:46 AM PDT 23 | May 26 12:24:46 AM PDT 23 | 29545652 ps | ||
| T51 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2878665699 | May 26 12:30:05 AM PDT 23 | May 26 12:30:06 AM PDT 23 | 32740604 ps | ||
| T52 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1235445800 | May 26 12:29:50 AM PDT 23 | May 26 12:29:51 AM PDT 23 | 28031617 ps | ||
| T53 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2296250290 | May 26 12:28:08 AM PDT 23 | May 26 12:28:09 AM PDT 23 | 29429094 ps | ||
| T54 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4187452346 | May 26 12:31:16 AM PDT 23 | May 26 12:31:17 AM PDT 23 | 30535298 ps | ||
| T55 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3329661277 | May 26 12:24:43 AM PDT 23 | May 26 12:24:44 AM PDT 23 | 29003764 ps | ||
| T5 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4218039710 | May 26 12:24:34 AM PDT 23 | May 26 12:24:35 AM PDT 23 | 29544908 ps | ||
| T19 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.801921592 | May 26 12:24:43 AM PDT 23 | May 26 12:24:44 AM PDT 23 | 31258470 ps | ||
| T16 | /workspace/coverage/sync_alert/15.prim_sync_alert.4110273314 | May 26 01:41:16 AM PDT 23 | May 26 01:41:17 AM PDT 23 | 8881017 ps | ||
| T38 | /workspace/coverage/sync_alert/9.prim_sync_alert.3676454609 | May 26 01:41:19 AM PDT 23 | May 26 01:41:19 AM PDT 23 | 9658278 ps | ||
| T11 | /workspace/coverage/sync_alert/5.prim_sync_alert.610634259 | May 26 01:41:07 AM PDT 23 | May 26 01:41:07 AM PDT 23 | 10138327 ps | ||
| T39 | /workspace/coverage/sync_alert/8.prim_sync_alert.3813353248 | May 26 01:41:15 AM PDT 23 | May 26 01:41:16 AM PDT 23 | 8402801 ps | ||
| T40 | /workspace/coverage/sync_alert/3.prim_sync_alert.919555716 | May 26 01:41:08 AM PDT 23 | May 26 01:41:09 AM PDT 23 | 9085305 ps | ||
| T30 | /workspace/coverage/sync_alert/0.prim_sync_alert.227052963 | May 26 01:41:16 AM PDT 23 | May 26 01:41:16 AM PDT 23 | 9240862 ps | ||
| T31 | /workspace/coverage/sync_alert/6.prim_sync_alert.1115063909 | May 26 01:41:16 AM PDT 23 | May 26 01:41:17 AM PDT 23 | 9841708 ps | ||
| T32 | /workspace/coverage/sync_alert/12.prim_sync_alert.3154547203 | May 26 01:41:09 AM PDT 23 | May 26 01:41:09 AM PDT 23 | 9467322 ps | ||
| T33 | /workspace/coverage/sync_alert/2.prim_sync_alert.2924442946 | May 26 01:41:16 AM PDT 23 | May 26 01:41:17 AM PDT 23 | 8485826 ps | ||
| T34 | /workspace/coverage/sync_alert/10.prim_sync_alert.3168606087 | May 26 01:41:07 AM PDT 23 | May 26 01:41:07 AM PDT 23 | 10026601 ps | ||
| T14 | /workspace/coverage/sync_alert/1.prim_sync_alert.1532464004 | May 26 01:41:20 AM PDT 23 | May 26 01:41:20 AM PDT 23 | 8784708 ps | ||
| T35 | /workspace/coverage/sync_alert/18.prim_sync_alert.517005002 | May 26 01:41:07 AM PDT 23 | May 26 01:41:08 AM PDT 23 | 9623978 ps | ||
| T36 | /workspace/coverage/sync_alert/14.prim_sync_alert.898636321 | May 26 01:41:15 AM PDT 23 | May 26 01:41:16 AM PDT 23 | 9645102 ps | ||
| T37 | /workspace/coverage/sync_alert/17.prim_sync_alert.3821937944 | May 26 01:41:17 AM PDT 23 | May 26 01:41:18 AM PDT 23 | 8281019 ps | ||
| T56 | /workspace/coverage/sync_alert/16.prim_sync_alert.2413218235 | May 26 01:41:16 AM PDT 23 | May 26 01:41:17 AM PDT 23 | 8617880 ps | ||
| T57 | /workspace/coverage/sync_alert/11.prim_sync_alert.1046337811 | May 26 01:40:57 AM PDT 23 | May 26 01:40:57 AM PDT 23 | 9023190 ps | ||
| T58 | /workspace/coverage/sync_alert/19.prim_sync_alert.4244995065 | May 26 01:41:01 AM PDT 23 | May 26 01:41:02 AM PDT 23 | 9375639 ps | ||
| T59 | /workspace/coverage/sync_alert/4.prim_sync_alert.3599949821 | May 26 01:41:08 AM PDT 23 | May 26 01:41:09 AM PDT 23 | 9074101 ps | ||
| T60 | /workspace/coverage/sync_alert/7.prim_sync_alert.3916317087 | May 26 01:41:06 AM PDT 23 | May 26 01:41:07 AM PDT 23 | 9618010 ps | ||
| T61 | /workspace/coverage/sync_alert/13.prim_sync_alert.146445081 | May 26 01:41:15 AM PDT 23 | May 26 01:41:15 AM PDT 23 | 9610703 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1574305985 | May 26 12:30:01 AM PDT 23 | May 26 12:30:02 AM PDT 23 | 27163015 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.43541934 | May 26 12:29:50 AM PDT 23 | May 26 12:29:51 AM PDT 23 | 27223988 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.4037470860 | May 26 12:27:38 AM PDT 23 | May 26 12:27:39 AM PDT 23 | 29007615 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.821811809 | May 26 12:30:53 AM PDT 23 | May 26 12:30:54 AM PDT 23 | 28395996 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2004307216 | May 26 12:31:12 AM PDT 23 | May 26 12:31:13 AM PDT 23 | 27909633 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1001984105 | May 26 12:29:39 AM PDT 23 | May 26 12:29:40 AM PDT 23 | 28248208 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1582313342 | May 26 12:31:04 AM PDT 23 | May 26 12:31:05 AM PDT 23 | 29792307 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.73020018 | May 26 12:30:04 AM PDT 23 | May 26 12:30:04 AM PDT 23 | 25852285 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.391960181 | May 26 12:27:18 AM PDT 23 | May 26 12:27:20 AM PDT 23 | 28968098 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3914291615 | May 26 12:27:36 AM PDT 23 | May 26 12:27:36 AM PDT 23 | 29007389 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3368740173 | May 26 12:31:04 AM PDT 23 | May 26 12:31:04 AM PDT 23 | 26393787 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2156659989 | May 26 12:27:27 AM PDT 23 | May 26 12:27:28 AM PDT 23 | 27293856 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2045559588 | May 26 12:30:05 AM PDT 23 | May 26 12:30:06 AM PDT 23 | 25688585 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.493638524 | May 26 12:29:50 AM PDT 23 | May 26 12:29:51 AM PDT 23 | 27875831 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.163564867 | May 26 12:30:54 AM PDT 23 | May 26 12:30:55 AM PDT 23 | 27860635 ps | ||
| T15 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4265434583 | May 26 12:27:44 AM PDT 23 | May 26 12:27:45 AM PDT 23 | 26987928 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2231344294 | May 26 12:30:05 AM PDT 23 | May 26 12:30:06 AM PDT 23 | 28173659 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2035336927 | May 26 12:27:34 AM PDT 23 | May 26 12:27:36 AM PDT 23 | 26030612 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2466583643 | May 26 12:27:15 AM PDT 23 | May 26 12:27:16 AM PDT 23 | 27988871 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1410792804 | May 26 12:30:20 AM PDT 23 | May 26 12:30:21 AM PDT 23 | 29738979 ps |
| Test location | /workspace/coverage/default/17.prim_async_alert.2893005965 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11669858 ps |
| CPU time | 0.39 seconds |
| Started | May 26 12:38:59 AM PDT 23 |
| Finished | May 26 12:39:00 AM PDT 23 |
| Peak memory | 145280 kb |
| Host | smart-54c0b187-6469-4bfc-9d53-aa376828b793 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2893005965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2893005965 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.1115063909 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9841708 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:41:16 AM PDT 23 |
| Finished | May 26 01:41:17 AM PDT 23 |
| Peak memory | 145400 kb |
| Host | smart-661760d7-9067-47eb-ae1f-1e2195e21f78 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1115063909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1115063909 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.782569571 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 30808464 ps |
| CPU time | 0.39 seconds |
| Started | May 26 12:24:44 AM PDT 23 |
| Finished | May 26 12:24:44 AM PDT 23 |
| Peak memory | 145212 kb |
| Host | smart-343f7ca8-0706-4df8-ba79-e848f6613b97 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=782569571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.782569571 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.3574002398 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11781737 ps |
| CPU time | 0.41 seconds |
| Started | May 26 12:38:58 AM PDT 23 |
| Finished | May 26 12:38:59 AM PDT 23 |
| Peak memory | 143752 kb |
| Host | smart-ec52f792-2983-44a4-af8e-994b768f3006 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3574002398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3574002398 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1196793897 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30182721 ps |
| CPU time | 0.43 seconds |
| Started | May 26 12:24:42 AM PDT 23 |
| Finished | May 26 12:24:42 AM PDT 23 |
| Peak memory | 145496 kb |
| Host | smart-2e7907a3-e141-4099-9624-e48728c0d79f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1196793897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1196793897 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.610634259 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10138327 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:41:07 AM PDT 23 |
| Finished | May 26 01:41:07 AM PDT 23 |
| Peak memory | 145528 kb |
| Host | smart-06717acf-e118-44a6-b074-02ad627f86c3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=610634259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.610634259 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.1401042049 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10943315 ps |
| CPU time | 0.39 seconds |
| Started | May 26 12:38:55 AM PDT 23 |
| Finished | May 26 12:38:56 AM PDT 23 |
| Peak memory | 145616 kb |
| Host | smart-c05fabc6-318a-4b24-9ac0-4412fedd811a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1401042049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1401042049 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.1861269885 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11420756 ps |
| CPU time | 0.37 seconds |
| Started | May 26 12:39:10 AM PDT 23 |
| Finished | May 26 12:39:11 AM PDT 23 |
| Peak memory | 145616 kb |
| Host | smart-a0d858d0-1445-4514-92c1-20e26cbff007 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1861269885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1861269885 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.2695508957 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11166088 ps |
| CPU time | 0.4 seconds |
| Started | May 26 12:38:59 AM PDT 23 |
| Finished | May 26 12:39:00 AM PDT 23 |
| Peak memory | 145584 kb |
| Host | smart-50440aa0-d496-4b15-b8f3-151580c4f6a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2695508957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2695508957 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.623785970 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9979669 ps |
| CPU time | 0.43 seconds |
| Started | May 26 12:38:58 AM PDT 23 |
| Finished | May 26 12:38:59 AM PDT 23 |
| Peak memory | 143748 kb |
| Host | smart-ca52cc6d-19a2-4c75-9a36-fc2e1c52cc14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=623785970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.623785970 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.3084511179 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11987809 ps |
| CPU time | 0.39 seconds |
| Started | May 26 12:38:59 AM PDT 23 |
| Finished | May 26 12:39:00 AM PDT 23 |
| Peak memory | 145344 kb |
| Host | smart-88d674bd-132d-459c-8abe-af0d1d1e1bb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3084511179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3084511179 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.358249635 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10939900 ps |
| CPU time | 0.4 seconds |
| Started | May 26 12:39:00 AM PDT 23 |
| Finished | May 26 12:39:01 AM PDT 23 |
| Peak memory | 145576 kb |
| Host | smart-f8a833fb-bf23-421f-abf4-717213fc815d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=358249635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.358249635 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.3314028005 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11040175 ps |
| CPU time | 0.43 seconds |
| Started | May 26 12:38:59 AM PDT 23 |
| Finished | May 26 12:39:00 AM PDT 23 |
| Peak memory | 145512 kb |
| Host | smart-e2adbe7b-344f-4602-a098-fd028e7333d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3314028005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3314028005 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.2483582365 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10238289 ps |
| CPU time | 0.39 seconds |
| Started | May 26 12:38:59 AM PDT 23 |
| Finished | May 26 12:39:00 AM PDT 23 |
| Peak memory | 145584 kb |
| Host | smart-636a42e0-1640-48da-b4d2-733d67b0588b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2483582365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2483582365 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.1115167177 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11602970 ps |
| CPU time | 0.38 seconds |
| Started | May 26 12:38:59 AM PDT 23 |
| Finished | May 26 12:39:00 AM PDT 23 |
| Peak memory | 145540 kb |
| Host | smart-c17d2d96-0b97-41f5-a854-9273a3da0956 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1115167177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1115167177 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.843606549 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11001516 ps |
| CPU time | 0.39 seconds |
| Started | May 26 12:39:00 AM PDT 23 |
| Finished | May 26 12:39:01 AM PDT 23 |
| Peak memory | 145628 kb |
| Host | smart-fc68d9ac-2832-4d4b-ab47-b9009ceae755 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=843606549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.843606549 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.3766656263 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 10748038 ps |
| CPU time | 0.41 seconds |
| Started | May 26 12:39:00 AM PDT 23 |
| Finished | May 26 12:39:01 AM PDT 23 |
| Peak memory | 145612 kb |
| Host | smart-c183aa99-13b9-4660-b643-af286238da1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3766656263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3766656263 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.4228715634 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10568615 ps |
| CPU time | 0.42 seconds |
| Started | May 26 12:39:07 AM PDT 23 |
| Finished | May 26 12:39:08 AM PDT 23 |
| Peak memory | 145612 kb |
| Host | smart-f5a73211-f5b4-460f-8c50-96d340addc5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4228715634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.4228715634 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.983745346 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10912285 ps |
| CPU time | 0.38 seconds |
| Started | May 26 12:38:59 AM PDT 23 |
| Finished | May 26 12:38:59 AM PDT 23 |
| Peak memory | 145580 kb |
| Host | smart-308a67b2-9d0c-461a-874e-23e5c1c329b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=983745346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.983745346 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.3262008233 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11026360 ps |
| CPU time | 0.43 seconds |
| Started | May 26 12:38:58 AM PDT 23 |
| Finished | May 26 12:38:59 AM PDT 23 |
| Peak memory | 143672 kb |
| Host | smart-2ed5dd4b-f3a4-46a5-a330-d56efe51c3f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3262008233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3262008233 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.1044280661 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11353090 ps |
| CPU time | 0.39 seconds |
| Started | May 26 12:38:59 AM PDT 23 |
| Finished | May 26 12:38:59 AM PDT 23 |
| Peak memory | 145200 kb |
| Host | smart-83b6f222-043b-4110-bcbd-fe6097c953a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1044280661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1044280661 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.1320512654 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10686925 ps |
| CPU time | 0.38 seconds |
| Started | May 26 12:38:58 AM PDT 23 |
| Finished | May 26 12:38:59 AM PDT 23 |
| Peak memory | 145608 kb |
| Host | smart-695a78c0-1c49-43ad-b6f2-164b35c5a581 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1320512654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1320512654 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.3756232333 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 10691139 ps |
| CPU time | 0.44 seconds |
| Started | May 26 12:39:00 AM PDT 23 |
| Finished | May 26 12:39:01 AM PDT 23 |
| Peak memory | 145576 kb |
| Host | smart-6fe4652d-0d95-4fc6-9425-3038986cbc85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3756232333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3756232333 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.429443343 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 10911785 ps |
| CPU time | 0.4 seconds |
| Started | May 26 12:38:59 AM PDT 23 |
| Finished | May 26 12:39:00 AM PDT 23 |
| Peak memory | 145512 kb |
| Host | smart-f622e797-c4b0-4431-b382-fdaa2ff205b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=429443343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.429443343 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.567545344 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 29545652 ps |
| CPU time | 0.44 seconds |
| Started | May 26 12:24:46 AM PDT 23 |
| Finished | May 26 12:24:46 AM PDT 23 |
| Peak memory | 145396 kb |
| Host | smart-9b965aae-39dd-48eb-be4a-ed23ec96ab6f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=567545344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.567545344 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.100388542 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 30365100 ps |
| CPU time | 0.44 seconds |
| Started | May 26 12:24:40 AM PDT 23 |
| Finished | May 26 12:24:41 AM PDT 23 |
| Peak memory | 145460 kb |
| Host | smart-e37e49da-a508-480e-9def-0dd00e761c75 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=100388542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.100388542 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3329661277 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 29003764 ps |
| CPU time | 0.45 seconds |
| Started | May 26 12:24:43 AM PDT 23 |
| Finished | May 26 12:24:44 AM PDT 23 |
| Peak memory | 145436 kb |
| Host | smart-53e39206-7eed-4e1a-bd95-5c7f28c0f829 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3329661277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3329661277 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2296250290 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 29429094 ps |
| CPU time | 0.44 seconds |
| Started | May 26 12:28:08 AM PDT 23 |
| Finished | May 26 12:28:09 AM PDT 23 |
| Peak memory | 145960 kb |
| Host | smart-556992e4-64d2-4374-aac2-e299ff521709 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2296250290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2296250290 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4187452346 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30535298 ps |
| CPU time | 0.38 seconds |
| Started | May 26 12:31:16 AM PDT 23 |
| Finished | May 26 12:31:17 AM PDT 23 |
| Peak memory | 145512 kb |
| Host | smart-322d88cc-f664-4fed-8697-7507327c4da1 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4187452346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.4187452346 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3047148674 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29324803 ps |
| CPU time | 0.45 seconds |
| Started | May 26 12:27:34 AM PDT 23 |
| Finished | May 26 12:27:36 AM PDT 23 |
| Peak memory | 145444 kb |
| Host | smart-293e86b8-8904-4d65-86d2-4684c0d3dade |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3047148674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3047148674 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2878665699 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 32740604 ps |
| CPU time | 0.5 seconds |
| Started | May 26 12:30:05 AM PDT 23 |
| Finished | May 26 12:30:06 AM PDT 23 |
| Peak memory | 144952 kb |
| Host | smart-09ad859a-8139-4cd5-a684-57bb6f7d0256 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2878665699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2878665699 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.829052439 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 30746336 ps |
| CPU time | 0.41 seconds |
| Started | May 26 12:30:06 AM PDT 23 |
| Finished | May 26 12:30:07 AM PDT 23 |
| Peak memory | 145904 kb |
| Host | smart-479d53b0-6152-4faa-929a-8a2d76a9d862 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=829052439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.829052439 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1235445800 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 28031617 ps |
| CPU time | 0.43 seconds |
| Started | May 26 12:29:50 AM PDT 23 |
| Finished | May 26 12:29:51 AM PDT 23 |
| Peak memory | 145112 kb |
| Host | smart-0a9d4123-05d7-467e-a8b6-619f36341c94 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1235445800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1235445800 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2483917108 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 32363189 ps |
| CPU time | 0.39 seconds |
| Started | May 26 12:29:36 AM PDT 23 |
| Finished | May 26 12:29:37 AM PDT 23 |
| Peak memory | 145812 kb |
| Host | smart-c02f664f-9d8e-4504-b101-3442ec88d570 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2483917108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2483917108 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.801921592 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 31258470 ps |
| CPU time | 0.41 seconds |
| Started | May 26 12:24:43 AM PDT 23 |
| Finished | May 26 12:24:44 AM PDT 23 |
| Peak memory | 145740 kb |
| Host | smart-40ec6c6c-dbfe-4466-a13a-6c18589bf016 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=801921592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.801921592 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2009033624 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 30350865 ps |
| CPU time | 0.44 seconds |
| Started | May 26 12:24:41 AM PDT 23 |
| Finished | May 26 12:24:41 AM PDT 23 |
| Peak memory | 145212 kb |
| Host | smart-d49a7fc3-2f17-4000-aa32-bbc1eae2d558 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2009033624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2009033624 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2568306863 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 30064111 ps |
| CPU time | 0.39 seconds |
| Started | May 26 12:24:47 AM PDT 23 |
| Finished | May 26 12:24:47 AM PDT 23 |
| Peak memory | 145904 kb |
| Host | smart-fe6b269e-ed18-4c52-a4a1-660b4f17d65d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2568306863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2568306863 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1588380956 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30028363 ps |
| CPU time | 0.4 seconds |
| Started | May 26 12:24:42 AM PDT 23 |
| Finished | May 26 12:24:43 AM PDT 23 |
| Peak memory | 145596 kb |
| Host | smart-1900b647-9631-480c-a266-f3b7f6ce02b1 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1588380956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1588380956 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3008724936 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 27558064 ps |
| CPU time | 0.42 seconds |
| Started | May 26 12:24:42 AM PDT 23 |
| Finished | May 26 12:24:42 AM PDT 23 |
| Peak memory | 145496 kb |
| Host | smart-58fe0c54-2c66-48cf-a40e-b5af21c7db96 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3008724936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3008724936 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1402527109 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 29793349 ps |
| CPU time | 0.42 seconds |
| Started | May 26 12:24:42 AM PDT 23 |
| Finished | May 26 12:24:43 AM PDT 23 |
| Peak memory | 145596 kb |
| Host | smart-b390b17f-9a3f-4dbe-87ce-04cf84237589 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1402527109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1402527109 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4218039710 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 29544908 ps |
| CPU time | 0.46 seconds |
| Started | May 26 12:24:34 AM PDT 23 |
| Finished | May 26 12:24:35 AM PDT 23 |
| Peak memory | 145960 kb |
| Host | smart-ded98eb1-1edb-43b1-9ac1-f4916a1e4c37 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4218039710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.4218039710 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.227052963 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9240862 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:41:16 AM PDT 23 |
| Finished | May 26 01:41:16 AM PDT 23 |
| Peak memory | 145404 kb |
| Host | smart-262a4e15-363c-4872-8ad4-bcb8032543a5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=227052963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.227052963 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.1532464004 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 8784708 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:41:20 AM PDT 23 |
| Finished | May 26 01:41:20 AM PDT 23 |
| Peak memory | 145408 kb |
| Host | smart-5f2673aa-9619-40fa-8697-c195c0b57a5a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1532464004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1532464004 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.3168606087 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10026601 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:41:07 AM PDT 23 |
| Finished | May 26 01:41:07 AM PDT 23 |
| Peak memory | 145524 kb |
| Host | smart-bff3fbe2-38fa-4e0b-87f7-378ab4fd267f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3168606087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3168606087 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.1046337811 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9023190 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:40:57 AM PDT 23 |
| Finished | May 26 01:40:57 AM PDT 23 |
| Peak memory | 145412 kb |
| Host | smart-f8bc61ff-6baf-4f6c-892e-cf049116cda6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1046337811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1046337811 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3154547203 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9467322 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:41:09 AM PDT 23 |
| Finished | May 26 01:41:09 AM PDT 23 |
| Peak memory | 145536 kb |
| Host | smart-63cac2bd-bbd2-4e1d-96c1-568ac1e81e2a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3154547203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3154547203 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.146445081 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9610703 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:41:15 AM PDT 23 |
| Finished | May 26 01:41:15 AM PDT 23 |
| Peak memory | 145528 kb |
| Host | smart-4b2f0254-ded5-4108-9e5a-fe094743a56c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=146445081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.146445081 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.898636321 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9645102 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:41:15 AM PDT 23 |
| Finished | May 26 01:41:16 AM PDT 23 |
| Peak memory | 145508 kb |
| Host | smart-00113914-cdc3-4944-8000-a00fc1742bd5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=898636321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.898636321 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.4110273314 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 8881017 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:41:16 AM PDT 23 |
| Finished | May 26 01:41:17 AM PDT 23 |
| Peak memory | 145500 kb |
| Host | smart-b9bf8712-80ec-467d-9bc7-ddedf2059a97 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4110273314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.4110273314 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.2413218235 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 8617880 ps |
| CPU time | 0.36 seconds |
| Started | May 26 01:41:16 AM PDT 23 |
| Finished | May 26 01:41:17 AM PDT 23 |
| Peak memory | 145548 kb |
| Host | smart-857e6a2f-c3ae-421f-8d85-47ff1a28cdb4 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2413218235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2413218235 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.3821937944 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8281019 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:41:17 AM PDT 23 |
| Finished | May 26 01:41:18 AM PDT 23 |
| Peak memory | 145552 kb |
| Host | smart-098ae3d9-b5b0-4693-965e-c747677e8492 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3821937944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3821937944 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.517005002 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9623978 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:41:07 AM PDT 23 |
| Finished | May 26 01:41:08 AM PDT 23 |
| Peak memory | 145528 kb |
| Host | smart-374ee786-93b3-44df-8478-9948cf1aa138 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=517005002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.517005002 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.4244995065 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9375639 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:41:01 AM PDT 23 |
| Finished | May 26 01:41:02 AM PDT 23 |
| Peak memory | 145536 kb |
| Host | smart-43c340f9-7a85-43f0-b5a7-8eefc84eb908 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4244995065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.4244995065 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.2924442946 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8485826 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:41:16 AM PDT 23 |
| Finished | May 26 01:41:17 AM PDT 23 |
| Peak memory | 145504 kb |
| Host | smart-5ed90823-0023-4bcc-933d-d866f7a43eba |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2924442946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2924442946 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.919555716 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9085305 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:41:08 AM PDT 23 |
| Finished | May 26 01:41:09 AM PDT 23 |
| Peak memory | 145528 kb |
| Host | smart-1500cd87-4757-4cbf-b4d8-9c91bd9e4730 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=919555716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.919555716 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.3599949821 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9074101 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:41:08 AM PDT 23 |
| Finished | May 26 01:41:09 AM PDT 23 |
| Peak memory | 145524 kb |
| Host | smart-6eae9286-086a-4a17-bef6-b9ef8b1c87b4 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3599949821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3599949821 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.3916317087 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9618010 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:41:06 AM PDT 23 |
| Finished | May 26 01:41:07 AM PDT 23 |
| Peak memory | 145524 kb |
| Host | smart-16a24601-bb83-477d-a8ed-76911f90d2aa |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3916317087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3916317087 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.3813353248 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8402801 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:41:15 AM PDT 23 |
| Finished | May 26 01:41:16 AM PDT 23 |
| Peak memory | 145504 kb |
| Host | smart-49308831-8f2e-4154-b2b9-7eb2f48ffecc |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3813353248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3813353248 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.3676454609 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9658278 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:41:19 AM PDT 23 |
| Finished | May 26 01:41:19 AM PDT 23 |
| Peak memory | 145568 kb |
| Host | smart-5ebc0940-4a86-4c24-9a51-08431b14435c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3676454609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3676454609 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3368740173 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 26393787 ps |
| CPU time | 0.39 seconds |
| Started | May 26 12:31:04 AM PDT 23 |
| Finished | May 26 12:31:04 AM PDT 23 |
| Peak memory | 145240 kb |
| Host | smart-985c53c1-82c7-498b-a485-66e308dfe445 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3368740173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3368740173 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2231344294 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 28173659 ps |
| CPU time | 0.45 seconds |
| Started | May 26 12:30:05 AM PDT 23 |
| Finished | May 26 12:30:06 AM PDT 23 |
| Peak memory | 144036 kb |
| Host | smart-0d076684-3da5-47c9-aa71-36ca3b84f88a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2231344294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2231344294 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.821811809 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 28395996 ps |
| CPU time | 0.39 seconds |
| Started | May 26 12:30:53 AM PDT 23 |
| Finished | May 26 12:30:54 AM PDT 23 |
| Peak memory | 145180 kb |
| Host | smart-0c8dab78-e7eb-45b4-8f35-b7c2b128554c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=821811809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.821811809 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2004307216 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 27909633 ps |
| CPU time | 0.47 seconds |
| Started | May 26 12:31:12 AM PDT 23 |
| Finished | May 26 12:31:13 AM PDT 23 |
| Peak memory | 143804 kb |
| Host | smart-9dec21e1-13e4-404c-b4cf-35bdeaae8228 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2004307216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2004307216 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.43541934 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 27223988 ps |
| CPU time | 0.53 seconds |
| Started | May 26 12:29:50 AM PDT 23 |
| Finished | May 26 12:29:51 AM PDT 23 |
| Peak memory | 145236 kb |
| Host | smart-cf817a6d-53e8-464c-8e02-5cabceaeb250 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=43541934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.43541934 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.73020018 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 25852285 ps |
| CPU time | 0.38 seconds |
| Started | May 26 12:30:04 AM PDT 23 |
| Finished | May 26 12:30:04 AM PDT 23 |
| Peak memory | 145172 kb |
| Host | smart-2aa348a7-126f-4b54-a26d-b8f8111329e6 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=73020018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.73020018 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2045559588 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 25688585 ps |
| CPU time | 0.49 seconds |
| Started | May 26 12:30:05 AM PDT 23 |
| Finished | May 26 12:30:06 AM PDT 23 |
| Peak memory | 143364 kb |
| Host | smart-8c128d96-c14a-4575-a17b-7b56ce2fa577 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2045559588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2045559588 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.493638524 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 27875831 ps |
| CPU time | 0.41 seconds |
| Started | May 26 12:29:50 AM PDT 23 |
| Finished | May 26 12:29:51 AM PDT 23 |
| Peak memory | 145740 kb |
| Host | smart-ed39bdbf-a614-4f35-bded-c0545c24083a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=493638524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.493638524 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1582313342 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 29792307 ps |
| CPU time | 0.47 seconds |
| Started | May 26 12:31:04 AM PDT 23 |
| Finished | May 26 12:31:05 AM PDT 23 |
| Peak memory | 144588 kb |
| Host | smart-ef384140-bb6c-4487-be58-d2a60db59fdb |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1582313342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1582313342 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3914291615 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 29007389 ps |
| CPU time | 0.4 seconds |
| Started | May 26 12:27:36 AM PDT 23 |
| Finished | May 26 12:27:36 AM PDT 23 |
| Peak memory | 145148 kb |
| Host | smart-4004aafc-c750-44bc-bdd3-986727f82c4c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3914291615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3914291615 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1410792804 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 29738979 ps |
| CPU time | 0.4 seconds |
| Started | May 26 12:30:20 AM PDT 23 |
| Finished | May 26 12:30:21 AM PDT 23 |
| Peak memory | 144780 kb |
| Host | smart-9dfc0b05-92fa-4c15-a76a-a0e48ad5ccf9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1410792804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1410792804 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2156659989 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 27293856 ps |
| CPU time | 0.4 seconds |
| Started | May 26 12:27:27 AM PDT 23 |
| Finished | May 26 12:27:28 AM PDT 23 |
| Peak memory | 144944 kb |
| Host | smart-6ee35ae1-c731-45cc-9ead-b08c7ed6fc6f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2156659989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2156659989 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4265434583 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 26987928 ps |
| CPU time | 0.38 seconds |
| Started | May 26 12:27:44 AM PDT 23 |
| Finished | May 26 12:27:45 AM PDT 23 |
| Peak memory | 144792 kb |
| Host | smart-18c8161b-5b3d-4173-a77f-e5a8da7833fa |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4265434583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.4265434583 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.4037470860 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 29007615 ps |
| CPU time | 0.42 seconds |
| Started | May 26 12:27:38 AM PDT 23 |
| Finished | May 26 12:27:39 AM PDT 23 |
| Peak memory | 145204 kb |
| Host | smart-f1f9d174-8bc0-42e4-b32d-09454bd9f47e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4037470860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.4037470860 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2466583643 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 27988871 ps |
| CPU time | 0.4 seconds |
| Started | May 26 12:27:15 AM PDT 23 |
| Finished | May 26 12:27:16 AM PDT 23 |
| Peak memory | 145204 kb |
| Host | smart-ded63aa3-8eb7-487c-930c-b2b7a610a6d1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2466583643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2466583643 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1574305985 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 27163015 ps |
| CPU time | 0.42 seconds |
| Started | May 26 12:30:01 AM PDT 23 |
| Finished | May 26 12:30:02 AM PDT 23 |
| Peak memory | 144792 kb |
| Host | smart-c9271278-ddc8-4027-ba17-4d7f38fccbdb |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1574305985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1574305985 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.163564867 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27860635 ps |
| CPU time | 0.42 seconds |
| Started | May 26 12:30:54 AM PDT 23 |
| Finished | May 26 12:30:55 AM PDT 23 |
| Peak memory | 144312 kb |
| Host | smart-28aa3251-9165-4d99-bd5f-3fa8bacbe2b9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=163564867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.163564867 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1001984105 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 28248208 ps |
| CPU time | 0.39 seconds |
| Started | May 26 12:29:39 AM PDT 23 |
| Finished | May 26 12:29:40 AM PDT 23 |
| Peak memory | 145240 kb |
| Host | smart-3f41f5fb-b1b0-4498-90cc-b1f639a2aeeb |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1001984105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1001984105 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.391960181 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 28968098 ps |
| CPU time | 0.46 seconds |
| Started | May 26 12:27:18 AM PDT 23 |
| Finished | May 26 12:27:20 AM PDT 23 |
| Peak memory | 144208 kb |
| Host | smart-0cd1cf4c-84cd-4b36-9234-26dd4ff1c7ef |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=391960181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.391960181 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2035336927 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 26030612 ps |
| CPU time | 0.43 seconds |
| Started | May 26 12:27:34 AM PDT 23 |
| Finished | May 26 12:27:36 AM PDT 23 |
| Peak memory | 144492 kb |
| Host | smart-b51aab50-df8b-4823-a0ac-51fe5be6e23d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2035336927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2035336927 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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