| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 94.60 | 100.00 | 100.00 | 100.00 | 85.71 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.67 | 88.67 | 100.00 | 100.00 | 93.75 | 93.75 | 96.43 | 96.43 | 78.57 | 78.57 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/18.prim_async_alert.1196707774 |
| 91.80 | 3.13 | 100.00 | 0.00 | 93.75 | 0.00 | 96.43 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/0.prim_sync_alert.1459587792 |
| 94.25 | 2.45 | 100.00 | 0.00 | 97.92 | 4.17 | 100.00 | 3.57 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1379209361 |
| 94.60 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_alert/2.prim_sync_alert.1741154748 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.4191696287 |
| /workspace/coverage/default/1.prim_async_alert.1518943270 |
| /workspace/coverage/default/10.prim_async_alert.61931156 |
| /workspace/coverage/default/11.prim_async_alert.3691601336 |
| /workspace/coverage/default/12.prim_async_alert.3036251684 |
| /workspace/coverage/default/13.prim_async_alert.3847784380 |
| /workspace/coverage/default/14.prim_async_alert.414374575 |
| /workspace/coverage/default/15.prim_async_alert.4292808417 |
| /workspace/coverage/default/16.prim_async_alert.1015186617 |
| /workspace/coverage/default/19.prim_async_alert.4035986386 |
| /workspace/coverage/default/2.prim_async_alert.273304381 |
| /workspace/coverage/default/3.prim_async_alert.1987038152 |
| /workspace/coverage/default/4.prim_async_alert.3501891001 |
| /workspace/coverage/default/5.prim_async_alert.2653583816 |
| /workspace/coverage/default/7.prim_async_alert.2461031714 |
| /workspace/coverage/default/8.prim_async_alert.158548460 |
| /workspace/coverage/default/9.prim_async_alert.4205973281 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3073459077 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2505771222 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3994756660 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1428686952 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3885417971 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4126988669 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.212087565 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1944079784 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.117737995 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1777049891 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.950813798 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3870787939 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1498683887 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.560940426 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3352509077 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.583925926 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2312572397 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.1607493754 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.374707874 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.4171336050 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.1122272021 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.2787829619 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.1200512980 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.115431856 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.1780863539 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.417378968 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.1163610594 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.3777654047 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.1828980503 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.518772892 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.1820832674 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.1192455621 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.3473042746 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.96511430 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.2288614179 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4087594453 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2171809146 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3573622612 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1118217325 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4211331168 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1619618267 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1527104401 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1192595552 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4063798789 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.91592036 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4150955075 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1137425275 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.961220192 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.4263063042 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.289223947 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3606887890 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.188993284 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1012422508 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3972704131 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3673997299 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/12.prim_async_alert.3036251684 | May 28 01:21:37 AM PDT 23 | May 28 01:21:38 AM PDT 23 | 11057299 ps | ||
| T2 | /workspace/coverage/default/13.prim_async_alert.3847784380 | May 28 01:21:46 AM PDT 23 | May 28 01:21:47 AM PDT 23 | 10803066 ps | ||
| T3 | /workspace/coverage/default/1.prim_async_alert.1518943270 | May 28 01:21:46 AM PDT 23 | May 28 01:21:47 AM PDT 23 | 11162378 ps | ||
| T16 | /workspace/coverage/default/7.prim_async_alert.2461031714 | May 28 01:21:46 AM PDT 23 | May 28 01:21:47 AM PDT 23 | 10205122 ps | ||
| T7 | /workspace/coverage/default/18.prim_async_alert.1196707774 | May 28 01:21:42 AM PDT 23 | May 28 01:21:42 AM PDT 23 | 10499365 ps | ||
| T17 | /workspace/coverage/default/14.prim_async_alert.414374575 | May 28 01:21:39 AM PDT 23 | May 28 01:21:40 AM PDT 23 | 10349876 ps | ||
| T8 | /workspace/coverage/default/15.prim_async_alert.4292808417 | May 28 01:21:48 AM PDT 23 | May 28 01:21:48 AM PDT 23 | 10799531 ps | ||
| T18 | /workspace/coverage/default/19.prim_async_alert.4035986386 | May 28 01:21:33 AM PDT 23 | May 28 01:21:34 AM PDT 23 | 11124368 ps | ||
| T10 | /workspace/coverage/default/3.prim_async_alert.1987038152 | May 28 01:21:48 AM PDT 23 | May 28 01:21:48 AM PDT 23 | 11777215 ps | ||
| T19 | /workspace/coverage/default/4.prim_async_alert.3501891001 | May 28 01:21:40 AM PDT 23 | May 28 01:21:41 AM PDT 23 | 10960687 ps | ||
| T22 | /workspace/coverage/default/8.prim_async_alert.158548460 | May 28 01:21:48 AM PDT 23 | May 28 01:21:48 AM PDT 23 | 11289671 ps | ||
| T11 | /workspace/coverage/default/5.prim_async_alert.2653583816 | May 28 01:21:44 AM PDT 23 | May 28 01:21:45 AM PDT 23 | 11426731 ps | ||
| T9 | /workspace/coverage/default/9.prim_async_alert.4205973281 | May 28 01:21:31 AM PDT 23 | May 28 01:21:31 AM PDT 23 | 12228145 ps | ||
| T35 | /workspace/coverage/default/11.prim_async_alert.3691601336 | May 28 01:21:41 AM PDT 23 | May 28 01:21:41 AM PDT 23 | 10755638 ps | ||
| T20 | /workspace/coverage/default/10.prim_async_alert.61931156 | May 28 01:21:36 AM PDT 23 | May 28 01:21:36 AM PDT 23 | 11258247 ps | ||
| T21 | /workspace/coverage/default/2.prim_async_alert.273304381 | May 28 01:21:39 AM PDT 23 | May 28 01:21:40 AM PDT 23 | 10806436 ps | ||
| T43 | /workspace/coverage/default/16.prim_async_alert.1015186617 | May 28 01:21:41 AM PDT 23 | May 28 01:21:42 AM PDT 23 | 11479046 ps | ||
| T14 | /workspace/coverage/default/0.prim_async_alert.4191696287 | May 28 01:21:48 AM PDT 23 | May 28 01:21:48 AM PDT 23 | 11036555 ps | ||
| T4 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.560940426 | May 28 01:22:15 AM PDT 23 | May 28 01:22:16 AM PDT 23 | 28886102 ps | ||
| T5 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3885417971 | May 28 01:22:18 AM PDT 23 | May 28 01:22:19 AM PDT 23 | 29556131 ps | ||
| T38 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2505771222 | May 28 01:22:15 AM PDT 23 | May 28 01:22:15 AM PDT 23 | 29241313 ps | ||
| T39 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.583925926 | May 28 01:22:16 AM PDT 23 | May 28 01:22:16 AM PDT 23 | 30866453 ps | ||
| T40 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1498683887 | May 28 01:22:14 AM PDT 23 | May 28 01:22:14 AM PDT 23 | 29698224 ps | ||
| T15 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.212087565 | May 28 01:22:13 AM PDT 23 | May 28 01:22:14 AM PDT 23 | 28566200 ps | ||
| T6 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1379209361 | May 28 01:22:07 AM PDT 23 | May 28 01:22:08 AM PDT 23 | 30512147 ps | ||
| T41 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3870787939 | May 28 01:21:31 AM PDT 23 | May 28 01:21:32 AM PDT 23 | 30677291 ps | ||
| T36 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1777049891 | May 28 01:22:14 AM PDT 23 | May 28 01:22:14 AM PDT 23 | 29741623 ps | ||
| T42 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3073459077 | May 28 01:21:48 AM PDT 23 | May 28 01:21:48 AM PDT 23 | 27909308 ps | ||
| T44 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.117737995 | May 28 01:22:15 AM PDT 23 | May 28 01:22:15 AM PDT 23 | 28314661 ps | ||
| T45 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4126988669 | May 28 01:22:18 AM PDT 23 | May 28 01:22:19 AM PDT 23 | 30634894 ps | ||
| T46 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.950813798 | May 28 01:21:40 AM PDT 23 | May 28 01:21:40 AM PDT 23 | 29995627 ps | ||
| T47 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1944079784 | May 28 01:22:16 AM PDT 23 | May 28 01:22:16 AM PDT 23 | 31607132 ps | ||
| T48 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3994756660 | May 28 01:22:16 AM PDT 23 | May 28 01:22:16 AM PDT 23 | 30796375 ps | ||
| T49 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1428686952 | May 28 01:22:16 AM PDT 23 | May 28 01:22:16 AM PDT 23 | 28204790 ps | ||
| T50 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2312572397 | May 28 01:22:18 AM PDT 23 | May 28 01:22:19 AM PDT 23 | 30329675 ps | ||
| T37 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3352509077 | May 28 01:22:14 AM PDT 23 | May 28 01:22:15 AM PDT 23 | 31105345 ps | ||
| T23 | /workspace/coverage/sync_alert/9.prim_sync_alert.2288614179 | May 28 01:04:23 AM PDT 23 | May 28 01:04:24 AM PDT 23 | 9074092 ps | ||
| T24 | /workspace/coverage/sync_alert/7.prim_sync_alert.3473042746 | May 28 01:04:30 AM PDT 23 | May 28 01:04:32 AM PDT 23 | 8867226 ps | ||
| T25 | /workspace/coverage/sync_alert/0.prim_sync_alert.1459587792 | May 28 01:04:23 AM PDT 23 | May 28 01:04:24 AM PDT 23 | 9595550 ps | ||
| T26 | /workspace/coverage/sync_alert/15.prim_sync_alert.115431856 | May 28 01:04:23 AM PDT 23 | May 28 01:04:23 AM PDT 23 | 8311573 ps | ||
| T32 | /workspace/coverage/sync_alert/14.prim_sync_alert.1200512980 | May 28 01:04:31 AM PDT 23 | May 28 01:04:32 AM PDT 23 | 8802703 ps | ||
| T33 | /workspace/coverage/sync_alert/4.prim_sync_alert.518772892 | May 28 01:04:30 AM PDT 23 | May 28 01:04:32 AM PDT 23 | 8419591 ps | ||
| T34 | /workspace/coverage/sync_alert/11.prim_sync_alert.4171336050 | May 28 01:04:30 AM PDT 23 | May 28 01:04:32 AM PDT 23 | 9022566 ps | ||
| T27 | /workspace/coverage/sync_alert/18.prim_sync_alert.1163610594 | May 28 01:04:23 AM PDT 23 | May 28 01:04:23 AM PDT 23 | 8699296 ps | ||
| T28 | /workspace/coverage/sync_alert/13.prim_sync_alert.2787829619 | May 28 01:04:09 AM PDT 23 | May 28 01:04:10 AM PDT 23 | 9179084 ps | ||
| T29 | /workspace/coverage/sync_alert/16.prim_sync_alert.1780863539 | May 28 01:04:08 AM PDT 23 | May 28 01:04:09 AM PDT 23 | 8972402 ps | ||
| T30 | /workspace/coverage/sync_alert/8.prim_sync_alert.96511430 | May 28 01:04:22 AM PDT 23 | May 28 01:04:23 AM PDT 23 | 9292928 ps | ||
| T12 | /workspace/coverage/sync_alert/2.prim_sync_alert.1741154748 | May 28 01:04:08 AM PDT 23 | May 28 01:04:09 AM PDT 23 | 9277432 ps | ||
| T31 | /workspace/coverage/sync_alert/5.prim_sync_alert.1820832674 | May 28 01:04:30 AM PDT 23 | May 28 01:04:30 AM PDT 23 | 9074457 ps | ||
| T51 | /workspace/coverage/sync_alert/1.prim_sync_alert.1607493754 | May 28 01:04:22 AM PDT 23 | May 28 01:04:23 AM PDT 23 | 8677962 ps | ||
| T52 | /workspace/coverage/sync_alert/3.prim_sync_alert.1828980503 | May 28 01:04:30 AM PDT 23 | May 28 01:04:32 AM PDT 23 | 9062251 ps | ||
| T53 | /workspace/coverage/sync_alert/19.prim_sync_alert.3777654047 | May 28 01:04:08 AM PDT 23 | May 28 01:04:09 AM PDT 23 | 8875916 ps | ||
| T54 | /workspace/coverage/sync_alert/6.prim_sync_alert.1192455621 | May 28 01:04:30 AM PDT 23 | May 28 01:04:32 AM PDT 23 | 8827947 ps | ||
| T55 | /workspace/coverage/sync_alert/17.prim_sync_alert.417378968 | May 28 01:04:08 AM PDT 23 | May 28 01:04:09 AM PDT 23 | 9107004 ps | ||
| T56 | /workspace/coverage/sync_alert/12.prim_sync_alert.1122272021 | May 28 01:04:09 AM PDT 23 | May 28 01:04:09 AM PDT 23 | 9786209 ps | ||
| T57 | /workspace/coverage/sync_alert/10.prim_sync_alert.374707874 | May 28 01:04:30 AM PDT 23 | May 28 01:04:32 AM PDT 23 | 9380582 ps | ||
| T58 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3673997299 | May 28 01:21:32 AM PDT 23 | May 28 01:21:33 AM PDT 23 | 27279797 ps | ||
| T59 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4211331168 | May 28 01:21:22 AM PDT 23 | May 28 01:21:23 AM PDT 23 | 28295235 ps | ||
| T60 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.4263063042 | May 28 01:21:18 AM PDT 23 | May 28 01:21:19 AM PDT 23 | 27938797 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1527104401 | May 28 01:21:45 AM PDT 23 | May 28 01:21:45 AM PDT 23 | 26032109 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1012422508 | May 28 01:21:17 AM PDT 23 | May 28 01:21:17 AM PDT 23 | 27910721 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1118217325 | May 28 01:21:17 AM PDT 23 | May 28 01:21:18 AM PDT 23 | 28019495 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1137425275 | May 28 01:21:42 AM PDT 23 | May 28 01:21:43 AM PDT 23 | 29487884 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1619618267 | May 28 01:21:25 AM PDT 23 | May 28 01:21:26 AM PDT 23 | 28802438 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4087594453 | May 28 01:21:17 AM PDT 23 | May 28 01:21:19 AM PDT 23 | 27363269 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4150955075 | May 28 01:21:42 AM PDT 23 | May 28 01:21:42 AM PDT 23 | 27873931 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.188993284 | May 28 01:21:18 AM PDT 23 | May 28 01:21:19 AM PDT 23 | 25878201 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1192595552 | May 28 01:21:40 AM PDT 23 | May 28 01:21:41 AM PDT 23 | 27306843 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.289223947 | May 28 01:21:07 AM PDT 23 | May 28 01:21:07 AM PDT 23 | 27181968 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4063798789 | May 28 01:21:43 AM PDT 23 | May 28 01:21:44 AM PDT 23 | 29541436 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3573622612 | May 28 01:21:25 AM PDT 23 | May 28 01:21:26 AM PDT 23 | 27712994 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.91592036 | May 28 01:21:42 AM PDT 23 | May 28 01:21:43 AM PDT 23 | 29336721 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2171809146 | May 28 01:21:15 AM PDT 23 | May 28 01:21:16 AM PDT 23 | 27461236 ps | ||
| T13 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3606887890 | May 28 01:21:21 AM PDT 23 | May 28 01:21:22 AM PDT 23 | 27031663 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.961220192 | May 28 01:21:24 AM PDT 23 | May 28 01:21:24 AM PDT 23 | 26828504 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3972704131 | May 28 01:21:07 AM PDT 23 | May 28 01:21:08 AM PDT 23 | 27066082 ps |
| Test location | /workspace/coverage/default/18.prim_async_alert.1196707774 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10499365 ps |
| CPU time | 0.38 seconds |
| Started | May 28 01:21:42 AM PDT 23 |
| Finished | May 28 01:21:42 AM PDT 23 |
| Peak memory | 145376 kb |
| Host | smart-a0667b1b-58de-4d11-b5a2-7b762e0426d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1196707774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1196707774 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.1459587792 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9595550 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:04:23 AM PDT 23 |
| Finished | May 28 01:04:24 AM PDT 23 |
| Peak memory | 145140 kb |
| Host | smart-444a14b5-c2ca-40d6-ab74-9b4da27a4c1b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1459587792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1459587792 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1379209361 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 30512147 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:22:07 AM PDT 23 |
| Finished | May 28 01:22:08 AM PDT 23 |
| Peak memory | 145512 kb |
| Host | smart-aa17f992-e0bf-4142-9feb-f69e4d120018 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1379209361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1379209361 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.1741154748 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 9277432 ps |
| CPU time | 0.42 seconds |
| Started | May 28 01:04:08 AM PDT 23 |
| Finished | May 28 01:04:09 AM PDT 23 |
| Peak memory | 144920 kb |
| Host | smart-c55aea50-97a3-4bb7-8f9c-cd9e233183b3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1741154748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1741154748 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.4191696287 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11036555 ps |
| CPU time | 0.43 seconds |
| Started | May 28 01:21:48 AM PDT 23 |
| Finished | May 28 01:21:48 AM PDT 23 |
| Peak memory | 145408 kb |
| Host | smart-4ac09346-2e00-412b-98f1-702e10fd4db7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4191696287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.4191696287 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.1518943270 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11162378 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:21:46 AM PDT 23 |
| Finished | May 28 01:21:47 AM PDT 23 |
| Peak memory | 145772 kb |
| Host | smart-d1425ac0-17ed-4a15-87db-2928e8124a6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1518943270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1518943270 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.61931156 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11258247 ps |
| CPU time | 0.38 seconds |
| Started | May 28 01:21:36 AM PDT 23 |
| Finished | May 28 01:21:36 AM PDT 23 |
| Peak memory | 145436 kb |
| Host | smart-c4dbb8b3-968b-4cca-9573-0b1f55db327b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61931156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.61931156 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.3691601336 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 10755638 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:21:41 AM PDT 23 |
| Finished | May 28 01:21:41 AM PDT 23 |
| Peak memory | 145348 kb |
| Host | smart-1f812278-29bc-4ae0-936d-cc8694c1b563 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691601336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3691601336 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.3036251684 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11057299 ps |
| CPU time | 0.38 seconds |
| Started | May 28 01:21:37 AM PDT 23 |
| Finished | May 28 01:21:38 AM PDT 23 |
| Peak memory | 145372 kb |
| Host | smart-8bfe4865-654e-4380-86f6-55fa0770c546 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3036251684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3036251684 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.3847784380 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10803066 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:21:46 AM PDT 23 |
| Finished | May 28 01:21:47 AM PDT 23 |
| Peak memory | 145748 kb |
| Host | smart-c5c60015-c705-4b12-9de3-ee52420e10ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3847784380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3847784380 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.414374575 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 10349876 ps |
| CPU time | 0.42 seconds |
| Started | May 28 01:21:39 AM PDT 23 |
| Finished | May 28 01:21:40 AM PDT 23 |
| Peak memory | 144492 kb |
| Host | smart-7d979032-7946-4767-bd82-a3adf27303f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=414374575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.414374575 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.4292808417 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10799531 ps |
| CPU time | 0.43 seconds |
| Started | May 28 01:21:48 AM PDT 23 |
| Finished | May 28 01:21:48 AM PDT 23 |
| Peak memory | 145324 kb |
| Host | smart-74d372fa-a7ad-4e55-bee6-cf2f46e77ee1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292808417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.4292808417 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.1015186617 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11479046 ps |
| CPU time | 0.38 seconds |
| Started | May 28 01:21:41 AM PDT 23 |
| Finished | May 28 01:21:42 AM PDT 23 |
| Peak memory | 145368 kb |
| Host | smart-574a948f-0aa1-4a18-96a0-166d3b763f70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1015186617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1015186617 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.4035986386 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11124368 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:21:33 AM PDT 23 |
| Finished | May 28 01:21:34 AM PDT 23 |
| Peak memory | 145352 kb |
| Host | smart-5d996ba1-ae5d-4ff3-8587-3457d6bb948b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4035986386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.4035986386 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.273304381 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10806436 ps |
| CPU time | 0.38 seconds |
| Started | May 28 01:21:39 AM PDT 23 |
| Finished | May 28 01:21:40 AM PDT 23 |
| Peak memory | 145368 kb |
| Host | smart-82e821c3-3225-4d9f-b7e5-b164565ad82a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=273304381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.273304381 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.1987038152 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11777215 ps |
| CPU time | 0.42 seconds |
| Started | May 28 01:21:48 AM PDT 23 |
| Finished | May 28 01:21:48 AM PDT 23 |
| Peak memory | 144776 kb |
| Host | smart-5a6a6b47-0d62-4e71-8a67-995538595bdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1987038152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1987038152 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.3501891001 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10960687 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:21:40 AM PDT 23 |
| Finished | May 28 01:21:41 AM PDT 23 |
| Peak memory | 145436 kb |
| Host | smart-7c690c1a-3fc4-49c5-b5c3-ef51e6b9643f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3501891001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3501891001 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.2653583816 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11426731 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:21:44 AM PDT 23 |
| Finished | May 28 01:21:45 AM PDT 23 |
| Peak memory | 145448 kb |
| Host | smart-773505ee-c3ac-4845-a549-ae7e6569b183 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2653583816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2653583816 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.2461031714 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10205122 ps |
| CPU time | 0.42 seconds |
| Started | May 28 01:21:46 AM PDT 23 |
| Finished | May 28 01:21:47 AM PDT 23 |
| Peak memory | 145772 kb |
| Host | smart-0de57f96-0108-45a6-a8b7-2f74d87a72af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2461031714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2461031714 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.158548460 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11289671 ps |
| CPU time | 0.45 seconds |
| Started | May 28 01:21:48 AM PDT 23 |
| Finished | May 28 01:21:48 AM PDT 23 |
| Peak memory | 145368 kb |
| Host | smart-aebd3dd8-9d37-4513-bea7-358685c777ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=158548460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.158548460 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.4205973281 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12228145 ps |
| CPU time | 0.38 seconds |
| Started | May 28 01:21:31 AM PDT 23 |
| Finished | May 28 01:21:31 AM PDT 23 |
| Peak memory | 145416 kb |
| Host | smart-0afd3fcd-57d0-4cf3-a26e-43c93c6fe5c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205973281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.4205973281 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3073459077 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 27909308 ps |
| CPU time | 0.44 seconds |
| Started | May 28 01:21:48 AM PDT 23 |
| Finished | May 28 01:21:48 AM PDT 23 |
| Peak memory | 144832 kb |
| Host | smart-5182a72c-2150-4305-a3fa-1d22128c3b4f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3073459077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3073459077 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2505771222 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 29241313 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:22:15 AM PDT 23 |
| Finished | May 28 01:22:15 AM PDT 23 |
| Peak memory | 145512 kb |
| Host | smart-05812545-9eae-4405-8d90-a551f02b7479 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2505771222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2505771222 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3994756660 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 30796375 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:22:16 AM PDT 23 |
| Finished | May 28 01:22:16 AM PDT 23 |
| Peak memory | 145132 kb |
| Host | smart-ce342414-4d6c-4bef-9ff4-8394eb1fadde |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3994756660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3994756660 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1428686952 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 28204790 ps |
| CPU time | 0.43 seconds |
| Started | May 28 01:22:16 AM PDT 23 |
| Finished | May 28 01:22:16 AM PDT 23 |
| Peak memory | 145156 kb |
| Host | smart-41fa785c-3c45-4648-8f80-eeecd875b9a6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1428686952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1428686952 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3885417971 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 29556131 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:22:18 AM PDT 23 |
| Finished | May 28 01:22:19 AM PDT 23 |
| Peak memory | 145512 kb |
| Host | smart-0b9ce686-a744-4e94-b769-e3f2103c2d3e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3885417971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3885417971 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4126988669 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 30634894 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:22:18 AM PDT 23 |
| Finished | May 28 01:22:19 AM PDT 23 |
| Peak memory | 145584 kb |
| Host | smart-c58f44d8-0c39-4f4b-96d5-aadc240def84 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4126988669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.4126988669 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.212087565 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 28566200 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:22:13 AM PDT 23 |
| Finished | May 28 01:22:14 AM PDT 23 |
| Peak memory | 145512 kb |
| Host | smart-29db7ef4-d61b-47a3-9fe1-2bc91d059360 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=212087565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.212087565 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1944079784 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 31607132 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:22:16 AM PDT 23 |
| Finished | May 28 01:22:16 AM PDT 23 |
| Peak memory | 145816 kb |
| Host | smart-29d19024-a889-49d4-bb22-a4b1701a1a2b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1944079784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1944079784 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.117737995 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 28314661 ps |
| CPU time | 0.42 seconds |
| Started | May 28 01:22:15 AM PDT 23 |
| Finished | May 28 01:22:15 AM PDT 23 |
| Peak memory | 145676 kb |
| Host | smart-e1b17f6a-d1a4-4fe4-af97-71d88393b962 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=117737995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.117737995 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1777049891 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 29741623 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:22:14 AM PDT 23 |
| Finished | May 28 01:22:14 AM PDT 23 |
| Peak memory | 145872 kb |
| Host | smart-8e7a5841-10a4-4a53-bd0f-bfbd3483d1f1 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1777049891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1777049891 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.950813798 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 29995627 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:21:40 AM PDT 23 |
| Finished | May 28 01:21:40 AM PDT 23 |
| Peak memory | 145448 kb |
| Host | smart-a08010a2-a0c1-4028-b424-bbb61ccfcb3e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=950813798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.950813798 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3870787939 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 30677291 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:21:31 AM PDT 23 |
| Finished | May 28 01:21:32 AM PDT 23 |
| Peak memory | 145496 kb |
| Host | smart-882fda09-4e54-4015-afad-b110066acd97 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3870787939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3870787939 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1498683887 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 29698224 ps |
| CPU time | 0.42 seconds |
| Started | May 28 01:22:14 AM PDT 23 |
| Finished | May 28 01:22:14 AM PDT 23 |
| Peak memory | 145836 kb |
| Host | smart-cab2cb9e-a132-470a-8140-00caef13bdec |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1498683887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1498683887 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.560940426 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 28886102 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:22:15 AM PDT 23 |
| Finished | May 28 01:22:16 AM PDT 23 |
| Peak memory | 145904 kb |
| Host | smart-ea9490e3-d861-44b5-8e01-3344a752e415 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=560940426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.560940426 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3352509077 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 31105345 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:22:14 AM PDT 23 |
| Finished | May 28 01:22:15 AM PDT 23 |
| Peak memory | 145532 kb |
| Host | smart-70a44939-90c5-4e4b-ab13-7e2a3c48b7f8 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3352509077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3352509077 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.583925926 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 30866453 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:22:16 AM PDT 23 |
| Finished | May 28 01:22:16 AM PDT 23 |
| Peak memory | 145480 kb |
| Host | smart-993d0661-38d6-4bfd-b4b4-4db295bba41f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=583925926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.583925926 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2312572397 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 30329675 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:22:18 AM PDT 23 |
| Finished | May 28 01:22:19 AM PDT 23 |
| Peak memory | 145584 kb |
| Host | smart-56bc674b-b0cc-44f7-a14d-a50d833ca915 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2312572397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2312572397 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.1607493754 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 8677962 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:04:22 AM PDT 23 |
| Finished | May 28 01:04:23 AM PDT 23 |
| Peak memory | 144612 kb |
| Host | smart-d4175b14-7e92-4e20-bf06-0754fd2031de |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1607493754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1607493754 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.374707874 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9380582 ps |
| CPU time | 0.57 seconds |
| Started | May 28 01:04:30 AM PDT 23 |
| Finished | May 28 01:04:32 AM PDT 23 |
| Peak memory | 143196 kb |
| Host | smart-8e68af72-ad37-44be-9cf9-e0ad8416ad86 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=374707874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.374707874 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.4171336050 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9022566 ps |
| CPU time | 0.5 seconds |
| Started | May 28 01:04:30 AM PDT 23 |
| Finished | May 28 01:04:32 AM PDT 23 |
| Peak memory | 143676 kb |
| Host | smart-55ab1bd2-cb84-4d87-bd23-10f9c8dd4038 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4171336050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.4171336050 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.1122272021 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 9786209 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:04:09 AM PDT 23 |
| Finished | May 28 01:04:09 AM PDT 23 |
| Peak memory | 144932 kb |
| Host | smart-47693c2f-2a32-495b-a8bf-c13853a9e874 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1122272021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1122272021 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.2787829619 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9179084 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:04:09 AM PDT 23 |
| Finished | May 28 01:04:10 AM PDT 23 |
| Peak memory | 145184 kb |
| Host | smart-a3e14bac-ab7e-4473-8d13-def2a2173d4e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2787829619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2787829619 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.1200512980 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8802703 ps |
| CPU time | 0.38 seconds |
| Started | May 28 01:04:31 AM PDT 23 |
| Finished | May 28 01:04:32 AM PDT 23 |
| Peak memory | 145280 kb |
| Host | smart-4cb86b5d-20f3-4498-8aae-d9946a3e43cf |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1200512980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1200512980 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.115431856 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8311573 ps |
| CPU time | 0.38 seconds |
| Started | May 28 01:04:23 AM PDT 23 |
| Finished | May 28 01:04:23 AM PDT 23 |
| Peak memory | 144892 kb |
| Host | smart-86ca9ac2-15ff-448f-b1d1-165a99df566c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=115431856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.115431856 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.1780863539 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8972402 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:04:08 AM PDT 23 |
| Finished | May 28 01:04:09 AM PDT 23 |
| Peak memory | 144892 kb |
| Host | smart-e48a6024-ebb7-44a1-95bf-b5033fdbe71e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1780863539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1780863539 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.417378968 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 9107004 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:04:08 AM PDT 23 |
| Finished | May 28 01:04:09 AM PDT 23 |
| Peak memory | 144856 kb |
| Host | smart-87c35292-c67e-448f-82e8-473ddd01b796 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=417378968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.417378968 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.1163610594 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8699296 ps |
| CPU time | 0.38 seconds |
| Started | May 28 01:04:23 AM PDT 23 |
| Finished | May 28 01:04:23 AM PDT 23 |
| Peak memory | 145488 kb |
| Host | smart-77cf11a9-1888-4589-a723-c3b50402cf06 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1163610594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1163610594 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.3777654047 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 8875916 ps |
| CPU time | 0.43 seconds |
| Started | May 28 01:04:08 AM PDT 23 |
| Finished | May 28 01:04:09 AM PDT 23 |
| Peak memory | 144904 kb |
| Host | smart-4185c57f-c072-4425-a4f5-dd1095d09425 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3777654047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3777654047 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.1828980503 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 9062251 ps |
| CPU time | 0.53 seconds |
| Started | May 28 01:04:30 AM PDT 23 |
| Finished | May 28 01:04:32 AM PDT 23 |
| Peak memory | 143024 kb |
| Host | smart-8bd20478-f482-49b4-bd93-a7f1a66459f7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1828980503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1828980503 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.518772892 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8419591 ps |
| CPU time | 0.5 seconds |
| Started | May 28 01:04:30 AM PDT 23 |
| Finished | May 28 01:04:32 AM PDT 23 |
| Peak memory | 143316 kb |
| Host | smart-0ccbd380-d5a2-43b1-bfca-75ebe646aee6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=518772892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.518772892 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.1820832674 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9074457 ps |
| CPU time | 0.37 seconds |
| Started | May 28 01:04:30 AM PDT 23 |
| Finished | May 28 01:04:30 AM PDT 23 |
| Peak memory | 145280 kb |
| Host | smart-b335d71a-d131-4f50-ba93-b3e1e3a0b137 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1820832674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1820832674 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.1192455621 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 8827947 ps |
| CPU time | 0.57 seconds |
| Started | May 28 01:04:30 AM PDT 23 |
| Finished | May 28 01:04:32 AM PDT 23 |
| Peak memory | 142768 kb |
| Host | smart-58dcc423-24c9-45db-8df1-90b3b8520cc6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1192455621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1192455621 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.3473042746 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8867226 ps |
| CPU time | 0.51 seconds |
| Started | May 28 01:04:30 AM PDT 23 |
| Finished | May 28 01:04:32 AM PDT 23 |
| Peak memory | 143884 kb |
| Host | smart-1d7dafca-eb16-4379-8995-d30b0cfed2b4 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3473042746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3473042746 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.96511430 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9292928 ps |
| CPU time | 0.43 seconds |
| Started | May 28 01:04:22 AM PDT 23 |
| Finished | May 28 01:04:23 AM PDT 23 |
| Peak memory | 144588 kb |
| Host | smart-bc587f89-a471-4a9d-90cb-15f11c363bd7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=96511430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.96511430 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.2288614179 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9074092 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:04:23 AM PDT 23 |
| Finished | May 28 01:04:24 AM PDT 23 |
| Peak memory | 145280 kb |
| Host | smart-e67e579c-9db5-4875-87dd-e55505e2099d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2288614179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2288614179 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4087594453 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 27363269 ps |
| CPU time | 0.42 seconds |
| Started | May 28 01:21:17 AM PDT 23 |
| Finished | May 28 01:21:19 AM PDT 23 |
| Peak memory | 145116 kb |
| Host | smart-d9f07298-1147-4dad-bc66-3dc07941f2fa |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4087594453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.4087594453 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2171809146 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 27461236 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:21:15 AM PDT 23 |
| Finished | May 28 01:21:16 AM PDT 23 |
| Peak memory | 144744 kb |
| Host | smart-f8399eda-8b07-4cab-a0be-dd93ea975768 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2171809146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2171809146 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3573622612 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 27712994 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:21:25 AM PDT 23 |
| Finished | May 28 01:21:26 AM PDT 23 |
| Peak memory | 144828 kb |
| Host | smart-f32ecca5-0abb-4764-a52f-466b525ec745 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3573622612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3573622612 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1118217325 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 28019495 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:21:17 AM PDT 23 |
| Finished | May 28 01:21:18 AM PDT 23 |
| Peak memory | 145128 kb |
| Host | smart-9758124e-3972-44ff-bb5b-5fcc22c822c4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1118217325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1118217325 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4211331168 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 28295235 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:21:22 AM PDT 23 |
| Finished | May 28 01:21:23 AM PDT 23 |
| Peak memory | 144820 kb |
| Host | smart-f693e3d5-20a5-439b-a02b-16b199899823 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4211331168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.4211331168 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1619618267 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 28802438 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:21:25 AM PDT 23 |
| Finished | May 28 01:21:26 AM PDT 23 |
| Peak memory | 144792 kb |
| Host | smart-16407e74-4bed-45ee-ad86-832c47128b68 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1619618267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1619618267 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1527104401 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 26032109 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:21:45 AM PDT 23 |
| Finished | May 28 01:21:45 AM PDT 23 |
| Peak memory | 144820 kb |
| Host | smart-255e5afb-cc5d-4024-a5e5-dbc54d9ce427 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1527104401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1527104401 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1192595552 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27306843 ps |
| CPU time | 0.45 seconds |
| Started | May 28 01:21:40 AM PDT 23 |
| Finished | May 28 01:21:41 AM PDT 23 |
| Peak memory | 144776 kb |
| Host | smart-99123fb3-655c-4d8c-8516-6b5c717a8a6c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1192595552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1192595552 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4063798789 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 29541436 ps |
| CPU time | 0.45 seconds |
| Started | May 28 01:21:43 AM PDT 23 |
| Finished | May 28 01:21:44 AM PDT 23 |
| Peak memory | 144820 kb |
| Host | smart-4382f658-2c61-4de6-9878-bf319208b5be |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4063798789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.4063798789 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.91592036 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 29336721 ps |
| CPU time | 0.48 seconds |
| Started | May 28 01:21:42 AM PDT 23 |
| Finished | May 28 01:21:43 AM PDT 23 |
| Peak memory | 143640 kb |
| Host | smart-b6018b71-14ef-48fb-9bfd-89856f9377bc |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=91592036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.91592036 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4150955075 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27873931 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:21:42 AM PDT 23 |
| Finished | May 28 01:21:42 AM PDT 23 |
| Peak memory | 144568 kb |
| Host | smart-8b6659ed-a53d-48b0-810c-29e8eb5e15b3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4150955075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.4150955075 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1137425275 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 29487884 ps |
| CPU time | 0.51 seconds |
| Started | May 28 01:21:42 AM PDT 23 |
| Finished | May 28 01:21:43 AM PDT 23 |
| Peak memory | 143792 kb |
| Host | smart-4b94893f-7d7b-4db1-af60-28a2121679b2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1137425275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1137425275 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.961220192 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 26828504 ps |
| CPU time | 0.38 seconds |
| Started | May 28 01:21:24 AM PDT 23 |
| Finished | May 28 01:21:24 AM PDT 23 |
| Peak memory | 144812 kb |
| Host | smart-481e11c3-5032-4643-ad66-b21cc2d044a4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=961220192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.961220192 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.4263063042 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 27938797 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:21:18 AM PDT 23 |
| Finished | May 28 01:21:19 AM PDT 23 |
| Peak memory | 144780 kb |
| Host | smart-a705b041-2a3e-4843-8a5d-e74404abc287 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4263063042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.4263063042 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.289223947 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27181968 ps |
| CPU time | 0.42 seconds |
| Started | May 28 01:21:07 AM PDT 23 |
| Finished | May 28 01:21:07 AM PDT 23 |
| Peak memory | 145016 kb |
| Host | smart-0387d0a6-dee3-4ca8-a21d-68190050b619 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=289223947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.289223947 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3606887890 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 27031663 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:21:21 AM PDT 23 |
| Finished | May 28 01:21:22 AM PDT 23 |
| Peak memory | 144788 kb |
| Host | smart-af0816dd-d002-4212-9255-f7fd3432ec0a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3606887890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3606887890 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.188993284 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 25878201 ps |
| CPU time | 0.43 seconds |
| Started | May 28 01:21:18 AM PDT 23 |
| Finished | May 28 01:21:19 AM PDT 23 |
| Peak memory | 144768 kb |
| Host | smart-6ed156bb-75d6-4fa8-86f7-0d83a9745105 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=188993284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.188993284 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1012422508 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 27910721 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:21:17 AM PDT 23 |
| Finished | May 28 01:21:17 AM PDT 23 |
| Peak memory | 145116 kb |
| Host | smart-d923bd73-5158-407f-a532-2e4da2f53ef9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1012422508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1012422508 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3972704131 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27066082 ps |
| CPU time | 0.38 seconds |
| Started | May 28 01:21:07 AM PDT 23 |
| Finished | May 28 01:21:08 AM PDT 23 |
| Peak memory | 144712 kb |
| Host | smart-28b1effa-8bd1-4e9a-bae4-97205ba9f3ae |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3972704131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3972704131 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3673997299 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 27279797 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:21:32 AM PDT 23 |
| Finished | May 28 01:21:33 AM PDT 23 |
| Peak memory | 144824 kb |
| Host | smart-e11dcafa-8341-4c5e-b85c-418919a123ce |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3673997299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3673997299 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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