Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	100.00	100.00	89.29	95.83	86.05

Total tests in report: 77

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
88.53	88.53	100.00	100.00	91.67	91.67	96.43	96.43	82.14	82.14	95.83	95.83	65.12	65.12	/workspace/coverage/default/11.prim_async_alert.4169666389
91.06	2.53	100.00	0.00	91.67	0.00	96.43	0.00	85.71	3.57	95.83	0.00	76.74	11.63	/workspace/coverage/sync_alert/0.prim_sync_alert.2319313904
93.56	2.49	100.00	0.00	93.75	2.08	100.00	3.57	85.71	0.00	95.83	0.00	86.05	9.30	/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4282623581
94.25	0.69	100.00	0.00	97.92	4.17	100.00	0.00	85.71	0.00	95.83	0.00	86.05	0.00	/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2176580788
94.85	0.60	100.00	0.00	97.92	0.00	100.00	0.00	89.29	3.57	95.83	0.00	86.05	0.00	/workspace/coverage/sync_alert/10.prim_sync_alert.215055875
95.19	0.35	100.00	0.00	100.00	2.08	100.00	0.00	89.29	0.00	95.83	0.00	86.05	0.00	/workspace/coverage/sync_alert/16.prim_sync_alert.3427243381

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.1946295761
/workspace/coverage/default/10.prim_async_alert.1347613737
/workspace/coverage/default/12.prim_async_alert.3268174761
/workspace/coverage/default/13.prim_async_alert.2297067822
/workspace/coverage/default/14.prim_async_alert.1778003289
/workspace/coverage/default/15.prim_async_alert.1939231732
/workspace/coverage/default/16.prim_async_alert.3738752299
/workspace/coverage/default/17.prim_async_alert.4090526373
/workspace/coverage/default/18.prim_async_alert.2823683820
/workspace/coverage/default/19.prim_async_alert.3150471975
/workspace/coverage/default/3.prim_async_alert.3618928789
/workspace/coverage/default/4.prim_async_alert.1779299588
/workspace/coverage/default/5.prim_async_alert.2560354514
/workspace/coverage/default/6.prim_async_alert.3193852565
/workspace/coverage/default/7.prim_async_alert.2082766803
/workspace/coverage/default/8.prim_async_alert.1872824635
/workspace/coverage/default/9.prim_async_alert.2020143456
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.330255359
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1105534505
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2201839525
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2997579047
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.979575216
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2271736461
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1605402149
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1802265715
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3110079036
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1218847062
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3429787560
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2733390653
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.756792058
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3553165272
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.92732564
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4235788528
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1599823259
/workspace/coverage/sync_alert/1.prim_sync_alert.3672823955
/workspace/coverage/sync_alert/11.prim_sync_alert.811510603
/workspace/coverage/sync_alert/12.prim_sync_alert.1169106198
/workspace/coverage/sync_alert/13.prim_sync_alert.164053926
/workspace/coverage/sync_alert/14.prim_sync_alert.456347597
/workspace/coverage/sync_alert/15.prim_sync_alert.1403194002
/workspace/coverage/sync_alert/17.prim_sync_alert.2133062828
/workspace/coverage/sync_alert/18.prim_sync_alert.2943332955
/workspace/coverage/sync_alert/19.prim_sync_alert.88979129
/workspace/coverage/sync_alert/2.prim_sync_alert.976417050
/workspace/coverage/sync_alert/3.prim_sync_alert.864008895
/workspace/coverage/sync_alert/4.prim_sync_alert.1309753693
/workspace/coverage/sync_alert/5.prim_sync_alert.531111739
/workspace/coverage/sync_alert/6.prim_sync_alert.2181966576
/workspace/coverage/sync_alert/7.prim_sync_alert.1208261638
/workspace/coverage/sync_alert/8.prim_sync_alert.2204301161
/workspace/coverage/sync_alert/9.prim_sync_alert.146581337
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.561907157
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.61296254
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3083085206
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3803009447
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2796946271
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3317308758
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.416825946
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1118487575
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1200654324
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1401388736
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2157330673
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2256620375
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1244345444
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2476606850
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3784807179
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2705842088
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2442367095
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.173755986
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.951285993
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2092524064

Total test records in report: 77

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/11.prim_async_alert.4169666389	May 29 12:23:28 AM PDT 23	May 29 12:23:29 AM PDT 23	11725713 ps
T2	/workspace/coverage/default/16.prim_async_alert.3738752299	May 29 12:23:31 AM PDT 23	May 29 12:23:31 AM PDT 23	11345217 ps
T3	/workspace/coverage/default/13.prim_async_alert.2297067822	May 29 12:25:03 AM PDT 23	May 29 12:25:05 AM PDT 23	10705145 ps
T19	/workspace/coverage/default/7.prim_async_alert.2082766803	May 29 12:23:30 AM PDT 23	May 29 12:23:31 AM PDT 23	11078342 ps
T7	/workspace/coverage/default/9.prim_async_alert.2020143456	May 29 12:23:58 AM PDT 23	May 29 12:23:59 AM PDT 23	11520163 ps
T15	/workspace/coverage/default/17.prim_async_alert.4090526373	May 29 12:23:24 AM PDT 23	May 29 12:23:25 AM PDT 23	10953213 ps
T9	/workspace/coverage/default/14.prim_async_alert.1778003289	May 29 12:23:56 AM PDT 23	May 29 12:23:57 AM PDT 23	11759398 ps
T17	/workspace/coverage/default/19.prim_async_alert.3150471975	May 29 12:24:11 AM PDT 23	May 29 12:24:12 AM PDT 23	10973926 ps
T8	/workspace/coverage/default/10.prim_async_alert.1347613737	May 29 12:25:16 AM PDT 23	May 29 12:25:16 AM PDT 23	11229943 ps
T10	/workspace/coverage/default/15.prim_async_alert.1939231732	May 29 12:25:02 AM PDT 23	May 29 12:25:03 AM PDT 23	11646902 ps
T20	/workspace/coverage/default/0.prim_async_alert.1946295761	May 29 12:23:25 AM PDT 23	May 29 12:23:26 AM PDT 23	11930609 ps
T21	/workspace/coverage/default/8.prim_async_alert.1872824635	May 29 12:25:10 AM PDT 23	May 29 12:25:11 AM PDT 23	11438204 ps
T25	/workspace/coverage/default/6.prim_async_alert.3193852565	May 29 12:24:59 AM PDT 23	May 29 12:25:01 AM PDT 23	11694105 ps
T18	/workspace/coverage/default/3.prim_async_alert.3618928789	May 29 12:22:19 AM PDT 23	May 29 12:22:20 AM PDT 23	10853944 ps
T46	/workspace/coverage/default/18.prim_async_alert.2823683820	May 29 12:23:24 AM PDT 23	May 29 12:23:25 AM PDT 23	11415333 ps
T22	/workspace/coverage/default/12.prim_async_alert.3268174761	May 29 12:23:29 AM PDT 23	May 29 12:23:30 AM PDT 23	11367830 ps
T47	/workspace/coverage/default/5.prim_async_alert.2560354514	May 29 12:23:44 AM PDT 23	May 29 12:23:45 AM PDT 23	11337317 ps
T23	/workspace/coverage/default/4.prim_async_alert.1779299588	May 29 12:23:35 AM PDT 23	May 29 12:23:37 AM PDT 23	11063377 ps
T14	/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.92732564	May 29 12:22:18 AM PDT 23	May 29 12:22:18 AM PDT 23	30149611 ps
T4	/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2733390653	May 29 12:24:04 AM PDT 23	May 29 12:24:05 AM PDT 23	28644434 ps
T40	/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1605402149	May 29 12:24:23 AM PDT 23	May 29 12:24:23 AM PDT 23	27513077 ps
T5	/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2176580788	May 29 12:22:38 AM PDT 23	May 29 12:22:38 AM PDT 23	30614089 ps
T41	/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1105534505	May 29 12:22:39 AM PDT 23	May 29 12:22:40 AM PDT 23	29789895 ps
T24	/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4282623581	May 29 12:22:22 AM PDT 23	May 29 12:22:24 AM PDT 23	30400434 ps
T42	/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2201839525	May 29 12:23:25 AM PDT 23	May 29 12:23:26 AM PDT 23	31861583 ps
T43	/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3429787560	May 29 12:22:39 AM PDT 23	May 29 12:22:40 AM PDT 23	30977645 ps
T44	/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.979575216	May 29 12:24:05 AM PDT 23	May 29 12:24:06 AM PDT 23	29185208 ps
T45	/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3110079036	May 29 12:23:44 AM PDT 23	May 29 12:23:45 AM PDT 23	30027844 ps
T48	/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1218847062	May 29 12:23:35 AM PDT 23	May 29 12:23:37 AM PDT 23	27748026 ps
T49	/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1802265715	May 29 12:23:44 AM PDT 23	May 29 12:23:45 AM PDT 23	30931307 ps
T50	/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.330255359	May 29 12:23:35 AM PDT 23	May 29 12:23:37 AM PDT 23	29329915 ps
T6	/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3553165272	May 29 12:22:25 AM PDT 23	May 29 12:22:26 AM PDT 23	31060398 ps
T51	/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2271736461	May 29 12:22:39 AM PDT 23	May 29 12:22:40 AM PDT 23	30730107 ps
T52	/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.756792058	May 29 12:23:50 AM PDT 23	May 29 12:23:51 AM PDT 23	32405268 ps
T53	/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1599823259	May 29 12:23:50 AM PDT 23	May 29 12:23:51 AM PDT 23	30362264 ps
T54	/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4235788528	May 29 12:23:25 AM PDT 23	May 29 12:23:26 AM PDT 23	29434448 ps
T55	/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2997579047	May 29 12:22:16 AM PDT 23	May 29 12:22:17 AM PDT 23	28581443 ps
T26	/workspace/coverage/sync_alert/6.prim_sync_alert.2181966576	May 29 12:50:23 AM PDT 23	May 29 12:50:24 AM PDT 23	8711478 ps
T27	/workspace/coverage/sync_alert/5.prim_sync_alert.531111739	May 29 12:50:20 AM PDT 23	May 29 12:50:21 AM PDT 23	8505588 ps
T34	/workspace/coverage/sync_alert/2.prim_sync_alert.976417050	May 29 12:50:11 AM PDT 23	May 29 12:50:11 AM PDT 23	9137922 ps
T16	/workspace/coverage/sync_alert/10.prim_sync_alert.215055875	May 29 12:50:31 AM PDT 23	May 29 12:50:32 AM PDT 23	9438960 ps
T35	/workspace/coverage/sync_alert/0.prim_sync_alert.2319313904	May 29 12:50:18 AM PDT 23	May 29 12:50:18 AM PDT 23	10385055 ps
T36	/workspace/coverage/sync_alert/11.prim_sync_alert.811510603	May 29 12:50:23 AM PDT 23	May 29 12:50:25 AM PDT 23	9204935 ps
T37	/workspace/coverage/sync_alert/8.prim_sync_alert.2204301161	May 29 12:50:31 AM PDT 23	May 29 12:50:32 AM PDT 23	9346936 ps
T38	/workspace/coverage/sync_alert/19.prim_sync_alert.88979129	May 29 12:51:00 AM PDT 23	May 29 12:51:01 AM PDT 23	8480711 ps
T39	/workspace/coverage/sync_alert/17.prim_sync_alert.2133062828	May 29 12:50:23 AM PDT 23	May 29 12:50:23 AM PDT 23	9075908 ps
T28	/workspace/coverage/sync_alert/7.prim_sync_alert.1208261638	May 29 12:50:23 AM PDT 23	May 29 12:50:24 AM PDT 23	8877314 ps
T11	/workspace/coverage/sync_alert/18.prim_sync_alert.2943332955	May 29 12:50:22 AM PDT 23	May 29 12:50:23 AM PDT 23	9355847 ps
T29	/workspace/coverage/sync_alert/12.prim_sync_alert.1169106198	May 29 12:50:31 AM PDT 23	May 29 12:50:32 AM PDT 23	9669921 ps
T30	/workspace/coverage/sync_alert/15.prim_sync_alert.1403194002	May 29 12:50:31 AM PDT 23	May 29 12:50:32 AM PDT 23	9584736 ps
T12	/workspace/coverage/sync_alert/16.prim_sync_alert.3427243381	May 29 12:50:31 AM PDT 23	May 29 12:50:32 AM PDT 23	8843035 ps
T31	/workspace/coverage/sync_alert/3.prim_sync_alert.864008895	May 29 12:50:31 AM PDT 23	May 29 12:50:32 AM PDT 23	8127196 ps
T32	/workspace/coverage/sync_alert/9.prim_sync_alert.146581337	May 29 12:50:23 AM PDT 23	May 29 12:50:25 AM PDT 23	10423771 ps
T33	/workspace/coverage/sync_alert/13.prim_sync_alert.164053926	May 29 12:50:21 AM PDT 23	May 29 12:50:22 AM PDT 23	8620618 ps
T56	/workspace/coverage/sync_alert/4.prim_sync_alert.1309753693	May 29 12:50:16 AM PDT 23	May 29 12:50:17 AM PDT 23	8959712 ps
T57	/workspace/coverage/sync_alert/1.prim_sync_alert.3672823955	May 29 12:50:23 AM PDT 23	May 29 12:50:25 AM PDT 23	9909101 ps
T58	/workspace/coverage/sync_alert/14.prim_sync_alert.456347597	May 29 12:50:22 AM PDT 23	May 29 12:50:23 AM PDT 23	10414111 ps
T59	/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.61296254	May 29 12:50:22 AM PDT 23	May 29 12:50:23 AM PDT 23	28014533 ps
T60	/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1244345444	May 29 12:50:13 AM PDT 23	May 29 12:50:14 AM PDT 23	26861832 ps
T61	/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2442367095	May 29 12:50:10 AM PDT 23	May 29 12:50:11 AM PDT 23	27353097 ps
T62	/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.561907157	May 29 12:50:22 AM PDT 23	May 29 12:50:23 AM PDT 23	26226111 ps
T63	/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.951285993	May 29 12:50:18 AM PDT 23	May 29 12:50:18 AM PDT 23	27786132 ps
T64	/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2256620375	May 29 12:50:18 AM PDT 23	May 29 12:50:18 AM PDT 23	28401045 ps
T65	/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2092524064	May 29 12:50:13 AM PDT 23	May 29 12:50:14 AM PDT 23	28337449 ps
T66	/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.416825946	May 29 12:50:09 AM PDT 23	May 29 12:50:09 AM PDT 23	27698627 ps
T67	/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3083085206	May 29 12:50:14 AM PDT 23	May 29 12:50:15 AM PDT 23	27207757 ps
T68	/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.173755986	May 29 12:50:10 AM PDT 23	May 29 12:50:11 AM PDT 23	30083600 ps
T69	/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1401388736	May 29 12:50:14 AM PDT 23	May 29 12:50:15 AM PDT 23	27394976 ps
T70	/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2705842088	May 29 12:50:02 AM PDT 23	May 29 12:50:02 AM PDT 23	27339492 ps
T71	/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2796946271	May 29 12:50:15 AM PDT 23	May 29 12:50:16 AM PDT 23	27167530 ps
T13	/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2157330673	May 29 12:50:18 AM PDT 23	May 29 12:50:18 AM PDT 23	27898549 ps
T72	/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3317308758	May 29 12:50:13 AM PDT 23	May 29 12:50:14 AM PDT 23	25973881 ps
T73	/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1118487575	May 29 12:50:07 AM PDT 23	May 29 12:50:08 AM PDT 23	29197852 ps
T74	/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3803009447	May 29 12:50:18 AM PDT 23	May 29 12:50:18 AM PDT 23	29353237 ps
T75	/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1200654324	May 29 12:50:13 AM PDT 23	May 29 12:50:14 AM PDT 23	26865055 ps
T76	/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2476606850	May 29 12:50:09 AM PDT 23	May 29 12:50:09 AM PDT 23	27031537 ps
T77	/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3784807179	May 29 12:50:17 AM PDT 23	May 29 12:50:17 AM PDT 23	27131584 ps

Test location	/workspace/coverage/default/11.prim_async_alert.4169666389
Short name	T1
Test name
Test status
Simulation time	11725713 ps
CPU time	0.4 seconds
Started	May 29 12:23:28 AM PDT 23
Finished	May 29 12:23:29 AM PDT 23
Peak memory	145452 kb
Host	smart-74bc16c0-b8c7-48c1-ae18-2cf8778654c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4169666389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.4169666389
Directory	/workspace/11.prim_async_alert/latest

Test location	/workspace/coverage/sync_alert/0.prim_sync_alert.2319313904
Short name	T35
Test name
Test status
Simulation time	10385055 ps
CPU time	0.39 seconds
Started	May 29 12:50:18 AM PDT 23
Finished	May 29 12:50:18 AM PDT 23
Peak memory	145372 kb
Host	smart-dc6fc212-ea2f-422d-b597-d4d8f36aadbf
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2319313904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2319313904
Directory	/workspace/0.prim_sync_alert/latest

Test location	/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4282623581
Short name	T24
Test name
Test status
Simulation time	30400434 ps
CPU time	0.46 seconds
Started	May 29 12:22:22 AM PDT 23
Finished	May 29 12:22:24 AM PDT 23
Peak memory	144772 kb
Host	smart-34405db5-d68a-4959-b1e2-062657b1270c
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4282623581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.4282623581
Directory	/workspace/1.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2176580788
Short name	T5
Test name
Test status
Simulation time	30614089 ps
CPU time	0.42 seconds
Started	May 29 12:22:38 AM PDT 23
Finished	May 29 12:22:38 AM PDT 23
Peak memory	145820 kb
Host	smart-a4d0ab79-371e-477c-abf3-fb9f909909e1
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2176580788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2176580788
Directory	/workspace/12.prim_async_fatal_alert/latest

Test location	/workspace/coverage/sync_alert/10.prim_sync_alert.215055875
Short name	T16
Test name
Test status
Simulation time	9438960 ps
CPU time	0.39 seconds
Started	May 29 12:50:31 AM PDT 23
Finished	May 29 12:50:32 AM PDT 23
Peak memory	145352 kb
Host	smart-67253b17-549d-40ca-a6b2-3bdea8f7c5f1
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=215055875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.215055875
Directory	/workspace/10.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/16.prim_sync_alert.3427243381
Short name	T12
Test name
Test status
Simulation time	8843035 ps
CPU time	0.42 seconds
Started	May 29 12:50:31 AM PDT 23
Finished	May 29 12:50:32 AM PDT 23
Peak memory	145412 kb
Host	smart-7788dc87-305a-4b28-97d8-1aab11f0e6fd
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3427243381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3427243381
Directory	/workspace/16.prim_sync_alert/latest

Test location	/workspace/coverage/default/0.prim_async_alert.1946295761
Short name	T20
Test name
Test status
Simulation time	11930609 ps
CPU time	0.51 seconds
Started	May 29 12:23:25 AM PDT 23
Finished	May 29 12:23:26 AM PDT 23
Peak memory	145320 kb
Host	smart-fc45a33b-5b1e-4ebe-b659-0edfb4bcb289
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1946295761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1946295761
Directory	/workspace/0.prim_async_alert/latest

Test location	/workspace/coverage/default/10.prim_async_alert.1347613737
Short name	T8
Test name
Test status
Simulation time	11229943 ps
CPU time	0.38 seconds
Started	May 29 12:25:16 AM PDT 23
Finished	May 29 12:25:16 AM PDT 23
Peak memory	145536 kb
Host	smart-cb5acdfc-7ecd-444f-9e54-972248f31446
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1347613737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1347613737
Directory	/workspace/10.prim_async_alert/latest

Test location	/workspace/coverage/default/12.prim_async_alert.3268174761
Short name	T22
Test name
Test status
Simulation time	11367830 ps
CPU time	0.38 seconds
Started	May 29 12:23:29 AM PDT 23
Finished	May 29 12:23:30 AM PDT 23
Peak memory	145324 kb
Host	smart-cd87e3f6-9c10-42f5-b8aa-f2142c6a8fbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3268174761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3268174761
Directory	/workspace/12.prim_async_alert/latest

Test location	/workspace/coverage/default/13.prim_async_alert.2297067822
Short name	T3
Test name
Test status
Simulation time	10705145 ps
CPU time	0.44 seconds
Started	May 29 12:25:03 AM PDT 23
Finished	May 29 12:25:05 AM PDT 23
Peak memory	145312 kb
Host	smart-96a375d2-126a-45df-9bb9-834410143580
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2297067822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2297067822
Directory	/workspace/13.prim_async_alert/latest

Test location	/workspace/coverage/default/14.prim_async_alert.1778003289
Short name	T9
Test name
Test status
Simulation time	11759398 ps
CPU time	0.42 seconds
Started	May 29 12:23:56 AM PDT 23
Finished	May 29 12:23:57 AM PDT 23
Peak memory	145452 kb
Host	smart-5626c4ad-e106-47a8-a5b9-19450ab047c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1778003289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1778003289
Directory	/workspace/14.prim_async_alert/latest

Test location	/workspace/coverage/default/15.prim_async_alert.1939231732
Short name	T10
Test name
Test status
Simulation time	11646902 ps
CPU time	0.38 seconds
Started	May 29 12:25:02 AM PDT 23
Finished	May 29 12:25:03 AM PDT 23
Peak memory	145528 kb
Host	smart-f8d0b5a7-db76-4e0e-87db-58319f87230d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1939231732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1939231732
Directory	/workspace/15.prim_async_alert/latest

Test location	/workspace/coverage/default/16.prim_async_alert.3738752299
Short name	T2
Test name
Test status
Simulation time	11345217 ps
CPU time	0.42 seconds
Started	May 29 12:23:31 AM PDT 23
Finished	May 29 12:23:31 AM PDT 23
Peak memory	145408 kb
Host	smart-09bf3bc3-6651-4817-b45e-49a39217173f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3738752299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3738752299
Directory	/workspace/16.prim_async_alert/latest

Test location	/workspace/coverage/default/17.prim_async_alert.4090526373
Short name	T15
Test name
Test status
Simulation time	10953213 ps
CPU time	0.4 seconds
Started	May 29 12:23:24 AM PDT 23
Finished	May 29 12:23:25 AM PDT 23
Peak memory	145748 kb
Host	smart-1c3d1b3d-7dfd-4613-be2d-594ccc5454b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4090526373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.4090526373
Directory	/workspace/17.prim_async_alert/latest

Test location	/workspace/coverage/default/18.prim_async_alert.2823683820
Short name	T46
Test name
Test status
Simulation time	11415333 ps
CPU time	0.39 seconds
Started	May 29 12:23:24 AM PDT 23
Finished	May 29 12:23:25 AM PDT 23
Peak memory	145372 kb
Host	smart-fb4f6660-2230-4c30-a4b2-574cefd9f622
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2823683820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2823683820
Directory	/workspace/18.prim_async_alert/latest

Test location	/workspace/coverage/default/19.prim_async_alert.3150471975
Short name	T17
Test name
Test status
Simulation time	10973926 ps
CPU time	0.38 seconds
Started	May 29 12:24:11 AM PDT 23
Finished	May 29 12:24:12 AM PDT 23
Peak memory	145496 kb
Host	smart-23e4ad78-8a01-4482-bb8f-2bd544658fe0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150471975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3150471975
Directory	/workspace/19.prim_async_alert/latest

Test location	/workspace/coverage/default/3.prim_async_alert.3618928789
Short name	T18
Test name
Test status
Simulation time	10853944 ps
CPU time	0.45 seconds
Started	May 29 12:22:19 AM PDT 23
Finished	May 29 12:22:20 AM PDT 23
Peak memory	145320 kb
Host	smart-9b4091db-5eef-45e6-a983-7579a0de4687
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3618928789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3618928789
Directory	/workspace/3.prim_async_alert/latest

Test location	/workspace/coverage/default/4.prim_async_alert.1779299588
Short name	T23
Test name
Test status
Simulation time	11063377 ps
CPU time	0.44 seconds
Started	May 29 12:23:35 AM PDT 23
Finished	May 29 12:23:37 AM PDT 23
Peak memory	145340 kb
Host	smart-b08b4cac-a3c4-4502-95bc-d2c3cf306c94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1779299588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1779299588
Directory	/workspace/4.prim_async_alert/latest

Test location	/workspace/coverage/default/5.prim_async_alert.2560354514
Short name	T47
Test name
Test status
Simulation time	11337317 ps
CPU time	0.37 seconds
Started	May 29 12:23:44 AM PDT 23
Finished	May 29 12:23:45 AM PDT 23
Peak memory	145392 kb
Host	smart-20ec1737-9de4-40cb-8149-1af4d503093e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2560354514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2560354514
Directory	/workspace/5.prim_async_alert/latest

Test location	/workspace/coverage/default/6.prim_async_alert.3193852565
Short name	T25
Test name
Test status
Simulation time	11694105 ps
CPU time	0.47 seconds
Started	May 29 12:24:59 AM PDT 23
Finished	May 29 12:25:01 AM PDT 23
Peak memory	145320 kb
Host	smart-e12e7e1e-d9c3-4b0b-8710-82eb5625e02a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3193852565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3193852565
Directory	/workspace/6.prim_async_alert/latest

Test location	/workspace/coverage/default/7.prim_async_alert.2082766803
Short name	T19
Test name
Test status
Simulation time	11078342 ps
CPU time	0.45 seconds
Started	May 29 12:23:30 AM PDT 23
Finished	May 29 12:23:31 AM PDT 23
Peak memory	145408 kb
Host	smart-e30f39bc-52e1-4514-a9dc-348c253dc276
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2082766803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2082766803
Directory	/workspace/7.prim_async_alert/latest

Test location	/workspace/coverage/default/8.prim_async_alert.1872824635
Short name	T21
Test name
Test status
Simulation time	11438204 ps
CPU time	0.38 seconds
Started	May 29 12:25:10 AM PDT 23
Finished	May 29 12:25:11 AM PDT 23
Peak memory	145552 kb
Host	smart-170e5c30-3ac8-44fa-b3b4-c368267399bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1872824635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1872824635
Directory	/workspace/8.prim_async_alert/latest

Test location	/workspace/coverage/default/9.prim_async_alert.2020143456
Short name	T7
Test name
Test status
Simulation time	11520163 ps
CPU time	0.4 seconds
Started	May 29 12:23:58 AM PDT 23
Finished	May 29 12:23:59 AM PDT 23
Peak memory	145804 kb
Host	smart-7d021cd3-c066-4fdd-85be-0862a84784f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2020143456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2020143456
Directory	/workspace/9.prim_async_alert/latest

Test location	/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.330255359
Short name	T50
Test name
Test status
Simulation time	29329915 ps
CPU time	0.41 seconds
Started	May 29 12:23:35 AM PDT 23
Finished	May 29 12:23:37 AM PDT 23
Peak memory	145152 kb
Host	smart-067cfeb9-aaed-4e03-ad64-0bfeddec4fa6
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=330255359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.330255359
Directory	/workspace/0.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1105534505
Short name	T41
Test name
Test status
Simulation time	29789895 ps
CPU time	0.43 seconds
Started	May 29 12:22:39 AM PDT 23
Finished	May 29 12:22:40 AM PDT 23
Peak memory	143568 kb
Host	smart-1c44bb02-49d6-4d5e-94f1-5a8ee15c476a
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1105534505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1105534505
Directory	/workspace/10.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2201839525
Short name	T42
Test name
Test status
Simulation time	31861583 ps
CPU time	0.42 seconds
Started	May 29 12:23:25 AM PDT 23
Finished	May 29 12:23:26 AM PDT 23
Peak memory	145228 kb
Host	smart-7739d0c2-32b8-4bed-ad9d-7507814edf3a
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2201839525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2201839525
Directory	/workspace/13.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2997579047
Short name	T55
Test name
Test status
Simulation time	28581443 ps
CPU time	0.43 seconds
Started	May 29 12:22:16 AM PDT 23
Finished	May 29 12:22:17 AM PDT 23
Peak memory	145512 kb
Host	smart-3bf72db9-4109-40db-936c-3d32640cf6e0
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2997579047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2997579047
Directory	/workspace/14.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.979575216
Short name	T44
Test name
Test status
Simulation time	29185208 ps
CPU time	0.4 seconds
Started	May 29 12:24:05 AM PDT 23
Finished	May 29 12:24:06 AM PDT 23
Peak memory	145272 kb
Host	smart-aa716db3-71e6-4d7f-bdee-aeafd39d094d
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=979575216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.979575216
Directory	/workspace/15.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2271736461
Short name	T51
Test name
Test status
Simulation time	30730107 ps
CPU time	0.44 seconds
Started	May 29 12:22:39 AM PDT 23
Finished	May 29 12:22:40 AM PDT 23
Peak memory	143740 kb
Host	smart-7bb8ec48-6cf9-4dfd-81e8-8eb3038a4507
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2271736461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2271736461
Directory	/workspace/16.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1605402149
Short name	T40
Test name
Test status
Simulation time	27513077 ps
CPU time	0.39 seconds
Started	May 29 12:24:23 AM PDT 23
Finished	May 29 12:24:23 AM PDT 23
Peak memory	145460 kb
Host	smart-adabd4ac-31f4-46ea-aaec-d8bcd4494c3e
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1605402149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1605402149
Directory	/workspace/17.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1802265715
Short name	T49
Test name
Test status
Simulation time	30931307 ps
CPU time	0.44 seconds
Started	May 29 12:23:44 AM PDT 23
Finished	May 29 12:23:45 AM PDT 23
Peak memory	145136 kb
Host	smart-b69f0879-cbd7-4683-ba61-d74d79f82054
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1802265715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1802265715
Directory	/workspace/18.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3110079036
Short name	T45
Test name
Test status
Simulation time	30027844 ps
CPU time	0.46 seconds
Started	May 29 12:23:44 AM PDT 23
Finished	May 29 12:23:45 AM PDT 23
Peak memory	145100 kb
Host	smart-b74dc9cb-a300-4681-89b0-a480e54a3957
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3110079036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3110079036
Directory	/workspace/19.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1218847062
Short name	T48
Test name
Test status
Simulation time	27748026 ps
CPU time	0.49 seconds
Started	May 29 12:23:35 AM PDT 23
Finished	May 29 12:23:37 AM PDT 23
Peak memory	144756 kb
Host	smart-1a1d2aa8-2112-4f91-aff0-5dc5a2c2ed6f
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1218847062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1218847062
Directory	/workspace/2.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3429787560
Short name	T43
Test name
Test status
Simulation time	30977645 ps
CPU time	0.42 seconds
Started	May 29 12:22:39 AM PDT 23
Finished	May 29 12:22:40 AM PDT 23
Peak memory	144640 kb
Host	smart-5240729c-ea91-4592-a763-e30452c6be18
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3429787560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3429787560
Directory	/workspace/3.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2733390653
Short name	T4
Test name
Test status
Simulation time	28644434 ps
CPU time	0.43 seconds
Started	May 29 12:24:04 AM PDT 23
Finished	May 29 12:24:05 AM PDT 23
Peak memory	144596 kb
Host	smart-f87798dc-b520-4606-8e9a-922aaad12567
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2733390653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2733390653
Directory	/workspace/4.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.756792058
Short name	T52
Test name
Test status
Simulation time	32405268 ps
CPU time	0.45 seconds
Started	May 29 12:23:50 AM PDT 23
Finished	May 29 12:23:51 AM PDT 23
Peak memory	144436 kb
Host	smart-a044cd02-ed61-4152-9a47-e896b3ea601b
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=756792058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.756792058
Directory	/workspace/5.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3553165272
Short name	T6
Test name
Test status
Simulation time	31060398 ps
CPU time	0.39 seconds
Started	May 29 12:22:25 AM PDT 23
Finished	May 29 12:22:26 AM PDT 23
Peak memory	145464 kb
Host	smart-348eaf83-79ac-4bb0-b483-3e029a230be0
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3553165272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3553165272
Directory	/workspace/6.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.92732564
Short name	T14
Test name
Test status
Simulation time	30149611 ps
CPU time	0.48 seconds
Started	May 29 12:22:18 AM PDT 23
Finished	May 29 12:22:18 AM PDT 23
Peak memory	145388 kb
Host	smart-c66e2a7a-c0e8-4953-b272-054106fa93f3
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=92732564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.92732564
Directory	/workspace/7.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4235788528
Short name	T54
Test name
Test status
Simulation time	29434448 ps
CPU time	0.44 seconds
Started	May 29 12:23:25 AM PDT 23
Finished	May 29 12:23:26 AM PDT 23
Peak memory	144992 kb
Host	smart-9ae48fa0-031b-4d42-a9e2-d6640896c6aa
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4235788528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.4235788528
Directory	/workspace/8.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1599823259
Short name	T53
Test name
Test status
Simulation time	30362264 ps
CPU time	0.43 seconds
Started	May 29 12:23:50 AM PDT 23
Finished	May 29 12:23:51 AM PDT 23
Peak memory	145088 kb
Host	smart-96995aad-e490-4454-b69c-7c1398000b64
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1599823259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1599823259
Directory	/workspace/9.prim_async_fatal_alert/latest

Test location	/workspace/coverage/sync_alert/1.prim_sync_alert.3672823955
Short name	T57
Test name
Test status
Simulation time	9909101 ps
CPU time	0.41 seconds
Started	May 29 12:50:23 AM PDT 23
Finished	May 29 12:50:25 AM PDT 23
Peak memory	145488 kb
Host	smart-43bde1ba-742b-419f-8a80-c9d3f1a962be
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3672823955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3672823955
Directory	/workspace/1.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/11.prim_sync_alert.811510603
Short name	T36
Test name
Test status
Simulation time	9204935 ps
CPU time	0.4 seconds
Started	May 29 12:50:23 AM PDT 23
Finished	May 29 12:50:25 AM PDT 23
Peak memory	145492 kb
Host	smart-6a63f78c-ba63-4343-ac4a-f8eb37869ffc
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=811510603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.811510603
Directory	/workspace/11.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/12.prim_sync_alert.1169106198
Short name	T29
Test name
Test status
Simulation time	9669921 ps
CPU time	0.38 seconds
Started	May 29 12:50:31 AM PDT 23
Finished	May 29 12:50:32 AM PDT 23
Peak memory	145412 kb
Host	smart-11eb0478-e15e-489a-84c3-7cac1e49d4cc
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1169106198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1169106198
Directory	/workspace/12.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/13.prim_sync_alert.164053926
Short name	T33
Test name
Test status
Simulation time	8620618 ps
CPU time	0.38 seconds
Started	May 29 12:50:21 AM PDT 23
Finished	May 29 12:50:22 AM PDT 23
Peak memory	145352 kb
Host	smart-5da19309-ba98-4496-b1e6-0b8e7dbe1f07
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=164053926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.164053926
Directory	/workspace/13.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/14.prim_sync_alert.456347597
Short name	T58
Test name
Test status
Simulation time	10414111 ps
CPU time	0.38 seconds
Started	May 29 12:50:22 AM PDT 23
Finished	May 29 12:50:23 AM PDT 23
Peak memory	145432 kb
Host	smart-3a7eb6c7-6630-4c0c-81a0-f998b0a7a381
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=456347597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.456347597
Directory	/workspace/14.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/15.prim_sync_alert.1403194002
Short name	T30
Test name
Test status
Simulation time	9584736 ps
CPU time	0.42 seconds
Started	May 29 12:50:31 AM PDT 23
Finished	May 29 12:50:32 AM PDT 23
Peak memory	145160 kb
Host	smart-c7df1110-7a6f-4b5b-9637-8535528a94d6
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1403194002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1403194002
Directory	/workspace/15.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/17.prim_sync_alert.2133062828
Short name	T39
Test name
Test status
Simulation time	9075908 ps
CPU time	0.38 seconds
Started	May 29 12:50:23 AM PDT 23
Finished	May 29 12:50:23 AM PDT 23
Peak memory	145488 kb
Host	smart-653c5880-f64f-4ee7-830d-200c411bff0b
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2133062828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2133062828
Directory	/workspace/17.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/18.prim_sync_alert.2943332955
Short name	T11
Test name
Test status
Simulation time	9355847 ps
CPU time	0.41 seconds
Started	May 29 12:50:22 AM PDT 23
Finished	May 29 12:50:23 AM PDT 23
Peak memory	145348 kb
Host	smart-08b4175c-8431-456d-9c7d-3c8d0ed36413
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2943332955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2943332955
Directory	/workspace/18.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/19.prim_sync_alert.88979129
Short name	T38
Test name
Test status
Simulation time	8480711 ps
CPU time	0.39 seconds
Started	May 29 12:51:00 AM PDT 23
Finished	May 29 12:51:01 AM PDT 23
Peak memory	145524 kb
Host	smart-bcfe8e5e-212d-4cf2-86dc-307e69bc9163
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=88979129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.88979129
Directory	/workspace/19.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/2.prim_sync_alert.976417050
Short name	T34
Test name
Test status
Simulation time	9137922 ps
CPU time	0.38 seconds
Started	May 29 12:50:11 AM PDT 23
Finished	May 29 12:50:11 AM PDT 23
Peak memory	145416 kb
Host	smart-703fa269-369e-4fb5-9f0c-b3e1980c4a5b
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=976417050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.976417050
Directory	/workspace/2.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/3.prim_sync_alert.864008895
Short name	T31
Test name
Test status
Simulation time	8127196 ps
CPU time	0.43 seconds
Started	May 29 12:50:31 AM PDT 23
Finished	May 29 12:50:32 AM PDT 23
Peak memory	144940 kb
Host	smart-e41afcd1-d039-4d10-ae08-c66c44aa5048
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=864008895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.864008895
Directory	/workspace/3.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/4.prim_sync_alert.1309753693
Short name	T56
Test name
Test status
Simulation time	8959712 ps
CPU time	0.41 seconds
Started	May 29 12:50:16 AM PDT 23
Finished	May 29 12:50:17 AM PDT 23
Peak memory	145504 kb
Host	smart-843ba56f-8484-4717-acde-f517b91c8bf6
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1309753693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1309753693
Directory	/workspace/4.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/5.prim_sync_alert.531111739
Short name	T27
Test name
Test status
Simulation time	8505588 ps
CPU time	0.38 seconds
Started	May 29 12:50:20 AM PDT 23
Finished	May 29 12:50:21 AM PDT 23
Peak memory	145524 kb
Host	smart-2a884bc0-d49c-4d91-bdc5-1d52bfe02f34
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=531111739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.531111739
Directory	/workspace/5.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/6.prim_sync_alert.2181966576
Short name	T26
Test name
Test status
Simulation time	8711478 ps
CPU time	0.38 seconds
Started	May 29 12:50:23 AM PDT 23
Finished	May 29 12:50:24 AM PDT 23
Peak memory	145348 kb
Host	smart-26711843-ffcb-47ca-989d-c148e3b58b58
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2181966576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2181966576
Directory	/workspace/6.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/7.prim_sync_alert.1208261638
Short name	T28
Test name
Test status
Simulation time	8877314 ps
CPU time	0.38 seconds
Started	May 29 12:50:23 AM PDT 23
Finished	May 29 12:50:24 AM PDT 23
Peak memory	145488 kb
Host	smart-d707de15-5a5a-41f5-8754-d7b6bfed9903
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1208261638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1208261638
Directory	/workspace/7.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/8.prim_sync_alert.2204301161
Short name	T37
Test name
Test status
Simulation time	9346936 ps
CPU time	0.42 seconds
Started	May 29 12:50:31 AM PDT 23
Finished	May 29 12:50:32 AM PDT 23
Peak memory	144872 kb
Host	smart-d9c0a461-9be0-4c2c-8545-70d81f151447
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2204301161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2204301161
Directory	/workspace/8.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/9.prim_sync_alert.146581337
Short name	T32
Test name
Test status
Simulation time	10423771 ps
CPU time	0.41 seconds
Started	May 29 12:50:23 AM PDT 23
Finished	May 29 12:50:25 AM PDT 23
Peak memory	145492 kb
Host	smart-85d9c345-df3c-4777-8a5d-70577a0da664
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=146581337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.146581337
Directory	/workspace/9.prim_sync_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.561907157
Short name	T62
Test name
Test status
Simulation time	26226111 ps
CPU time	0.4 seconds
Started	May 29 12:50:22 AM PDT 23
Finished	May 29 12:50:23 AM PDT 23
Peak memory	144972 kb
Host	smart-c607be30-0856-49b5-9445-81860efd173f
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=561907157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.561907157
Directory	/workspace/0.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.61296254
Short name	T59
Test name
Test status
Simulation time	28014533 ps
CPU time	0.39 seconds
Started	May 29 12:50:22 AM PDT 23
Finished	May 29 12:50:23 AM PDT 23
Peak memory	145052 kb
Host	smart-dc6e7cde-26f8-4814-8273-c7a7043d5570
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=61296254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.61296254
Directory	/workspace/1.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3083085206
Short name	T67
Test name
Test status
Simulation time	27207757 ps
CPU time	0.4 seconds
Started	May 29 12:50:14 AM PDT 23
Finished	May 29 12:50:15 AM PDT 23
Peak memory	145068 kb
Host	smart-4a155ae7-e7f1-47ea-9e49-ed924cf17ed2
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3083085206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3083085206
Directory	/workspace/10.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3803009447
Short name	T74
Test name
Test status
Simulation time	29353237 ps
CPU time	0.4 seconds
Started	May 29 12:50:18 AM PDT 23
Finished	May 29 12:50:18 AM PDT 23
Peak memory	144924 kb
Host	smart-3c928624-bb27-405e-9518-ac7011ce9f95
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3803009447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3803009447
Directory	/workspace/11.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2796946271
Short name	T71
Test name
Test status
Simulation time	27167530 ps
CPU time	0.4 seconds
Started	May 29 12:50:15 AM PDT 23
Finished	May 29 12:50:16 AM PDT 23
Peak memory	145048 kb
Host	smart-ff3688a1-8847-43f0-93fc-efd7720673d1
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2796946271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2796946271
Directory	/workspace/12.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3317308758
Short name	T72
Test name
Test status
Simulation time	25973881 ps
CPU time	0.4 seconds
Started	May 29 12:50:13 AM PDT 23
Finished	May 29 12:50:14 AM PDT 23
Peak memory	144968 kb
Host	smart-6c24bf5e-7364-4395-9d7d-450810ca0399
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3317308758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3317308758
Directory	/workspace/13.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.416825946
Short name	T66
Test name
Test status
Simulation time	27698627 ps
CPU time	0.39 seconds
Started	May 29 12:50:09 AM PDT 23
Finished	May 29 12:50:09 AM PDT 23
Peak memory	145064 kb
Host	smart-c0cc3656-b275-4afb-aaac-e01a2dad117a
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=416825946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.416825946
Directory	/workspace/14.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1118487575
Short name	T73
Test name
Test status
Simulation time	29197852 ps
CPU time	0.4 seconds
Started	May 29 12:50:07 AM PDT 23
Finished	May 29 12:50:08 AM PDT 23
Peak memory	145004 kb
Host	smart-ccab527c-7625-4535-b770-743c9400b16d
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1118487575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1118487575
Directory	/workspace/15.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1200654324
Short name	T75
Test name
Test status
Simulation time	26865055 ps
CPU time	0.4 seconds
Started	May 29 12:50:13 AM PDT 23
Finished	May 29 12:50:14 AM PDT 23
Peak memory	145044 kb
Host	smart-087cd8d3-60a9-4832-8699-54d5115613cd
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1200654324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1200654324
Directory	/workspace/16.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1401388736
Short name	T69
Test name
Test status
Simulation time	27394976 ps
CPU time	0.41 seconds
Started	May 29 12:50:14 AM PDT 23
Finished	May 29 12:50:15 AM PDT 23
Peak memory	145068 kb
Host	smart-b0fe872d-89fa-4cfc-93ed-3461da6a2116
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1401388736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1401388736
Directory	/workspace/17.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2157330673
Short name	T13
Test name
Test status
Simulation time	27898549 ps
CPU time	0.44 seconds
Started	May 29 12:50:18 AM PDT 23
Finished	May 29 12:50:18 AM PDT 23
Peak memory	145068 kb
Host	smart-c3ebc0fb-d101-404b-8daa-abe403c860b9
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2157330673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2157330673
Directory	/workspace/18.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2256620375
Short name	T64
Test name
Test status
Simulation time	28401045 ps
CPU time	0.41 seconds
Started	May 29 12:50:18 AM PDT 23
Finished	May 29 12:50:18 AM PDT 23
Peak memory	145068 kb
Host	smart-5c3fc563-48e6-424e-9b49-95bdff99366e
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2256620375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2256620375
Directory	/workspace/19.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1244345444
Short name	T60
Test name
Test status
Simulation time	26861832 ps
CPU time	0.4 seconds
Started	May 29 12:50:13 AM PDT 23
Finished	May 29 12:50:14 AM PDT 23
Peak memory	145068 kb
Host	smart-38996eab-598d-48a0-aeb7-be0763605744
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1244345444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1244345444
Directory	/workspace/2.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2476606850
Short name	T76
Test name
Test status
Simulation time	27031537 ps
CPU time	0.41 seconds
Started	May 29 12:50:09 AM PDT 23
Finished	May 29 12:50:09 AM PDT 23
Peak memory	145064 kb
Host	smart-6cf9b581-c667-45b7-9552-e23e60817000
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2476606850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2476606850
Directory	/workspace/3.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3784807179
Short name	T77
Test name
Test status
Simulation time	27131584 ps
CPU time	0.39 seconds
Started	May 29 12:50:17 AM PDT 23
Finished	May 29 12:50:17 AM PDT 23
Peak memory	144984 kb
Host	smart-36870ff7-bf78-4532-90c4-ae411f7457b3
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3784807179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3784807179
Directory	/workspace/4.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2705842088
Short name	T70
Test name
Test status
Simulation time	27339492 ps
CPU time	0.39 seconds
Started	May 29 12:50:02 AM PDT 23
Finished	May 29 12:50:02 AM PDT 23
Peak memory	145068 kb
Host	smart-be391ed5-5004-46ae-836e-5212de7c9e6d
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2705842088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2705842088
Directory	/workspace/5.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2442367095
Short name	T61
Test name
Test status
Simulation time	27353097 ps
CPU time	0.43 seconds
Started	May 29 12:50:10 AM PDT 23
Finished	May 29 12:50:11 AM PDT 23
Peak memory	145064 kb
Host	smart-a884be79-7a0f-4137-9ddc-4413288c4785
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2442367095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2442367095
Directory	/workspace/6.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.173755986
Short name	T68
Test name
Test status
Simulation time	30083600 ps
CPU time	0.41 seconds
Started	May 29 12:50:10 AM PDT 23
Finished	May 29 12:50:11 AM PDT 23
Peak memory	145044 kb
Host	smart-c8e2c82e-ebb5-415d-8c35-e855640aa72a
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=173755986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.173755986
Directory	/workspace/7.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.951285993
Short name	T63
Test name
Test status
Simulation time	27786132 ps
CPU time	0.4 seconds
Started	May 29 12:50:18 AM PDT 23
Finished	May 29 12:50:18 AM PDT 23
Peak memory	144912 kb
Host	smart-9e2ac9c2-c84b-451e-98ac-561df50557e7
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=951285993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.951285993
Directory	/workspace/8.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2092524064
Short name	T65
Test name
Test status
Simulation time	28337449 ps
CPU time	0.4 seconds
Started	May 29 12:50:13 AM PDT 23
Finished	May 29 12:50:14 AM PDT 23
Peak memory	144968 kb
Host	smart-64ac5216-129e-4f33-ad23-a375edea375e
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2092524064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2092524064
Directory	/workspace/9.prim_sync_fatal_alert/latest