Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.67 88.67 100.00 100.00 93.75 93.75 96.43 96.43 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/14.prim_async_alert.1621645476
91.80 3.13 100.00 0.00 93.75 0.00 96.43 0.00 85.71 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/0.prim_sync_alert.1112550862
93.90 2.11 100.00 0.00 95.83 2.08 100.00 3.57 85.71 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1743915281
94.50 0.60 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/13.prim_async_alert.3563889085
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2202736169

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.1733001013
/workspace/coverage/default/1.prim_async_alert.4081744569
/workspace/coverage/default/10.prim_async_alert.1549134658
/workspace/coverage/default/11.prim_async_alert.4095275496
/workspace/coverage/default/12.prim_async_alert.357744396
/workspace/coverage/default/15.prim_async_alert.2795019025
/workspace/coverage/default/16.prim_async_alert.1918707884
/workspace/coverage/default/17.prim_async_alert.3309839374
/workspace/coverage/default/18.prim_async_alert.3910739469
/workspace/coverage/default/19.prim_async_alert.2907264097
/workspace/coverage/default/2.prim_async_alert.2908353207
/workspace/coverage/default/3.prim_async_alert.385840786
/workspace/coverage/default/4.prim_async_alert.1937954071
/workspace/coverage/default/5.prim_async_alert.2063926912
/workspace/coverage/default/6.prim_async_alert.2125145173
/workspace/coverage/default/7.prim_async_alert.868238454
/workspace/coverage/default/8.prim_async_alert.2379418992
/workspace/coverage/default/9.prim_async_alert.2947826954
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4247069454
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2156024446
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1536467415
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.671561043
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3914268837
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1916208021
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2763202088
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.79963334
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1671140156
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2001553193
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1291163212
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1093955026
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3983948604
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2994707492
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1461100830
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1117558511
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2865642768
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2990766812
/workspace/coverage/sync_alert/1.prim_sync_alert.3754524921
/workspace/coverage/sync_alert/10.prim_sync_alert.3575263831
/workspace/coverage/sync_alert/11.prim_sync_alert.1801593905
/workspace/coverage/sync_alert/12.prim_sync_alert.2561885506
/workspace/coverage/sync_alert/13.prim_sync_alert.2026370536
/workspace/coverage/sync_alert/14.prim_sync_alert.1465688607
/workspace/coverage/sync_alert/15.prim_sync_alert.3537723725
/workspace/coverage/sync_alert/16.prim_sync_alert.797142468
/workspace/coverage/sync_alert/17.prim_sync_alert.411984024
/workspace/coverage/sync_alert/18.prim_sync_alert.2631571601
/workspace/coverage/sync_alert/19.prim_sync_alert.489272986
/workspace/coverage/sync_alert/2.prim_sync_alert.1466063862
/workspace/coverage/sync_alert/3.prim_sync_alert.1411335407
/workspace/coverage/sync_alert/4.prim_sync_alert.3388536057
/workspace/coverage/sync_alert/5.prim_sync_alert.2644326598
/workspace/coverage/sync_alert/6.prim_sync_alert.2261599314
/workspace/coverage/sync_alert/7.prim_sync_alert.2844165226
/workspace/coverage/sync_alert/8.prim_sync_alert.2282344389
/workspace/coverage/sync_alert/9.prim_sync_alert.762521210
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.945074911
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3854913763
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1550064141
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1583192492
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1675415571
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2521089688
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1477800982
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2779759197
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2887416918
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.644197117
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.741601646
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2411838200
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.252838395
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3801700685
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4029948133
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1075061054
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4257731685
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2966642992
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2469805579
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3645382595



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/15.prim_async_alert.2795019025 Oct 01 12:18:14 PM PDT 23 Oct 01 12:18:15 PM PDT 23 11716284 ps
T2 /workspace/coverage/default/3.prim_async_alert.385840786 Oct 01 12:15:06 PM PDT 23 Oct 01 12:15:08 PM PDT 23 11786033 ps
T3 /workspace/coverage/default/6.prim_async_alert.2125145173 Oct 01 12:19:33 PM PDT 23 Oct 01 12:19:34 PM PDT 23 11364174 ps
T7 /workspace/coverage/default/14.prim_async_alert.1621645476 Oct 01 12:21:52 PM PDT 23 Oct 01 12:21:53 PM PDT 23 11110075 ps
T8 /workspace/coverage/default/0.prim_async_alert.1733001013 Oct 01 12:21:06 PM PDT 23 Oct 01 12:21:06 PM PDT 23 10547143 ps
T16 /workspace/coverage/default/10.prim_async_alert.1549134658 Oct 01 12:19:23 PM PDT 23 Oct 01 12:19:24 PM PDT 23 10921183 ps
T9 /workspace/coverage/default/4.prim_async_alert.1937954071 Oct 01 12:18:08 PM PDT 23 Oct 01 12:18:08 PM PDT 23 10928420 ps
T17 /workspace/coverage/default/1.prim_async_alert.4081744569 Oct 01 12:21:16 PM PDT 23 Oct 01 12:21:16 PM PDT 23 11168642 ps
T18 /workspace/coverage/default/5.prim_async_alert.2063926912 Oct 01 12:18:51 PM PDT 23 Oct 01 12:18:52 PM PDT 23 11604264 ps
T19 /workspace/coverage/default/12.prim_async_alert.357744396 Oct 01 12:19:23 PM PDT 23 Oct 01 12:19:24 PM PDT 23 10818509 ps
T14 /workspace/coverage/default/2.prim_async_alert.2908353207 Oct 01 12:20:23 PM PDT 23 Oct 01 12:20:23 PM PDT 23 11590319 ps
T20 /workspace/coverage/default/16.prim_async_alert.1918707884 Oct 01 12:20:12 PM PDT 23 Oct 01 12:20:14 PM PDT 23 11899466 ps
T15 /workspace/coverage/default/11.prim_async_alert.4095275496 Oct 01 12:19:18 PM PDT 23 Oct 01 12:19:19 PM PDT 23 11112878 ps
T10 /workspace/coverage/default/13.prim_async_alert.3563889085 Oct 01 12:19:32 PM PDT 23 Oct 01 12:19:32 PM PDT 23 12245137 ps
T44 /workspace/coverage/default/8.prim_async_alert.2379418992 Oct 01 12:20:21 PM PDT 23 Oct 01 12:20:21 PM PDT 23 11091254 ps
T13 /workspace/coverage/default/7.prim_async_alert.868238454 Oct 01 12:21:32 PM PDT 23 Oct 01 12:21:32 PM PDT 23 10397226 ps
T21 /workspace/coverage/default/19.prim_async_alert.2907264097 Oct 01 12:14:16 PM PDT 23 Oct 01 12:14:17 PM PDT 23 11260920 ps
T22 /workspace/coverage/default/9.prim_async_alert.2947826954 Oct 01 12:18:04 PM PDT 23 Oct 01 12:18:05 PM PDT 23 11182317 ps
T23 /workspace/coverage/default/18.prim_async_alert.3910739469 Oct 01 12:19:23 PM PDT 23 Oct 01 12:19:23 PM PDT 23 10730380 ps
T24 /workspace/coverage/default/17.prim_async_alert.3309839374 Oct 01 12:21:20 PM PDT 23 Oct 01 12:21:21 PM PDT 23 11029337 ps
T11 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1117558511 Oct 01 12:20:20 PM PDT 23 Oct 01 12:20:21 PM PDT 23 30085441 ps
T25 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2156024446 Oct 01 12:21:15 PM PDT 23 Oct 01 12:21:15 PM PDT 23 30872201 ps
T38 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4247069454 Oct 01 12:19:42 PM PDT 23 Oct 01 12:19:43 PM PDT 23 30057322 ps
T39 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3914268837 Oct 01 12:20:28 PM PDT 23 Oct 01 12:20:28 PM PDT 23 31642413 ps
T40 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2990766812 Oct 01 12:19:33 PM PDT 23 Oct 01 12:19:34 PM PDT 23 29537944 ps
T41 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1743915281 Oct 01 12:20:41 PM PDT 23 Oct 01 12:20:42 PM PDT 23 31193844 ps
T42 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1671140156 Oct 01 12:18:30 PM PDT 23 Oct 01 12:18:31 PM PDT 23 31265227 ps
T4 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2202736169 Oct 01 12:15:53 PM PDT 23 Oct 01 12:15:53 PM PDT 23 29514773 ps
T36 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.79963334 Oct 01 12:15:53 PM PDT 23 Oct 01 12:15:54 PM PDT 23 30750724 ps
T43 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1916208021 Oct 01 12:20:51 PM PDT 23 Oct 01 12:20:52 PM PDT 23 29170238 ps
T45 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2001553193 Oct 01 12:20:43 PM PDT 23 Oct 01 12:20:44 PM PDT 23 30279500 ps
T5 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3983948604 Oct 01 12:20:46 PM PDT 23 Oct 01 12:20:47 PM PDT 23 31090070 ps
T37 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.671561043 Oct 01 12:21:19 PM PDT 23 Oct 01 12:21:19 PM PDT 23 31337407 ps
T46 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2763202088 Oct 01 12:21:32 PM PDT 23 Oct 01 12:21:33 PM PDT 23 29111958 ps
T12 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1291163212 Oct 01 12:21:01 PM PDT 23 Oct 01 12:21:02 PM PDT 23 30440693 ps
T47 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1461100830 Oct 01 12:21:02 PM PDT 23 Oct 01 12:21:03 PM PDT 23 29826740 ps
T6 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1093955026 Oct 01 12:14:29 PM PDT 23 Oct 01 12:14:30 PM PDT 23 33544021 ps
T48 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2994707492 Oct 01 12:21:02 PM PDT 23 Oct 01 12:21:03 PM PDT 23 28399391 ps
T49 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2865642768 Oct 01 12:20:36 PM PDT 23 Oct 01 12:20:36 PM PDT 23 31010017 ps
T50 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1536467415 Oct 01 12:18:21 PM PDT 23 Oct 01 12:18:21 PM PDT 23 30491141 ps
T26 /workspace/coverage/sync_alert/10.prim_sync_alert.3575263831 Oct 01 12:13:40 PM PDT 23 Oct 01 12:13:40 PM PDT 23 9180260 ps
T27 /workspace/coverage/sync_alert/7.prim_sync_alert.2844165226 Oct 01 12:13:40 PM PDT 23 Oct 01 12:13:41 PM PDT 23 9197271 ps
T28 /workspace/coverage/sync_alert/9.prim_sync_alert.762521210 Oct 01 12:13:34 PM PDT 23 Oct 01 12:13:34 PM PDT 23 8236546 ps
T29 /workspace/coverage/sync_alert/18.prim_sync_alert.2631571601 Oct 01 12:13:40 PM PDT 23 Oct 01 12:13:41 PM PDT 23 8499639 ps
T30 /workspace/coverage/sync_alert/4.prim_sync_alert.3388536057 Oct 01 12:20:49 PM PDT 23 Oct 01 12:20:49 PM PDT 23 9604125 ps
T31 /workspace/coverage/sync_alert/8.prim_sync_alert.2282344389 Oct 01 12:13:27 PM PDT 23 Oct 01 12:13:28 PM PDT 23 8969923 ps
T32 /workspace/coverage/sync_alert/6.prim_sync_alert.2261599314 Oct 01 12:13:27 PM PDT 23 Oct 01 12:13:27 PM PDT 23 8924846 ps
T33 /workspace/coverage/sync_alert/0.prim_sync_alert.1112550862 Oct 01 12:13:27 PM PDT 23 Oct 01 12:13:28 PM PDT 23 9210021 ps
T34 /workspace/coverage/sync_alert/12.prim_sync_alert.2561885506 Oct 01 12:13:33 PM PDT 23 Oct 01 12:13:34 PM PDT 23 9671305 ps
T35 /workspace/coverage/sync_alert/15.prim_sync_alert.3537723725 Oct 01 12:13:33 PM PDT 23 Oct 01 12:13:34 PM PDT 23 9142751 ps
T51 /workspace/coverage/sync_alert/14.prim_sync_alert.1465688607 Oct 01 12:20:31 PM PDT 23 Oct 01 12:20:31 PM PDT 23 8875874 ps
T52 /workspace/coverage/sync_alert/3.prim_sync_alert.1411335407 Oct 01 12:20:20 PM PDT 23 Oct 01 12:20:21 PM PDT 23 9053972 ps
T53 /workspace/coverage/sync_alert/1.prim_sync_alert.3754524921 Oct 01 12:13:36 PM PDT 23 Oct 01 12:13:36 PM PDT 23 8164213 ps
T54 /workspace/coverage/sync_alert/5.prim_sync_alert.2644326598 Oct 01 12:13:28 PM PDT 23 Oct 01 12:13:29 PM PDT 23 8050743 ps
T55 /workspace/coverage/sync_alert/13.prim_sync_alert.2026370536 Oct 01 12:13:29 PM PDT 23 Oct 01 12:13:29 PM PDT 23 9626674 ps
T56 /workspace/coverage/sync_alert/19.prim_sync_alert.489272986 Oct 01 12:19:35 PM PDT 23 Oct 01 12:19:38 PM PDT 23 10274010 ps
T57 /workspace/coverage/sync_alert/16.prim_sync_alert.797142468 Oct 01 12:13:32 PM PDT 23 Oct 01 12:13:33 PM PDT 23 8759405 ps
T58 /workspace/coverage/sync_alert/11.prim_sync_alert.1801593905 Oct 01 12:19:47 PM PDT 23 Oct 01 12:19:48 PM PDT 23 9577471 ps
T59 /workspace/coverage/sync_alert/17.prim_sync_alert.411984024 Oct 01 12:19:46 PM PDT 23 Oct 01 12:19:47 PM PDT 23 8353288 ps
T60 /workspace/coverage/sync_alert/2.prim_sync_alert.1466063862 Oct 01 12:20:21 PM PDT 23 Oct 01 12:20:21 PM PDT 23 9375962 ps
T61 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1075061054 Oct 01 12:16:47 PM PDT 23 Oct 01 12:16:48 PM PDT 23 26454240 ps
T62 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2521089688 Oct 01 12:20:02 PM PDT 23 Oct 01 12:20:02 PM PDT 23 27709588 ps
T63 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3801700685 Oct 01 12:13:28 PM PDT 23 Oct 01 12:13:28 PM PDT 23 27619714 ps
T64 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1477800982 Oct 01 12:20:34 PM PDT 23 Oct 01 12:20:34 PM PDT 23 27791183 ps
T65 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3645382595 Oct 01 12:13:36 PM PDT 23 Oct 01 12:13:37 PM PDT 23 27690118 ps
T66 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4029948133 Oct 01 12:13:34 PM PDT 23 Oct 01 12:13:34 PM PDT 23 26150219 ps
T67 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4257731685 Oct 01 12:13:27 PM PDT 23 Oct 01 12:13:28 PM PDT 23 27011685 ps
T68 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1675415571 Oct 01 12:19:36 PM PDT 23 Oct 01 12:19:38 PM PDT 23 25278965 ps
T69 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3854913763 Oct 01 12:13:34 PM PDT 23 Oct 01 12:13:34 PM PDT 23 29223065 ps
T70 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2887416918 Oct 01 12:19:47 PM PDT 23 Oct 01 12:19:48 PM PDT 23 26959342 ps
T71 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.945074911 Oct 01 12:13:27 PM PDT 23 Oct 01 12:13:28 PM PDT 23 25695119 ps
T72 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2411838200 Oct 01 12:13:38 PM PDT 23 Oct 01 12:13:39 PM PDT 23 27884973 ps
T73 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2779759197 Oct 01 12:13:32 PM PDT 23 Oct 01 12:13:32 PM PDT 23 27362778 ps
T74 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2469805579 Oct 01 12:13:27 PM PDT 23 Oct 01 12:13:28 PM PDT 23 27565088 ps
T75 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.644197117 Oct 01 12:13:32 PM PDT 23 Oct 01 12:13:33 PM PDT 23 30505159 ps
T76 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1550064141 Oct 01 12:13:32 PM PDT 23 Oct 01 12:13:33 PM PDT 23 27219603 ps
T77 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1583192492 Oct 01 12:20:33 PM PDT 23 Oct 01 12:20:34 PM PDT 23 27231889 ps
T78 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.741601646 Oct 01 12:13:32 PM PDT 23 Oct 01 12:13:33 PM PDT 23 27671232 ps
T79 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2966642992 Oct 01 12:20:19 PM PDT 23 Oct 01 12:20:20 PM PDT 23 28062712 ps
T80 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.252838395 Oct 01 12:13:34 PM PDT 23 Oct 01 12:13:34 PM PDT 23 28588851 ps

Test location /workspace/coverage/default/14.prim_async_alert.1621645476
Short name T7
Test name
Test status
Simulation time 11110075 ps
CPU time 0.38 seconds
Started Oct 01 12:21:52 PM PDT 23
Finished Oct 01 12:21:53 PM PDT 23
Peak memory 145316 kb
Host smart-3bfa206e-2d76-4606-8f28-ee10f102c1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621645476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1621645476
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1112550862
Short name T33
Test name
Test status
Simulation time 9210021 ps
CPU time 0.43 seconds
Started Oct 01 12:13:27 PM PDT 23
Finished Oct 01 12:13:28 PM PDT 23
Peak memory 145088 kb
Host smart-063f314b-2249-492f-839b-d512ebcc331d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1112550862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1112550862
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1743915281
Short name T41
Test name
Test status
Simulation time 31193844 ps
CPU time 0.42 seconds
Started Oct 01 12:20:41 PM PDT 23
Finished Oct 01 12:20:42 PM PDT 23
Peak memory 145548 kb
Host smart-b0604bbe-c86c-4ac3-bc90-a9bd7dcbc513
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1743915281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1743915281
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3563889085
Short name T10
Test name
Test status
Simulation time 12245137 ps
CPU time 0.38 seconds
Started Oct 01 12:19:32 PM PDT 23
Finished Oct 01 12:19:32 PM PDT 23
Peak memory 145428 kb
Host smart-261bffb5-09f1-42f6-bcc2-00bb3f882407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563889085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3563889085
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2202736169
Short name T4
Test name
Test status
Simulation time 29514773 ps
CPU time 0.4 seconds
Started Oct 01 12:15:53 PM PDT 23
Finished Oct 01 12:15:53 PM PDT 23
Peak memory 145656 kb
Host smart-66c0c3f0-4073-41b5-a9f5-3eae042e9ed7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2202736169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2202736169
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.1733001013
Short name T8
Test name
Test status
Simulation time 10547143 ps
CPU time 0.38 seconds
Started Oct 01 12:21:06 PM PDT 23
Finished Oct 01 12:21:06 PM PDT 23
Peak memory 145404 kb
Host smart-4c4afb06-4f75-4835-8432-bdf567b8f8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733001013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1733001013
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.4081744569
Short name T17
Test name
Test status
Simulation time 11168642 ps
CPU time 0.39 seconds
Started Oct 01 12:21:16 PM PDT 23
Finished Oct 01 12:21:16 PM PDT 23
Peak memory 145184 kb
Host smart-85b33a4c-b4eb-4e0a-bc27-ccc708b2d224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081744569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.4081744569
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.1549134658
Short name T16
Test name
Test status
Simulation time 10921183 ps
CPU time 0.38 seconds
Started Oct 01 12:19:23 PM PDT 23
Finished Oct 01 12:19:24 PM PDT 23
Peak memory 145296 kb
Host smart-cf906f3e-bee1-4ad1-b5a6-21a0cf420995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549134658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1549134658
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.4095275496
Short name T15
Test name
Test status
Simulation time 11112878 ps
CPU time 0.37 seconds
Started Oct 01 12:19:18 PM PDT 23
Finished Oct 01 12:19:19 PM PDT 23
Peak memory 145760 kb
Host smart-ef15cdd8-0fdb-4a74-8f56-df5dd51aade2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095275496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.4095275496
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.357744396
Short name T19
Test name
Test status
Simulation time 10818509 ps
CPU time 0.56 seconds
Started Oct 01 12:19:23 PM PDT 23
Finished Oct 01 12:19:24 PM PDT 23
Peak memory 143860 kb
Host smart-1036d7c5-c0b8-4e41-a68b-f6ba1094cdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357744396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.357744396
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.2795019025
Short name T1
Test name
Test status
Simulation time 11716284 ps
CPU time 0.39 seconds
Started Oct 01 12:18:14 PM PDT 23
Finished Oct 01 12:18:15 PM PDT 23
Peak memory 145192 kb
Host smart-8b69096b-da18-465f-9c7a-3208a98c56c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795019025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2795019025
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.1918707884
Short name T20
Test name
Test status
Simulation time 11899466 ps
CPU time 0.44 seconds
Started Oct 01 12:20:12 PM PDT 23
Finished Oct 01 12:20:14 PM PDT 23
Peak memory 145140 kb
Host smart-4c0422ad-627d-41a3-b712-f7ec2342edf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918707884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1918707884
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.3309839374
Short name T24
Test name
Test status
Simulation time 11029337 ps
CPU time 0.37 seconds
Started Oct 01 12:21:20 PM PDT 23
Finished Oct 01 12:21:21 PM PDT 23
Peak memory 145748 kb
Host smart-93743b40-0a24-4158-9120-c1485726fb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309839374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3309839374
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.3910739469
Short name T23
Test name
Test status
Simulation time 10730380 ps
CPU time 0.42 seconds
Started Oct 01 12:19:23 PM PDT 23
Finished Oct 01 12:19:23 PM PDT 23
Peak memory 144356 kb
Host smart-7859106d-94f5-490b-8cfc-67c6a3b1810d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910739469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3910739469
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2907264097
Short name T21
Test name
Test status
Simulation time 11260920 ps
CPU time 0.38 seconds
Started Oct 01 12:14:16 PM PDT 23
Finished Oct 01 12:14:17 PM PDT 23
Peak memory 145548 kb
Host smart-a3b7e4bd-bb2a-403a-9812-cbb5d0337281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907264097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2907264097
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.2908353207
Short name T14
Test name
Test status
Simulation time 11590319 ps
CPU time 0.36 seconds
Started Oct 01 12:20:23 PM PDT 23
Finished Oct 01 12:20:23 PM PDT 23
Peak memory 145264 kb
Host smart-caacdc38-1b5e-440a-b480-708ea2d06b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908353207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2908353207
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.385840786
Short name T2
Test name
Test status
Simulation time 11786033 ps
CPU time 0.41 seconds
Started Oct 01 12:15:06 PM PDT 23
Finished Oct 01 12:15:08 PM PDT 23
Peak memory 145604 kb
Host smart-0fe19b38-9186-4608-8443-d94d202df281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385840786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.385840786
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1937954071
Short name T9
Test name
Test status
Simulation time 10928420 ps
CPU time 0.39 seconds
Started Oct 01 12:18:08 PM PDT 23
Finished Oct 01 12:18:08 PM PDT 23
Peak memory 145588 kb
Host smart-08c009ad-a0a0-4fe2-8b22-322f4ad7ddec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937954071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1937954071
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2063926912
Short name T18
Test name
Test status
Simulation time 11604264 ps
CPU time 0.4 seconds
Started Oct 01 12:18:51 PM PDT 23
Finished Oct 01 12:18:52 PM PDT 23
Peak memory 145580 kb
Host smart-576b38e6-298c-4cd3-b9fb-0c12b78eed91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063926912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2063926912
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.2125145173
Short name T3
Test name
Test status
Simulation time 11364174 ps
CPU time 0.37 seconds
Started Oct 01 12:19:33 PM PDT 23
Finished Oct 01 12:19:34 PM PDT 23
Peak memory 145344 kb
Host smart-c2b24ff3-fce2-4854-9e3a-405a5261e7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125145173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2125145173
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.868238454
Short name T13
Test name
Test status
Simulation time 10397226 ps
CPU time 0.38 seconds
Started Oct 01 12:21:32 PM PDT 23
Finished Oct 01 12:21:32 PM PDT 23
Peak memory 145352 kb
Host smart-5a31a20b-7fd7-4005-99b0-8b9f809935c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868238454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.868238454
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2379418992
Short name T44
Test name
Test status
Simulation time 11091254 ps
CPU time 0.37 seconds
Started Oct 01 12:20:21 PM PDT 23
Finished Oct 01 12:20:21 PM PDT 23
Peak memory 145192 kb
Host smart-cb44cce7-8c18-46f3-b8ac-7229b41aa33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379418992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2379418992
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2947826954
Short name T22
Test name
Test status
Simulation time 11182317 ps
CPU time 0.41 seconds
Started Oct 01 12:18:04 PM PDT 23
Finished Oct 01 12:18:05 PM PDT 23
Peak memory 145128 kb
Host smart-9eb3226e-274e-4dc3-a5a3-bd11d889e2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947826954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2947826954
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4247069454
Short name T38
Test name
Test status
Simulation time 30057322 ps
CPU time 0.37 seconds
Started Oct 01 12:19:42 PM PDT 23
Finished Oct 01 12:19:43 PM PDT 23
Peak memory 145500 kb
Host smart-eac6c6dc-b72a-4ea1-9f97-39023f747ca7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4247069454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.4247069454
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2156024446
Short name T25
Test name
Test status
Simulation time 30872201 ps
CPU time 0.39 seconds
Started Oct 01 12:21:15 PM PDT 23
Finished Oct 01 12:21:15 PM PDT 23
Peak memory 145836 kb
Host smart-a06fd28f-cb78-4d15-89da-45b474e4c208
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2156024446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2156024446
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1536467415
Short name T50
Test name
Test status
Simulation time 30491141 ps
CPU time 0.44 seconds
Started Oct 01 12:18:21 PM PDT 23
Finished Oct 01 12:18:21 PM PDT 23
Peak memory 145616 kb
Host smart-c5029325-0827-417c-bfed-47465e3d2bd9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1536467415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1536467415
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.671561043
Short name T37
Test name
Test status
Simulation time 31337407 ps
CPU time 0.39 seconds
Started Oct 01 12:21:19 PM PDT 23
Finished Oct 01 12:21:19 PM PDT 23
Peak memory 145348 kb
Host smart-29c8cd60-9084-4b8b-baf6-7465d2268fb6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=671561043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.671561043
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3914268837
Short name T39
Test name
Test status
Simulation time 31642413 ps
CPU time 0.38 seconds
Started Oct 01 12:20:28 PM PDT 23
Finished Oct 01 12:20:28 PM PDT 23
Peak memory 145388 kb
Host smart-aa5f8c1d-412e-466e-92bf-14dd555912b0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3914268837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3914268837
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1916208021
Short name T43
Test name
Test status
Simulation time 29170238 ps
CPU time 0.38 seconds
Started Oct 01 12:20:51 PM PDT 23
Finished Oct 01 12:20:52 PM PDT 23
Peak memory 145560 kb
Host smart-ce81784c-b3db-4929-a0ce-0702a7b9db3c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1916208021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1916208021
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2763202088
Short name T46
Test name
Test status
Simulation time 29111958 ps
CPU time 0.39 seconds
Started Oct 01 12:21:32 PM PDT 23
Finished Oct 01 12:21:33 PM PDT 23
Peak memory 145572 kb
Host smart-daf11cb6-f7ff-4ca3-994a-22dbf129eb76
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2763202088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2763202088
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.79963334
Short name T36
Test name
Test status
Simulation time 30750724 ps
CPU time 0.41 seconds
Started Oct 01 12:15:53 PM PDT 23
Finished Oct 01 12:15:54 PM PDT 23
Peak memory 145716 kb
Host smart-910eae36-d0eb-4157-904a-5b49a4e30714
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=79963334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.79963334
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1671140156
Short name T42
Test name
Test status
Simulation time 31265227 ps
CPU time 0.41 seconds
Started Oct 01 12:18:30 PM PDT 23
Finished Oct 01 12:18:31 PM PDT 23
Peak memory 145576 kb
Host smart-96300ff0-71a8-4b3b-ada5-bf4ed0653943
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1671140156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1671140156
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2001553193
Short name T45
Test name
Test status
Simulation time 30279500 ps
CPU time 0.39 seconds
Started Oct 01 12:20:43 PM PDT 23
Finished Oct 01 12:20:44 PM PDT 23
Peak memory 145560 kb
Host smart-8be1a1f4-4b2e-4cd1-a8d3-1c41403d3f0f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2001553193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2001553193
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1291163212
Short name T12
Test name
Test status
Simulation time 30440693 ps
CPU time 0.43 seconds
Started Oct 01 12:21:01 PM PDT 23
Finished Oct 01 12:21:02 PM PDT 23
Peak memory 145292 kb
Host smart-1f24f35c-bc9c-49c8-9487-a132b069b1de
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1291163212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1291163212
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1093955026
Short name T6
Test name
Test status
Simulation time 33544021 ps
CPU time 0.4 seconds
Started Oct 01 12:14:29 PM PDT 23
Finished Oct 01 12:14:30 PM PDT 23
Peak memory 145616 kb
Host smart-16b1b9b5-3e6b-4c57-b050-55dc2572215b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1093955026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1093955026
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3983948604
Short name T5
Test name
Test status
Simulation time 31090070 ps
CPU time 0.46 seconds
Started Oct 01 12:20:46 PM PDT 23
Finished Oct 01 12:20:47 PM PDT 23
Peak memory 145292 kb
Host smart-0350991b-de5c-47d4-83af-07839046b37b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3983948604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3983948604
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2994707492
Short name T48
Test name
Test status
Simulation time 28399391 ps
CPU time 0.42 seconds
Started Oct 01 12:21:02 PM PDT 23
Finished Oct 01 12:21:03 PM PDT 23
Peak memory 145372 kb
Host smart-83b294b5-52fa-45db-bb72-e2302854ea3d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2994707492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2994707492
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1461100830
Short name T47
Test name
Test status
Simulation time 29826740 ps
CPU time 0.44 seconds
Started Oct 01 12:21:02 PM PDT 23
Finished Oct 01 12:21:03 PM PDT 23
Peak memory 145292 kb
Host smart-8c98c064-4997-46e0-8f75-0fc7dd602274
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1461100830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1461100830
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1117558511
Short name T11
Test name
Test status
Simulation time 30085441 ps
CPU time 0.38 seconds
Started Oct 01 12:20:20 PM PDT 23
Finished Oct 01 12:20:21 PM PDT 23
Peak memory 145404 kb
Host smart-e3a3fc12-3b41-47ea-8168-f19c6f3e9d8e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1117558511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1117558511
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2865642768
Short name T49
Test name
Test status
Simulation time 31010017 ps
CPU time 0.39 seconds
Started Oct 01 12:20:36 PM PDT 23
Finished Oct 01 12:20:36 PM PDT 23
Peak memory 145536 kb
Host smart-f3729bb2-1978-4a79-9b6a-de099352560f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2865642768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2865642768
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2990766812
Short name T40
Test name
Test status
Simulation time 29537944 ps
CPU time 0.41 seconds
Started Oct 01 12:19:33 PM PDT 23
Finished Oct 01 12:19:34 PM PDT 23
Peak memory 144636 kb
Host smart-fa4f621d-feb8-4e79-9027-b69bfe28969c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2990766812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2990766812
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3754524921
Short name T53
Test name
Test status
Simulation time 8164213 ps
CPU time 0.38 seconds
Started Oct 01 12:13:36 PM PDT 23
Finished Oct 01 12:13:36 PM PDT 23
Peak memory 145120 kb
Host smart-0680bc31-c41b-44be-96be-1c18459d47fe
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3754524921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3754524921
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.3575263831
Short name T26
Test name
Test status
Simulation time 9180260 ps
CPU time 0.38 seconds
Started Oct 01 12:13:40 PM PDT 23
Finished Oct 01 12:13:40 PM PDT 23
Peak memory 145008 kb
Host smart-f4d87e65-c696-42fb-b85f-ec30b556549b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3575263831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3575263831
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.1801593905
Short name T58
Test name
Test status
Simulation time 9577471 ps
CPU time 0.5 seconds
Started Oct 01 12:19:47 PM PDT 23
Finished Oct 01 12:19:48 PM PDT 23
Peak memory 143148 kb
Host smart-4826ef95-0d2a-4bf3-88f0-bffec27b3466
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1801593905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1801593905
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.2561885506
Short name T34
Test name
Test status
Simulation time 9671305 ps
CPU time 0.4 seconds
Started Oct 01 12:13:33 PM PDT 23
Finished Oct 01 12:13:34 PM PDT 23
Peak memory 144996 kb
Host smart-feab8c8c-47de-4a53-b43c-188f873ef0bb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2561885506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2561885506
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2026370536
Short name T55
Test name
Test status
Simulation time 9626674 ps
CPU time 0.42 seconds
Started Oct 01 12:13:29 PM PDT 23
Finished Oct 01 12:13:29 PM PDT 23
Peak memory 145100 kb
Host smart-01bffb14-01e8-4915-812b-5045cdf8f0ff
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2026370536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2026370536
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.1465688607
Short name T51
Test name
Test status
Simulation time 8875874 ps
CPU time 0.36 seconds
Started Oct 01 12:20:31 PM PDT 23
Finished Oct 01 12:20:31 PM PDT 23
Peak memory 144740 kb
Host smart-f6d6de9c-4c94-46c5-ac4d-3b9b2427e2cf
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1465688607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1465688607
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3537723725
Short name T35
Test name
Test status
Simulation time 9142751 ps
CPU time 0.4 seconds
Started Oct 01 12:13:33 PM PDT 23
Finished Oct 01 12:13:34 PM PDT 23
Peak memory 144976 kb
Host smart-fe31b874-0560-49fc-afc4-c4f1689c63a2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3537723725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3537723725
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.797142468
Short name T57
Test name
Test status
Simulation time 8759405 ps
CPU time 0.41 seconds
Started Oct 01 12:13:32 PM PDT 23
Finished Oct 01 12:13:33 PM PDT 23
Peak memory 145080 kb
Host smart-812c8b25-896d-4a3c-99e1-724b439ef543
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=797142468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.797142468
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.411984024
Short name T59
Test name
Test status
Simulation time 8353288 ps
CPU time 0.37 seconds
Started Oct 01 12:19:46 PM PDT 23
Finished Oct 01 12:19:47 PM PDT 23
Peak memory 144932 kb
Host smart-95a6d22a-6515-422f-808c-42eea5d5a133
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=411984024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.411984024
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2631571601
Short name T29
Test name
Test status
Simulation time 8499639 ps
CPU time 0.38 seconds
Started Oct 01 12:13:40 PM PDT 23
Finished Oct 01 12:13:41 PM PDT 23
Peak memory 145004 kb
Host smart-28a50268-aa86-4e67-b415-83f197d24d7a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2631571601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2631571601
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.489272986
Short name T56
Test name
Test status
Simulation time 10274010 ps
CPU time 0.39 seconds
Started Oct 01 12:19:35 PM PDT 23
Finished Oct 01 12:19:38 PM PDT 23
Peak memory 143808 kb
Host smart-85022375-acd1-4dd8-b1d7-ef80da614897
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=489272986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.489272986
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1466063862
Short name T60
Test name
Test status
Simulation time 9375962 ps
CPU time 0.39 seconds
Started Oct 01 12:20:21 PM PDT 23
Finished Oct 01 12:20:21 PM PDT 23
Peak memory 144748 kb
Host smart-cc240036-3c8a-4cec-b1b4-c5cf1c19391d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1466063862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1466063862
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1411335407
Short name T52
Test name
Test status
Simulation time 9053972 ps
CPU time 0.37 seconds
Started Oct 01 12:20:20 PM PDT 23
Finished Oct 01 12:20:21 PM PDT 23
Peak memory 144748 kb
Host smart-ef7354b0-006e-48a3-bde3-39f1e9b73084
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1411335407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1411335407
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3388536057
Short name T30
Test name
Test status
Simulation time 9604125 ps
CPU time 0.36 seconds
Started Oct 01 12:20:49 PM PDT 23
Finished Oct 01 12:20:49 PM PDT 23
Peak memory 144852 kb
Host smart-ff8af2df-9e4d-418f-a5f0-a8b9481e7dfb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3388536057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3388536057
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2644326598
Short name T54
Test name
Test status
Simulation time 8050743 ps
CPU time 0.38 seconds
Started Oct 01 12:13:28 PM PDT 23
Finished Oct 01 12:13:29 PM PDT 23
Peak memory 144964 kb
Host smart-3e0e6bec-86bd-4485-a086-bd7c4da20ee3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2644326598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2644326598
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2261599314
Short name T32
Test name
Test status
Simulation time 8924846 ps
CPU time 0.37 seconds
Started Oct 01 12:13:27 PM PDT 23
Finished Oct 01 12:13:27 PM PDT 23
Peak memory 145056 kb
Host smart-fe1f0654-9fff-407a-8049-2e1752f3cce4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2261599314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2261599314
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.2844165226
Short name T27
Test name
Test status
Simulation time 9197271 ps
CPU time 0.37 seconds
Started Oct 01 12:13:40 PM PDT 23
Finished Oct 01 12:13:41 PM PDT 23
Peak memory 145120 kb
Host smart-411b68c0-5ba8-4c1e-a620-29ae0321753b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2844165226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2844165226
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2282344389
Short name T31
Test name
Test status
Simulation time 8969923 ps
CPU time 0.38 seconds
Started Oct 01 12:13:27 PM PDT 23
Finished Oct 01 12:13:28 PM PDT 23
Peak memory 145120 kb
Host smart-485768bf-d209-41f4-9c1c-3d08a842d354
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2282344389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2282344389
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.762521210
Short name T28
Test name
Test status
Simulation time 8236546 ps
CPU time 0.39 seconds
Started Oct 01 12:13:34 PM PDT 23
Finished Oct 01 12:13:34 PM PDT 23
Peak memory 144820 kb
Host smart-32053a0e-c5cd-468c-95a0-1660e38b9744
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=762521210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.762521210
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.945074911
Short name T71
Test name
Test status
Simulation time 25695119 ps
CPU time 0.39 seconds
Started Oct 01 12:13:27 PM PDT 23
Finished Oct 01 12:13:28 PM PDT 23
Peak memory 145124 kb
Host smart-35d9d8d1-5986-4337-84a7-17fbcda6ecf7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=945074911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.945074911
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3854913763
Short name T69
Test name
Test status
Simulation time 29223065 ps
CPU time 0.4 seconds
Started Oct 01 12:13:34 PM PDT 23
Finished Oct 01 12:13:34 PM PDT 23
Peak memory 145020 kb
Host smart-5582912c-7781-462a-aeff-e020f46c7e0a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3854913763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3854913763
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1550064141
Short name T76
Test name
Test status
Simulation time 27219603 ps
CPU time 0.4 seconds
Started Oct 01 12:13:32 PM PDT 23
Finished Oct 01 12:13:33 PM PDT 23
Peak memory 145020 kb
Host smart-2b311b57-1af6-44fb-9fe7-f38c403bc096
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1550064141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1550064141
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1583192492
Short name T77
Test name
Test status
Simulation time 27231889 ps
CPU time 0.37 seconds
Started Oct 01 12:20:33 PM PDT 23
Finished Oct 01 12:20:34 PM PDT 23
Peak memory 144760 kb
Host smart-3938f9e9-3149-4d73-9109-2dcf276cd91d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1583192492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1583192492
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1675415571
Short name T68
Test name
Test status
Simulation time 25278965 ps
CPU time 0.37 seconds
Started Oct 01 12:19:36 PM PDT 23
Finished Oct 01 12:19:38 PM PDT 23
Peak memory 144528 kb
Host smart-b439859f-9d8a-4e3f-8186-9846cfcd3ea8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1675415571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1675415571
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2521089688
Short name T62
Test name
Test status
Simulation time 27709588 ps
CPU time 0.44 seconds
Started Oct 01 12:20:02 PM PDT 23
Finished Oct 01 12:20:02 PM PDT 23
Peak memory 145072 kb
Host smart-b19b7fc6-8598-41ce-8d94-ca8228022599
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2521089688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2521089688
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1477800982
Short name T64
Test name
Test status
Simulation time 27791183 ps
CPU time 0.38 seconds
Started Oct 01 12:20:34 PM PDT 23
Finished Oct 01 12:20:34 PM PDT 23
Peak memory 144856 kb
Host smart-6ae3b95c-ff61-4381-9454-e9efc5de73b5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1477800982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1477800982
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2779759197
Short name T73
Test name
Test status
Simulation time 27362778 ps
CPU time 0.41 seconds
Started Oct 01 12:13:32 PM PDT 23
Finished Oct 01 12:13:32 PM PDT 23
Peak memory 145020 kb
Host smart-ea9a298a-2e00-45da-b775-ca51d9454f96
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2779759197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2779759197
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2887416918
Short name T70
Test name
Test status
Simulation time 26959342 ps
CPU time 0.51 seconds
Started Oct 01 12:19:47 PM PDT 23
Finished Oct 01 12:19:48 PM PDT 23
Peak memory 142792 kb
Host smart-a5c226e8-bd6a-4ede-9c23-20f22309882e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2887416918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2887416918
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.644197117
Short name T75
Test name
Test status
Simulation time 30505159 ps
CPU time 0.4 seconds
Started Oct 01 12:13:32 PM PDT 23
Finished Oct 01 12:13:33 PM PDT 23
Peak memory 145024 kb
Host smart-05037a66-5427-4e2b-83a9-859ee2f9a555
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=644197117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.644197117
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.741601646
Short name T78
Test name
Test status
Simulation time 27671232 ps
CPU time 0.4 seconds
Started Oct 01 12:13:32 PM PDT 23
Finished Oct 01 12:13:33 PM PDT 23
Peak memory 145024 kb
Host smart-11ad619a-7a8a-4ef1-930b-1b1f6f768a81
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=741601646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.741601646
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2411838200
Short name T72
Test name
Test status
Simulation time 27884973 ps
CPU time 0.39 seconds
Started Oct 01 12:13:38 PM PDT 23
Finished Oct 01 12:13:39 PM PDT 23
Peak memory 145104 kb
Host smart-6c61c824-3fde-42dc-b56d-eea1e52825b2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2411838200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2411838200
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.252838395
Short name T80
Test name
Test status
Simulation time 28588851 ps
CPU time 0.39 seconds
Started Oct 01 12:13:34 PM PDT 23
Finished Oct 01 12:13:34 PM PDT 23
Peak memory 145024 kb
Host smart-7a0326f8-ef70-4d8d-9e70-1e5da12d1f4c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=252838395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.252838395
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3801700685
Short name T63
Test name
Test status
Simulation time 27619714 ps
CPU time 0.4 seconds
Started Oct 01 12:13:28 PM PDT 23
Finished Oct 01 12:13:28 PM PDT 23
Peak memory 145108 kb
Host smart-61bcde7b-b24a-424e-ab57-c92f7817f2ef
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3801700685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3801700685
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4029948133
Short name T66
Test name
Test status
Simulation time 26150219 ps
CPU time 0.4 seconds
Started Oct 01 12:13:34 PM PDT 23
Finished Oct 01 12:13:34 PM PDT 23
Peak memory 145020 kb
Host smart-55cc3622-3b6b-4cb9-99bf-6c04f02ea985
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4029948133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.4029948133
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1075061054
Short name T61
Test name
Test status
Simulation time 26454240 ps
CPU time 0.4 seconds
Started Oct 01 12:16:47 PM PDT 23
Finished Oct 01 12:16:48 PM PDT 23
Peak memory 145076 kb
Host smart-6f45bf1e-37de-441c-b376-7c514f0a3995
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1075061054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1075061054
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4257731685
Short name T67
Test name
Test status
Simulation time 27011685 ps
CPU time 0.4 seconds
Started Oct 01 12:13:27 PM PDT 23
Finished Oct 01 12:13:28 PM PDT 23
Peak memory 145108 kb
Host smart-8e750014-647e-498d-9ec5-19e21ef0b49f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4257731685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.4257731685
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2966642992
Short name T79
Test name
Test status
Simulation time 28062712 ps
CPU time 0.43 seconds
Started Oct 01 12:20:19 PM PDT 23
Finished Oct 01 12:20:20 PM PDT 23
Peak memory 144512 kb
Host smart-ae580002-64f1-433a-8a28-1cd3aec6d66b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2966642992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2966642992
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2469805579
Short name T74
Test name
Test status
Simulation time 27565088 ps
CPU time 0.39 seconds
Started Oct 01 12:13:27 PM PDT 23
Finished Oct 01 12:13:28 PM PDT 23
Peak memory 145120 kb
Host smart-1ece989b-a517-4c1d-b417-b51ea4311abc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2469805579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2469805579
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3645382595
Short name T65
Test name
Test status
Simulation time 27690118 ps
CPU time 0.41 seconds
Started Oct 01 12:13:36 PM PDT 23
Finished Oct 01 12:13:37 PM PDT 23
Peak memory 145132 kb
Host smart-d7ee453c-fee7-41e3-8ebc-20cba09a87b6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3645382595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3645382595
Directory /workspace/9.prim_sync_fatal_alert/latest
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