Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.82 89.82 100.00 100.00 95.83 95.83 100.00 100.00 82.14 82.14 95.83 95.83 65.12 65.12 /workspace/coverage/default/4.prim_async_alert.4269500877
92.35 2.53 100.00 0.00 95.83 0.00 100.00 0.00 85.71 3.57 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/0.prim_sync_alert.1967948366
94.11 1.76 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 83.72 6.98 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4233701109
94.50 0.39 100.00 0.00 95.83 0.00 100.00 0.00 89.29 0.00 95.83 0.00 86.05 2.33 /workspace/coverage/default/1.prim_async_alert.2526675836
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3444411899
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/7.prim_sync_alert.3680386235

Tests that do not contribute to grading

Name
/workspace/coverage/default/10.prim_async_alert.3600116316
/workspace/coverage/default/11.prim_async_alert.1060863073
/workspace/coverage/default/12.prim_async_alert.3849127233
/workspace/coverage/default/13.prim_async_alert.2695261913
/workspace/coverage/default/14.prim_async_alert.3201620608
/workspace/coverage/default/15.prim_async_alert.3256973479
/workspace/coverage/default/16.prim_async_alert.2495029171
/workspace/coverage/default/17.prim_async_alert.2439822225
/workspace/coverage/default/18.prim_async_alert.235449819
/workspace/coverage/default/19.prim_async_alert.3997870325
/workspace/coverage/default/2.prim_async_alert.3603305110
/workspace/coverage/default/3.prim_async_alert.2760621358
/workspace/coverage/default/5.prim_async_alert.2049596498
/workspace/coverage/default/6.prim_async_alert.2864888306
/workspace/coverage/default/7.prim_async_alert.2436674753
/workspace/coverage/default/8.prim_async_alert.3504899834
/workspace/coverage/default/9.prim_async_alert.1226554727
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2649831562
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2738726280
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2679813048
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3331945507
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.225995762
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1215286889
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2988834979
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4011486663
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2671948509
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4196969382
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.240521840
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4168612878
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.428601570
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.588011754
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2968198055
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2738498900
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.940104695
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.810979007
/workspace/coverage/sync_alert/1.prim_sync_alert.845360585
/workspace/coverage/sync_alert/10.prim_sync_alert.2184652562
/workspace/coverage/sync_alert/11.prim_sync_alert.3030599755
/workspace/coverage/sync_alert/12.prim_sync_alert.943619018
/workspace/coverage/sync_alert/13.prim_sync_alert.3121794494
/workspace/coverage/sync_alert/14.prim_sync_alert.2730113451
/workspace/coverage/sync_alert/15.prim_sync_alert.3825956008
/workspace/coverage/sync_alert/16.prim_sync_alert.2114796305
/workspace/coverage/sync_alert/17.prim_sync_alert.4011540303
/workspace/coverage/sync_alert/18.prim_sync_alert.1445080571
/workspace/coverage/sync_alert/19.prim_sync_alert.986883950
/workspace/coverage/sync_alert/2.prim_sync_alert.61218992
/workspace/coverage/sync_alert/3.prim_sync_alert.1100791986
/workspace/coverage/sync_alert/4.prim_sync_alert.202989481
/workspace/coverage/sync_alert/5.prim_sync_alert.1624628609
/workspace/coverage/sync_alert/6.prim_sync_alert.3459743778
/workspace/coverage/sync_alert/8.prim_sync_alert.3674227133
/workspace/coverage/sync_alert/9.prim_sync_alert.1453592494
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2806478095
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2337220847
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2677033441
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2185712925
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.501401121
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3860337458
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2080545505
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3506380151
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1654967300
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2893714252
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2616967456
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1944630123
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.964036403
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3565165578
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3422503296
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3579990110
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.894370070
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4076237834
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.663031066
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3210704938



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/12.prim_async_alert.3849127233 Oct 08 12:42:01 PM PDT 23 Oct 08 12:42:02 PM PDT 23 11559286 ps
T2 /workspace/coverage/default/3.prim_async_alert.2760621358 Oct 08 12:43:18 PM PDT 23 Oct 08 12:43:19 PM PDT 23 11185745 ps
T3 /workspace/coverage/default/6.prim_async_alert.2864888306 Oct 08 12:44:43 PM PDT 23 Oct 08 12:44:44 PM PDT 23 10906870 ps
T7 /workspace/coverage/default/16.prim_async_alert.2495029171 Oct 08 12:23:36 PM PDT 23 Oct 08 12:23:36 PM PDT 23 10840787 ps
T8 /workspace/coverage/default/1.prim_async_alert.2526675836 Oct 08 12:41:36 PM PDT 23 Oct 08 12:41:36 PM PDT 23 10954479 ps
T15 /workspace/coverage/default/18.prim_async_alert.235449819 Oct 08 12:43:24 PM PDT 23 Oct 08 12:43:25 PM PDT 23 10685711 ps
T9 /workspace/coverage/default/8.prim_async_alert.3504899834 Oct 08 12:40:18 PM PDT 23 Oct 08 12:40:18 PM PDT 23 11391567 ps
T19 /workspace/coverage/default/5.prim_async_alert.2049596498 Oct 08 12:33:22 PM PDT 23 Oct 08 12:33:23 PM PDT 23 11420821 ps
T10 /workspace/coverage/default/10.prim_async_alert.3600116316 Oct 08 12:30:03 PM PDT 23 Oct 08 12:30:04 PM PDT 23 11253671 ps
T11 /workspace/coverage/default/4.prim_async_alert.4269500877 Oct 08 12:31:38 PM PDT 23 Oct 08 12:31:39 PM PDT 23 12949964 ps
T20 /workspace/coverage/default/17.prim_async_alert.2439822225 Oct 08 12:33:36 PM PDT 23 Oct 08 12:33:37 PM PDT 23 11512137 ps
T14 /workspace/coverage/default/9.prim_async_alert.1226554727 Oct 08 12:36:37 PM PDT 23 Oct 08 12:36:37 PM PDT 23 11909988 ps
T21 /workspace/coverage/default/15.prim_async_alert.3256973479 Oct 08 12:41:04 PM PDT 23 Oct 08 12:41:04 PM PDT 23 11220141 ps
T45 /workspace/coverage/default/14.prim_async_alert.3201620608 Oct 08 12:43:40 PM PDT 23 Oct 08 12:43:40 PM PDT 23 10824597 ps
T46 /workspace/coverage/default/13.prim_async_alert.2695261913 Oct 08 12:42:02 PM PDT 23 Oct 08 12:42:02 PM PDT 23 11447541 ps
T47 /workspace/coverage/default/11.prim_async_alert.1060863073 Oct 08 12:46:25 PM PDT 23 Oct 08 12:46:25 PM PDT 23 11371148 ps
T48 /workspace/coverage/default/19.prim_async_alert.3997870325 Oct 08 12:23:42 PM PDT 23 Oct 08 12:23:43 PM PDT 23 10555953 ps
T22 /workspace/coverage/default/7.prim_async_alert.2436674753 Oct 08 12:40:16 PM PDT 23 Oct 08 12:40:17 PM PDT 23 11095693 ps
T49 /workspace/coverage/default/2.prim_async_alert.3603305110 Oct 08 12:27:47 PM PDT 23 Oct 08 12:27:47 PM PDT 23 10863283 ps
T40 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4011486663 Oct 08 12:30:54 PM PDT 23 Oct 08 12:30:56 PM PDT 23 28855551 ps
T41 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.588011754 Oct 08 12:29:39 PM PDT 23 Oct 08 12:29:40 PM PDT 23 29396291 ps
T23 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2968198055 Oct 08 12:45:19 PM PDT 23 Oct 08 12:45:19 PM PDT 23 29298156 ps
T24 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.428601570 Oct 08 12:40:11 PM PDT 23 Oct 08 12:40:11 PM PDT 23 29991327 ps
T42 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2738726280 Oct 08 12:30:44 PM PDT 23 Oct 08 12:30:45 PM PDT 23 29782051 ps
T25 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.810979007 Oct 08 12:34:06 PM PDT 23 Oct 08 12:34:07 PM PDT 23 30526954 ps
T16 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4233701109 Oct 08 12:39:17 PM PDT 23 Oct 08 12:39:17 PM PDT 23 29909845 ps
T43 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1215286889 Oct 08 12:39:15 PM PDT 23 Oct 08 12:39:17 PM PDT 23 29929112 ps
T17 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2988834979 Oct 08 12:39:58 PM PDT 23 Oct 08 12:39:59 PM PDT 23 32207831 ps
T44 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4196969382 Oct 08 12:30:55 PM PDT 23 Oct 08 12:30:56 PM PDT 23 29191007 ps
T50 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2671948509 Oct 08 12:39:52 PM PDT 23 Oct 08 12:39:53 PM PDT 23 29821150 ps
T18 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3331945507 Oct 08 01:25:19 PM PDT 23 Oct 08 01:25:19 PM PDT 23 31152744 ps
T51 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4168612878 Oct 08 12:47:46 PM PDT 23 Oct 08 12:47:47 PM PDT 23 31816882 ps
T52 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.225995762 Oct 08 01:32:40 PM PDT 23 Oct 08 01:32:40 PM PDT 23 30808335 ps
T4 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3444411899 Oct 08 12:35:11 PM PDT 23 Oct 08 12:35:12 PM PDT 23 29675035 ps
T53 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.940104695 Oct 08 12:36:50 PM PDT 23 Oct 08 12:36:52 PM PDT 23 31850717 ps
T54 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2738498900 Oct 08 12:29:03 PM PDT 23 Oct 08 12:29:03 PM PDT 23 31740299 ps
T55 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2679813048 Oct 08 12:31:57 PM PDT 23 Oct 08 12:31:58 PM PDT 23 29762464 ps
T56 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.240521840 Oct 08 12:30:56 PM PDT 23 Oct 08 12:30:56 PM PDT 23 29384474 ps
T57 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2649831562 Oct 08 12:37:42 PM PDT 23 Oct 08 12:37:42 PM PDT 23 28924170 ps
T35 /workspace/coverage/sync_alert/17.prim_sync_alert.4011540303 Oct 08 12:24:23 PM PDT 23 Oct 08 12:24:23 PM PDT 23 9201180 ps
T36 /workspace/coverage/sync_alert/16.prim_sync_alert.2114796305 Oct 08 12:29:27 PM PDT 23 Oct 08 12:29:27 PM PDT 23 10128025 ps
T37 /workspace/coverage/sync_alert/19.prim_sync_alert.986883950 Oct 08 12:26:45 PM PDT 23 Oct 08 12:26:46 PM PDT 23 8681939 ps
T38 /workspace/coverage/sync_alert/8.prim_sync_alert.3674227133 Oct 08 12:28:41 PM PDT 23 Oct 08 12:28:42 PM PDT 23 9329351 ps
T39 /workspace/coverage/sync_alert/0.prim_sync_alert.1967948366 Oct 08 12:45:28 PM PDT 23 Oct 08 12:45:29 PM PDT 23 10445448 ps
T26 /workspace/coverage/sync_alert/14.prim_sync_alert.2730113451 Oct 08 12:27:56 PM PDT 23 Oct 08 12:27:56 PM PDT 23 9062701 ps
T27 /workspace/coverage/sync_alert/5.prim_sync_alert.1624628609 Oct 08 12:47:47 PM PDT 23 Oct 08 12:47:48 PM PDT 23 9455104 ps
T28 /workspace/coverage/sync_alert/12.prim_sync_alert.943619018 Oct 08 12:39:31 PM PDT 23 Oct 08 12:39:32 PM PDT 23 8924187 ps
T29 /workspace/coverage/sync_alert/18.prim_sync_alert.1445080571 Oct 08 12:24:23 PM PDT 23 Oct 08 12:24:23 PM PDT 23 9754287 ps
T30 /workspace/coverage/sync_alert/13.prim_sync_alert.3121794494 Oct 08 12:39:05 PM PDT 23 Oct 08 12:39:06 PM PDT 23 9884164 ps
T31 /workspace/coverage/sync_alert/2.prim_sync_alert.61218992 Oct 08 12:45:47 PM PDT 23 Oct 08 12:45:48 PM PDT 23 8608542 ps
T32 /workspace/coverage/sync_alert/15.prim_sync_alert.3825956008 Oct 08 12:41:22 PM PDT 23 Oct 08 12:41:23 PM PDT 23 9086587 ps
T33 /workspace/coverage/sync_alert/11.prim_sync_alert.3030599755 Oct 08 12:27:36 PM PDT 23 Oct 08 12:27:37 PM PDT 23 9158679 ps
T34 /workspace/coverage/sync_alert/10.prim_sync_alert.2184652562 Oct 08 12:41:22 PM PDT 23 Oct 08 12:41:23 PM PDT 23 9024405 ps
T58 /workspace/coverage/sync_alert/4.prim_sync_alert.202989481 Oct 08 12:34:59 PM PDT 23 Oct 08 12:34:59 PM PDT 23 8159667 ps
T59 /workspace/coverage/sync_alert/1.prim_sync_alert.845360585 Oct 08 12:46:52 PM PDT 23 Oct 08 12:46:53 PM PDT 23 8948154 ps
T60 /workspace/coverage/sync_alert/3.prim_sync_alert.1100791986 Oct 08 12:39:06 PM PDT 23 Oct 08 12:39:07 PM PDT 23 8563743 ps
T61 /workspace/coverage/sync_alert/6.prim_sync_alert.3459743778 Oct 08 12:40:20 PM PDT 23 Oct 08 12:40:21 PM PDT 23 8667101 ps
T12 /workspace/coverage/sync_alert/7.prim_sync_alert.3680386235 Oct 08 12:30:57 PM PDT 23 Oct 08 12:30:58 PM PDT 23 8984748 ps
T62 /workspace/coverage/sync_alert/9.prim_sync_alert.1453592494 Oct 08 12:43:24 PM PDT 23 Oct 08 12:43:25 PM PDT 23 9405385 ps
T63 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3860337458 Oct 08 12:44:18 PM PDT 23 Oct 08 12:44:19 PM PDT 23 31036768 ps
T64 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2806478095 Oct 08 12:41:09 PM PDT 23 Oct 08 12:41:10 PM PDT 23 28570779 ps
T65 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2185712925 Oct 08 12:26:00 PM PDT 23 Oct 08 12:26:00 PM PDT 23 27043299 ps
T66 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3565165578 Oct 08 12:44:26 PM PDT 23 Oct 08 12:44:27 PM PDT 23 27253230 ps
T67 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3579990110 Oct 08 12:29:48 PM PDT 23 Oct 08 12:29:48 PM PDT 23 27345671 ps
T68 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.501401121 Oct 08 12:42:44 PM PDT 23 Oct 08 12:42:45 PM PDT 23 27253013 ps
T69 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2677033441 Oct 08 12:40:25 PM PDT 23 Oct 08 12:40:26 PM PDT 23 26617178 ps
T70 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.964036403 Oct 08 12:39:37 PM PDT 23 Oct 08 12:39:38 PM PDT 23 24859477 ps
T71 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3210704938 Oct 08 12:33:56 PM PDT 23 Oct 08 12:33:57 PM PDT 23 26037838 ps
T13 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1654967300 Oct 08 12:45:34 PM PDT 23 Oct 08 12:45:35 PM PDT 23 26312795 ps
T72 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1944630123 Oct 08 12:25:50 PM PDT 23 Oct 08 12:25:50 PM PDT 23 28980848 ps
T73 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4076237834 Oct 08 12:23:35 PM PDT 23 Oct 08 12:23:36 PM PDT 23 28672814 ps
T5 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.663031066 Oct 08 12:39:42 PM PDT 23 Oct 08 12:39:43 PM PDT 23 27765547 ps
T74 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2337220847 Oct 08 12:40:28 PM PDT 23 Oct 08 12:40:28 PM PDT 23 27259851 ps
T75 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2080545505 Oct 08 12:34:16 PM PDT 23 Oct 08 12:34:17 PM PDT 23 25658991 ps
T76 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2893714252 Oct 08 12:41:44 PM PDT 23 Oct 08 12:41:45 PM PDT 23 27546733 ps
T6 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3422503296 Oct 08 12:40:38 PM PDT 23 Oct 08 12:40:39 PM PDT 23 28726046 ps
T77 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2616967456 Oct 08 12:33:53 PM PDT 23 Oct 08 12:33:53 PM PDT 23 27337132 ps
T78 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3506380151 Oct 08 12:45:49 PM PDT 23 Oct 08 12:45:50 PM PDT 23 27989694 ps
T79 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.894370070 Oct 08 12:43:53 PM PDT 23 Oct 08 12:43:54 PM PDT 23 27718189 ps

Test location /workspace/coverage/default/4.prim_async_alert.4269500877
Short name T11
Test name
Test status
Simulation time 12949964 ps
CPU time 0.4 seconds
Started Oct 08 12:31:38 PM PDT 23
Finished Oct 08 12:31:39 PM PDT 23
Peak memory 145396 kb
Host smart-baa25033-fd09-4f5a-8f8d-9ce1fec682e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269500877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.4269500877
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1967948366
Short name T39
Test name
Test status
Simulation time 10445448 ps
CPU time 0.39 seconds
Started Oct 08 12:45:28 PM PDT 23
Finished Oct 08 12:45:29 PM PDT 23
Peak memory 145036 kb
Host smart-d54aed32-64b3-40c9-8b28-46aa694eed73
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1967948366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1967948366
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4233701109
Short name T16
Test name
Test status
Simulation time 29909845 ps
CPU time 0.41 seconds
Started Oct 08 12:39:17 PM PDT 23
Finished Oct 08 12:39:17 PM PDT 23
Peak memory 145328 kb
Host smart-66ae14b1-bbea-4b2f-9cc0-224320ad0c1c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4233701109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.4233701109
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2526675836
Short name T8
Test name
Test status
Simulation time 10954479 ps
CPU time 0.38 seconds
Started Oct 08 12:41:36 PM PDT 23
Finished Oct 08 12:41:36 PM PDT 23
Peak memory 145436 kb
Host smart-92ec94fe-9254-4fba-bed5-d28241f7bf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526675836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2526675836
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3444411899
Short name T4
Test name
Test status
Simulation time 29675035 ps
CPU time 0.56 seconds
Started Oct 08 12:35:11 PM PDT 23
Finished Oct 08 12:35:12 PM PDT 23
Peak memory 143164 kb
Host smart-69d30f9c-8954-4ce9-a70f-b702b4c221ed
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3444411899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3444411899
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3680386235
Short name T12
Test name
Test status
Simulation time 8984748 ps
CPU time 0.39 seconds
Started Oct 08 12:30:57 PM PDT 23
Finished Oct 08 12:30:58 PM PDT 23
Peak memory 145116 kb
Host smart-3af47c3e-92ae-4f97-a6ca-310a4e6e836e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3680386235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3680386235
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3600116316
Short name T10
Test name
Test status
Simulation time 11253671 ps
CPU time 0.39 seconds
Started Oct 08 12:30:03 PM PDT 23
Finished Oct 08 12:30:04 PM PDT 23
Peak memory 145580 kb
Host smart-e89e7fee-d45f-429b-b8f3-74c9f0eef405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600116316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3600116316
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1060863073
Short name T47
Test name
Test status
Simulation time 11371148 ps
CPU time 0.38 seconds
Started Oct 08 12:46:25 PM PDT 23
Finished Oct 08 12:46:25 PM PDT 23
Peak memory 145456 kb
Host smart-6482f0b3-da88-4d80-b3e7-9881c29cf77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060863073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1060863073
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.3849127233
Short name T1
Test name
Test status
Simulation time 11559286 ps
CPU time 0.36 seconds
Started Oct 08 12:42:01 PM PDT 23
Finished Oct 08 12:42:02 PM PDT 23
Peak memory 145408 kb
Host smart-20a77dc9-2fba-452c-b9ac-934b9f7cf7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849127233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3849127233
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2695261913
Short name T46
Test name
Test status
Simulation time 11447541 ps
CPU time 0.38 seconds
Started Oct 08 12:42:02 PM PDT 23
Finished Oct 08 12:42:02 PM PDT 23
Peak memory 145540 kb
Host smart-9b11c9c6-ea50-4e36-af57-074ace975455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695261913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2695261913
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.3201620608
Short name T45
Test name
Test status
Simulation time 10824597 ps
CPU time 0.38 seconds
Started Oct 08 12:43:40 PM PDT 23
Finished Oct 08 12:43:40 PM PDT 23
Peak memory 145412 kb
Host smart-03d07b65-4be4-4b13-bbbb-43cac7290892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201620608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3201620608
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.3256973479
Short name T21
Test name
Test status
Simulation time 11220141 ps
CPU time 0.39 seconds
Started Oct 08 12:41:04 PM PDT 23
Finished Oct 08 12:41:04 PM PDT 23
Peak memory 145584 kb
Host smart-60b02dd1-c15f-4064-97dc-3a4752dab5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256973479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3256973479
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.2495029171
Short name T7
Test name
Test status
Simulation time 10840787 ps
CPU time 0.38 seconds
Started Oct 08 12:23:36 PM PDT 23
Finished Oct 08 12:23:36 PM PDT 23
Peak memory 145572 kb
Host smart-04239abd-6674-43f6-8da7-bbae8b3e9991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495029171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2495029171
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2439822225
Short name T20
Test name
Test status
Simulation time 11512137 ps
CPU time 0.38 seconds
Started Oct 08 12:33:36 PM PDT 23
Finished Oct 08 12:33:37 PM PDT 23
Peak memory 145396 kb
Host smart-6058e9b8-22e3-48a6-96cc-986d54050740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439822225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2439822225
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.235449819
Short name T15
Test name
Test status
Simulation time 10685711 ps
CPU time 0.51 seconds
Started Oct 08 12:43:24 PM PDT 23
Finished Oct 08 12:43:25 PM PDT 23
Peak memory 143700 kb
Host smart-4fdb60f9-1808-4a57-add5-f6d02866e735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235449819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.235449819
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3997870325
Short name T48
Test name
Test status
Simulation time 10555953 ps
CPU time 0.4 seconds
Started Oct 08 12:23:42 PM PDT 23
Finished Oct 08 12:23:43 PM PDT 23
Peak memory 145384 kb
Host smart-b2868a61-59a4-4f01-9ea0-142c29bf358b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997870325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3997870325
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3603305110
Short name T49
Test name
Test status
Simulation time 10863283 ps
CPU time 0.39 seconds
Started Oct 08 12:27:47 PM PDT 23
Finished Oct 08 12:27:47 PM PDT 23
Peak memory 145572 kb
Host smart-50ca13fb-3eed-4bc7-8ed9-0bcdeea79bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603305110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3603305110
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.2760621358
Short name T2
Test name
Test status
Simulation time 11185745 ps
CPU time 0.37 seconds
Started Oct 08 12:43:18 PM PDT 23
Finished Oct 08 12:43:19 PM PDT 23
Peak memory 145344 kb
Host smart-e0dee005-815e-45a1-9bd7-c2af7e968a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760621358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2760621358
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2049596498
Short name T19
Test name
Test status
Simulation time 11420821 ps
CPU time 0.39 seconds
Started Oct 08 12:33:22 PM PDT 23
Finished Oct 08 12:33:23 PM PDT 23
Peak memory 145572 kb
Host smart-a5a24ba3-0bd1-4ebc-bdf1-33a907a42729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049596498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2049596498
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.2864888306
Short name T3
Test name
Test status
Simulation time 10906870 ps
CPU time 0.38 seconds
Started Oct 08 12:44:43 PM PDT 23
Finished Oct 08 12:44:44 PM PDT 23
Peak memory 145336 kb
Host smart-2d4b83db-5d56-4367-9e65-fd2ac488866f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864888306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2864888306
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2436674753
Short name T22
Test name
Test status
Simulation time 11095693 ps
CPU time 0.38 seconds
Started Oct 08 12:40:16 PM PDT 23
Finished Oct 08 12:40:17 PM PDT 23
Peak memory 145620 kb
Host smart-eb977651-8cf2-4f53-abbf-6d96cc403250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436674753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2436674753
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.3504899834
Short name T9
Test name
Test status
Simulation time 11391567 ps
CPU time 0.38 seconds
Started Oct 08 12:40:18 PM PDT 23
Finished Oct 08 12:40:18 PM PDT 23
Peak memory 145384 kb
Host smart-7e250c10-6663-40aa-b6dd-24bce198c19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504899834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3504899834
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.1226554727
Short name T14
Test name
Test status
Simulation time 11909988 ps
CPU time 0.41 seconds
Started Oct 08 12:36:37 PM PDT 23
Finished Oct 08 12:36:37 PM PDT 23
Peak memory 145388 kb
Host smart-f933b4da-068e-4eab-a8ac-111482abbf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226554727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1226554727
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2649831562
Short name T57
Test name
Test status
Simulation time 28924170 ps
CPU time 0.4 seconds
Started Oct 08 12:37:42 PM PDT 23
Finished Oct 08 12:37:42 PM PDT 23
Peak memory 145492 kb
Host smart-62d5d9e6-5eba-43e6-8349-0c2a31fba767
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2649831562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2649831562
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2738726280
Short name T42
Test name
Test status
Simulation time 29782051 ps
CPU time 0.41 seconds
Started Oct 08 12:30:44 PM PDT 23
Finished Oct 08 12:30:45 PM PDT 23
Peak memory 145600 kb
Host smart-e4ed17ed-a42d-4e13-9f1a-dabcf29d5ed6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2738726280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2738726280
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2679813048
Short name T55
Test name
Test status
Simulation time 29762464 ps
CPU time 0.43 seconds
Started Oct 08 12:31:57 PM PDT 23
Finished Oct 08 12:31:58 PM PDT 23
Peak memory 145504 kb
Host smart-a5b78d86-4de6-4262-b763-588fb7130d89
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2679813048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2679813048
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3331945507
Short name T18
Test name
Test status
Simulation time 31152744 ps
CPU time 0.39 seconds
Started Oct 08 01:25:19 PM PDT 23
Finished Oct 08 01:25:19 PM PDT 23
Peak memory 145720 kb
Host smart-341e8b25-a658-45bd-afd6-9693d6b1d08f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3331945507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3331945507
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.225995762
Short name T52
Test name
Test status
Simulation time 30808335 ps
CPU time 0.44 seconds
Started Oct 08 01:32:40 PM PDT 23
Finished Oct 08 01:32:40 PM PDT 23
Peak memory 145636 kb
Host smart-30d7064d-4e04-48db-b309-512fc17a1a26
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=225995762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.225995762
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1215286889
Short name T43
Test name
Test status
Simulation time 29929112 ps
CPU time 0.49 seconds
Started Oct 08 12:39:15 PM PDT 23
Finished Oct 08 12:39:17 PM PDT 23
Peak memory 143420 kb
Host smart-35fd9a08-1ca1-41bc-ba88-5234540df5a6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1215286889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1215286889
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2988834979
Short name T17
Test name
Test status
Simulation time 32207831 ps
CPU time 0.39 seconds
Started Oct 08 12:39:58 PM PDT 23
Finished Oct 08 12:39:59 PM PDT 23
Peak memory 145608 kb
Host smart-715a62a0-cfec-49aa-80b4-4dfdf5c5a786
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2988834979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2988834979
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4011486663
Short name T40
Test name
Test status
Simulation time 28855551 ps
CPU time 0.46 seconds
Started Oct 08 12:30:54 PM PDT 23
Finished Oct 08 12:30:56 PM PDT 23
Peak memory 145156 kb
Host smart-091a0388-7561-45b9-bded-a56f98417d03
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4011486663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.4011486663
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2671948509
Short name T50
Test name
Test status
Simulation time 29821150 ps
CPU time 0.43 seconds
Started Oct 08 12:39:52 PM PDT 23
Finished Oct 08 12:39:53 PM PDT 23
Peak memory 145632 kb
Host smart-6fd5f5c4-b7d2-45fc-aaf9-f5fffe088dab
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2671948509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2671948509
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4196969382
Short name T44
Test name
Test status
Simulation time 29191007 ps
CPU time 0.39 seconds
Started Oct 08 12:30:55 PM PDT 23
Finished Oct 08 12:30:56 PM PDT 23
Peak memory 145624 kb
Host smart-235710f9-ca11-4470-b86d-bb86d205be66
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4196969382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.4196969382
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.240521840
Short name T56
Test name
Test status
Simulation time 29384474 ps
CPU time 0.39 seconds
Started Oct 08 12:30:56 PM PDT 23
Finished Oct 08 12:30:56 PM PDT 23
Peak memory 145264 kb
Host smart-fb36303c-4422-4289-94ef-56b103cfff77
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=240521840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.240521840
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4168612878
Short name T51
Test name
Test status
Simulation time 31816882 ps
CPU time 0.4 seconds
Started Oct 08 12:47:46 PM PDT 23
Finished Oct 08 12:47:47 PM PDT 23
Peak memory 145492 kb
Host smart-624828ee-665d-4e1f-8f98-3053f7992991
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4168612878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.4168612878
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.428601570
Short name T24
Test name
Test status
Simulation time 29991327 ps
CPU time 0.38 seconds
Started Oct 08 12:40:11 PM PDT 23
Finished Oct 08 12:40:11 PM PDT 23
Peak memory 145492 kb
Host smart-2b53defe-90fe-43f8-b374-4f33974e74ba
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=428601570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.428601570
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.588011754
Short name T41
Test name
Test status
Simulation time 29396291 ps
CPU time 0.4 seconds
Started Oct 08 12:29:39 PM PDT 23
Finished Oct 08 12:29:40 PM PDT 23
Peak memory 145480 kb
Host smart-8cb4b759-db11-47a3-bb3c-bbe2f974aabc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=588011754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.588011754
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2968198055
Short name T23
Test name
Test status
Simulation time 29298156 ps
CPU time 0.39 seconds
Started Oct 08 12:45:19 PM PDT 23
Finished Oct 08 12:45:19 PM PDT 23
Peak memory 145592 kb
Host smart-6194585d-f701-479a-b4f2-fd3a925b7a1c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2968198055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2968198055
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2738498900
Short name T54
Test name
Test status
Simulation time 31740299 ps
CPU time 0.39 seconds
Started Oct 08 12:29:03 PM PDT 23
Finished Oct 08 12:29:03 PM PDT 23
Peak memory 145500 kb
Host smart-b013dc0c-b86b-4944-92ce-2e180c976d6e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2738498900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2738498900
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.940104695
Short name T53
Test name
Test status
Simulation time 31850717 ps
CPU time 0.46 seconds
Started Oct 08 12:36:50 PM PDT 23
Finished Oct 08 12:36:52 PM PDT 23
Peak memory 143932 kb
Host smart-68f6a046-9a34-4946-af54-72766649625e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=940104695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.940104695
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.810979007
Short name T25
Test name
Test status
Simulation time 30526954 ps
CPU time 0.4 seconds
Started Oct 08 12:34:06 PM PDT 23
Finished Oct 08 12:34:07 PM PDT 23
Peak memory 145660 kb
Host smart-0f2422c9-8e37-4e34-90a3-9c43400f951c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=810979007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.810979007
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.845360585
Short name T59
Test name
Test status
Simulation time 8948154 ps
CPU time 0.39 seconds
Started Oct 08 12:46:52 PM PDT 23
Finished Oct 08 12:46:53 PM PDT 23
Peak memory 145044 kb
Host smart-964c013c-bdcf-4d0b-8541-89c281e03127
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=845360585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.845360585
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.2184652562
Short name T34
Test name
Test status
Simulation time 9024405 ps
CPU time 0.38 seconds
Started Oct 08 12:41:22 PM PDT 23
Finished Oct 08 12:41:23 PM PDT 23
Peak memory 145044 kb
Host smart-cc36b7ad-a898-49f0-8293-24a6b2f25a72
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2184652562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2184652562
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3030599755
Short name T33
Test name
Test status
Simulation time 9158679 ps
CPU time 0.39 seconds
Started Oct 08 12:27:36 PM PDT 23
Finished Oct 08 12:27:37 PM PDT 23
Peak memory 145172 kb
Host smart-b5738268-da2b-41f3-afe3-adc1fa084de3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3030599755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3030599755
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.943619018
Short name T28
Test name
Test status
Simulation time 8924187 ps
CPU time 0.41 seconds
Started Oct 08 12:39:31 PM PDT 23
Finished Oct 08 12:39:32 PM PDT 23
Peak memory 144912 kb
Host smart-a865335b-7b64-4073-ad42-64cf71746d40
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=943619018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.943619018
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3121794494
Short name T30
Test name
Test status
Simulation time 9884164 ps
CPU time 0.37 seconds
Started Oct 08 12:39:05 PM PDT 23
Finished Oct 08 12:39:06 PM PDT 23
Peak memory 144876 kb
Host smart-de152134-62cc-404d-b7d8-e00b1af6660b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3121794494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3121794494
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2730113451
Short name T26
Test name
Test status
Simulation time 9062701 ps
CPU time 0.38 seconds
Started Oct 08 12:27:56 PM PDT 23
Finished Oct 08 12:27:56 PM PDT 23
Peak memory 145124 kb
Host smart-cf7fe0f7-c2d0-4c1d-a1f9-0daf4100ea42
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2730113451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2730113451
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3825956008
Short name T32
Test name
Test status
Simulation time 9086587 ps
CPU time 0.37 seconds
Started Oct 08 12:41:22 PM PDT 23
Finished Oct 08 12:41:23 PM PDT 23
Peak memory 145012 kb
Host smart-d73eaf49-1662-485a-a8c0-5c2fa991ce50
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3825956008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3825956008
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.2114796305
Short name T36
Test name
Test status
Simulation time 10128025 ps
CPU time 0.39 seconds
Started Oct 08 12:29:27 PM PDT 23
Finished Oct 08 12:29:27 PM PDT 23
Peak memory 144920 kb
Host smart-6838a91f-c861-4ad4-8942-584b2f07ad7b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2114796305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2114796305
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.4011540303
Short name T35
Test name
Test status
Simulation time 9201180 ps
CPU time 0.42 seconds
Started Oct 08 12:24:23 PM PDT 23
Finished Oct 08 12:24:23 PM PDT 23
Peak memory 145044 kb
Host smart-8214c711-acd9-44e6-8af2-ed8919481b7b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4011540303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.4011540303
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.1445080571
Short name T29
Test name
Test status
Simulation time 9754287 ps
CPU time 0.41 seconds
Started Oct 08 12:24:23 PM PDT 23
Finished Oct 08 12:24:23 PM PDT 23
Peak memory 145044 kb
Host smart-53c2545e-6f47-4e51-b6a0-0b20bdf8f864
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1445080571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1445080571
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.986883950
Short name T37
Test name
Test status
Simulation time 8681939 ps
CPU time 0.39 seconds
Started Oct 08 12:26:45 PM PDT 23
Finished Oct 08 12:26:46 PM PDT 23
Peak memory 145144 kb
Host smart-4d60fee3-de34-415b-aa12-47fbfdb997e6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=986883950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.986883950
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.61218992
Short name T31
Test name
Test status
Simulation time 8608542 ps
CPU time 0.37 seconds
Started Oct 08 12:45:47 PM PDT 23
Finished Oct 08 12:45:48 PM PDT 23
Peak memory 144912 kb
Host smart-62d205dd-2915-428b-b10b-273245a41893
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=61218992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.61218992
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1100791986
Short name T60
Test name
Test status
Simulation time 8563743 ps
CPU time 0.37 seconds
Started Oct 08 12:39:06 PM PDT 23
Finished Oct 08 12:39:07 PM PDT 23
Peak memory 144924 kb
Host smart-7433c42a-c974-467f-81e5-69fa4b91c83c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1100791986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1100791986
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.202989481
Short name T58
Test name
Test status
Simulation time 8159667 ps
CPU time 0.37 seconds
Started Oct 08 12:34:59 PM PDT 23
Finished Oct 08 12:34:59 PM PDT 23
Peak memory 145152 kb
Host smart-a1f74869-a5cc-4da0-801e-5e5def91444f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=202989481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.202989481
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1624628609
Short name T27
Test name
Test status
Simulation time 9455104 ps
CPU time 0.4 seconds
Started Oct 08 12:47:47 PM PDT 23
Finished Oct 08 12:47:48 PM PDT 23
Peak memory 144928 kb
Host smart-42c8efe2-247a-466a-a6d8-b94c27e69379
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1624628609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1624628609
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.3459743778
Short name T61
Test name
Test status
Simulation time 8667101 ps
CPU time 0.38 seconds
Started Oct 08 12:40:20 PM PDT 23
Finished Oct 08 12:40:21 PM PDT 23
Peak memory 144992 kb
Host smart-3f6eb40f-d91d-49e0-ac42-7bba228b2bcb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3459743778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3459743778
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.3674227133
Short name T38
Test name
Test status
Simulation time 9329351 ps
CPU time 0.39 seconds
Started Oct 08 12:28:41 PM PDT 23
Finished Oct 08 12:28:42 PM PDT 23
Peak memory 144920 kb
Host smart-ec0e9c8a-d389-4a5d-a4f2-67f8dde607c2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3674227133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3674227133
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1453592494
Short name T62
Test name
Test status
Simulation time 9405385 ps
CPU time 0.4 seconds
Started Oct 08 12:43:24 PM PDT 23
Finished Oct 08 12:43:25 PM PDT 23
Peak memory 143364 kb
Host smart-7ed72a8e-12ec-40e0-99e5-963af9497cd2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1453592494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1453592494
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2806478095
Short name T64
Test name
Test status
Simulation time 28570779 ps
CPU time 0.4 seconds
Started Oct 08 12:41:09 PM PDT 23
Finished Oct 08 12:41:10 PM PDT 23
Peak memory 144940 kb
Host smart-e76c2cae-38fd-41ea-820e-1a958735b058
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2806478095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2806478095
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2337220847
Short name T74
Test name
Test status
Simulation time 27259851 ps
CPU time 0.4 seconds
Started Oct 08 12:40:28 PM PDT 23
Finished Oct 08 12:40:28 PM PDT 23
Peak memory 145000 kb
Host smart-b342a535-1070-4204-bcb6-45589f707326
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2337220847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2337220847
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2677033441
Short name T69
Test name
Test status
Simulation time 26617178 ps
CPU time 0.39 seconds
Started Oct 08 12:40:25 PM PDT 23
Finished Oct 08 12:40:26 PM PDT 23
Peak memory 144904 kb
Host smart-39bbc6ce-401f-4dff-9a28-acab99be0fde
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2677033441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2677033441
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2185712925
Short name T65
Test name
Test status
Simulation time 27043299 ps
CPU time 0.41 seconds
Started Oct 08 12:26:00 PM PDT 23
Finished Oct 08 12:26:00 PM PDT 23
Peak memory 145116 kb
Host smart-335e2367-3254-4b02-a49d-9818c81f33f7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2185712925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2185712925
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.501401121
Short name T68
Test name
Test status
Simulation time 27253013 ps
CPU time 0.4 seconds
Started Oct 08 12:42:44 PM PDT 23
Finished Oct 08 12:42:45 PM PDT 23
Peak memory 144940 kb
Host smart-66f1aa9d-0ca5-4bcb-8aae-e69384fa036f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=501401121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.501401121
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3860337458
Short name T63
Test name
Test status
Simulation time 31036768 ps
CPU time 0.38 seconds
Started Oct 08 12:44:18 PM PDT 23
Finished Oct 08 12:44:19 PM PDT 23
Peak memory 145044 kb
Host smart-ad99a40d-12cb-4f4d-9ad9-1e8a2cb58052
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3860337458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3860337458
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2080545505
Short name T75
Test name
Test status
Simulation time 25658991 ps
CPU time 0.39 seconds
Started Oct 08 12:34:16 PM PDT 23
Finished Oct 08 12:34:17 PM PDT 23
Peak memory 145008 kb
Host smart-82adaedc-054e-4bc1-8938-df5e916dc84c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2080545505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2080545505
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3506380151
Short name T78
Test name
Test status
Simulation time 27989694 ps
CPU time 0.42 seconds
Started Oct 08 12:45:49 PM PDT 23
Finished Oct 08 12:45:50 PM PDT 23
Peak memory 144936 kb
Host smart-17cc2711-909b-4274-aa38-b4492dcccdcc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3506380151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3506380151
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1654967300
Short name T13
Test name
Test status
Simulation time 26312795 ps
CPU time 0.4 seconds
Started Oct 08 12:45:34 PM PDT 23
Finished Oct 08 12:45:35 PM PDT 23
Peak memory 145000 kb
Host smart-ec4198ec-b12b-4516-b9fe-c0dde8385c50
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1654967300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1654967300
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2893714252
Short name T76
Test name
Test status
Simulation time 27546733 ps
CPU time 0.39 seconds
Started Oct 08 12:41:44 PM PDT 23
Finished Oct 08 12:41:45 PM PDT 23
Peak memory 144980 kb
Host smart-8b80d489-e5e6-43d8-b583-cb2a51bee973
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2893714252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2893714252
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2616967456
Short name T77
Test name
Test status
Simulation time 27337132 ps
CPU time 0.41 seconds
Started Oct 08 12:33:53 PM PDT 23
Finished Oct 08 12:33:53 PM PDT 23
Peak memory 145068 kb
Host smart-ef1cc747-a581-4ea1-9b96-320e1d148607
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2616967456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2616967456
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1944630123
Short name T72
Test name
Test status
Simulation time 28980848 ps
CPU time 0.42 seconds
Started Oct 08 12:25:50 PM PDT 23
Finished Oct 08 12:25:50 PM PDT 23
Peak memory 144948 kb
Host smart-d22bdd12-b8cb-4fb7-8d87-e894eaa8c2cd
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1944630123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1944630123
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.964036403
Short name T70
Test name
Test status
Simulation time 24859477 ps
CPU time 0.4 seconds
Started Oct 08 12:39:37 PM PDT 23
Finished Oct 08 12:39:38 PM PDT 23
Peak memory 144804 kb
Host smart-0b06fd61-64dd-4e70-a245-a825a83e4fa7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=964036403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.964036403
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3565165578
Short name T66
Test name
Test status
Simulation time 27253230 ps
CPU time 0.39 seconds
Started Oct 08 12:44:26 PM PDT 23
Finished Oct 08 12:44:27 PM PDT 23
Peak memory 144968 kb
Host smart-9f8e3eb8-67ca-40a8-85ae-bc7e41d8a77f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3565165578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3565165578
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3422503296
Short name T6
Test name
Test status
Simulation time 28726046 ps
CPU time 0.43 seconds
Started Oct 08 12:40:38 PM PDT 23
Finished Oct 08 12:40:39 PM PDT 23
Peak memory 144940 kb
Host smart-95cb5a30-6ae9-4165-aa82-37325e30648f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3422503296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3422503296
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3579990110
Short name T67
Test name
Test status
Simulation time 27345671 ps
CPU time 0.4 seconds
Started Oct 08 12:29:48 PM PDT 23
Finished Oct 08 12:29:48 PM PDT 23
Peak memory 144936 kb
Host smart-cbc398ad-c245-46a8-a925-2d9f259663fe
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3579990110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3579990110
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.894370070
Short name T79
Test name
Test status
Simulation time 27718189 ps
CPU time 0.39 seconds
Started Oct 08 12:43:53 PM PDT 23
Finished Oct 08 12:43:54 PM PDT 23
Peak memory 144940 kb
Host smart-694a764e-c7c1-4583-a8d4-981cf0f28d57
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=894370070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.894370070
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4076237834
Short name T73
Test name
Test status
Simulation time 28672814 ps
CPU time 0.4 seconds
Started Oct 08 12:23:35 PM PDT 23
Finished Oct 08 12:23:36 PM PDT 23
Peak memory 145144 kb
Host smart-06f1aaca-34e5-429d-b71d-01c81228edb9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4076237834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.4076237834
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.663031066
Short name T5
Test name
Test status
Simulation time 27765547 ps
CPU time 0.38 seconds
Started Oct 08 12:39:42 PM PDT 23
Finished Oct 08 12:39:43 PM PDT 23
Peak memory 145008 kb
Host smart-74a5c1e0-9b66-4ef4-9600-bcc4af29e7d4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=663031066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.663031066
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3210704938
Short name T71
Test name
Test status
Simulation time 26037838 ps
CPU time 0.41 seconds
Started Oct 08 12:33:56 PM PDT 23
Finished Oct 08 12:33:57 PM PDT 23
Peak memory 144944 kb
Host smart-4f75c833-7415-4247-9742-9b66316a3c84
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3210704938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3210704938
Directory /workspace/9.prim_sync_fatal_alert/latest
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