Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.28 88.28 100.00 100.00 93.75 93.75 100.00 100.00 75.00 75.00 95.83 95.83 65.12 65.12 /workspace/coverage/default/15.prim_async_alert.3090281234
92.01 3.72 100.00 0.00 93.75 0.00 100.00 0.00 85.71 10.71 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/9.prim_sync_alert.1202943249
94.11 2.11 100.00 0.00 95.83 2.08 100.00 0.00 89.29 3.57 95.83 0.00 83.72 6.98 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3226621160
94.81 0.69 100.00 0.00 100.00 4.17 100.00 0.00 89.29 0.00 95.83 0.00 83.72 0.00 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.636758183
95.19 0.39 100.00 0.00 100.00 0.00 100.00 0.00 89.29 0.00 95.83 0.00 86.05 2.33 /workspace/coverage/default/12.prim_async_alert.2961682005

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3175401941
/workspace/coverage/default/1.prim_async_alert.659275950
/workspace/coverage/default/10.prim_async_alert.3872343977
/workspace/coverage/default/11.prim_async_alert.3056440991
/workspace/coverage/default/13.prim_async_alert.2221899932
/workspace/coverage/default/14.prim_async_alert.325008668
/workspace/coverage/default/16.prim_async_alert.3291785263
/workspace/coverage/default/17.prim_async_alert.3980176693
/workspace/coverage/default/18.prim_async_alert.2017102268
/workspace/coverage/default/19.prim_async_alert.1491381313
/workspace/coverage/default/2.prim_async_alert.1242163692
/workspace/coverage/default/3.prim_async_alert.2560580609
/workspace/coverage/default/4.prim_async_alert.1921202736
/workspace/coverage/default/5.prim_async_alert.1999800462
/workspace/coverage/default/6.prim_async_alert.791417890
/workspace/coverage/default/7.prim_async_alert.2110902623
/workspace/coverage/default/8.prim_async_alert.2777397660
/workspace/coverage/default/9.prim_async_alert.1344231451
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3279733026
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4018945957
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1267158924
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.4250211628
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1474492406
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2152799223
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1080954391
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1461155511
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2252229543
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1835910689
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.891665215
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2511184186
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1970167990
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1295889528
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3238686372
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.457008739
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2039721340
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3023599924
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2206711494
/workspace/coverage/sync_alert/0.prim_sync_alert.1685167029
/workspace/coverage/sync_alert/1.prim_sync_alert.969082823
/workspace/coverage/sync_alert/10.prim_sync_alert.1898580244
/workspace/coverage/sync_alert/11.prim_sync_alert.2623862617
/workspace/coverage/sync_alert/12.prim_sync_alert.3790692272
/workspace/coverage/sync_alert/13.prim_sync_alert.903899630
/workspace/coverage/sync_alert/14.prim_sync_alert.1849775064
/workspace/coverage/sync_alert/15.prim_sync_alert.1635386701
/workspace/coverage/sync_alert/16.prim_sync_alert.3118677008
/workspace/coverage/sync_alert/17.prim_sync_alert.666751809
/workspace/coverage/sync_alert/18.prim_sync_alert.1827105968
/workspace/coverage/sync_alert/19.prim_sync_alert.3596727156
/workspace/coverage/sync_alert/2.prim_sync_alert.2039520700
/workspace/coverage/sync_alert/3.prim_sync_alert.3920815332
/workspace/coverage/sync_alert/4.prim_sync_alert.3049916577
/workspace/coverage/sync_alert/5.prim_sync_alert.3321585739
/workspace/coverage/sync_alert/6.prim_sync_alert.997055827
/workspace/coverage/sync_alert/7.prim_sync_alert.3203280713
/workspace/coverage/sync_alert/8.prim_sync_alert.2868201265
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1780156981
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.4006950538
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1937914213
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2925658864
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2795308510
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2890881018
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3536860851
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1288417312
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1543902777
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.555360978
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.657165437
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4036277103
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1535562952
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3708858307
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.279848077
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3454510414
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1525582850
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3275089272
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3290971835



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/7.prim_async_alert.2110902623 Oct 15 12:20:49 PM PDT 23 Oct 15 12:20:50 PM PDT 23 10659692 ps
T2 /workspace/coverage/default/18.prim_async_alert.2017102268 Oct 15 12:22:02 PM PDT 23 Oct 15 12:22:03 PM PDT 23 11057867 ps
T3 /workspace/coverage/default/15.prim_async_alert.3090281234 Oct 15 12:22:03 PM PDT 23 Oct 15 12:22:04 PM PDT 23 11489133 ps
T14 /workspace/coverage/default/3.prim_async_alert.2560580609 Oct 15 12:21:02 PM PDT 23 Oct 15 12:21:03 PM PDT 23 11733659 ps
T21 /workspace/coverage/default/0.prim_async_alert.3175401941 Oct 15 12:23:29 PM PDT 23 Oct 15 12:23:30 PM PDT 23 10794420 ps
T7 /workspace/coverage/default/13.prim_async_alert.2221899932 Oct 15 12:21:13 PM PDT 23 Oct 15 12:21:15 PM PDT 23 11174914 ps
T22 /workspace/coverage/default/16.prim_async_alert.3291785263 Oct 15 12:20:58 PM PDT 23 Oct 15 12:20:59 PM PDT 23 10899079 ps
T23 /workspace/coverage/default/19.prim_async_alert.1491381313 Oct 15 12:21:24 PM PDT 23 Oct 15 12:21:25 PM PDT 23 11561265 ps
T20 /workspace/coverage/default/2.prim_async_alert.1242163692 Oct 15 12:21:03 PM PDT 23 Oct 15 12:21:04 PM PDT 23 11824802 ps
T24 /workspace/coverage/default/4.prim_async_alert.1921202736 Oct 15 12:20:24 PM PDT 23 Oct 15 12:20:25 PM PDT 23 11118453 ps
T15 /workspace/coverage/default/11.prim_async_alert.3056440991 Oct 15 12:21:12 PM PDT 23 Oct 15 12:21:14 PM PDT 23 11850417 ps
T8 /workspace/coverage/default/17.prim_async_alert.3980176693 Oct 15 12:20:57 PM PDT 23 Oct 15 12:20:58 PM PDT 23 11489029 ps
T9 /workspace/coverage/default/6.prim_async_alert.791417890 Oct 15 12:22:05 PM PDT 23 Oct 15 12:22:06 PM PDT 23 12123389 ps
T10 /workspace/coverage/default/5.prim_async_alert.1999800462 Oct 15 12:21:14 PM PDT 23 Oct 15 12:21:16 PM PDT 23 11117497 ps
T25 /workspace/coverage/default/12.prim_async_alert.2961682005 Oct 15 12:21:13 PM PDT 23 Oct 15 12:21:15 PM PDT 23 11023638 ps
T26 /workspace/coverage/default/8.prim_async_alert.2777397660 Oct 15 12:21:01 PM PDT 23 Oct 15 12:21:03 PM PDT 23 12113479 ps
T16 /workspace/coverage/default/1.prim_async_alert.659275950 Oct 15 12:20:57 PM PDT 23 Oct 15 12:20:58 PM PDT 23 12000712 ps
T42 /workspace/coverage/default/10.prim_async_alert.3872343977 Oct 15 12:22:09 PM PDT 23 Oct 15 12:22:10 PM PDT 23 10293201 ps
T17 /workspace/coverage/default/14.prim_async_alert.325008668 Oct 15 12:22:02 PM PDT 23 Oct 15 12:22:03 PM PDT 23 12332510 ps
T47 /workspace/coverage/default/9.prim_async_alert.1344231451 Oct 15 12:22:12 PM PDT 23 Oct 15 12:22:12 PM PDT 23 11087632 ps
T4 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1295889528 Oct 15 12:15:19 PM PDT 23 Oct 15 12:15:20 PM PDT 23 28780668 ps
T27 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4018945957 Oct 15 12:15:25 PM PDT 23 Oct 15 12:15:26 PM PDT 23 27332396 ps
T28 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1474492406 Oct 15 12:15:31 PM PDT 23 Oct 15 12:15:32 PM PDT 23 31787072 ps
T5 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3023599924 Oct 15 12:15:42 PM PDT 23 Oct 15 12:15:43 PM PDT 23 28031716 ps
T29 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1835910689 Oct 15 12:15:31 PM PDT 23 Oct 15 12:15:32 PM PDT 23 30760838 ps
T43 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1080954391 Oct 15 12:15:40 PM PDT 23 Oct 15 12:15:41 PM PDT 23 30738725 ps
T44 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3226621160 Oct 15 12:15:24 PM PDT 23 Oct 15 12:15:25 PM PDT 23 30969631 ps
T6 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1267158924 Oct 15 12:15:25 PM PDT 23 Oct 15 12:15:25 PM PDT 23 29857641 ps
T45 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1461155511 Oct 15 12:15:30 PM PDT 23 Oct 15 12:15:31 PM PDT 23 30423050 ps
T46 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2152799223 Oct 15 12:15:40 PM PDT 23 Oct 15 12:15:41 PM PDT 23 28935834 ps
T41 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2206711494 Oct 15 12:15:24 PM PDT 23 Oct 15 12:15:24 PM PDT 23 27763344 ps
T48 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1970167990 Oct 15 12:15:30 PM PDT 23 Oct 15 12:15:31 PM PDT 23 30998015 ps
T49 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2039721340 Oct 15 12:15:34 PM PDT 23 Oct 15 12:15:35 PM PDT 23 30127845 ps
T50 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3279733026 Oct 15 12:15:24 PM PDT 23 Oct 15 12:15:24 PM PDT 23 29116114 ps
T51 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.4250211628 Oct 15 12:15:34 PM PDT 23 Oct 15 12:15:35 PM PDT 23 29945717 ps
T52 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.891665215 Oct 15 12:15:20 PM PDT 23 Oct 15 12:15:21 PM PDT 23 29413900 ps
T53 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3238686372 Oct 15 12:15:24 PM PDT 23 Oct 15 12:15:24 PM PDT 23 30479436 ps
T54 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2252229543 Oct 15 12:15:24 PM PDT 23 Oct 15 12:15:25 PM PDT 23 30561552 ps
T55 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2511184186 Oct 15 12:15:24 PM PDT 23 Oct 15 12:15:24 PM PDT 23 31645338 ps
T56 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.457008739 Oct 15 12:15:24 PM PDT 23 Oct 15 12:15:25 PM PDT 23 30951817 ps
T38 /workspace/coverage/sync_alert/7.prim_sync_alert.3203280713 Oct 15 12:23:03 PM PDT 23 Oct 15 12:23:04 PM PDT 23 9256063 ps
T39 /workspace/coverage/sync_alert/3.prim_sync_alert.3920815332 Oct 15 12:21:09 PM PDT 23 Oct 15 12:21:10 PM PDT 23 9318714 ps
T40 /workspace/coverage/sync_alert/6.prim_sync_alert.997055827 Oct 15 12:23:03 PM PDT 23 Oct 15 12:23:04 PM PDT 23 9049824 ps
T30 /workspace/coverage/sync_alert/15.prim_sync_alert.1635386701 Oct 15 12:23:18 PM PDT 23 Oct 15 12:23:19 PM PDT 23 8656791 ps
T18 /workspace/coverage/sync_alert/18.prim_sync_alert.1827105968 Oct 15 12:20:57 PM PDT 23 Oct 15 12:20:58 PM PDT 23 9956959 ps
T19 /workspace/coverage/sync_alert/19.prim_sync_alert.3596727156 Oct 15 12:22:49 PM PDT 23 Oct 15 12:22:49 PM PDT 23 10478124 ps
T31 /workspace/coverage/sync_alert/2.prim_sync_alert.2039520700 Oct 15 12:19:22 PM PDT 23 Oct 15 12:19:23 PM PDT 23 8537545 ps
T32 /workspace/coverage/sync_alert/13.prim_sync_alert.903899630 Oct 15 12:20:57 PM PDT 23 Oct 15 12:20:58 PM PDT 23 8343167 ps
T33 /workspace/coverage/sync_alert/9.prim_sync_alert.1202943249 Oct 15 12:23:17 PM PDT 23 Oct 15 12:23:18 PM PDT 23 9674804 ps
T34 /workspace/coverage/sync_alert/12.prim_sync_alert.3790692272 Oct 15 12:19:22 PM PDT 23 Oct 15 12:19:22 PM PDT 23 9243312 ps
T35 /workspace/coverage/sync_alert/0.prim_sync_alert.1685167029 Oct 15 12:19:21 PM PDT 23 Oct 15 12:19:22 PM PDT 23 9329493 ps
T36 /workspace/coverage/sync_alert/17.prim_sync_alert.666751809 Oct 15 12:21:11 PM PDT 23 Oct 15 12:21:12 PM PDT 23 8750120 ps
T37 /workspace/coverage/sync_alert/1.prim_sync_alert.969082823 Oct 15 12:21:24 PM PDT 23 Oct 15 12:21:25 PM PDT 23 9430034 ps
T57 /workspace/coverage/sync_alert/10.prim_sync_alert.1898580244 Oct 15 12:19:22 PM PDT 23 Oct 15 12:19:23 PM PDT 23 8925095 ps
T58 /workspace/coverage/sync_alert/16.prim_sync_alert.3118677008 Oct 15 12:23:03 PM PDT 23 Oct 15 12:23:09 PM PDT 23 8909359 ps
T59 /workspace/coverage/sync_alert/8.prim_sync_alert.2868201265 Oct 15 12:20:59 PM PDT 23 Oct 15 12:21:00 PM PDT 23 9786021 ps
T60 /workspace/coverage/sync_alert/14.prim_sync_alert.1849775064 Oct 15 12:20:57 PM PDT 23 Oct 15 12:20:58 PM PDT 23 8859991 ps
T61 /workspace/coverage/sync_alert/4.prim_sync_alert.3049916577 Oct 15 12:20:57 PM PDT 23 Oct 15 12:20:58 PM PDT 23 9426984 ps
T62 /workspace/coverage/sync_alert/11.prim_sync_alert.2623862617 Oct 15 12:23:32 PM PDT 23 Oct 15 12:23:43 PM PDT 23 9311316 ps
T63 /workspace/coverage/sync_alert/5.prim_sync_alert.3321585739 Oct 15 12:19:34 PM PDT 23 Oct 15 12:19:35 PM PDT 23 9324284 ps
T11 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1525582850 Oct 15 12:21:01 PM PDT 23 Oct 15 12:21:02 PM PDT 23 26330634 ps
T64 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1937914213 Oct 15 12:21:49 PM PDT 23 Oct 15 12:21:50 PM PDT 23 28292914 ps
T65 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1780156981 Oct 15 12:23:00 PM PDT 23 Oct 15 12:23:01 PM PDT 23 26262825 ps
T66 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2925658864 Oct 15 12:21:01 PM PDT 23 Oct 15 12:21:02 PM PDT 23 27010641 ps
T67 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.555360978 Oct 15 12:23:29 PM PDT 23 Oct 15 12:23:30 PM PDT 23 27835498 ps
T68 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2795308510 Oct 15 12:21:23 PM PDT 23 Oct 15 12:21:24 PM PDT 23 26348479 ps
T69 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3454510414 Oct 15 12:21:00 PM PDT 23 Oct 15 12:21:02 PM PDT 23 28171671 ps
T70 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.657165437 Oct 15 12:22:26 PM PDT 23 Oct 15 12:22:27 PM PDT 23 27291742 ps
T12 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.636758183 Oct 15 12:21:33 PM PDT 23 Oct 15 12:21:34 PM PDT 23 27647653 ps
T71 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4036277103 Oct 15 12:23:06 PM PDT 23 Oct 15 12:23:07 PM PDT 23 27593704 ps
T72 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.4006950538 Oct 15 12:23:21 PM PDT 23 Oct 15 12:23:22 PM PDT 23 25912311 ps
T73 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3536860851 Oct 15 12:21:49 PM PDT 23 Oct 15 12:21:50 PM PDT 23 26937716 ps
T74 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3290971835 Oct 15 12:18:56 PM PDT 23 Oct 15 12:18:57 PM PDT 23 28065599 ps
T75 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1543902777 Oct 15 12:21:00 PM PDT 23 Oct 15 12:21:02 PM PDT 23 28318159 ps
T76 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.279848077 Oct 15 12:21:11 PM PDT 23 Oct 15 12:21:11 PM PDT 23 27587536 ps
T77 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2890881018 Oct 15 12:22:37 PM PDT 23 Oct 15 12:22:38 PM PDT 23 26190460 ps
T13 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3275089272 Oct 15 12:19:17 PM PDT 23 Oct 15 12:19:18 PM PDT 23 27747219 ps
T78 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1288417312 Oct 15 12:21:01 PM PDT 23 Oct 15 12:21:02 PM PDT 23 27319005 ps
T79 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3708858307 Oct 15 12:23:19 PM PDT 23 Oct 15 12:23:20 PM PDT 23 26974827 ps
T80 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1535562952 Oct 15 12:20:57 PM PDT 23 Oct 15 12:20:58 PM PDT 23 29015600 ps

Test location /workspace/coverage/default/15.prim_async_alert.3090281234
Short name T3
Test name
Test status
Simulation time 11489133 ps
CPU time 0.4 seconds
Started Oct 15 12:22:03 PM PDT 23
Finished Oct 15 12:22:04 PM PDT 23
Peak memory 145384 kb
Host smart-a62e6d0e-c4b1-4351-89c9-92ccf030482d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090281234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3090281234
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1202943249
Short name T33
Test name
Test status
Simulation time 9674804 ps
CPU time 0.38 seconds
Started Oct 15 12:23:17 PM PDT 23
Finished Oct 15 12:23:18 PM PDT 23
Peak memory 144908 kb
Host smart-abdf1ed7-a731-4962-aad7-36764681443a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1202943249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1202943249
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3226621160
Short name T44
Test name
Test status
Simulation time 30969631 ps
CPU time 0.41 seconds
Started Oct 15 12:15:24 PM PDT 23
Finished Oct 15 12:15:25 PM PDT 23
Peak memory 145396 kb
Host smart-f4bd9137-945f-4a18-8a20-c7f6915aee6f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3226621160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3226621160
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.636758183
Short name T12
Test name
Test status
Simulation time 27647653 ps
CPU time 0.45 seconds
Started Oct 15 12:21:33 PM PDT 23
Finished Oct 15 12:21:34 PM PDT 23
Peak memory 143524 kb
Host smart-99b52010-536e-4561-972d-28cfd494c022
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=636758183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.636758183
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2961682005
Short name T25
Test name
Test status
Simulation time 11023638 ps
CPU time 0.48 seconds
Started Oct 15 12:21:13 PM PDT 23
Finished Oct 15 12:21:15 PM PDT 23
Peak memory 143680 kb
Host smart-51a1d8e1-faf7-4156-be16-864d17d85860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961682005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2961682005
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3175401941
Short name T21
Test name
Test status
Simulation time 10794420 ps
CPU time 0.4 seconds
Started Oct 15 12:23:29 PM PDT 23
Finished Oct 15 12:23:30 PM PDT 23
Peak memory 145340 kb
Host smart-980bb73f-0586-4cac-b2e9-fe27c104a103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175401941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3175401941
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.659275950
Short name T16
Test name
Test status
Simulation time 12000712 ps
CPU time 0.39 seconds
Started Oct 15 12:20:57 PM PDT 23
Finished Oct 15 12:20:58 PM PDT 23
Peak memory 145312 kb
Host smart-c332a32f-0b40-441a-9722-5239ff9937b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659275950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.659275950
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3872343977
Short name T42
Test name
Test status
Simulation time 10293201 ps
CPU time 0.38 seconds
Started Oct 15 12:22:09 PM PDT 23
Finished Oct 15 12:22:10 PM PDT 23
Peak memory 145204 kb
Host smart-30765f95-84c4-4f8b-8f2d-32a8fa26be06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872343977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3872343977
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.3056440991
Short name T15
Test name
Test status
Simulation time 11850417 ps
CPU time 0.41 seconds
Started Oct 15 12:21:12 PM PDT 23
Finished Oct 15 12:21:14 PM PDT 23
Peak memory 145336 kb
Host smart-33dc7095-c18d-44a0-99a8-d2cdd98821a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056440991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3056440991
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2221899932
Short name T7
Test name
Test status
Simulation time 11174914 ps
CPU time 0.49 seconds
Started Oct 15 12:21:13 PM PDT 23
Finished Oct 15 12:21:15 PM PDT 23
Peak memory 144296 kb
Host smart-a18e2a63-85dc-4972-a4e1-06a1f45fd50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221899932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2221899932
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.325008668
Short name T17
Test name
Test status
Simulation time 12332510 ps
CPU time 0.4 seconds
Started Oct 15 12:22:02 PM PDT 23
Finished Oct 15 12:22:03 PM PDT 23
Peak memory 145664 kb
Host smart-66682a04-e2fd-41da-b698-0252b65bbf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325008668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.325008668
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3291785263
Short name T22
Test name
Test status
Simulation time 10899079 ps
CPU time 0.39 seconds
Started Oct 15 12:20:58 PM PDT 23
Finished Oct 15 12:20:59 PM PDT 23
Peak memory 145384 kb
Host smart-4b0957fc-5b23-4058-b29c-e782f9d4a7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291785263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3291785263
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.3980176693
Short name T8
Test name
Test status
Simulation time 11489029 ps
CPU time 0.37 seconds
Started Oct 15 12:20:57 PM PDT 23
Finished Oct 15 12:20:58 PM PDT 23
Peak memory 145744 kb
Host smart-f49b064e-674b-447f-913a-fd763f7758b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980176693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3980176693
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2017102268
Short name T2
Test name
Test status
Simulation time 11057867 ps
CPU time 0.39 seconds
Started Oct 15 12:22:02 PM PDT 23
Finished Oct 15 12:22:03 PM PDT 23
Peak memory 145384 kb
Host smart-61f7c25f-d74e-46d6-87ec-1816180ba000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017102268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2017102268
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.1491381313
Short name T23
Test name
Test status
Simulation time 11561265 ps
CPU time 0.37 seconds
Started Oct 15 12:21:24 PM PDT 23
Finished Oct 15 12:21:25 PM PDT 23
Peak memory 145412 kb
Host smart-682c4c4f-5993-45d6-98ee-943c39280d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491381313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1491381313
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.1242163692
Short name T20
Test name
Test status
Simulation time 11824802 ps
CPU time 0.38 seconds
Started Oct 15 12:21:03 PM PDT 23
Finished Oct 15 12:21:04 PM PDT 23
Peak memory 145348 kb
Host smart-899f6d3c-de06-4baf-9b1c-44cd57810af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242163692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1242163692
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.2560580609
Short name T14
Test name
Test status
Simulation time 11733659 ps
CPU time 0.38 seconds
Started Oct 15 12:21:02 PM PDT 23
Finished Oct 15 12:21:03 PM PDT 23
Peak memory 145148 kb
Host smart-37a40e88-2aa5-4c58-8744-a9587a08d6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560580609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2560580609
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1921202736
Short name T24
Test name
Test status
Simulation time 11118453 ps
CPU time 0.39 seconds
Started Oct 15 12:20:24 PM PDT 23
Finished Oct 15 12:20:25 PM PDT 23
Peak memory 145664 kb
Host smart-5dd353ec-66ad-40c1-b556-5572e743aabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921202736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1921202736
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.1999800462
Short name T10
Test name
Test status
Simulation time 11117497 ps
CPU time 0.39 seconds
Started Oct 15 12:21:14 PM PDT 23
Finished Oct 15 12:21:16 PM PDT 23
Peak memory 145356 kb
Host smart-d3231713-16eb-4657-9f0b-90e9f03ab2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999800462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1999800462
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.791417890
Short name T9
Test name
Test status
Simulation time 12123389 ps
CPU time 0.41 seconds
Started Oct 15 12:22:05 PM PDT 23
Finished Oct 15 12:22:06 PM PDT 23
Peak memory 145664 kb
Host smart-e02e478d-f7f6-4603-b669-cf99f3180b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791417890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.791417890
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2110902623
Short name T1
Test name
Test status
Simulation time 10659692 ps
CPU time 0.38 seconds
Started Oct 15 12:20:49 PM PDT 23
Finished Oct 15 12:20:50 PM PDT 23
Peak memory 145340 kb
Host smart-9d559cbc-b015-40cc-8d8a-81658fc0d358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110902623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2110902623
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2777397660
Short name T26
Test name
Test status
Simulation time 12113479 ps
CPU time 0.44 seconds
Started Oct 15 12:21:01 PM PDT 23
Finished Oct 15 12:21:03 PM PDT 23
Peak memory 144168 kb
Host smart-3bc5bebe-3831-4c8a-8ef6-760b23ec73ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777397660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2777397660
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.1344231451
Short name T47
Test name
Test status
Simulation time 11087632 ps
CPU time 0.38 seconds
Started Oct 15 12:22:12 PM PDT 23
Finished Oct 15 12:22:12 PM PDT 23
Peak memory 145168 kb
Host smart-457a5ed1-da5b-4d7d-894a-a0b92c5fac33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344231451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1344231451
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3279733026
Short name T50
Test name
Test status
Simulation time 29116114 ps
CPU time 0.41 seconds
Started Oct 15 12:15:24 PM PDT 23
Finished Oct 15 12:15:24 PM PDT 23
Peak memory 145712 kb
Host smart-c5fce2ba-7003-4502-8e3c-be51bbef9d80
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3279733026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3279733026
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4018945957
Short name T27
Test name
Test status
Simulation time 27332396 ps
CPU time 0.4 seconds
Started Oct 15 12:15:25 PM PDT 23
Finished Oct 15 12:15:26 PM PDT 23
Peak memory 145652 kb
Host smart-c5961ebc-d07a-43f8-b647-2ce4940bde58
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4018945957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.4018945957
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1267158924
Short name T6
Test name
Test status
Simulation time 29857641 ps
CPU time 0.41 seconds
Started Oct 15 12:15:25 PM PDT 23
Finished Oct 15 12:15:25 PM PDT 23
Peak memory 145652 kb
Host smart-99f2d0b7-3fef-492b-8abc-6f9daa9e3c44
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1267158924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1267158924
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.4250211628
Short name T51
Test name
Test status
Simulation time 29945717 ps
CPU time 0.4 seconds
Started Oct 15 12:15:34 PM PDT 23
Finished Oct 15 12:15:35 PM PDT 23
Peak memory 145588 kb
Host smart-a831ca20-1e1b-4036-93cf-9066a1f1734d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4250211628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.4250211628
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1474492406
Short name T28
Test name
Test status
Simulation time 31787072 ps
CPU time 0.41 seconds
Started Oct 15 12:15:31 PM PDT 23
Finished Oct 15 12:15:32 PM PDT 23
Peak memory 145588 kb
Host smart-e35959b7-b7fb-4598-805f-efd57d35eee6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1474492406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1474492406
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2152799223
Short name T46
Test name
Test status
Simulation time 28935834 ps
CPU time 0.4 seconds
Started Oct 15 12:15:40 PM PDT 23
Finished Oct 15 12:15:41 PM PDT 23
Peak memory 146992 kb
Host smart-b497ebba-e8c0-4b6a-aa7d-1018c49466a2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2152799223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2152799223
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1080954391
Short name T43
Test name
Test status
Simulation time 30738725 ps
CPU time 0.4 seconds
Started Oct 15 12:15:40 PM PDT 23
Finished Oct 15 12:15:41 PM PDT 23
Peak memory 146888 kb
Host smart-fc609633-01b5-4f4a-b353-612f31b2c254
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1080954391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1080954391
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1461155511
Short name T45
Test name
Test status
Simulation time 30423050 ps
CPU time 0.41 seconds
Started Oct 15 12:15:30 PM PDT 23
Finished Oct 15 12:15:31 PM PDT 23
Peak memory 145444 kb
Host smart-0c141f57-8e21-420d-bca7-38cebd177336
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1461155511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1461155511
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2252229543
Short name T54
Test name
Test status
Simulation time 30561552 ps
CPU time 0.41 seconds
Started Oct 15 12:15:24 PM PDT 23
Finished Oct 15 12:15:25 PM PDT 23
Peak memory 145612 kb
Host smart-80c84aad-744c-4176-be20-a72b987d7393
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2252229543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2252229543
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1835910689
Short name T29
Test name
Test status
Simulation time 30760838 ps
CPU time 0.42 seconds
Started Oct 15 12:15:31 PM PDT 23
Finished Oct 15 12:15:32 PM PDT 23
Peak memory 145588 kb
Host smart-0837fc34-396b-4989-835b-671bfa9b511a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1835910689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1835910689
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.891665215
Short name T52
Test name
Test status
Simulation time 29413900 ps
CPU time 0.41 seconds
Started Oct 15 12:15:20 PM PDT 23
Finished Oct 15 12:15:21 PM PDT 23
Peak memory 145724 kb
Host smart-f51abf12-c050-4ad8-a7b4-40747ee50295
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=891665215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.891665215
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2511184186
Short name T55
Test name
Test status
Simulation time 31645338 ps
CPU time 0.41 seconds
Started Oct 15 12:15:24 PM PDT 23
Finished Oct 15 12:15:24 PM PDT 23
Peak memory 145712 kb
Host smart-4d168ec1-b338-4fec-8f53-c7550495b623
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2511184186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2511184186
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1970167990
Short name T48
Test name
Test status
Simulation time 30998015 ps
CPU time 0.41 seconds
Started Oct 15 12:15:30 PM PDT 23
Finished Oct 15 12:15:31 PM PDT 23
Peak memory 145564 kb
Host smart-49bdecc0-6df2-4c80-be59-ff3bcb22a09a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1970167990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1970167990
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1295889528
Short name T4
Test name
Test status
Simulation time 28780668 ps
CPU time 0.4 seconds
Started Oct 15 12:15:19 PM PDT 23
Finished Oct 15 12:15:20 PM PDT 23
Peak memory 145724 kb
Host smart-8767ce82-f30e-4efa-8efc-99de6c84a786
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1295889528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1295889528
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3238686372
Short name T53
Test name
Test status
Simulation time 30479436 ps
CPU time 0.44 seconds
Started Oct 15 12:15:24 PM PDT 23
Finished Oct 15 12:15:24 PM PDT 23
Peak memory 145712 kb
Host smart-42f54884-c374-4544-b358-e09a6e51c54d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3238686372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3238686372
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.457008739
Short name T56
Test name
Test status
Simulation time 30951817 ps
CPU time 0.41 seconds
Started Oct 15 12:15:24 PM PDT 23
Finished Oct 15 12:15:25 PM PDT 23
Peak memory 145432 kb
Host smart-15b89a13-330d-4ed4-a0ed-45d0ff702568
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=457008739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.457008739
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2039721340
Short name T49
Test name
Test status
Simulation time 30127845 ps
CPU time 0.4 seconds
Started Oct 15 12:15:34 PM PDT 23
Finished Oct 15 12:15:35 PM PDT 23
Peak memory 145576 kb
Host smart-a3b57e0a-d91a-4d8a-85bf-995f33261c08
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2039721340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2039721340
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3023599924
Short name T5
Test name
Test status
Simulation time 28031716 ps
CPU time 0.42 seconds
Started Oct 15 12:15:42 PM PDT 23
Finished Oct 15 12:15:43 PM PDT 23
Peak memory 145576 kb
Host smart-deb15ed3-ad06-4a0c-b4dd-fc4a7c370ccc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3023599924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3023599924
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2206711494
Short name T41
Test name
Test status
Simulation time 27763344 ps
CPU time 0.4 seconds
Started Oct 15 12:15:24 PM PDT 23
Finished Oct 15 12:15:24 PM PDT 23
Peak memory 145708 kb
Host smart-2d788ed0-2508-4a55-b086-55d72b5f2713
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2206711494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2206711494
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1685167029
Short name T35
Test name
Test status
Simulation time 9329493 ps
CPU time 0.43 seconds
Started Oct 15 12:19:21 PM PDT 23
Finished Oct 15 12:19:22 PM PDT 23
Peak memory 145112 kb
Host smart-0efdc29d-7e6d-43dc-8719-62b3d1690930
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1685167029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1685167029
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.969082823
Short name T37
Test name
Test status
Simulation time 9430034 ps
CPU time 0.36 seconds
Started Oct 15 12:21:24 PM PDT 23
Finished Oct 15 12:21:25 PM PDT 23
Peak memory 144908 kb
Host smart-90729e3f-a7b8-47d9-a0a6-fd828f5dfade
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=969082823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.969082823
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1898580244
Short name T57
Test name
Test status
Simulation time 8925095 ps
CPU time 0.38 seconds
Started Oct 15 12:19:22 PM PDT 23
Finished Oct 15 12:19:23 PM PDT 23
Peak memory 144804 kb
Host smart-bbd0cb9e-348e-4052-95fd-b2a009f8d9a0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1898580244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1898580244
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.2623862617
Short name T62
Test name
Test status
Simulation time 9311316 ps
CPU time 0.38 seconds
Started Oct 15 12:23:32 PM PDT 23
Finished Oct 15 12:23:43 PM PDT 23
Peak memory 144904 kb
Host smart-0237bd97-6e93-4920-be2d-4e18a1f58519
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2623862617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2623862617
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3790692272
Short name T34
Test name
Test status
Simulation time 9243312 ps
CPU time 0.38 seconds
Started Oct 15 12:19:22 PM PDT 23
Finished Oct 15 12:19:22 PM PDT 23
Peak memory 144768 kb
Host smart-2b1fa040-d442-4a7f-bada-681906a5881a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3790692272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3790692272
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.903899630
Short name T32
Test name
Test status
Simulation time 8343167 ps
CPU time 0.49 seconds
Started Oct 15 12:20:57 PM PDT 23
Finished Oct 15 12:20:58 PM PDT 23
Peak memory 143052 kb
Host smart-0acb0770-778a-4ee7-8db9-6adfdfafd169
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=903899630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.903899630
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.1849775064
Short name T60
Test name
Test status
Simulation time 8859991 ps
CPU time 0.49 seconds
Started Oct 15 12:20:57 PM PDT 23
Finished Oct 15 12:20:58 PM PDT 23
Peak memory 143128 kb
Host smart-66da91de-5d3b-4e9d-bd03-dbc07163936c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1849775064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1849775064
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.1635386701
Short name T30
Test name
Test status
Simulation time 8656791 ps
CPU time 0.38 seconds
Started Oct 15 12:23:18 PM PDT 23
Finished Oct 15 12:23:19 PM PDT 23
Peak memory 144904 kb
Host smart-bd2d5e2d-5215-4209-8928-d69422ecab88
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1635386701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1635386701
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3118677008
Short name T58
Test name
Test status
Simulation time 8909359 ps
CPU time 0.38 seconds
Started Oct 15 12:23:03 PM PDT 23
Finished Oct 15 12:23:09 PM PDT 23
Peak memory 144352 kb
Host smart-fe4c8208-c7b0-49a8-8500-d7724711c851
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3118677008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3118677008
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.666751809
Short name T36
Test name
Test status
Simulation time 8750120 ps
CPU time 0.37 seconds
Started Oct 15 12:21:11 PM PDT 23
Finished Oct 15 12:21:12 PM PDT 23
Peak memory 144920 kb
Host smart-f145c511-f9a4-4390-99fb-6a4f5bf52e3d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=666751809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.666751809
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.1827105968
Short name T18
Test name
Test status
Simulation time 9956959 ps
CPU time 0.5 seconds
Started Oct 15 12:20:57 PM PDT 23
Finished Oct 15 12:20:58 PM PDT 23
Peak memory 142876 kb
Host smart-0e03578f-7272-48f2-bf1e-a6e3f11dd5bf
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1827105968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1827105968
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3596727156
Short name T19
Test name
Test status
Simulation time 10478124 ps
CPU time 0.39 seconds
Started Oct 15 12:22:49 PM PDT 23
Finished Oct 15 12:22:49 PM PDT 23
Peak memory 144860 kb
Host smart-298d2486-8f4d-41e8-9d12-619793960a55
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3596727156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3596727156
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.2039520700
Short name T31
Test name
Test status
Simulation time 8537545 ps
CPU time 0.37 seconds
Started Oct 15 12:19:22 PM PDT 23
Finished Oct 15 12:19:23 PM PDT 23
Peak memory 144804 kb
Host smart-3f7c9b0b-7ae7-4fa5-93b4-6f86862132e9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2039520700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2039520700
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.3920815332
Short name T39
Test name
Test status
Simulation time 9318714 ps
CPU time 0.42 seconds
Started Oct 15 12:21:09 PM PDT 23
Finished Oct 15 12:21:10 PM PDT 23
Peak memory 144512 kb
Host smart-3ec3586a-217e-4849-8791-081291c41d41
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3920815332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3920815332
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3049916577
Short name T61
Test name
Test status
Simulation time 9426984 ps
CPU time 0.55 seconds
Started Oct 15 12:20:57 PM PDT 23
Finished Oct 15 12:20:58 PM PDT 23
Peak memory 143884 kb
Host smart-30e0aeab-3795-42a1-bb95-ee5fcf4026ef
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3049916577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3049916577
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.3321585739
Short name T63
Test name
Test status
Simulation time 9324284 ps
CPU time 0.38 seconds
Started Oct 15 12:19:34 PM PDT 23
Finished Oct 15 12:19:35 PM PDT 23
Peak memory 145100 kb
Host smart-7865de79-e20d-473b-8771-fbefd2b5883c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3321585739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3321585739
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.997055827
Short name T40
Test name
Test status
Simulation time 9049824 ps
CPU time 0.4 seconds
Started Oct 15 12:23:03 PM PDT 23
Finished Oct 15 12:23:04 PM PDT 23
Peak memory 144756 kb
Host smart-0d9eba17-cbd1-41d6-8ee6-47ea975f0b99
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=997055827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.997055827
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3203280713
Short name T38
Test name
Test status
Simulation time 9256063 ps
CPU time 0.36 seconds
Started Oct 15 12:23:03 PM PDT 23
Finished Oct 15 12:23:04 PM PDT 23
Peak memory 144764 kb
Host smart-b790014b-8f5f-468a-bee6-eae6665584ae
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3203280713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3203280713
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2868201265
Short name T59
Test name
Test status
Simulation time 9786021 ps
CPU time 0.54 seconds
Started Oct 15 12:20:59 PM PDT 23
Finished Oct 15 12:21:00 PM PDT 23
Peak memory 143428 kb
Host smart-8ad9d551-2a96-40ed-9699-1412a6be8f1e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2868201265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2868201265
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1780156981
Short name T65
Test name
Test status
Simulation time 26262825 ps
CPU time 0.38 seconds
Started Oct 15 12:23:00 PM PDT 23
Finished Oct 15 12:23:01 PM PDT 23
Peak memory 144896 kb
Host smart-97e9cde9-5df4-48bd-af7e-edc0bef98f80
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1780156981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1780156981
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.4006950538
Short name T72
Test name
Test status
Simulation time 25912311 ps
CPU time 0.42 seconds
Started Oct 15 12:23:21 PM PDT 23
Finished Oct 15 12:23:22 PM PDT 23
Peak memory 144916 kb
Host smart-f7896b09-86d1-4d81-8793-ec9efaa4656f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4006950538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.4006950538
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1937914213
Short name T64
Test name
Test status
Simulation time 28292914 ps
CPU time 0.43 seconds
Started Oct 15 12:21:49 PM PDT 23
Finished Oct 15 12:21:50 PM PDT 23
Peak memory 144912 kb
Host smart-98e1d22a-8a58-48b8-b540-dbe72775d101
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1937914213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1937914213
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2925658864
Short name T66
Test name
Test status
Simulation time 27010641 ps
CPU time 0.38 seconds
Started Oct 15 12:21:01 PM PDT 23
Finished Oct 15 12:21:02 PM PDT 23
Peak memory 145008 kb
Host smart-47dd15ae-766c-451e-a5be-7b00b7b1fc84
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2925658864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2925658864
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2795308510
Short name T68
Test name
Test status
Simulation time 26348479 ps
CPU time 0.4 seconds
Started Oct 15 12:21:23 PM PDT 23
Finished Oct 15 12:21:24 PM PDT 23
Peak memory 144912 kb
Host smart-de13bed2-e199-4bae-be26-3c385ce35bf8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2795308510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2795308510
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2890881018
Short name T77
Test name
Test status
Simulation time 26190460 ps
CPU time 0.38 seconds
Started Oct 15 12:22:37 PM PDT 23
Finished Oct 15 12:22:38 PM PDT 23
Peak memory 144884 kb
Host smart-37b71db6-cc96-4c54-a4fd-1ab6664b98c0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2890881018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2890881018
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3536860851
Short name T73
Test name
Test status
Simulation time 26937716 ps
CPU time 0.39 seconds
Started Oct 15 12:21:49 PM PDT 23
Finished Oct 15 12:21:50 PM PDT 23
Peak memory 144832 kb
Host smart-de06599d-3b11-42ba-98dd-7e8767aa089f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3536860851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3536860851
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1288417312
Short name T78
Test name
Test status
Simulation time 27319005 ps
CPU time 0.38 seconds
Started Oct 15 12:21:01 PM PDT 23
Finished Oct 15 12:21:02 PM PDT 23
Peak memory 145528 kb
Host smart-b198c109-ab8e-4c50-81ed-635799a5f640
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1288417312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1288417312
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1543902777
Short name T75
Test name
Test status
Simulation time 28318159 ps
CPU time 0.42 seconds
Started Oct 15 12:21:00 PM PDT 23
Finished Oct 15 12:21:02 PM PDT 23
Peak memory 145112 kb
Host smart-00dc7faf-208c-4fc6-81e8-42a0fff008d7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1543902777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1543902777
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.555360978
Short name T67
Test name
Test status
Simulation time 27835498 ps
CPU time 0.38 seconds
Started Oct 15 12:23:29 PM PDT 23
Finished Oct 15 12:23:30 PM PDT 23
Peak memory 144952 kb
Host smart-e2dfce25-d05f-406d-bbaa-ec8ed359b740
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=555360978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.555360978
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.657165437
Short name T70
Test name
Test status
Simulation time 27291742 ps
CPU time 0.38 seconds
Started Oct 15 12:22:26 PM PDT 23
Finished Oct 15 12:22:27 PM PDT 23
Peak memory 144848 kb
Host smart-284bf488-ccc0-4a9e-ab4a-d14e97e657d5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=657165437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.657165437
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4036277103
Short name T71
Test name
Test status
Simulation time 27593704 ps
CPU time 0.39 seconds
Started Oct 15 12:23:06 PM PDT 23
Finished Oct 15 12:23:07 PM PDT 23
Peak memory 144936 kb
Host smart-922cd80e-5576-4815-bfb8-f062968aa5e0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4036277103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.4036277103
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1535562952
Short name T80
Test name
Test status
Simulation time 29015600 ps
CPU time 0.5 seconds
Started Oct 15 12:20:57 PM PDT 23
Finished Oct 15 12:20:58 PM PDT 23
Peak memory 143488 kb
Host smart-e95f7353-f883-4154-9cdf-eca2a3aa0ac7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1535562952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1535562952
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3708858307
Short name T79
Test name
Test status
Simulation time 26974827 ps
CPU time 0.39 seconds
Started Oct 15 12:23:19 PM PDT 23
Finished Oct 15 12:23:20 PM PDT 23
Peak memory 144920 kb
Host smart-0d3e761b-96e8-4fbd-b1f7-6b15d10ec288
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3708858307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3708858307
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.279848077
Short name T76
Test name
Test status
Simulation time 27587536 ps
CPU time 0.38 seconds
Started Oct 15 12:21:11 PM PDT 23
Finished Oct 15 12:21:11 PM PDT 23
Peak memory 144784 kb
Host smart-6c8dd73a-b957-4293-80a3-246ba09eae62
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=279848077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.279848077
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3454510414
Short name T69
Test name
Test status
Simulation time 28171671 ps
CPU time 0.45 seconds
Started Oct 15 12:21:00 PM PDT 23
Finished Oct 15 12:21:02 PM PDT 23
Peak memory 144852 kb
Host smart-82d868a8-a17a-4a92-9a11-236be8e1bd74
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3454510414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3454510414
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1525582850
Short name T11
Test name
Test status
Simulation time 26330634 ps
CPU time 0.39 seconds
Started Oct 15 12:21:01 PM PDT 23
Finished Oct 15 12:21:02 PM PDT 23
Peak memory 144892 kb
Host smart-814da809-0fc2-4a00-9408-ccaa2995d502
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1525582850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1525582850
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3275089272
Short name T13
Test name
Test status
Simulation time 27747219 ps
CPU time 0.4 seconds
Started Oct 15 12:19:17 PM PDT 23
Finished Oct 15 12:19:18 PM PDT 23
Peak memory 145052 kb
Host smart-0a110406-123e-4bcc-b442-ca15b98e8c4f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3275089272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3275089272
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3290971835
Short name T74
Test name
Test status
Simulation time 28065599 ps
CPU time 0.4 seconds
Started Oct 15 12:18:56 PM PDT 23
Finished Oct 15 12:18:57 PM PDT 23
Peak memory 144828 kb
Host smart-c28d2840-58bc-42f5-b6a8-b44f295d65b1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3290971835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3290971835
Directory /workspace/9.prim_sync_fatal_alert/latest
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