| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.96 | 100.00 | 93.75 | 100.00 | 82.14 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.29 | 86.29 | 100.00 | 100.00 | 93.75 | 93.75 | 96.43 | 96.43 | 64.29 | 64.29 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/0.prim_async_alert.76435722518841616854543764961134425703988822825334098592367000951906972919132 |
| 90.01 | 3.72 | 100.00 | 0.00 | 93.75 | 0.00 | 96.43 | 0.00 | 75.00 | 10.71 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/1.prim_sync_alert.32204789835237964356144020456961394680358822332275190909782637614015062935461 |
| 92.96 | 2.95 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 3.57 | 82.14 | 7.14 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.42576029488084238759307107603653728922179484705634673135290099686177877817984 |
| Name |
|---|
| /workspace/coverage/default/1.prim_async_alert.43692980823624849590753163608776838404710623059590503197453808505051501405957 |
| /workspace/coverage/default/10.prim_async_alert.98000261823085687319008790204430702435519076990290045166402572871350628909717 |
| /workspace/coverage/default/11.prim_async_alert.93262685508039052870419247923056425814738550441900286888186075310954198159669 |
| /workspace/coverage/default/12.prim_async_alert.98997704505187434034425999058282704714002950951543360282492954588220467550397 |
| /workspace/coverage/default/13.prim_async_alert.35549341587506930809882862469943291629998538281828430145945535025208552194196 |
| /workspace/coverage/default/14.prim_async_alert.101820061268007789755171010125955966263408115445386283062472865891743511829516 |
| /workspace/coverage/default/15.prim_async_alert.580198667302621781107546739143441635375229249659542324376655453316942612433 |
| /workspace/coverage/default/16.prim_async_alert.2558414606919219575829264877126478857441441796918663853733760520164654355573 |
| /workspace/coverage/default/17.prim_async_alert.30363629943315995963556587753489063838998372698610387375391450883945807459717 |
| /workspace/coverage/default/18.prim_async_alert.2545098692588448981841615929570468447709840104609367887872080112889238251214 |
| /workspace/coverage/default/19.prim_async_alert.46594164082165955788405151336361079119916444724554537989660835286886221434296 |
| /workspace/coverage/default/2.prim_async_alert.81818935521592498299377705102109805966260175029306066093008743630564690976709 |
| /workspace/coverage/default/3.prim_async_alert.6120812414405184552241014009883045612130269087615735927664560555919103251802 |
| /workspace/coverage/default/4.prim_async_alert.29418250262722959615974444056151960548638974583951069843617370231242770110726 |
| /workspace/coverage/default/5.prim_async_alert.112814746871829123171699109183430055407356389803898187429339966891844250416244 |
| /workspace/coverage/default/6.prim_async_alert.68044568610425783475006078066884772983493553731077341514820352937764569350714 |
| /workspace/coverage/default/7.prim_async_alert.81635402413749829700849724830641161868088822606235499542378384987049478593915 |
| /workspace/coverage/default/8.prim_async_alert.25239214604347309048952867147182557731182523711646075502047151752617767506613 |
| /workspace/coverage/default/9.prim_async_alert.71826001359875991272133431508400670008674937936843278663173570822119977771423 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.16769186589863869521212156681536511778571462100436129090563906354811312911405 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.21548313525577088012335442216128410322760876621005947105851209763293964394757 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1508283067895191546144533412342084725933135995839758866065094324876299558155 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.6862455671003617840903638514529408278219422852795833027599257044275204922711 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.97385676803083570192001098468316599841456255989573669520383502490724385979594 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.63149245992494352459413060817089449440885530942817161019454908949041483922224 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.45528374919880120708605320225592726144661078322394974295466303834411141940154 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.92672498810485462343987519550711040447545754125655327807896856330871149984323 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.33781561021252387847686941598913877514479109952063889475153716119096236487355 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.84653614187125092859964220791096509693328848736135605829752153785123053714911 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.12189816388292710222533349837396572659465023569354147377821357985298977691697 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.110332035229050157389245663418646694214826928408298762581601323849587489607002 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.42730104559886420899535165057780022430554423855276136323180190313272162249142 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.65645052562003354036136238769310909911672139282342498597275485361064356727645 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.115064727087048887431930923084434958295758359288629889166140728438556849229192 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.101128161930255653084180640745013101165310907981380720011536036730520347745857 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.62275321088896663007616017360186839668989276155898067378953315142483058808597 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.70562344573421236281150431612528478490655563739622080964958872277077387354861 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.53006446116526749363007045385488201052200629531962955376164605120235462489982 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.27361767513857197636828745972873502614889563806966745881640053782541189852561 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.36464659150671199225379281951216645527686789587162545370380466314816183546857 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.68861710098911349038504034612517158395550734799699252588252286456475061875351 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.115260814734828993964301017841109136280062031144792036249883927401094682949880 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.3690795694697413259559252601218437963961749456862919637990857136567957768968 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.102707751280740056851552819139819513517157079147192751872021884619040125569339 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.982339519067005419274678793849234484623448792948613308997554917295941605817 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.109434604158533431241530691887820892503762080586602095710428088640649947017813 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.39572436563680109771940306683335873620712632822936257777891263860929671148362 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.35429761464286601210715854764496333952251528406689867073515616059493611642139 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.934768502883149983434715253483129895540153267270084452825699549813089981 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.96797087516452664678876217530650485125468148931461117072265656014530243630730 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.46380390636101413665298368983610467091298159968518546275837679859894844021941 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.70219233900635455674618345719519780079244926405982397901763640383272006133481 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.75039402986986695257145806318839515715668735670584877394768621978284489473231 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.45911048201807709331560860858624884929814043618826448362213871428049748419310 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.12698806522672853867496129460426025389085231241924521626092673019265825089519 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.60213587947589614006711529713410254501819469397521118115432676414915420486967 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.22761099426674127402983793429339139857791257678352247218741007818110912045623 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.53859229405170938978252791075822875780360932967155223036489497252065434948854 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.102772469185254332455938975011495319617321310545770269901148737774590551879152 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.100609380750360750841515695119767743510297182278481515761209158516554100670621 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.40164883703707162521584770725893913575086044399922494856185576367536416001643 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.80616729996268906397883868161338400879314809077624815164088496305323689973106 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.106125662804572019582261029215660257680472063909029423722450171457933869166681 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.20420235689379743814148103920634837858071240036324354113957422713560074900577 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.86975356666949566595058684098788187150657889569450325289333202838252994617285 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.72822545635936545390303976321667704912688635064405889039476633294883874180224 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.114469355257005053828728049336533067821054110741896578116093250948767340607526 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.36608228106812193029682941605136008372656856199686176783233815226308216930770 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.89869132565464636274115651259233637785051259920133021600445388948096231494659 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.27908936427133835611999517881699326670219069971433464302577171651906887441851 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.13764044464206033610311579864185008059206568985363933951676295859429863183861 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.11827128577570407072611770585352561141361261498707144588076820103285405472735 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.69443217261977813067443091571186876063334966838362119051014112402958443982732 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.25460841178376776761669891988763464080658473778650630293942510506878301996807 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.48382621214679157158949242900451422417773897954231911545047474424463434563864 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.112539102199883886944983668190999597169795102350874489386435497750802577671485 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.35546612713760032042505813168077955924007752723571801103047932110025326281032 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/9.prim_async_alert.71826001359875991272133431508400670008674937936843278663173570822119977771423 | Nov 01 12:26:00 PM PDT 23 | Nov 01 12:26:02 PM PDT 23 | 11469183 ps | ||
| T2 | /workspace/coverage/default/14.prim_async_alert.101820061268007789755171010125955966263408115445386283062472865891743511829516 | Nov 01 12:18:34 PM PDT 23 | Nov 01 12:18:35 PM PDT 23 | 11469183 ps | ||
| T3 | /workspace/coverage/default/11.prim_async_alert.93262685508039052870419247923056425814738550441900286888186075310954198159669 | Nov 01 12:26:15 PM PDT 23 | Nov 01 12:26:17 PM PDT 23 | 11469183 ps | ||
| T10 | /workspace/coverage/default/1.prim_async_alert.43692980823624849590753163608776838404710623059590503197453808505051501405957 | Nov 01 12:20:24 PM PDT 23 | Nov 01 12:20:25 PM PDT 23 | 11469183 ps | ||
| T11 | /workspace/coverage/default/4.prim_async_alert.29418250262722959615974444056151960548638974583951069843617370231242770110726 | Nov 01 12:26:15 PM PDT 23 | Nov 01 12:26:17 PM PDT 23 | 11469183 ps | ||
| T12 | /workspace/coverage/default/7.prim_async_alert.81635402413749829700849724830641161868088822606235499542378384987049478593915 | Nov 01 12:24:00 PM PDT 23 | Nov 01 12:24:02 PM PDT 23 | 11469183 ps | ||
| T13 | /workspace/coverage/default/2.prim_async_alert.81818935521592498299377705102109805966260175029306066093008743630564690976709 | Nov 01 12:24:07 PM PDT 23 | Nov 01 12:24:11 PM PDT 23 | 11469183 ps | ||
| T14 | /workspace/coverage/default/0.prim_async_alert.76435722518841616854543764961134425703988822825334098592367000951906972919132 | Nov 01 12:21:08 PM PDT 23 | Nov 01 12:21:09 PM PDT 23 | 11469183 ps | ||
| T15 | /workspace/coverage/default/8.prim_async_alert.25239214604347309048952867147182557731182523711646075502047151752617767506613 | Nov 01 12:18:18 PM PDT 23 | Nov 01 12:18:19 PM PDT 23 | 11469183 ps | ||
| T16 | /workspace/coverage/default/15.prim_async_alert.580198667302621781107546739143441635375229249659542324376655453316942612433 | Nov 01 12:24:00 PM PDT 23 | Nov 01 12:24:02 PM PDT 23 | 11469183 ps | ||
| T31 | /workspace/coverage/default/16.prim_async_alert.2558414606919219575829264877126478857441441796918663853733760520164654355573 | Nov 01 12:24:14 PM PDT 23 | Nov 01 12:24:26 PM PDT 23 | 11469183 ps | ||
| T32 | /workspace/coverage/default/6.prim_async_alert.68044568610425783475006078066884772983493553731077341514820352937764569350714 | Nov 01 12:18:16 PM PDT 23 | Nov 01 12:18:18 PM PDT 23 | 11469183 ps | ||
| T33 | /workspace/coverage/default/17.prim_async_alert.30363629943315995963556587753489063838998372698610387375391450883945807459717 | Nov 01 12:24:19 PM PDT 23 | Nov 01 12:24:30 PM PDT 23 | 11469183 ps | ||
| T34 | /workspace/coverage/default/13.prim_async_alert.35549341587506930809882862469943291629998538281828430145945535025208552194196 | Nov 01 12:24:18 PM PDT 23 | Nov 01 12:24:27 PM PDT 23 | 11469183 ps | ||
| T35 | /workspace/coverage/default/5.prim_async_alert.112814746871829123171699109183430055407356389803898187429339966891844250416244 | Nov 01 12:25:58 PM PDT 23 | Nov 01 12:26:00 PM PDT 23 | 11469183 ps | ||
| T36 | /workspace/coverage/default/12.prim_async_alert.98997704505187434034425999058282704714002950951543360282492954588220467550397 | Nov 01 12:18:39 PM PDT 23 | Nov 01 12:18:40 PM PDT 23 | 11469183 ps | ||
| T37 | /workspace/coverage/default/18.prim_async_alert.2545098692588448981841615929570468447709840104609367887872080112889238251214 | Nov 01 12:24:15 PM PDT 23 | Nov 01 12:24:26 PM PDT 23 | 11469183 ps | ||
| T38 | /workspace/coverage/default/19.prim_async_alert.46594164082165955788405151336361079119916444724554537989660835286886221434296 | Nov 01 12:22:05 PM PDT 23 | Nov 01 12:22:06 PM PDT 23 | 11469183 ps | ||
| T39 | /workspace/coverage/default/10.prim_async_alert.98000261823085687319008790204430702435519076990290045166402572871350628909717 | Nov 01 12:18:41 PM PDT 23 | Nov 01 12:18:43 PM PDT 23 | 11469183 ps | ||
| T40 | /workspace/coverage/default/3.prim_async_alert.6120812414405184552241014009883045612130269087615735927664560555919103251802 | Nov 01 12:19:24 PM PDT 23 | Nov 01 12:19:25 PM PDT 23 | 11469183 ps | ||
| T4 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.42576029488084238759307107603653728922179484705634673135290099686177877817984 | Nov 01 12:24:17 PM PDT 23 | Nov 01 12:24:27 PM PDT 23 | 30019183 ps | ||
| T5 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.62275321088896663007616017360186839668989276155898067378953315142483058808597 | Nov 01 12:20:29 PM PDT 23 | Nov 01 12:20:30 PM PDT 23 | 30019183 ps | ||
| T6 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.6862455671003617840903638514529408278219422852795833027599257044275204922711 | Nov 01 12:24:25 PM PDT 23 | Nov 01 12:24:36 PM PDT 23 | 30019183 ps | ||
| T24 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.101128161930255653084180640745013101165310907981380720011536036730520347745857 | Nov 01 12:24:21 PM PDT 23 | Nov 01 12:24:33 PM PDT 23 | 30019183 ps | ||
| T25 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.12189816388292710222533349837396572659465023569354147377821357985298977691697 | Nov 01 12:24:16 PM PDT 23 | Nov 01 12:24:29 PM PDT 23 | 30019183 ps | ||
| T26 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.110332035229050157389245663418646694214826928408298762581601323849587489607002 | Nov 01 12:21:18 PM PDT 23 | Nov 01 12:21:19 PM PDT 23 | 30019183 ps | ||
| T27 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.21548313525577088012335442216128410322760876621005947105851209763293964394757 | Nov 01 12:24:25 PM PDT 23 | Nov 01 12:24:36 PM PDT 23 | 30019183 ps | ||
| T28 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.33781561021252387847686941598913877514479109952063889475153716119096236487355 | Nov 01 12:18:34 PM PDT 23 | Nov 01 12:18:35 PM PDT 23 | 30019183 ps | ||
| T29 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.65645052562003354036136238769310909911672139282342498597275485361064356727645 | Nov 01 12:24:23 PM PDT 23 | Nov 01 12:24:35 PM PDT 23 | 30019183 ps | ||
| T30 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.16769186589863869521212156681536511778571462100436129090563906354811312911405 | Nov 01 12:27:03 PM PDT 23 | Nov 01 12:27:04 PM PDT 23 | 30019183 ps | ||
| T41 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.45528374919880120708605320225592726144661078322394974295466303834411141940154 | Nov 01 12:26:46 PM PDT 23 | Nov 01 12:26:49 PM PDT 23 | 30019183 ps | ||
| T42 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.115064727087048887431930923084434958295758359288629889166140728438556849229192 | Nov 01 12:24:20 PM PDT 23 | Nov 01 12:24:33 PM PDT 23 | 30019183 ps | ||
| T43 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.53006446116526749363007045385488201052200629531962955376164605120235462489982 | Nov 01 12:24:20 PM PDT 23 | Nov 01 12:24:32 PM PDT 23 | 30019183 ps | ||
| T44 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1508283067895191546144533412342084725933135995839758866065094324876299558155 | Nov 01 12:24:16 PM PDT 23 | Nov 01 12:24:29 PM PDT 23 | 30019183 ps | ||
| T45 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.63149245992494352459413060817089449440885530942817161019454908949041483922224 | Nov 01 12:26:39 PM PDT 23 | Nov 01 12:26:41 PM PDT 23 | 30019183 ps | ||
| T46 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.70562344573421236281150431612528478490655563739622080964958872277077387354861 | Nov 01 12:18:41 PM PDT 23 | Nov 01 12:18:42 PM PDT 23 | 30019183 ps | ||
| T47 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.92672498810485462343987519550711040447545754125655327807896856330871149984323 | Nov 01 12:24:28 PM PDT 23 | Nov 01 12:24:37 PM PDT 23 | 30019183 ps | ||
| T48 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.84653614187125092859964220791096509693328848736135605829752153785123053714911 | Nov 01 12:24:06 PM PDT 23 | Nov 01 12:24:08 PM PDT 23 | 30019183 ps | ||
| T49 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.42730104559886420899535165057780022430554423855276136323180190313272162249142 | Nov 01 12:24:19 PM PDT 23 | Nov 01 12:24:31 PM PDT 23 | 30019183 ps | ||
| T50 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.97385676803083570192001098468316599841456255989573669520383502490724385979594 | Nov 01 12:18:39 PM PDT 23 | Nov 01 12:18:41 PM PDT 23 | 30019183 ps | ||
| T7 | /workspace/coverage/sync_alert/3.prim_sync_alert.46380390636101413665298368983610467091298159968518546275837679859894844021941 | Nov 01 01:14:14 PM PDT 23 | Nov 01 01:14:15 PM PDT 23 | 9009183 ps | ||
| T8 | /workspace/coverage/sync_alert/8.prim_sync_alert.60213587947589614006711529713410254501819469397521118115432676414915420486967 | Nov 01 01:14:30 PM PDT 23 | Nov 01 01:14:31 PM PDT 23 | 9009183 ps | ||
| T9 | /workspace/coverage/sync_alert/1.prim_sync_alert.32204789835237964356144020456961394680358822332275190909782637614015062935461 | Nov 01 01:14:27 PM PDT 23 | Nov 01 01:14:29 PM PDT 23 | 9009183 ps | ||
| T17 | /workspace/coverage/sync_alert/6.prim_sync_alert.45911048201807709331560860858624884929814043618826448362213871428049748419310 | Nov 01 01:14:26 PM PDT 23 | Nov 01 01:14:28 PM PDT 23 | 9009183 ps | ||
| T18 | /workspace/coverage/sync_alert/17.prim_sync_alert.39572436563680109771940306683335873620712632822936257777891263860929671148362 | Nov 01 01:14:24 PM PDT 23 | Nov 01 01:14:25 PM PDT 23 | 9009183 ps | ||
| T19 | /workspace/coverage/sync_alert/13.prim_sync_alert.3690795694697413259559252601218437963961749456862919637990857136567957768968 | Nov 01 01:14:32 PM PDT 23 | Nov 01 01:14:35 PM PDT 23 | 9009183 ps | ||
| T20 | /workspace/coverage/sync_alert/14.prim_sync_alert.102707751280740056851552819139819513517157079147192751872021884619040125569339 | Nov 01 01:14:23 PM PDT 23 | Nov 01 01:14:24 PM PDT 23 | 9009183 ps | ||
| T21 | /workspace/coverage/sync_alert/7.prim_sync_alert.12698806522672853867496129460426025389085231241924521626092673019265825089519 | Nov 01 01:14:33 PM PDT 23 | Nov 01 01:14:35 PM PDT 23 | 9009183 ps | ||
| T22 | /workspace/coverage/sync_alert/12.prim_sync_alert.115260814734828993964301017841109136280062031144792036249883927401094682949880 | Nov 01 01:14:17 PM PDT 23 | Nov 01 01:14:19 PM PDT 23 | 9009183 ps | ||
| T23 | /workspace/coverage/sync_alert/10.prim_sync_alert.36464659150671199225379281951216645527686789587162545370380466314816183546857 | Nov 01 01:14:25 PM PDT 23 | Nov 01 01:14:27 PM PDT 23 | 9009183 ps | ||
| T51 | /workspace/coverage/sync_alert/0.prim_sync_alert.27361767513857197636828745972873502614889563806966745881640053782541189852561 | Nov 01 01:14:26 PM PDT 23 | Nov 01 01:14:28 PM PDT 23 | 9009183 ps | ||
| T52 | /workspace/coverage/sync_alert/5.prim_sync_alert.75039402986986695257145806318839515715668735670584877394768621978284489473231 | Nov 01 01:14:26 PM PDT 23 | Nov 01 01:14:28 PM PDT 23 | 9009183 ps | ||
| T53 | /workspace/coverage/sync_alert/16.prim_sync_alert.109434604158533431241530691887820892503762080586602095710428088640649947017813 | Nov 01 01:14:33 PM PDT 23 | Nov 01 01:14:35 PM PDT 23 | 9009183 ps | ||
| T54 | /workspace/coverage/sync_alert/19.prim_sync_alert.934768502883149983434715253483129895540153267270084452825699549813089981 | Nov 01 01:14:16 PM PDT 23 | Nov 01 01:14:17 PM PDT 23 | 9009183 ps | ||
| T55 | /workspace/coverage/sync_alert/11.prim_sync_alert.68861710098911349038504034612517158395550734799699252588252286456475061875351 | Nov 01 01:14:28 PM PDT 23 | Nov 01 01:14:30 PM PDT 23 | 9009183 ps | ||
| T56 | /workspace/coverage/sync_alert/2.prim_sync_alert.96797087516452664678876217530650485125468148931461117072265656014530243630730 | Nov 01 01:14:25 PM PDT 23 | Nov 01 01:14:26 PM PDT 23 | 9009183 ps | ||
| T57 | /workspace/coverage/sync_alert/4.prim_sync_alert.70219233900635455674618345719519780079244926405982397901763640383272006133481 | Nov 01 01:14:33 PM PDT 23 | Nov 01 01:14:35 PM PDT 23 | 9009183 ps | ||
| T58 | /workspace/coverage/sync_alert/18.prim_sync_alert.35429761464286601210715854764496333952251528406689867073515616059493611642139 | Nov 01 01:14:16 PM PDT 23 | Nov 01 01:14:17 PM PDT 23 | 9009183 ps | ||
| T59 | /workspace/coverage/sync_alert/9.prim_sync_alert.22761099426674127402983793429339139857791257678352247218741007818110912045623 | Nov 01 01:14:26 PM PDT 23 | Nov 01 01:14:28 PM PDT 23 | 9009183 ps | ||
| T60 | /workspace/coverage/sync_alert/15.prim_sync_alert.982339519067005419274678793849234484623448792948613308997554917295941605817 | Nov 01 01:14:25 PM PDT 23 | Nov 01 01:14:26 PM PDT 23 | 9009183 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.13764044464206033610311579864185008059206568985363933951676295859429863183861 | Nov 01 12:17:45 PM PDT 23 | Nov 01 12:17:46 PM PDT 23 | 26839183 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.72822545635936545390303976321667704912688635064405889039476633294883874180224 | Nov 01 12:18:02 PM PDT 23 | Nov 01 12:18:06 PM PDT 23 | 26839183 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.40164883703707162521584770725893913575086044399922494856185576367536416001643 | Nov 01 12:18:41 PM PDT 23 | Nov 01 12:18:42 PM PDT 23 | 26839183 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.69443217261977813067443091571186876063334966838362119051014112402958443982732 | Nov 01 12:17:53 PM PDT 23 | Nov 01 12:17:55 PM PDT 23 | 26839183 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.35546612713760032042505813168077955924007752723571801103047932110025326281032 | Nov 01 12:17:59 PM PDT 23 | Nov 01 12:18:05 PM PDT 23 | 26839183 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.106125662804572019582261029215660257680472063909029423722450171457933869166681 | Nov 01 12:17:43 PM PDT 23 | Nov 01 12:17:45 PM PDT 23 | 26839183 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.100609380750360750841515695119767743510297182278481515761209158516554100670621 | Nov 01 12:17:59 PM PDT 23 | Nov 01 12:18:05 PM PDT 23 | 26839183 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.11827128577570407072611770585352561141361261498707144588076820103285405472735 | Nov 01 12:17:48 PM PDT 23 | Nov 01 12:17:49 PM PDT 23 | 26839183 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.27908936427133835611999517881699326670219069971433464302577171651906887441851 | Nov 01 12:18:02 PM PDT 23 | Nov 01 12:18:06 PM PDT 23 | 26839183 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.36608228106812193029682941605136008372656856199686176783233815226308216930770 | Nov 01 12:17:57 PM PDT 23 | Nov 01 12:18:03 PM PDT 23 | 26839183 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.102772469185254332455938975011495319617321310545770269901148737774590551879152 | Nov 01 12:17:59 PM PDT 23 | Nov 01 12:18:05 PM PDT 23 | 26839183 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.89869132565464636274115651259233637785051259920133021600445388948096231494659 | Nov 01 12:17:57 PM PDT 23 | Nov 01 12:18:03 PM PDT 23 | 26839183 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.48382621214679157158949242900451422417773897954231911545047474424463434563864 | Nov 01 12:17:53 PM PDT 23 | Nov 01 12:17:55 PM PDT 23 | 26839183 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.80616729996268906397883868161338400879314809077624815164088496305323689973106 | Nov 01 12:18:00 PM PDT 23 | Nov 01 12:18:05 PM PDT 23 | 26839183 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.114469355257005053828728049336533067821054110741896578116093250948767340607526 | Nov 01 12:17:52 PM PDT 23 | Nov 01 12:17:53 PM PDT 23 | 26839183 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.112539102199883886944983668190999597169795102350874489386435497750802577671485 | Nov 01 12:17:48 PM PDT 23 | Nov 01 12:17:49 PM PDT 23 | 26839183 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.53859229405170938978252791075822875780360932967155223036489497252065434948854 | Nov 01 12:17:59 PM PDT 23 | Nov 01 12:18:05 PM PDT 23 | 26839183 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.20420235689379743814148103920634837858071240036324354113957422713560074900577 | Nov 01 12:17:52 PM PDT 23 | Nov 01 12:17:53 PM PDT 23 | 26839183 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.86975356666949566595058684098788187150657889569450325289333202838252994617285 | Nov 01 12:17:59 PM PDT 23 | Nov 01 12:18:05 PM PDT 23 | 26839183 ps | ||
| T80 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.25460841178376776761669891988763464080658473778650630293942510506878301996807 | Nov 01 12:17:52 PM PDT 23 | Nov 01 12:17:53 PM PDT 23 | 26839183 ps |
| Test location | /workspace/coverage/default/0.prim_async_alert.76435722518841616854543764961134425703988822825334098592367000951906972919132 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.42 seconds |
| Started | Nov 01 12:21:08 PM PDT 23 |
| Finished | Nov 01 12:21:09 PM PDT 23 |
| Peak memory | 145316 kb |
| Host | smart-1a27d305-94b1-44d8-8586-52b9581f753f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=76435722518841616854543764961134425703988822825334098592367000951906972919132 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.7643572 2518841616854543764961134425703988822825334098592367000951906972919132 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.32204789835237964356144020456961394680358822332275190909782637614015062935461 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.37 seconds |
| Started | Nov 01 01:14:27 PM PDT 23 |
| Finished | Nov 01 01:14:29 PM PDT 23 |
| Peak memory | 145084 kb |
| Host | smart-69b467b0-f254-4a0d-a7d5-9ced32035622 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=32204789835237964356144020456961394680358822332275190909782637614015062935461 -assert nopostproc +UVM_TESTNAME= +UVM_ TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.32 204789835237964356144020456961394680358822332275190909782637614015062935461 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.42576029488084238759307107603653728922179484705634673135290099686177877817984 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.38 seconds |
| Started | Nov 01 12:24:17 PM PDT 23 |
| Finished | Nov 01 12:24:27 PM PDT 23 |
| Peak memory | 145232 kb |
| Host | smart-d0b03c29-3950-4813-b15b-8db0a96ab645 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=42576029488084238759307107603653728922179484705634673135290099686177877817984 -assert nopostproc +UVM_TESTNAME= +UVM _TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal _alert.42576029488084238759307107603653728922179484705634673135290099686177877817984 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.43692980823624849590753163608776838404710623059590503197453808505051501405957 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.39 seconds |
| Started | Nov 01 12:20:24 PM PDT 23 |
| Finished | Nov 01 12:20:25 PM PDT 23 |
| Peak memory | 145564 kb |
| Host | smart-2aae9eb8-283a-4da2-9cba-fe8caf40c749 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43692980823624849590753163608776838404710623059590503197453808505051501405957 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.4369298 0823624849590753163608776838404710623059590503197453808505051501405957 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.98000261823085687319008790204430702435519076990290045166402572871350628909717 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.4 seconds |
| Started | Nov 01 12:18:41 PM PDT 23 |
| Finished | Nov 01 12:18:43 PM PDT 23 |
| Peak memory | 145312 kb |
| Host | smart-8ae7d60f-bf42-45ed-9029-d8c65f7bc5b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98000261823085687319008790204430702435519076990290045166402572871350628909717 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.980002 61823085687319008790204430702435519076990290045166402572871350628909717 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.93262685508039052870419247923056425814738550441900286888186075310954198159669 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.38 seconds |
| Started | Nov 01 12:26:15 PM PDT 23 |
| Finished | Nov 01 12:26:17 PM PDT 23 |
| Peak memory | 145300 kb |
| Host | smart-55d7767b-80b9-4fce-adb7-19aa72b150a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=93262685508039052870419247923056425814738550441900286888186075310954198159669 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.932626 85508039052870419247923056425814738550441900286888186075310954198159669 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.98997704505187434034425999058282704714002950951543360282492954588220467550397 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.39 seconds |
| Started | Nov 01 12:18:39 PM PDT 23 |
| Finished | Nov 01 12:18:40 PM PDT 23 |
| Peak memory | 145744 kb |
| Host | smart-da596d8b-8d67-45ba-a13b-7292589991c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98997704505187434034425999058282704714002950951543360282492954588220467550397 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.989977 04505187434034425999058282704714002950951543360282492954588220467550397 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.35549341587506930809882862469943291629998538281828430145945535025208552194196 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.39 seconds |
| Started | Nov 01 12:24:18 PM PDT 23 |
| Finished | Nov 01 12:24:27 PM PDT 23 |
| Peak memory | 145472 kb |
| Host | smart-f33a951b-a476-4cbe-b4e1-b337ee5b718d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=35549341587506930809882862469943291629998538281828430145945535025208552194196 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.355493 41587506930809882862469943291629998538281828430145945535025208552194196 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.101820061268007789755171010125955966263408115445386283062472865891743511829516 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.39 seconds |
| Started | Nov 01 12:18:34 PM PDT 23 |
| Finished | Nov 01 12:18:35 PM PDT 23 |
| Peak memory | 144640 kb |
| Host | smart-76e2bc2b-135a-4fd3-980d-1d463cf5b528 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=101820061268007789755171010125955966263408115445386283062472865891743511829516 -assert nopostproc +UVM_TESTNAME= +UVM_TE ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.10182 0061268007789755171010125955966263408115445386283062472865891743511829516 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.580198667302621781107546739143441635375229249659542324376655453316942612433 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.4 seconds |
| Started | Nov 01 12:24:00 PM PDT 23 |
| Finished | Nov 01 12:24:02 PM PDT 23 |
| Peak memory | 143836 kb |
| Host | smart-6e3494b9-5445-4cae-908c-7f64359362fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=580198667302621781107546739143441635375229249659542324376655453316942612433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_ SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.58019866 7302621781107546739143441635375229249659542324376655453316942612433 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.2558414606919219575829264877126478857441441796918663853733760520164654355573 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.44 seconds |
| Started | Nov 01 12:24:14 PM PDT 23 |
| Finished | Nov 01 12:24:26 PM PDT 23 |
| Peak memory | 144268 kb |
| Host | smart-ba236dfb-6daa-462b-9ff4-6e4df1496a1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2558414606919219575829264877126478857441441796918663853733760520164654355573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST _SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2558414 606919219575829264877126478857441441796918663853733760520164654355573 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.30363629943315995963556587753489063838998372698610387375391450883945807459717 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.37 seconds |
| Started | Nov 01 12:24:19 PM PDT 23 |
| Finished | Nov 01 12:24:30 PM PDT 23 |
| Peak memory | 145216 kb |
| Host | smart-3f1b73c7-4ad1-43b2-be58-7da8ce0045b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30363629943315995963556587753489063838998372698610387375391450883945807459717 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.303636 29943315995963556587753489063838998372698610387375391450883945807459717 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.2545098692588448981841615929570468447709840104609367887872080112889238251214 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.37 seconds |
| Started | Nov 01 12:24:15 PM PDT 23 |
| Finished | Nov 01 12:24:26 PM PDT 23 |
| Peak memory | 144496 kb |
| Host | smart-b8ebeee2-58f2-456f-bf4a-d9dce35b4f0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2545098692588448981841615929570468447709840104609367887872080112889238251214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST _SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2545098 692588448981841615929570468447709840104609367887872080112889238251214 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.46594164082165955788405151336361079119916444724554537989660835286886221434296 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.43 seconds |
| Started | Nov 01 12:22:05 PM PDT 23 |
| Finished | Nov 01 12:22:06 PM PDT 23 |
| Peak memory | 145572 kb |
| Host | smart-ba124655-1b23-4cdf-b783-41f02804af3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=46594164082165955788405151336361079119916444724554537989660835286886221434296 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.465941 64082165955788405151336361079119916444724554537989660835286886221434296 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.81818935521592498299377705102109805966260175029306066093008743630564690976709 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.37 seconds |
| Started | Nov 01 12:24:07 PM PDT 23 |
| Finished | Nov 01 12:24:11 PM PDT 23 |
| Peak memory | 145148 kb |
| Host | smart-fff508b3-6bde-42cc-a8c8-7e59fdd55f79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81818935521592498299377705102109805966260175029306066093008743630564690976709 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.8181893 5521592498299377705102109805966260175029306066093008743630564690976709 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.6120812414405184552241014009883045612130269087615735927664560555919103251802 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.41 seconds |
| Started | Nov 01 12:19:24 PM PDT 23 |
| Finished | Nov 01 12:19:25 PM PDT 23 |
| Peak memory | 145444 kb |
| Host | smart-aa1b9a56-0369-4c2b-9a21-00227e9c949f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6120812414405184552241014009883045612130269087615735927664560555919103251802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST _SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.61208124 14405184552241014009883045612130269087615735927664560555919103251802 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.29418250262722959615974444056151960548638974583951069843617370231242770110726 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.37 seconds |
| Started | Nov 01 12:26:15 PM PDT 23 |
| Finished | Nov 01 12:26:17 PM PDT 23 |
| Peak memory | 145300 kb |
| Host | smart-488961a5-00e2-4a73-b1e5-497b884f1906 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=29418250262722959615974444056151960548638974583951069843617370231242770110726 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2941825 0262722959615974444056151960548638974583951069843617370231242770110726 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.112814746871829123171699109183430055407356389803898187429339966891844250416244 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.4 seconds |
| Started | Nov 01 12:25:58 PM PDT 23 |
| Finished | Nov 01 12:26:00 PM PDT 23 |
| Peak memory | 145036 kb |
| Host | smart-d248564e-c880-4b29-b024-cc329a8124fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=112814746871829123171699109183430055407356389803898187429339966891844250416244 -assert nopostproc +UVM_TESTNAME= +UVM_TE ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.112814 746871829123171699109183430055407356389803898187429339966891844250416244 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.68044568610425783475006078066884772983493553731077341514820352937764569350714 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.42 seconds |
| Started | Nov 01 12:18:16 PM PDT 23 |
| Finished | Nov 01 12:18:18 PM PDT 23 |
| Peak memory | 145304 kb |
| Host | smart-aa91f426-62de-4481-9aaf-237f48c86a3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68044568610425783475006078066884772983493553731077341514820352937764569350714 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.6804456 8610425783475006078066884772983493553731077341514820352937764569350714 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.81635402413749829700849724830641161868088822606235499542378384987049478593915 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.44 seconds |
| Started | Nov 01 12:24:00 PM PDT 23 |
| Finished | Nov 01 12:24:02 PM PDT 23 |
| Peak memory | 143512 kb |
| Host | smart-93006130-2bd8-408e-b0ff-52a676874f91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81635402413749829700849724830641161868088822606235499542378384987049478593915 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.8163540 2413749829700849724830641161868088822606235499542378384987049478593915 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.25239214604347309048952867147182557731182523711646075502047151752617767506613 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.38 seconds |
| Started | Nov 01 12:18:18 PM PDT 23 |
| Finished | Nov 01 12:18:19 PM PDT 23 |
| Peak memory | 145312 kb |
| Host | smart-d279bcab-be2a-488a-9b64-be16181e75b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=25239214604347309048952867147182557731182523711646075502047151752617767506613 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2523921 4604347309048952867147182557731182523711646075502047151752617767506613 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.71826001359875991272133431508400670008674937936843278663173570822119977771423 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11469183 ps |
| CPU time | 0.38 seconds |
| Started | Nov 01 12:26:00 PM PDT 23 |
| Finished | Nov 01 12:26:02 PM PDT 23 |
| Peak memory | 145300 kb |
| Host | smart-7e059b00-89e3-44f8-bb15-1bb1c9afe2b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71826001359875991272133431508400670008674937936843278663173570822119977771423 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.7182600 1359875991272133431508400670008674937936843278663173570822119977771423 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.16769186589863869521212156681536511778571462100436129090563906354811312911405 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.38 seconds |
| Started | Nov 01 12:27:03 PM PDT 23 |
| Finished | Nov 01 12:27:04 PM PDT 23 |
| Peak memory | 145896 kb |
| Host | smart-df142d5b-5457-4720-9036-33eeae5fdd58 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=16769186589863869521212156681536511778571462100436129090563906354811312911405 -assert nopostproc +UVM_TESTNAME= +UVM _TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal _alert.16769186589863869521212156681536511778571462100436129090563906354811312911405 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.21548313525577088012335442216128410322760876621005947105851209763293964394757 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.53 seconds |
| Started | Nov 01 12:24:25 PM PDT 23 |
| Finished | Nov 01 12:24:36 PM PDT 23 |
| Peak memory | 144348 kb |
| Host | smart-f7854a1b-0cc8-4cfb-8255-5aed34289a01 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=21548313525577088012335442216128410322760876621005947105851209763293964394757 -assert nopostproc +UVM_TESTNAME= +UVM _TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fata l_alert.21548313525577088012335442216128410322760876621005947105851209763293964394757 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1508283067895191546144533412342084725933135995839758866065094324876299558155 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.4 seconds |
| Started | Nov 01 12:24:16 PM PDT 23 |
| Finished | Nov 01 12:24:29 PM PDT 23 |
| Peak memory | 145364 kb |
| Host | smart-3251dddf-dcf6-4fe6-a23e-bc876bcdfee1 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1508283067895191546144533412342084725933135995839758866065094324876299558155 -assert nopostproc +UVM_TESTNAME= +UVM_ TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal _alert.1508283067895191546144533412342084725933135995839758866065094324876299558155 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.6862455671003617840903638514529408278219422852795833027599257044275204922711 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.42 seconds |
| Started | Nov 01 12:24:25 PM PDT 23 |
| Finished | Nov 01 12:24:36 PM PDT 23 |
| Peak memory | 145436 kb |
| Host | smart-dac07c91-e07f-4578-9fd1-012677762f9a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=6862455671003617840903638514529408278219422852795833027599257044275204922711 -assert nopostproc +UVM_TESTNAME= +UVM_ TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal _alert.6862455671003617840903638514529408278219422852795833027599257044275204922711 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.97385676803083570192001098468316599841456255989573669520383502490724385979594 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.4 seconds |
| Started | Nov 01 12:18:39 PM PDT 23 |
| Finished | Nov 01 12:18:41 PM PDT 23 |
| Peak memory | 145248 kb |
| Host | smart-37c36a1a-66b4-4fc5-b1b2-c61b1667999a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=97385676803083570192001098468316599841456255989573669520383502490724385979594 -assert nopostproc +UVM_TESTNAME= +UVM _TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fata l_alert.97385676803083570192001098468316599841456255989573669520383502490724385979594 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.63149245992494352459413060817089449440885530942817161019454908949041483922224 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.42 seconds |
| Started | Nov 01 12:26:39 PM PDT 23 |
| Finished | Nov 01 12:26:41 PM PDT 23 |
| Peak memory | 145800 kb |
| Host | smart-ff35940f-c1f8-4fb7-a032-c7f1ba69bf02 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=63149245992494352459413060817089449440885530942817161019454908949041483922224 -assert nopostproc +UVM_TESTNAME= +UVM _TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fata l_alert.63149245992494352459413060817089449440885530942817161019454908949041483922224 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.45528374919880120708605320225592726144661078322394974295466303834411141940154 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.38 seconds |
| Started | Nov 01 12:26:46 PM PDT 23 |
| Finished | Nov 01 12:26:49 PM PDT 23 |
| Peak memory | 145436 kb |
| Host | smart-b446719d-aa04-46bb-892e-7ff2b855ade2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=45528374919880120708605320225592726144661078322394974295466303834411141940154 -assert nopostproc +UVM_TESTNAME= +UVM _TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fata l_alert.45528374919880120708605320225592726144661078322394974295466303834411141940154 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.92672498810485462343987519550711040447545754125655327807896856330871149984323 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.4 seconds |
| Started | Nov 01 12:24:28 PM PDT 23 |
| Finished | Nov 01 12:24:37 PM PDT 23 |
| Peak memory | 145276 kb |
| Host | smart-2eb8a123-b0f4-491a-b028-2d9abfc12aee |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=92672498810485462343987519550711040447545754125655327807896856330871149984323 -assert nopostproc +UVM_TESTNAME= +UVM _TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fata l_alert.92672498810485462343987519550711040447545754125655327807896856330871149984323 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.33781561021252387847686941598913877514479109952063889475153716119096236487355 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.43 seconds |
| Started | Nov 01 12:18:34 PM PDT 23 |
| Finished | Nov 01 12:18:35 PM PDT 23 |
| Peak memory | 144820 kb |
| Host | smart-8bd986fc-6aed-4663-81c8-6fb6d57c37f5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=33781561021252387847686941598913877514479109952063889475153716119096236487355 -assert nopostproc +UVM_TESTNAME= +UVM _TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fata l_alert.33781561021252387847686941598913877514479109952063889475153716119096236487355 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.84653614187125092859964220791096509693328848736135605829752153785123053714911 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.43 seconds |
| Started | Nov 01 12:24:06 PM PDT 23 |
| Finished | Nov 01 12:24:08 PM PDT 23 |
| Peak memory | 144828 kb |
| Host | smart-6090d774-b0ea-4f10-8c20-59d0b65efae6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=84653614187125092859964220791096509693328848736135605829752153785123053714911 -assert nopostproc +UVM_TESTNAME= +UVM _TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fata l_alert.84653614187125092859964220791096509693328848736135605829752153785123053714911 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.12189816388292710222533349837396572659465023569354147377821357985298977691697 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.43 seconds |
| Started | Nov 01 12:24:16 PM PDT 23 |
| Finished | Nov 01 12:24:29 PM PDT 23 |
| Peak memory | 145404 kb |
| Host | smart-e43236b1-3285-4707-bc14-4fcfb671afb5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=12189816388292710222533349837396572659465023569354147377821357985298977691697 -assert nopostproc +UVM_TESTNAME= +UVM _TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fata l_alert.12189816388292710222533349837396572659465023569354147377821357985298977691697 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.110332035229050157389245663418646694214826928408298762581601323849587489607002 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.4 seconds |
| Started | Nov 01 12:21:18 PM PDT 23 |
| Finished | Nov 01 12:21:19 PM PDT 23 |
| Peak memory | 145832 kb |
| Host | smart-b2703834-2639-4fb6-a534-bf347e38b048 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=110332035229050157389245663418646694214826928408298762581601323849587489607002 -assert nopostproc +UVM_TESTNAME= +UV M_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fata l_alert.110332035229050157389245663418646694214826928408298762581601323849587489607002 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.42730104559886420899535165057780022430554423855276136323180190313272162249142 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.39 seconds |
| Started | Nov 01 12:24:19 PM PDT 23 |
| Finished | Nov 01 12:24:31 PM PDT 23 |
| Peak memory | 145696 kb |
| Host | smart-1107ff52-9783-42b5-b6a0-e2cbda84a277 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=42730104559886420899535165057780022430554423855276136323180190313272162249142 -assert nopostproc +UVM_TESTNAME= +UVM _TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal _alert.42730104559886420899535165057780022430554423855276136323180190313272162249142 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.65645052562003354036136238769310909911672139282342498597275485361064356727645 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.4 seconds |
| Started | Nov 01 12:24:23 PM PDT 23 |
| Finished | Nov 01 12:24:35 PM PDT 23 |
| Peak memory | 145468 kb |
| Host | smart-15ea1596-bf21-43bf-bf8b-e4640904d83e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=65645052562003354036136238769310909911672139282342498597275485361064356727645 -assert nopostproc +UVM_TESTNAME= +UVM _TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal _alert.65645052562003354036136238769310909911672139282342498597275485361064356727645 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.115064727087048887431930923084434958295758359288629889166140728438556849229192 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.38 seconds |
| Started | Nov 01 12:24:20 PM PDT 23 |
| Finished | Nov 01 12:24:33 PM PDT 23 |
| Peak memory | 145092 kb |
| Host | smart-165117d7-078d-4bd3-95f4-1409d082853c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=115064727087048887431930923084434958295758359288629889166140728438556849229192 -assert nopostproc +UVM_TESTNAME= +UV M_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fata l_alert.115064727087048887431930923084434958295758359288629889166140728438556849229192 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.101128161930255653084180640745013101165310907981380720011536036730520347745857 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.39 seconds |
| Started | Nov 01 12:24:21 PM PDT 23 |
| Finished | Nov 01 12:24:33 PM PDT 23 |
| Peak memory | 145724 kb |
| Host | smart-e70498ec-be01-439d-8c6c-56c7646dcf21 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=101128161930255653084180640745013101165310907981380720011536036730520347745857 -assert nopostproc +UVM_TESTNAME= +UV M_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fata l_alert.101128161930255653084180640745013101165310907981380720011536036730520347745857 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.62275321088896663007616017360186839668989276155898067378953315142483058808597 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.41 seconds |
| Started | Nov 01 12:20:29 PM PDT 23 |
| Finished | Nov 01 12:20:30 PM PDT 23 |
| Peak memory | 145680 kb |
| Host | smart-c31f131c-de77-4783-8e46-9ea586028885 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=62275321088896663007616017360186839668989276155898067378953315142483058808597 -assert nopostproc +UVM_TESTNAME= +UVM _TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal _alert.62275321088896663007616017360186839668989276155898067378953315142483058808597 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.70562344573421236281150431612528478490655563739622080964958872277077387354861 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.46 seconds |
| Started | Nov 01 12:18:41 PM PDT 23 |
| Finished | Nov 01 12:18:42 PM PDT 23 |
| Peak memory | 145180 kb |
| Host | smart-9a51dde3-b1ce-4bfb-a266-dc6e16f2d23d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=70562344573421236281150431612528478490655563739622080964958872277077387354861 -assert nopostproc +UVM_TESTNAME= +UVM _TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal _alert.70562344573421236281150431612528478490655563739622080964958872277077387354861 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.53006446116526749363007045385488201052200629531962955376164605120235462489982 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 30019183 ps |
| CPU time | 0.39 seconds |
| Started | Nov 01 12:24:20 PM PDT 23 |
| Finished | Nov 01 12:24:32 PM PDT 23 |
| Peak memory | 145644 kb |
| Host | smart-29ef49e9-34b7-40e4-b228-c2bb230cd255 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=53006446116526749363007045385488201052200629531962955376164605120235462489982 -assert nopostproc +UVM_TESTNAME= +UVM _TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal _alert.53006446116526749363007045385488201052200629531962955376164605120235462489982 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.27361767513857197636828745972873502614889563806966745881640053782541189852561 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.39 seconds |
| Started | Nov 01 01:14:26 PM PDT 23 |
| Finished | Nov 01 01:14:28 PM PDT 23 |
| Peak memory | 144980 kb |
| Host | smart-d902f1d2-4024-4fe2-b691-774b3a1c1342 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=27361767513857197636828745972873502614889563806966745881640053782541189852561 -assert nopostproc +UVM_TESTNAME= +UVM_ TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.27 361767513857197636828745972873502614889563806966745881640053782541189852561 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.36464659150671199225379281951216645527686789587162545370380466314816183546857 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.41 seconds |
| Started | Nov 01 01:14:25 PM PDT 23 |
| Finished | Nov 01 01:14:27 PM PDT 23 |
| Peak memory | 145076 kb |
| Host | smart-edb392ec-c47e-4828-ab31-36aebb2c4aa6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=36464659150671199225379281951216645527686789587162545370380466314816183546857 -assert nopostproc +UVM_TESTNAME= +UVM_ TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3 6464659150671199225379281951216645527686789587162545370380466314816183546857 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.68861710098911349038504034612517158395550734799699252588252286456475061875351 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.37 seconds |
| Started | Nov 01 01:14:28 PM PDT 23 |
| Finished | Nov 01 01:14:30 PM PDT 23 |
| Peak memory | 145020 kb |
| Host | smart-b1d02d43-7675-4a66-982a-475f13eb447a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=68861710098911349038504034612517158395550734799699252588252286456475061875351 -assert nopostproc +UVM_TESTNAME= +UVM_ TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.6 8861710098911349038504034612517158395550734799699252588252286456475061875351 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.115260814734828993964301017841109136280062031144792036249883927401094682949880 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.37 seconds |
| Started | Nov 01 01:14:17 PM PDT 23 |
| Finished | Nov 01 01:14:19 PM PDT 23 |
| Peak memory | 144924 kb |
| Host | smart-2ca74644-d518-4d2d-97ce-ab1fe0f71eeb |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=115260814734828993964301017841109136280062031144792036249883927401094682949880 -assert nopostproc +UVM_TESTNAME= +UVM _TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert. 115260814734828993964301017841109136280062031144792036249883927401094682949880 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.3690795694697413259559252601218437963961749456862919637990857136567957768968 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.38 seconds |
| Started | Nov 01 01:14:32 PM PDT 23 |
| Finished | Nov 01 01:14:35 PM PDT 23 |
| Peak memory | 144972 kb |
| Host | smart-13bcb953-7024-4f5c-8677-e2b37a4c41dd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3690795694697413259559252601218437963961749456862919637990857136567957768968 -assert nopostproc +UVM_TESTNAME= +UVM_T EST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.36 90795694697413259559252601218437963961749456862919637990857136567957768968 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.102707751280740056851552819139819513517157079147192751872021884619040125569339 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.36 seconds |
| Started | Nov 01 01:14:23 PM PDT 23 |
| Finished | Nov 01 01:14:24 PM PDT 23 |
| Peak memory | 145004 kb |
| Host | smart-86eff193-e841-4c74-8444-8ce30db7afa5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=102707751280740056851552819139819513517157079147192751872021884619040125569339 -assert nopostproc +UVM_TESTNAME= +UVM _TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert. 102707751280740056851552819139819513517157079147192751872021884619040125569339 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.982339519067005419274678793849234484623448792948613308997554917295941605817 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.37 seconds |
| Started | Nov 01 01:14:25 PM PDT 23 |
| Finished | Nov 01 01:14:26 PM PDT 23 |
| Peak memory | 144988 kb |
| Host | smart-a0ebc90a-bf3c-47c4-850d-308f70cf4eae |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=982339519067005419274678793849234484623448792948613308997554917295941605817 -assert nopostproc +UVM_TESTNAME= +UVM_TE ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.982 339519067005419274678793849234484623448792948613308997554917295941605817 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.109434604158533431241530691887820892503762080586602095710428088640649947017813 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.37 seconds |
| Started | Nov 01 01:14:33 PM PDT 23 |
| Finished | Nov 01 01:14:35 PM PDT 23 |
| Peak memory | 145064 kb |
| Host | smart-6ab7feb7-afa3-4b01-a105-786ad626dd9c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=109434604158533431241530691887820892503762080586602095710428088640649947017813 -assert nopostproc +UVM_TESTNAME= +UVM _TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert. 109434604158533431241530691887820892503762080586602095710428088640649947017813 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.39572436563680109771940306683335873620712632822936257777891263860929671148362 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.39 seconds |
| Started | Nov 01 01:14:24 PM PDT 23 |
| Finished | Nov 01 01:14:25 PM PDT 23 |
| Peak memory | 145072 kb |
| Host | smart-2aa74023-cfd3-41cc-8958-1bc3f21bdef7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=39572436563680109771940306683335873620712632822936257777891263860929671148362 -assert nopostproc +UVM_TESTNAME= +UVM_ TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3 9572436563680109771940306683335873620712632822936257777891263860929671148362 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.35429761464286601210715854764496333952251528406689867073515616059493611642139 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.39 seconds |
| Started | Nov 01 01:14:16 PM PDT 23 |
| Finished | Nov 01 01:14:17 PM PDT 23 |
| Peak memory | 144984 kb |
| Host | smart-8a39ff10-f7aa-4cea-ad70-202609ed63fb |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=35429761464286601210715854764496333952251528406689867073515616059493611642139 -assert nopostproc +UVM_TESTNAME= +UVM_ TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3 5429761464286601210715854764496333952251528406689867073515616059493611642139 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.934768502883149983434715253483129895540153267270084452825699549813089981 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.42 seconds |
| Started | Nov 01 01:14:16 PM PDT 23 |
| Finished | Nov 01 01:14:17 PM PDT 23 |
| Peak memory | 144952 kb |
| Host | smart-b6e68f13-47a5-488d-ba0e-2e86a1ff16fa |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=934768502883149983434715253483129895540153267270084452825699549813089981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_ SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.934768 502883149983434715253483129895540153267270084452825699549813089981 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.96797087516452664678876217530650485125468148931461117072265656014530243630730 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.37 seconds |
| Started | Nov 01 01:14:25 PM PDT 23 |
| Finished | Nov 01 01:14:26 PM PDT 23 |
| Peak memory | 145172 kb |
| Host | smart-3b810201-27ff-4667-9f6b-3a6e4135d6d6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=96797087516452664678876217530650485125468148931461117072265656014530243630730 -assert nopostproc +UVM_TESTNAME= +UVM_ TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.96 797087516452664678876217530650485125468148931461117072265656014530243630730 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.46380390636101413665298368983610467091298159968518546275837679859894844021941 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.43 seconds |
| Started | Nov 01 01:14:14 PM PDT 23 |
| Finished | Nov 01 01:14:15 PM PDT 23 |
| Peak memory | 145204 kb |
| Host | smart-06233809-b22d-4896-9bb9-7ae93d1e9f12 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=46380390636101413665298368983610467091298159968518546275837679859894844021941 -assert nopostproc +UVM_TESTNAME= +UVM_ TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.46 380390636101413665298368983610467091298159968518546275837679859894844021941 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.70219233900635455674618345719519780079244926405982397901763640383272006133481 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.37 seconds |
| Started | Nov 01 01:14:33 PM PDT 23 |
| Finished | Nov 01 01:14:35 PM PDT 23 |
| Peak memory | 144976 kb |
| Host | smart-0f8b5b6a-ff21-4963-b660-2b85538ab02e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=70219233900635455674618345719519780079244926405982397901763640383272006133481 -assert nopostproc +UVM_TESTNAME= +UVM_ TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.70 219233900635455674618345719519780079244926405982397901763640383272006133481 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.75039402986986695257145806318839515715668735670584877394768621978284489473231 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.38 seconds |
| Started | Nov 01 01:14:26 PM PDT 23 |
| Finished | Nov 01 01:14:28 PM PDT 23 |
| Peak memory | 144940 kb |
| Host | smart-a7893e62-93bb-43bf-a234-27dfbbca24c5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=75039402986986695257145806318839515715668735670584877394768621978284489473231 -assert nopostproc +UVM_TESTNAME= +UVM_ TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.75 039402986986695257145806318839515715668735670584877394768621978284489473231 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.45911048201807709331560860858624884929814043618826448362213871428049748419310 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.42 seconds |
| Started | Nov 01 01:14:26 PM PDT 23 |
| Finished | Nov 01 01:14:28 PM PDT 23 |
| Peak memory | 144940 kb |
| Host | smart-d85e19c9-a957-4b2f-b5a0-da9957af7504 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=45911048201807709331560860858624884929814043618826448362213871428049748419310 -assert nopostproc +UVM_TESTNAME= +UVM_ TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.45 911048201807709331560860858624884929814043618826448362213871428049748419310 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.12698806522672853867496129460426025389085231241924521626092673019265825089519 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.39 seconds |
| Started | Nov 01 01:14:33 PM PDT 23 |
| Finished | Nov 01 01:14:35 PM PDT 23 |
| Peak memory | 144920 kb |
| Host | smart-16a66498-4f78-479c-9f2a-c0052012af3a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=12698806522672853867496129460426025389085231241924521626092673019265825089519 -assert nopostproc +UVM_TESTNAME= +UVM_ TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.12 698806522672853867496129460426025389085231241924521626092673019265825089519 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.60213587947589614006711529713410254501819469397521118115432676414915420486967 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.38 seconds |
| Started | Nov 01 01:14:30 PM PDT 23 |
| Finished | Nov 01 01:14:31 PM PDT 23 |
| Peak memory | 145076 kb |
| Host | smart-9f185a1e-2204-4b81-bb02-1a12681bd2c7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=60213587947589614006711529713410254501819469397521118115432676414915420486967 -assert nopostproc +UVM_TESTNAME= +UVM_ TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.60 213587947589614006711529713410254501819469397521118115432676414915420486967 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.22761099426674127402983793429339139857791257678352247218741007818110912045623 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9009183 ps |
| CPU time | 0.37 seconds |
| Started | Nov 01 01:14:26 PM PDT 23 |
| Finished | Nov 01 01:14:28 PM PDT 23 |
| Peak memory | 144968 kb |
| Host | smart-811ed7de-254a-43cd-9294-d489d9ce5d41 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=22761099426674127402983793429339139857791257678352247218741007818110912045623 -assert nopostproc +UVM_TESTNAME= +UVM_ TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.22 761099426674127402983793429339139857791257678352247218741007818110912045623 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.53859229405170938978252791075822875780360932967155223036489497252065434948854 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.52 seconds |
| Started | Nov 01 12:17:59 PM PDT 23 |
| Finished | Nov 01 12:18:05 PM PDT 23 |
| Peak memory | 143080 kb |
| Host | smart-a6973bf9-4f0e-4fa5-8f76-cb5500221913 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=53859229405170938978252791075822875780360932967155223036489497252065434948854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_s ync_fatal_alert.53859229405170938978252791075822875780360932967155223036489497252065434948854 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.102772469185254332455938975011495319617321310545770269901148737774590551879152 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.53 seconds |
| Started | Nov 01 12:17:59 PM PDT 23 |
| Finished | Nov 01 12:18:05 PM PDT 23 |
| Peak memory | 143164 kb |
| Host | smart-ed35e461-0cc6-4f4e-938b-243b91d6376c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=102772469185254332455938975011495319617321310545770269901148737774590551879152 -assert nopostproc +UVM_TESTNAME = +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_ sync_fatal_alert.102772469185254332455938975011495319617321310545770269901148737774590551879152 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.100609380750360750841515695119767743510297182278481515761209158516554100670621 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.52 seconds |
| Started | Nov 01 12:17:59 PM PDT 23 |
| Finished | Nov 01 12:18:05 PM PDT 23 |
| Peak memory | 143332 kb |
| Host | smart-23949da9-bd72-4359-bf42-0f3e6df7e785 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=100609380750360750841515695119767743510297182278481515761209158516554100670621 -assert nopostproc +UVM_TESTNAME = +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim _sync_fatal_alert.100609380750360750841515695119767743510297182278481515761209158516554100670621 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.40164883703707162521584770725893913575086044399922494856185576367536416001643 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.45 seconds |
| Started | Nov 01 12:18:41 PM PDT 23 |
| Finished | Nov 01 12:18:42 PM PDT 23 |
| Peak memory | 144688 kb |
| Host | smart-6c825bfc-d998-45cc-811d-82cfaf7d4613 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=40164883703707162521584770725893913575086044399922494856185576367536416001643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_ sync_fatal_alert.40164883703707162521584770725893913575086044399922494856185576367536416001643 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.80616729996268906397883868161338400879314809077624815164088496305323689973106 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.41 seconds |
| Started | Nov 01 12:18:00 PM PDT 23 |
| Finished | Nov 01 12:18:05 PM PDT 23 |
| Peak memory | 143968 kb |
| Host | smart-fe8bab76-3ec3-4eb0-86de-89dae92254ce |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=80616729996268906397883868161338400879314809077624815164088496305323689973106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_ sync_fatal_alert.80616729996268906397883868161338400879314809077624815164088496305323689973106 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.106125662804572019582261029215660257680472063909029423722450171457933869166681 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.45 seconds |
| Started | Nov 01 12:17:43 PM PDT 23 |
| Finished | Nov 01 12:17:45 PM PDT 23 |
| Peak memory | 144968 kb |
| Host | smart-964a5b73-09bf-426b-a9d5-58bf241e62a8 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=106125662804572019582261029215660257680472063909029423722450171457933869166681 -assert nopostproc +UVM_TESTNAME = +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim _sync_fatal_alert.106125662804572019582261029215660257680472063909029423722450171457933869166681 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.20420235689379743814148103920634837858071240036324354113957422713560074900577 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.39 seconds |
| Started | Nov 01 12:17:52 PM PDT 23 |
| Finished | Nov 01 12:17:53 PM PDT 23 |
| Peak memory | 145204 kb |
| Host | smart-171dc5a2-da98-469e-bee4-a8ef7b54d917 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=20420235689379743814148103920634837858071240036324354113957422713560074900577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_ sync_fatal_alert.20420235689379743814148103920634837858071240036324354113957422713560074900577 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.86975356666949566595058684098788187150657889569450325289333202838252994617285 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.53 seconds |
| Started | Nov 01 12:17:59 PM PDT 23 |
| Finished | Nov 01 12:18:05 PM PDT 23 |
| Peak memory | 142960 kb |
| Host | smart-7190c40e-3340-4da2-ae61-d4e3ee6a4721 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=86975356666949566595058684098788187150657889569450325289333202838252994617285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_ sync_fatal_alert.86975356666949566595058684098788187150657889569450325289333202838252994617285 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.72822545635936545390303976321667704912688635064405889039476633294883874180224 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.43 seconds |
| Started | Nov 01 12:18:02 PM PDT 23 |
| Finished | Nov 01 12:18:06 PM PDT 23 |
| Peak memory | 144960 kb |
| Host | smart-b6426e3a-8658-40dd-a3f8-62f90da23985 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=72822545635936545390303976321667704912688635064405889039476633294883874180224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_ sync_fatal_alert.72822545635936545390303976321667704912688635064405889039476633294883874180224 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.114469355257005053828728049336533067821054110741896578116093250948767340607526 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.43 seconds |
| Started | Nov 01 12:17:52 PM PDT 23 |
| Finished | Nov 01 12:17:53 PM PDT 23 |
| Peak memory | 145204 kb |
| Host | smart-11331958-75df-4be1-ac66-17a2117aacd5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=114469355257005053828728049336533067821054110741896578116093250948767340607526 -assert nopostproc +UVM_TESTNAME = +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim _sync_fatal_alert.114469355257005053828728049336533067821054110741896578116093250948767340607526 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.36608228106812193029682941605136008372656856199686176783233815226308216930770 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.42 seconds |
| Started | Nov 01 12:17:57 PM PDT 23 |
| Finished | Nov 01 12:18:03 PM PDT 23 |
| Peak memory | 144844 kb |
| Host | smart-a8a8cb74-704f-47bd-abfb-d1031014a450 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=36608228106812193029682941605136008372656856199686176783233815226308216930770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_ sync_fatal_alert.36608228106812193029682941605136008372656856199686176783233815226308216930770 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.89869132565464636274115651259233637785051259920133021600445388948096231494659 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.43 seconds |
| Started | Nov 01 12:17:57 PM PDT 23 |
| Finished | Nov 01 12:18:03 PM PDT 23 |
| Peak memory | 144884 kb |
| Host | smart-fd4ef781-d6e4-4beb-9bc8-652746b6426e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=89869132565464636274115651259233637785051259920133021600445388948096231494659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_ sync_fatal_alert.89869132565464636274115651259233637785051259920133021600445388948096231494659 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.27908936427133835611999517881699326670219069971433464302577171651906887441851 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.44 seconds |
| Started | Nov 01 12:18:02 PM PDT 23 |
| Finished | Nov 01 12:18:06 PM PDT 23 |
| Peak memory | 144948 kb |
| Host | smart-fa81619c-764b-43d5-a946-cf5b675a4a6f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=27908936427133835611999517881699326670219069971433464302577171651906887441851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_s ync_fatal_alert.27908936427133835611999517881699326670219069971433464302577171651906887441851 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.13764044464206033610311579864185008059206568985363933951676295859429863183861 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.39 seconds |
| Started | Nov 01 12:17:45 PM PDT 23 |
| Finished | Nov 01 12:17:46 PM PDT 23 |
| Peak memory | 145256 kb |
| Host | smart-bf0328be-1a0c-4780-b3aa-64e2596f49b7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=13764044464206033610311579864185008059206568985363933951676295859429863183861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_s ync_fatal_alert.13764044464206033610311579864185008059206568985363933951676295859429863183861 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.11827128577570407072611770585352561141361261498707144588076820103285405472735 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.51 seconds |
| Started | Nov 01 12:17:48 PM PDT 23 |
| Finished | Nov 01 12:17:49 PM PDT 23 |
| Peak memory | 143696 kb |
| Host | smart-ebf316eb-ab2d-488b-897a-c47df60f00c8 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=11827128577570407072611770585352561141361261498707144588076820103285405472735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_s ync_fatal_alert.11827128577570407072611770585352561141361261498707144588076820103285405472735 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.69443217261977813067443091571186876063334966838362119051014112402958443982732 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.43 seconds |
| Started | Nov 01 12:17:53 PM PDT 23 |
| Finished | Nov 01 12:17:55 PM PDT 23 |
| Peak memory | 144408 kb |
| Host | smart-d8ddd51c-d4c2-45d4-899b-2a0c4ad518c1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=69443217261977813067443091571186876063334966838362119051014112402958443982732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_s ync_fatal_alert.69443217261977813067443091571186876063334966838362119051014112402958443982732 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.25460841178376776761669891988763464080658473778650630293942510506878301996807 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.4 seconds |
| Started | Nov 01 12:17:52 PM PDT 23 |
| Finished | Nov 01 12:17:53 PM PDT 23 |
| Peak memory | 145204 kb |
| Host | smart-45a5e6d3-c0cc-45ff-ab96-7eabb973fd7e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=25460841178376776761669891988763464080658473778650630293942510506878301996807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_s ync_fatal_alert.25460841178376776761669891988763464080658473778650630293942510506878301996807 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.48382621214679157158949242900451422417773897954231911545047474424463434563864 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.43 seconds |
| Started | Nov 01 12:17:53 PM PDT 23 |
| Finished | Nov 01 12:17:55 PM PDT 23 |
| Peak memory | 144460 kb |
| Host | smart-51c50b77-74dc-4f0d-a8e4-1095124f202a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=48382621214679157158949242900451422417773897954231911545047474424463434563864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_s ync_fatal_alert.48382621214679157158949242900451422417773897954231911545047474424463434563864 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.112539102199883886944983668190999597169795102350874489386435497750802577671485 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.47 seconds |
| Started | Nov 01 12:17:48 PM PDT 23 |
| Finished | Nov 01 12:17:49 PM PDT 23 |
| Peak memory | 144500 kb |
| Host | smart-393de9cd-69a0-46bc-a217-623abbaa3e0e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=112539102199883886944983668190999597169795102350874489386435497750802577671485 -assert nopostproc +UVM_TESTNAME = +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_ sync_fatal_alert.112539102199883886944983668190999597169795102350874489386435497750802577671485 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.35546612713760032042505813168077955924007752723571801103047932110025326281032 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 26839183 ps |
| CPU time | 0.51 seconds |
| Started | Nov 01 12:17:59 PM PDT 23 |
| Finished | Nov 01 12:18:05 PM PDT 23 |
| Peak memory | 143260 kb |
| Host | smart-897548e0-da8d-441f-95c2-34d117bec6b2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=35546612713760032042505813168077955924007752723571801103047932110025326281032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_s ync_fatal_alert.35546612713760032042505813168077955924007752723571801103047932110025326281032 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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