Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 78
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.67 88.67 100.00 100.00 93.75 93.75 96.43 96.43 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/18.prim_async_alert.2555574650
91.20 2.53 100.00 0.00 93.75 0.00 96.43 0.00 82.14 3.57 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/17.prim_sync_alert.1223353044
93.31 2.11 100.00 0.00 95.83 2.08 100.00 3.57 82.14 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.878634786
94.50 1.19 100.00 0.00 95.83 0.00 100.00 0.00 89.29 7.14 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1831955214
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.722992630
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2349244964

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.1915559469
/workspace/coverage/default/1.prim_async_alert.2829777969
/workspace/coverage/default/10.prim_async_alert.109119971
/workspace/coverage/default/11.prim_async_alert.941910992
/workspace/coverage/default/12.prim_async_alert.2057693370
/workspace/coverage/default/13.prim_async_alert.1121673022
/workspace/coverage/default/14.prim_async_alert.1462137304
/workspace/coverage/default/15.prim_async_alert.878382347
/workspace/coverage/default/16.prim_async_alert.1441641931
/workspace/coverage/default/17.prim_async_alert.1210525564
/workspace/coverage/default/19.prim_async_alert.3159244763
/workspace/coverage/default/2.prim_async_alert.2969504242
/workspace/coverage/default/3.prim_async_alert.3183805360
/workspace/coverage/default/4.prim_async_alert.3981161125
/workspace/coverage/default/5.prim_async_alert.2802419694
/workspace/coverage/default/6.prim_async_alert.2084823480
/workspace/coverage/default/7.prim_async_alert.1136144793
/workspace/coverage/default/8.prim_async_alert.2041543292
/workspace/coverage/default/9.prim_async_alert.2649695466
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.45261601
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2368007551
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3498700448
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3407179655
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2976843134
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.126556037
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.105029322
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1430539818
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2909400564
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3732091093
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1409611516
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2101949584
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.99693763
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3440476126
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1965597790
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.353462622
/workspace/coverage/sync_alert/0.prim_sync_alert.3187679309
/workspace/coverage/sync_alert/1.prim_sync_alert.3358040135
/workspace/coverage/sync_alert/10.prim_sync_alert.2823928767
/workspace/coverage/sync_alert/11.prim_sync_alert.133926555
/workspace/coverage/sync_alert/12.prim_sync_alert.1833645748
/workspace/coverage/sync_alert/13.prim_sync_alert.837246210
/workspace/coverage/sync_alert/14.prim_sync_alert.917384584
/workspace/coverage/sync_alert/15.prim_sync_alert.303933862
/workspace/coverage/sync_alert/16.prim_sync_alert.3294500178
/workspace/coverage/sync_alert/18.prim_sync_alert.2628622480
/workspace/coverage/sync_alert/19.prim_sync_alert.1724381688
/workspace/coverage/sync_alert/2.prim_sync_alert.1340556655
/workspace/coverage/sync_alert/3.prim_sync_alert.492585313
/workspace/coverage/sync_alert/4.prim_sync_alert.2173182908
/workspace/coverage/sync_alert/5.prim_sync_alert.3745237298
/workspace/coverage/sync_alert/6.prim_sync_alert.7558360
/workspace/coverage/sync_alert/7.prim_sync_alert.1135267899
/workspace/coverage/sync_alert/8.prim_sync_alert.3803181722
/workspace/coverage/sync_alert/9.prim_sync_alert.1867638660
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.171298781
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1258775442
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4235213229
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4109630553
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1376830834
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.318404665
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1758163945
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1634063801
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2399701009
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.540146233
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3814736172
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.760234475
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3863673849
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.623223336
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1753842895
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2265353462
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2378842640
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.913546548



Total test records in report: 78
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/10.prim_async_alert.109119971 Dec 20 12:16:43 PM PST 23 Dec 20 12:16:47 PM PST 23 11982407 ps
T2 /workspace/coverage/default/2.prim_async_alert.2969504242 Dec 20 12:16:45 PM PST 23 Dec 20 12:16:51 PM PST 23 10974420 ps
T3 /workspace/coverage/default/11.prim_async_alert.941910992 Dec 20 12:16:38 PM PST 23 Dec 20 12:16:45 PM PST 23 11145991 ps
T9 /workspace/coverage/default/17.prim_async_alert.1210525564 Dec 20 12:16:44 PM PST 23 Dec 20 12:16:50 PM PST 23 11213394 ps
T20 /workspace/coverage/default/12.prim_async_alert.2057693370 Dec 20 12:16:43 PM PST 23 Dec 20 12:16:47 PM PST 23 11270001 ps
T7 /workspace/coverage/default/6.prim_async_alert.2084823480 Dec 20 12:16:43 PM PST 23 Dec 20 12:16:47 PM PST 23 11832244 ps
T10 /workspace/coverage/default/18.prim_async_alert.2555574650 Dec 20 12:16:44 PM PST 23 Dec 20 12:16:50 PM PST 23 11190919 ps
T13 /workspace/coverage/default/5.prim_async_alert.2802419694 Dec 20 12:16:44 PM PST 23 Dec 20 12:16:49 PM PST 23 11894970 ps
T8 /workspace/coverage/default/7.prim_async_alert.1136144793 Dec 20 12:16:44 PM PST 23 Dec 20 12:16:50 PM PST 23 11334416 ps
T21 /workspace/coverage/default/0.prim_async_alert.1915559469 Dec 20 12:16:44 PM PST 23 Dec 20 12:16:49 PM PST 23 10939002 ps
T22 /workspace/coverage/default/16.prim_async_alert.1441641931 Dec 20 12:16:42 PM PST 23 Dec 20 12:16:47 PM PST 23 9855767 ps
T45 /workspace/coverage/default/8.prim_async_alert.2041543292 Dec 20 12:16:42 PM PST 23 Dec 20 12:16:47 PM PST 23 12370736 ps
T23 /workspace/coverage/default/19.prim_async_alert.3159244763 Dec 20 12:16:43 PM PST 23 Dec 20 12:16:47 PM PST 23 9978561 ps
T24 /workspace/coverage/default/9.prim_async_alert.2649695466 Dec 20 12:16:43 PM PST 23 Dec 20 12:16:47 PM PST 23 10753825 ps
T11 /workspace/coverage/default/3.prim_async_alert.3183805360 Dec 20 12:16:44 PM PST 23 Dec 20 12:16:49 PM PST 23 10656938 ps
T25 /workspace/coverage/default/15.prim_async_alert.878382347 Dec 20 12:16:43 PM PST 23 Dec 20 12:16:48 PM PST 23 10900614 ps
T46 /workspace/coverage/default/14.prim_async_alert.1462137304 Dec 20 12:16:43 PM PST 23 Dec 20 12:16:48 PM PST 23 11371807 ps
T47 /workspace/coverage/default/13.prim_async_alert.1121673022 Dec 20 12:16:44 PM PST 23 Dec 20 12:16:49 PM PST 23 11407717 ps
T48 /workspace/coverage/default/4.prim_async_alert.3981161125 Dec 20 12:16:42 PM PST 23 Dec 20 12:16:47 PM PST 23 12581863 ps
T18 /workspace/coverage/default/1.prim_async_alert.2829777969 Dec 20 12:16:44 PM PST 23 Dec 20 12:16:49 PM PST 23 10788932 ps
T26 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.878634786 Dec 20 12:18:38 PM PST 23 Dec 20 12:18:45 PM PST 23 30311536 ps
T39 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3732091093 Dec 20 12:18:33 PM PST 23 Dec 20 12:18:38 PM PST 23 29888693 ps
T40 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1430539818 Dec 20 12:18:39 PM PST 23 Dec 20 12:18:46 PM PST 23 28521443 ps
T41 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2368007551 Dec 20 12:18:45 PM PST 23 Dec 20 12:18:50 PM PST 23 30867427 ps
T16 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1409611516 Dec 20 12:18:43 PM PST 23 Dec 20 12:18:49 PM PST 23 29752172 ps
T42 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.353462622 Dec 20 12:18:39 PM PST 23 Dec 20 12:18:47 PM PST 23 31980272 ps
T43 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3440476126 Dec 20 12:18:28 PM PST 23 Dec 20 12:18:36 PM PST 23 31636360 ps
T37 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3407179655 Dec 20 12:18:46 PM PST 23 Dec 20 12:18:52 PM PST 23 28897920 ps
T17 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3498700448 Dec 20 12:18:44 PM PST 23 Dec 20 12:18:49 PM PST 23 31333352 ps
T44 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.126556037 Dec 20 12:18:39 PM PST 23 Dec 20 12:18:46 PM PST 23 30728079 ps
T49 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1965597790 Dec 20 12:18:39 PM PST 23 Dec 20 12:18:49 PM PST 23 28793166 ps
T4 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2101949584 Dec 20 12:18:39 PM PST 23 Dec 20 12:18:46 PM PST 23 30061055 ps
T50 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2976843134 Dec 20 12:18:43 PM PST 23 Dec 20 12:18:48 PM PST 23 31993282 ps
T5 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.99693763 Dec 20 12:18:38 PM PST 23 Dec 20 12:18:43 PM PST 23 29626812 ps
T38 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.45261601 Dec 20 12:18:48 PM PST 23 Dec 20 12:18:55 PM PST 23 29720337 ps
T51 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2909400564 Dec 20 12:18:40 PM PST 23 Dec 20 12:18:47 PM PST 23 28788815 ps
T52 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.105029322 Dec 20 12:18:40 PM PST 23 Dec 20 12:18:47 PM PST 23 30008138 ps
T6 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.722992630 Dec 20 12:18:43 PM PST 23 Dec 20 12:18:49 PM PST 23 29644131 ps
T35 /workspace/coverage/sync_alert/5.prim_sync_alert.3745237298 Dec 20 12:32:24 PM PST 23 Dec 20 12:33:06 PM PST 23 9975919 ps
T36 /workspace/coverage/sync_alert/15.prim_sync_alert.303933862 Dec 20 12:32:26 PM PST 23 Dec 20 12:33:08 PM PST 23 9364643 ps
T19 /workspace/coverage/sync_alert/19.prim_sync_alert.1724381688 Dec 20 12:32:33 PM PST 23 Dec 20 12:33:16 PM PST 23 9869289 ps
T27 /workspace/coverage/sync_alert/8.prim_sync_alert.3803181722 Dec 20 12:32:30 PM PST 23 Dec 20 12:33:13 PM PST 23 8475783 ps
T28 /workspace/coverage/sync_alert/9.prim_sync_alert.1867638660 Dec 20 12:32:28 PM PST 23 Dec 20 12:33:11 PM PST 23 8856552 ps
T29 /workspace/coverage/sync_alert/3.prim_sync_alert.492585313 Dec 20 12:34:05 PM PST 23 Dec 20 12:34:17 PM PST 23 8779565 ps
T30 /workspace/coverage/sync_alert/17.prim_sync_alert.1223353044 Dec 20 12:32:27 PM PST 23 Dec 20 12:33:11 PM PST 23 9238053 ps
T31 /workspace/coverage/sync_alert/2.prim_sync_alert.1340556655 Dec 20 12:33:03 PM PST 23 Dec 20 12:33:52 PM PST 23 9736694 ps
T32 /workspace/coverage/sync_alert/12.prim_sync_alert.1833645748 Dec 20 12:32:38 PM PST 23 Dec 20 12:33:28 PM PST 23 9086448 ps
T33 /workspace/coverage/sync_alert/4.prim_sync_alert.2173182908 Dec 20 12:32:58 PM PST 23 Dec 20 12:33:47 PM PST 23 9442759 ps
T34 /workspace/coverage/sync_alert/18.prim_sync_alert.2628622480 Dec 20 12:32:43 PM PST 23 Dec 20 12:33:28 PM PST 23 9178856 ps
T53 /workspace/coverage/sync_alert/10.prim_sync_alert.2823928767 Dec 20 12:32:35 PM PST 23 Dec 20 12:33:18 PM PST 23 10775831 ps
T54 /workspace/coverage/sync_alert/1.prim_sync_alert.3358040135 Dec 20 12:34:05 PM PST 23 Dec 20 12:34:17 PM PST 23 10459546 ps
T55 /workspace/coverage/sync_alert/13.prim_sync_alert.837246210 Dec 20 12:32:30 PM PST 23 Dec 20 12:33:13 PM PST 23 9636620 ps
T56 /workspace/coverage/sync_alert/14.prim_sync_alert.917384584 Dec 20 12:32:32 PM PST 23 Dec 20 12:33:16 PM PST 23 10655037 ps
T57 /workspace/coverage/sync_alert/7.prim_sync_alert.1135267899 Dec 20 12:33:01 PM PST 23 Dec 20 12:33:51 PM PST 23 8402029 ps
T58 /workspace/coverage/sync_alert/16.prim_sync_alert.3294500178 Dec 20 12:32:43 PM PST 23 Dec 20 12:33:28 PM PST 23 9778696 ps
T59 /workspace/coverage/sync_alert/0.prim_sync_alert.3187679309 Dec 20 12:32:30 PM PST 23 Dec 20 12:33:13 PM PST 23 9305802 ps
T60 /workspace/coverage/sync_alert/11.prim_sync_alert.133926555 Dec 20 12:34:01 PM PST 23 Dec 20 12:34:17 PM PST 23 8608668 ps
T61 /workspace/coverage/sync_alert/6.prim_sync_alert.7558360 Dec 20 12:32:36 PM PST 23 Dec 20 12:33:20 PM PST 23 8755607 ps
T62 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3814736172 Dec 20 12:18:42 PM PST 23 Dec 20 12:18:48 PM PST 23 27302387 ps
T63 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.913546548 Dec 20 12:18:43 PM PST 23 Dec 20 12:18:49 PM PST 23 27832535 ps
T64 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1634063801 Dec 20 12:18:37 PM PST 23 Dec 20 12:18:42 PM PST 23 25935432 ps
T65 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.540146233 Dec 20 12:18:43 PM PST 23 Dec 20 12:18:48 PM PST 23 29788769 ps
T66 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.623223336 Dec 20 12:18:28 PM PST 23 Dec 20 12:18:36 PM PST 23 28058322 ps
T67 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4109630553 Dec 20 12:18:43 PM PST 23 Dec 20 12:18:49 PM PST 23 27013031 ps
T14 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1831955214 Dec 20 12:18:39 PM PST 23 Dec 20 12:18:46 PM PST 23 28726287 ps
T68 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2399701009 Dec 20 12:18:43 PM PST 23 Dec 20 12:18:49 PM PST 23 27923684 ps
T69 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3863673849 Dec 20 12:18:39 PM PST 23 Dec 20 12:18:46 PM PST 23 28483951 ps
T70 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.760234475 Dec 20 12:18:38 PM PST 23 Dec 20 12:18:44 PM PST 23 26845421 ps
T71 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1758163945 Dec 20 12:18:38 PM PST 23 Dec 20 12:18:44 PM PST 23 26481802 ps
T72 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.318404665 Dec 20 12:18:39 PM PST 23 Dec 20 12:18:46 PM PST 23 27008849 ps
T73 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1258775442 Dec 20 12:18:44 PM PST 23 Dec 20 12:18:49 PM PST 23 27888761 ps
T74 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1376830834 Dec 20 12:18:39 PM PST 23 Dec 20 12:18:46 PM PST 23 29556424 ps
T15 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4235213229 Dec 20 12:18:43 PM PST 23 Dec 20 12:18:48 PM PST 23 28366903 ps
T75 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2378842640 Dec 20 12:18:37 PM PST 23 Dec 20 12:18:42 PM PST 23 27236765 ps
T12 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2349244964 Dec 20 12:18:39 PM PST 23 Dec 20 12:18:46 PM PST 23 26294923 ps
T76 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2265353462 Dec 20 12:18:43 PM PST 23 Dec 20 12:18:48 PM PST 23 26940153 ps
T77 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.171298781 Dec 20 12:18:24 PM PST 23 Dec 20 12:18:27 PM PST 23 26656029 ps
T78 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1753842895 Dec 20 12:18:37 PM PST 23 Dec 20 12:18:42 PM PST 23 29019795 ps

Test location /workspace/coverage/default/18.prim_async_alert.2555574650
Short name T10
Test name
Test status
Simulation time 11190919 ps
CPU time 0.42 seconds
Started Dec 20 12:16:44 PM PST 23
Finished Dec 20 12:16:50 PM PST 23
Peak memory 145500 kb
Host smart-d7a05da5-07f9-4583-bcab-bf8a45e16530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555574650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2555574650
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1223353044
Short name T30
Test name
Test status
Simulation time 9238053 ps
CPU time 0.37 seconds
Started Dec 20 12:32:27 PM PST 23
Finished Dec 20 12:33:11 PM PST 23
Peak memory 145076 kb
Host smart-5f18361a-f18e-4be4-9e49-0f643dfce107
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1223353044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1223353044
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.878634786
Short name T26
Test name
Test status
Simulation time 30311536 ps
CPU time 0.4 seconds
Started Dec 20 12:18:38 PM PST 23
Finished Dec 20 12:18:45 PM PST 23
Peak memory 145684 kb
Host smart-70a4b7ac-5fb6-4c36-98a3-ea508f3a7ce6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=878634786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.878634786
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1831955214
Short name T14
Test name
Test status
Simulation time 28726287 ps
CPU time 0.39 seconds
Started Dec 20 12:18:39 PM PST 23
Finished Dec 20 12:18:46 PM PST 23
Peak memory 145068 kb
Host smart-ecb1b410-0af2-424c-843c-c4007ef5549d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1831955214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1831955214
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.722992630
Short name T6
Test name
Test status
Simulation time 29644131 ps
CPU time 0.42 seconds
Started Dec 20 12:18:43 PM PST 23
Finished Dec 20 12:18:49 PM PST 23
Peak memory 145640 kb
Host smart-68ac6b79-7e14-4527-a4cd-4fb9d674be7f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=722992630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.722992630
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2349244964
Short name T12
Test name
Test status
Simulation time 26294923 ps
CPU time 0.39 seconds
Started Dec 20 12:18:39 PM PST 23
Finished Dec 20 12:18:46 PM PST 23
Peak memory 145084 kb
Host smart-b952dc70-57c3-4017-ba66-9d17b1671ffa
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2349244964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2349244964
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.1915559469
Short name T21
Test name
Test status
Simulation time 10939002 ps
CPU time 0.4 seconds
Started Dec 20 12:16:44 PM PST 23
Finished Dec 20 12:16:49 PM PST 23
Peak memory 145608 kb
Host smart-6a3fd330-98e4-4be7-a8c8-5332362f40b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915559469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1915559469
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2829777969
Short name T18
Test name
Test status
Simulation time 10788932 ps
CPU time 0.37 seconds
Started Dec 20 12:16:44 PM PST 23
Finished Dec 20 12:16:49 PM PST 23
Peak memory 146564 kb
Host smart-2424405d-8018-4dc7-b771-98fa4023cc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829777969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2829777969
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.109119971
Short name T1
Test name
Test status
Simulation time 11982407 ps
CPU time 0.37 seconds
Started Dec 20 12:16:43 PM PST 23
Finished Dec 20 12:16:47 PM PST 23
Peak memory 145536 kb
Host smart-56ff3018-e5a6-41b4-911b-d0611cd9d9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109119971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.109119971
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.941910992
Short name T3
Test name
Test status
Simulation time 11145991 ps
CPU time 0.39 seconds
Started Dec 20 12:16:38 PM PST 23
Finished Dec 20 12:16:45 PM PST 23
Peak memory 145612 kb
Host smart-e162323c-75e6-423f-a5b0-5ed91f7bcae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941910992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.941910992
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2057693370
Short name T20
Test name
Test status
Simulation time 11270001 ps
CPU time 0.37 seconds
Started Dec 20 12:16:43 PM PST 23
Finished Dec 20 12:16:47 PM PST 23
Peak memory 145536 kb
Host smart-4b1ddb72-c962-4efe-a677-378522f6d7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057693370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2057693370
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.1121673022
Short name T47
Test name
Test status
Simulation time 11407717 ps
CPU time 0.37 seconds
Started Dec 20 12:16:44 PM PST 23
Finished Dec 20 12:16:49 PM PST 23
Peak memory 145536 kb
Host smart-d05db8ff-e46e-4ca6-94a3-c126a82fb818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121673022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1121673022
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.1462137304
Short name T46
Test name
Test status
Simulation time 11371807 ps
CPU time 0.39 seconds
Started Dec 20 12:16:43 PM PST 23
Finished Dec 20 12:16:48 PM PST 23
Peak memory 145536 kb
Host smart-4fdd0410-9b2d-4e04-9dd1-2aee4c68a552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462137304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1462137304
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.878382347
Short name T25
Test name
Test status
Simulation time 10900614 ps
CPU time 0.38 seconds
Started Dec 20 12:16:43 PM PST 23
Finished Dec 20 12:16:48 PM PST 23
Peak memory 145536 kb
Host smart-97721e61-c9fa-4e91-b776-3aefa3e519b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878382347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.878382347
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.1441641931
Short name T22
Test name
Test status
Simulation time 9855767 ps
CPU time 0.38 seconds
Started Dec 20 12:16:42 PM PST 23
Finished Dec 20 12:16:47 PM PST 23
Peak memory 145216 kb
Host smart-cd55fd6f-e27d-4855-a07b-7c7d8b75e8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441641931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1441641931
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1210525564
Short name T9
Test name
Test status
Simulation time 11213394 ps
CPU time 0.38 seconds
Started Dec 20 12:16:44 PM PST 23
Finished Dec 20 12:16:50 PM PST 23
Peak memory 145500 kb
Host smart-3680feda-d08d-44da-857d-50641b5bbb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210525564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1210525564
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3159244763
Short name T23
Test name
Test status
Simulation time 9978561 ps
CPU time 0.39 seconds
Started Dec 20 12:16:43 PM PST 23
Finished Dec 20 12:16:47 PM PST 23
Peak memory 145480 kb
Host smart-4b6652be-5302-45d9-bea5-324d54025399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159244763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3159244763
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.2969504242
Short name T2
Test name
Test status
Simulation time 10974420 ps
CPU time 0.38 seconds
Started Dec 20 12:16:45 PM PST 23
Finished Dec 20 12:16:51 PM PST 23
Peak memory 145608 kb
Host smart-53998709-f1e5-40df-962e-248a5051307c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969504242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2969504242
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.3183805360
Short name T11
Test name
Test status
Simulation time 10656938 ps
CPU time 0.38 seconds
Started Dec 20 12:16:44 PM PST 23
Finished Dec 20 12:16:49 PM PST 23
Peak memory 145748 kb
Host smart-574852af-9363-4e49-9a94-972c8dcd0c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183805360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3183805360
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.3981161125
Short name T48
Test name
Test status
Simulation time 12581863 ps
CPU time 0.38 seconds
Started Dec 20 12:16:42 PM PST 23
Finished Dec 20 12:16:47 PM PST 23
Peak memory 145524 kb
Host smart-6bfe8704-f987-443b-8fa2-d308f993d566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981161125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3981161125
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2802419694
Short name T13
Test name
Test status
Simulation time 11894970 ps
CPU time 0.41 seconds
Started Dec 20 12:16:44 PM PST 23
Finished Dec 20 12:16:49 PM PST 23
Peak memory 145568 kb
Host smart-64a8d525-7072-411a-b4a3-0a9c2ec32f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802419694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2802419694
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.2084823480
Short name T7
Test name
Test status
Simulation time 11832244 ps
CPU time 0.37 seconds
Started Dec 20 12:16:43 PM PST 23
Finished Dec 20 12:16:47 PM PST 23
Peak memory 145532 kb
Host smart-2dcb08c5-5595-4afb-8436-77c761c42f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084823480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2084823480
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1136144793
Short name T8
Test name
Test status
Simulation time 11334416 ps
CPU time 0.42 seconds
Started Dec 20 12:16:44 PM PST 23
Finished Dec 20 12:16:50 PM PST 23
Peak memory 145496 kb
Host smart-2eff515d-fda0-465a-a204-5d2969030ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136144793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1136144793
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2041543292
Short name T45
Test name
Test status
Simulation time 12370736 ps
CPU time 0.37 seconds
Started Dec 20 12:16:42 PM PST 23
Finished Dec 20 12:16:47 PM PST 23
Peak memory 145168 kb
Host smart-85bd84d6-fe57-42e7-a826-a6704e176305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041543292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2041543292
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2649695466
Short name T24
Test name
Test status
Simulation time 10753825 ps
CPU time 0.39 seconds
Started Dec 20 12:16:43 PM PST 23
Finished Dec 20 12:16:47 PM PST 23
Peak memory 145496 kb
Host smart-d402cf6d-0581-45e6-9a2e-7156fb87184a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649695466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2649695466
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.45261601
Short name T38
Test name
Test status
Simulation time 29720337 ps
CPU time 0.4 seconds
Started Dec 20 12:18:48 PM PST 23
Finished Dec 20 12:18:55 PM PST 23
Peak memory 145708 kb
Host smart-5dd4e8f4-4603-47de-a202-ca467260d2fa
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=45261601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.45261601
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2368007551
Short name T41
Test name
Test status
Simulation time 30867427 ps
CPU time 0.39 seconds
Started Dec 20 12:18:45 PM PST 23
Finished Dec 20 12:18:50 PM PST 23
Peak memory 145716 kb
Host smart-75942fa8-b057-4f53-af78-8f8f72145323
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2368007551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2368007551
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3498700448
Short name T17
Test name
Test status
Simulation time 31333352 ps
CPU time 0.4 seconds
Started Dec 20 12:18:44 PM PST 23
Finished Dec 20 12:18:49 PM PST 23
Peak memory 145704 kb
Host smart-845af068-17bb-43db-bc64-c242eeb58b48
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3498700448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3498700448
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3407179655
Short name T37
Test name
Test status
Simulation time 28897920 ps
CPU time 0.39 seconds
Started Dec 20 12:18:46 PM PST 23
Finished Dec 20 12:18:52 PM PST 23
Peak memory 145716 kb
Host smart-e84e294c-973b-457c-842a-a12f76f8cf3f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3407179655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3407179655
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2976843134
Short name T50
Test name
Test status
Simulation time 31993282 ps
CPU time 0.44 seconds
Started Dec 20 12:18:43 PM PST 23
Finished Dec 20 12:18:48 PM PST 23
Peak memory 145528 kb
Host smart-15fdc5c7-e654-4bd3-9f5d-e06afd17918a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2976843134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2976843134
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.126556037
Short name T44
Test name
Test status
Simulation time 30728079 ps
CPU time 0.41 seconds
Started Dec 20 12:18:39 PM PST 23
Finished Dec 20 12:18:46 PM PST 23
Peak memory 145664 kb
Host smart-14511680-119a-4e08-8701-08fbab98a7c4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=126556037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.126556037
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.105029322
Short name T52
Test name
Test status
Simulation time 30008138 ps
CPU time 0.42 seconds
Started Dec 20 12:18:40 PM PST 23
Finished Dec 20 12:18:47 PM PST 23
Peak memory 145680 kb
Host smart-f14454d9-d634-4828-a420-529fdae14570
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=105029322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.105029322
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1430539818
Short name T40
Test name
Test status
Simulation time 28521443 ps
CPU time 0.39 seconds
Started Dec 20 12:18:39 PM PST 23
Finished Dec 20 12:18:46 PM PST 23
Peak memory 145660 kb
Host smart-450f888e-0f35-43f0-8745-2ea79b8637f7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1430539818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1430539818
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2909400564
Short name T51
Test name
Test status
Simulation time 28788815 ps
CPU time 0.4 seconds
Started Dec 20 12:18:40 PM PST 23
Finished Dec 20 12:18:47 PM PST 23
Peak memory 145600 kb
Host smart-af76e016-dcba-4ca3-ba4c-754c2cf9b915
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2909400564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2909400564
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3732091093
Short name T39
Test name
Test status
Simulation time 29888693 ps
CPU time 0.4 seconds
Started Dec 20 12:18:33 PM PST 23
Finished Dec 20 12:18:38 PM PST 23
Peak memory 145632 kb
Host smart-112b20c7-d5a9-489a-bfde-e96f8f8285cd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3732091093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3732091093
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1409611516
Short name T16
Test name
Test status
Simulation time 29752172 ps
CPU time 0.47 seconds
Started Dec 20 12:18:43 PM PST 23
Finished Dec 20 12:18:49 PM PST 23
Peak memory 145668 kb
Host smart-68cb2ee4-1d01-4cce-9048-395bc29962da
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1409611516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1409611516
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2101949584
Short name T4
Test name
Test status
Simulation time 30061055 ps
CPU time 0.39 seconds
Started Dec 20 12:18:39 PM PST 23
Finished Dec 20 12:18:46 PM PST 23
Peak memory 145660 kb
Host smart-4785e546-0618-4600-856a-8dfa87db076b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2101949584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2101949584
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.99693763
Short name T5
Test name
Test status
Simulation time 29626812 ps
CPU time 0.38 seconds
Started Dec 20 12:18:38 PM PST 23
Finished Dec 20 12:18:43 PM PST 23
Peak memory 145704 kb
Host smart-55ea85b4-6647-4793-b9d3-e74b3951e491
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=99693763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.99693763
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3440476126
Short name T43
Test name
Test status
Simulation time 31636360 ps
CPU time 0.39 seconds
Started Dec 20 12:18:28 PM PST 23
Finished Dec 20 12:18:36 PM PST 23
Peak memory 145688 kb
Host smart-7c38f1ab-ed9d-4646-8aba-cce3af0277b6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3440476126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3440476126
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1965597790
Short name T49
Test name
Test status
Simulation time 28793166 ps
CPU time 0.4 seconds
Started Dec 20 12:18:39 PM PST 23
Finished Dec 20 12:18:49 PM PST 23
Peak memory 145660 kb
Host smart-f246aa79-3469-4b3d-86fa-1e851a5fbd13
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1965597790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1965597790
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.353462622
Short name T42
Test name
Test status
Simulation time 31980272 ps
CPU time 0.43 seconds
Started Dec 20 12:18:39 PM PST 23
Finished Dec 20 12:18:47 PM PST 23
Peak memory 145664 kb
Host smart-5b0f18a0-7e80-4e1d-89a9-96cde463d2af
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=353462622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.353462622
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3187679309
Short name T59
Test name
Test status
Simulation time 9305802 ps
CPU time 0.37 seconds
Started Dec 20 12:32:30 PM PST 23
Finished Dec 20 12:33:13 PM PST 23
Peak memory 144996 kb
Host smart-bd83722f-465c-498c-b98e-a050c8d467d1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3187679309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3187679309
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3358040135
Short name T54
Test name
Test status
Simulation time 10459546 ps
CPU time 0.48 seconds
Started Dec 20 12:34:05 PM PST 23
Finished Dec 20 12:34:17 PM PST 23
Peak memory 142788 kb
Host smart-16f4decb-9896-4125-b1c8-3aa00e375861
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3358040135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3358040135
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.2823928767
Short name T53
Test name
Test status
Simulation time 10775831 ps
CPU time 0.37 seconds
Started Dec 20 12:32:35 PM PST 23
Finished Dec 20 12:33:18 PM PST 23
Peak memory 145028 kb
Host smart-6ad80c86-ca10-4590-abac-3df910d1cc9a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2823928767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2823928767
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.133926555
Short name T60
Test name
Test status
Simulation time 8608668 ps
CPU time 0.42 seconds
Started Dec 20 12:34:01 PM PST 23
Finished Dec 20 12:34:17 PM PST 23
Peak memory 143324 kb
Host smart-9a47a4b3-5365-467d-bf3b-92793f2f7d14
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=133926555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.133926555
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.1833645748
Short name T32
Test name
Test status
Simulation time 9086448 ps
CPU time 0.37 seconds
Started Dec 20 12:32:38 PM PST 23
Finished Dec 20 12:33:28 PM PST 23
Peak memory 145028 kb
Host smart-fd3ca939-e300-44c8-9b36-046c5746924c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1833645748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1833645748
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.837246210
Short name T55
Test name
Test status
Simulation time 9636620 ps
CPU time 0.37 seconds
Started Dec 20 12:32:30 PM PST 23
Finished Dec 20 12:33:13 PM PST 23
Peak memory 145080 kb
Host smart-50ca3efd-7751-49be-a7a2-e2bf397dae4d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=837246210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.837246210
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.917384584
Short name T56
Test name
Test status
Simulation time 10655037 ps
CPU time 0.37 seconds
Started Dec 20 12:32:32 PM PST 23
Finished Dec 20 12:33:16 PM PST 23
Peak memory 145036 kb
Host smart-ec74b0f5-13cc-4119-aa95-eca4ae89251b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=917384584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.917384584
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.303933862
Short name T36
Test name
Test status
Simulation time 9364643 ps
CPU time 0.38 seconds
Started Dec 20 12:32:26 PM PST 23
Finished Dec 20 12:33:08 PM PST 23
Peak memory 145044 kb
Host smart-59f58fbe-0d19-4ab9-be12-7853c46f3de8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=303933862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.303933862
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3294500178
Short name T58
Test name
Test status
Simulation time 9778696 ps
CPU time 0.38 seconds
Started Dec 20 12:32:43 PM PST 23
Finished Dec 20 12:33:28 PM PST 23
Peak memory 145028 kb
Host smart-cb17d843-51ec-4386-a775-e398f76b9a0a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3294500178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3294500178
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2628622480
Short name T34
Test name
Test status
Simulation time 9178856 ps
CPU time 0.37 seconds
Started Dec 20 12:32:43 PM PST 23
Finished Dec 20 12:33:28 PM PST 23
Peak memory 145000 kb
Host smart-42ffbffe-a032-4e25-99ef-953696e66697
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2628622480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2628622480
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.1724381688
Short name T19
Test name
Test status
Simulation time 9869289 ps
CPU time 0.38 seconds
Started Dec 20 12:32:33 PM PST 23
Finished Dec 20 12:33:16 PM PST 23
Peak memory 145076 kb
Host smart-3ae32e03-43a6-4472-be5e-9b5fe367922e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1724381688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1724381688
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1340556655
Short name T31
Test name
Test status
Simulation time 9736694 ps
CPU time 0.37 seconds
Started Dec 20 12:33:03 PM PST 23
Finished Dec 20 12:33:52 PM PST 23
Peak memory 145056 kb
Host smart-6fa873b3-dcd6-465c-9756-337a39f330fd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1340556655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1340556655
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.492585313
Short name T29
Test name
Test status
Simulation time 8779565 ps
CPU time 0.47 seconds
Started Dec 20 12:34:05 PM PST 23
Finished Dec 20 12:34:17 PM PST 23
Peak memory 142712 kb
Host smart-66f9eda7-f002-498c-8c7d-5d92a27065f6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=492585313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.492585313
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.2173182908
Short name T33
Test name
Test status
Simulation time 9442759 ps
CPU time 0.39 seconds
Started Dec 20 12:32:58 PM PST 23
Finished Dec 20 12:33:47 PM PST 23
Peak memory 145016 kb
Host smart-423ed55f-0412-4e73-a537-9d1a59d778d4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2173182908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2173182908
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.3745237298
Short name T35
Test name
Test status
Simulation time 9975919 ps
CPU time 0.36 seconds
Started Dec 20 12:32:24 PM PST 23
Finished Dec 20 12:33:06 PM PST 23
Peak memory 144964 kb
Host smart-07f3eb01-e352-41c5-b06a-dcddf4eaa954
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3745237298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3745237298
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.7558360
Short name T61
Test name
Test status
Simulation time 8755607 ps
CPU time 0.37 seconds
Started Dec 20 12:32:36 PM PST 23
Finished Dec 20 12:33:20 PM PST 23
Peak memory 145036 kb
Host smart-0b76bd6d-3392-4331-8b20-49fdedc45ea7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=7558360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.7558360
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1135267899
Short name T57
Test name
Test status
Simulation time 8402029 ps
CPU time 0.37 seconds
Started Dec 20 12:33:01 PM PST 23
Finished Dec 20 12:33:51 PM PST 23
Peak memory 145048 kb
Host smart-05443319-b5a5-45fb-8747-5229a46f3f9f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1135267899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1135267899
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.3803181722
Short name T27
Test name
Test status
Simulation time 8475783 ps
CPU time 0.38 seconds
Started Dec 20 12:32:30 PM PST 23
Finished Dec 20 12:33:13 PM PST 23
Peak memory 145088 kb
Host smart-eda578d4-e8f0-4fac-9870-a5d4f4f1e0a9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3803181722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3803181722
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1867638660
Short name T28
Test name
Test status
Simulation time 8856552 ps
CPU time 0.41 seconds
Started Dec 20 12:32:28 PM PST 23
Finished Dec 20 12:33:11 PM PST 23
Peak memory 145048 kb
Host smart-1af3c6ea-0372-4f8c-a214-e815f0d0fc19
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1867638660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1867638660
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.171298781
Short name T77
Test name
Test status
Simulation time 26656029 ps
CPU time 0.41 seconds
Started Dec 20 12:18:24 PM PST 23
Finished Dec 20 12:18:27 PM PST 23
Peak memory 144952 kb
Host smart-b9b00933-5680-4e92-8f09-1353c8cb4fdc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=171298781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.171298781
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1258775442
Short name T73
Test name
Test status
Simulation time 27888761 ps
CPU time 0.39 seconds
Started Dec 20 12:18:44 PM PST 23
Finished Dec 20 12:18:49 PM PST 23
Peak memory 145036 kb
Host smart-9d678bf5-a2bd-46d1-b307-b654f0ab84b8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1258775442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1258775442
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4235213229
Short name T15
Test name
Test status
Simulation time 28366903 ps
CPU time 0.43 seconds
Started Dec 20 12:18:43 PM PST 23
Finished Dec 20 12:18:48 PM PST 23
Peak memory 144880 kb
Host smart-b108c4a8-fb47-4281-b824-0b1bd380ab4c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4235213229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.4235213229
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4109630553
Short name T67
Test name
Test status
Simulation time 27013031 ps
CPU time 0.43 seconds
Started Dec 20 12:18:43 PM PST 23
Finished Dec 20 12:18:49 PM PST 23
Peak memory 144744 kb
Host smart-d8e464a1-d159-4f2e-8486-129f6ef239d5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4109630553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.4109630553
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1376830834
Short name T74
Test name
Test status
Simulation time 29556424 ps
CPU time 0.39 seconds
Started Dec 20 12:18:39 PM PST 23
Finished Dec 20 12:18:46 PM PST 23
Peak memory 145068 kb
Host smart-a6bb4d97-2a72-4a63-8319-8ba3f877168d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1376830834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1376830834
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.318404665
Short name T72
Test name
Test status
Simulation time 27008849 ps
CPU time 0.38 seconds
Started Dec 20 12:18:39 PM PST 23
Finished Dec 20 12:18:46 PM PST 23
Peak memory 145068 kb
Host smart-abf37093-0427-4e60-a573-39b85e5b28d7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=318404665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.318404665
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1758163945
Short name T71
Test name
Test status
Simulation time 26481802 ps
CPU time 0.38 seconds
Started Dec 20 12:18:38 PM PST 23
Finished Dec 20 12:18:44 PM PST 23
Peak memory 145136 kb
Host smart-c52e2bb3-9bb5-4bdc-81be-7fb61be466e1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1758163945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1758163945
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1634063801
Short name T64
Test name
Test status
Simulation time 25935432 ps
CPU time 0.39 seconds
Started Dec 20 12:18:37 PM PST 23
Finished Dec 20 12:18:42 PM PST 23
Peak memory 145136 kb
Host smart-59f5eb77-e762-4de3-b44c-f1d847dd5ffd
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1634063801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1634063801
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2399701009
Short name T68
Test name
Test status
Simulation time 27923684 ps
CPU time 0.39 seconds
Started Dec 20 12:18:43 PM PST 23
Finished Dec 20 12:18:49 PM PST 23
Peak memory 145036 kb
Host smart-7c8a1b7c-58ae-4c61-a65c-35d81fb54766
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2399701009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2399701009
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.540146233
Short name T65
Test name
Test status
Simulation time 29788769 ps
CPU time 0.44 seconds
Started Dec 20 12:18:43 PM PST 23
Finished Dec 20 12:18:48 PM PST 23
Peak memory 144836 kb
Host smart-dd581924-8ca0-43f8-8967-cc4d247f7a5a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=540146233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.540146233
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3814736172
Short name T62
Test name
Test status
Simulation time 27302387 ps
CPU time 0.39 seconds
Started Dec 20 12:18:42 PM PST 23
Finished Dec 20 12:18:48 PM PST 23
Peak memory 145036 kb
Host smart-13ff1a3b-c4d8-4165-9838-1783b588a7cf
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3814736172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3814736172
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.760234475
Short name T70
Test name
Test status
Simulation time 26845421 ps
CPU time 0.39 seconds
Started Dec 20 12:18:38 PM PST 23
Finished Dec 20 12:18:44 PM PST 23
Peak memory 145104 kb
Host smart-6b78f64c-1705-4946-8dc6-2e30039be9d2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=760234475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.760234475
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3863673849
Short name T69
Test name
Test status
Simulation time 28483951 ps
CPU time 0.39 seconds
Started Dec 20 12:18:39 PM PST 23
Finished Dec 20 12:18:46 PM PST 23
Peak memory 145072 kb
Host smart-62b327b5-4b49-4128-8175-8e5a76034abb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3863673849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3863673849
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.623223336
Short name T66
Test name
Test status
Simulation time 28058322 ps
CPU time 0.38 seconds
Started Dec 20 12:18:28 PM PST 23
Finished Dec 20 12:18:36 PM PST 23
Peak memory 145064 kb
Host smart-e0439521-8d50-4838-aef2-42b937f4dfcd
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=623223336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.623223336
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1753842895
Short name T78
Test name
Test status
Simulation time 29019795 ps
CPU time 0.41 seconds
Started Dec 20 12:18:37 PM PST 23
Finished Dec 20 12:18:42 PM PST 23
Peak memory 145132 kb
Host smart-a25dbd48-c46c-4d25-876e-4d5d31906558
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1753842895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1753842895
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2265353462
Short name T76
Test name
Test status
Simulation time 26940153 ps
CPU time 0.43 seconds
Started Dec 20 12:18:43 PM PST 23
Finished Dec 20 12:18:48 PM PST 23
Peak memory 144836 kb
Host smart-89706326-c6e0-46b3-8a3c-3e9ec560047b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2265353462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2265353462
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2378842640
Short name T75
Test name
Test status
Simulation time 27236765 ps
CPU time 0.39 seconds
Started Dec 20 12:18:37 PM PST 23
Finished Dec 20 12:18:42 PM PST 23
Peak memory 145132 kb
Host smart-aa0d1f21-e9e0-472f-9107-a900202d9151
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2378842640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2378842640
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.913546548
Short name T63
Test name
Test status
Simulation time 27832535 ps
CPU time 0.43 seconds
Started Dec 20 12:18:43 PM PST 23
Finished Dec 20 12:18:49 PM PST 23
Peak memory 145056 kb
Host smart-aeb2e28b-d459-44e4-bead-94343d0c23b6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=913546548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.913546548
Directory /workspace/9.prim_sync_fatal_alert/latest
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