Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.92 88.92 100.00 100.00 91.67 91.67 100.00 100.00 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/2.prim_async_alert.3602209227
92.64 3.72 100.00 0.00 91.67 0.00 100.00 0.00 89.29 10.71 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/5.prim_sync_alert.2825046193
94.50 1.86 100.00 0.00 95.83 4.17 100.00 0.00 89.29 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.646837177
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/default/0.prim_async_alert.1571575405
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/15.prim_sync_alert.1629836072

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_async_alert.3382488960
/workspace/coverage/default/10.prim_async_alert.341655432
/workspace/coverage/default/11.prim_async_alert.3766455803
/workspace/coverage/default/12.prim_async_alert.3387517739
/workspace/coverage/default/13.prim_async_alert.2670001686
/workspace/coverage/default/14.prim_async_alert.1120240892
/workspace/coverage/default/15.prim_async_alert.3973941537
/workspace/coverage/default/16.prim_async_alert.1384285602
/workspace/coverage/default/17.prim_async_alert.2177642253
/workspace/coverage/default/18.prim_async_alert.2382238553
/workspace/coverage/default/19.prim_async_alert.305906123
/workspace/coverage/default/3.prim_async_alert.395262963
/workspace/coverage/default/4.prim_async_alert.3632885356
/workspace/coverage/default/5.prim_async_alert.1811302505
/workspace/coverage/default/6.prim_async_alert.3663422930
/workspace/coverage/default/7.prim_async_alert.4043482866
/workspace/coverage/default/8.prim_async_alert.1551372192
/workspace/coverage/default/9.prim_async_alert.764856618
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3332034464
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2686447598
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2163789951
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1379103102
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2072902484
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2810244632
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1018181445
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3626995841
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2001762522
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3799426211
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3309468216
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1982874475
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1490617169
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1432536276
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2475128192
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.956400147
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3062200149
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.882486595
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.365799665
/workspace/coverage/sync_alert/0.prim_sync_alert.916529727
/workspace/coverage/sync_alert/1.prim_sync_alert.3763332472
/workspace/coverage/sync_alert/10.prim_sync_alert.828061483
/workspace/coverage/sync_alert/11.prim_sync_alert.2954769929
/workspace/coverage/sync_alert/12.prim_sync_alert.907081133
/workspace/coverage/sync_alert/13.prim_sync_alert.3568545668
/workspace/coverage/sync_alert/14.prim_sync_alert.380913577
/workspace/coverage/sync_alert/16.prim_sync_alert.475432166
/workspace/coverage/sync_alert/17.prim_sync_alert.1546672875
/workspace/coverage/sync_alert/18.prim_sync_alert.2740269798
/workspace/coverage/sync_alert/19.prim_sync_alert.1945884876
/workspace/coverage/sync_alert/2.prim_sync_alert.2347004203
/workspace/coverage/sync_alert/3.prim_sync_alert.2226154092
/workspace/coverage/sync_alert/4.prim_sync_alert.700551002
/workspace/coverage/sync_alert/6.prim_sync_alert.679698160
/workspace/coverage/sync_alert/7.prim_sync_alert.1691953681
/workspace/coverage/sync_alert/8.prim_sync_alert.1220274272
/workspace/coverage/sync_alert/9.prim_sync_alert.616668674
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3348886051
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1262124408
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3724949527
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3181761767
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1229148831
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3270712176
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.340344359
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3925457
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2444061444
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1868626768
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2154871022
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2871673936
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3296990427
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3264658010
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2000886839
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1597927677
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2698266375
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1639039620
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2893627996
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3808745848



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/8.prim_async_alert.1551372192 Dec 24 12:30:03 PM PST 23 Dec 24 12:30:29 PM PST 23 10849097 ps
T2 /workspace/coverage/default/2.prim_async_alert.3602209227 Dec 24 12:31:13 PM PST 23 Dec 24 12:31:35 PM PST 23 11774106 ps
T3 /workspace/coverage/default/6.prim_async_alert.3663422930 Dec 24 12:29:37 PM PST 23 Dec 24 12:29:54 PM PST 23 10782962 ps
T13 /workspace/coverage/default/11.prim_async_alert.3766455803 Dec 24 12:30:18 PM PST 23 Dec 24 12:30:40 PM PST 23 12299369 ps
T16 /workspace/coverage/default/18.prim_async_alert.2382238553 Dec 24 12:31:01 PM PST 23 Dec 24 12:31:22 PM PST 23 10912564 ps
T7 /workspace/coverage/default/10.prim_async_alert.341655432 Dec 24 12:29:55 PM PST 23 Dec 24 12:30:20 PM PST 23 11690281 ps
T19 /workspace/coverage/default/17.prim_async_alert.2177642253 Dec 24 12:30:12 PM PST 23 Dec 24 12:30:36 PM PST 23 10738137 ps
T10 /workspace/coverage/default/19.prim_async_alert.305906123 Dec 24 12:29:53 PM PST 23 Dec 24 12:30:20 PM PST 23 10975665 ps
T20 /workspace/coverage/default/16.prim_async_alert.1384285602 Dec 24 12:30:13 PM PST 23 Dec 24 12:30:37 PM PST 23 10848234 ps
T8 /workspace/coverage/default/12.prim_async_alert.3387517739 Dec 24 12:29:54 PM PST 23 Dec 24 12:30:20 PM PST 23 11113442 ps
T11 /workspace/coverage/default/0.prim_async_alert.1571575405 Dec 24 12:30:34 PM PST 23 Dec 24 12:31:01 PM PST 23 11293892 ps
T9 /workspace/coverage/default/5.prim_async_alert.1811302505 Dec 24 12:30:20 PM PST 23 Dec 24 12:30:42 PM PST 23 11231048 ps
T44 /workspace/coverage/default/1.prim_async_alert.3382488960 Dec 24 12:29:56 PM PST 23 Dec 24 12:30:22 PM PST 23 12053006 ps
T21 /workspace/coverage/default/15.prim_async_alert.3973941537 Dec 24 12:29:48 PM PST 23 Dec 24 12:30:11 PM PST 23 11552175 ps
T18 /workspace/coverage/default/7.prim_async_alert.4043482866 Dec 24 12:29:43 PM PST 23 Dec 24 12:30:04 PM PST 23 11798814 ps
T17 /workspace/coverage/default/4.prim_async_alert.3632885356 Dec 24 12:30:34 PM PST 23 Dec 24 12:31:01 PM PST 23 12592903 ps
T45 /workspace/coverage/default/3.prim_async_alert.395262963 Dec 24 12:31:16 PM PST 23 Dec 24 12:31:39 PM PST 23 11883577 ps
T46 /workspace/coverage/default/14.prim_async_alert.1120240892 Dec 24 12:30:18 PM PST 23 Dec 24 12:30:40 PM PST 23 11488218 ps
T22 /workspace/coverage/default/13.prim_async_alert.2670001686 Dec 24 12:29:57 PM PST 23 Dec 24 12:30:24 PM PST 23 10499491 ps
T47 /workspace/coverage/default/9.prim_async_alert.764856618 Dec 24 12:30:03 PM PST 23 Dec 24 12:30:29 PM PST 23 10998082 ps
T23 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1018181445 Dec 24 12:30:25 PM PST 23 Dec 24 12:30:50 PM PST 23 26818864 ps
T36 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1379103102 Dec 24 12:30:13 PM PST 23 Dec 24 12:30:37 PM PST 23 30671754 ps
T37 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1490617169 Dec 24 12:30:00 PM PST 23 Dec 24 12:30:26 PM PST 23 30921410 ps
T4 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.646837177 Dec 24 12:30:32 PM PST 23 Dec 24 12:30:59 PM PST 23 29961034 ps
T38 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.882486595 Dec 24 12:30:19 PM PST 23 Dec 24 12:30:42 PM PST 23 28088090 ps
T39 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.956400147 Dec 24 12:30:11 PM PST 23 Dec 24 12:30:36 PM PST 23 31310590 ps
T40 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1432536276 Dec 24 12:30:06 PM PST 23 Dec 24 12:30:31 PM PST 23 31119474 ps
T41 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2001762522 Dec 24 12:29:47 PM PST 23 Dec 24 12:30:11 PM PST 23 29994887 ps
T42 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3626995841 Dec 24 12:30:24 PM PST 23 Dec 24 12:30:47 PM PST 23 31148019 ps
T43 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3332034464 Dec 24 12:29:36 PM PST 23 Dec 24 12:29:53 PM PST 23 30712169 ps
T48 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.365799665 Dec 24 12:30:05 PM PST 23 Dec 24 12:30:30 PM PST 23 29867892 ps
T14 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2072902484 Dec 24 12:30:24 PM PST 23 Dec 24 12:30:48 PM PST 23 31376235 ps
T49 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2810244632 Dec 24 12:30:26 PM PST 23 Dec 24 12:30:51 PM PST 23 29248231 ps
T50 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1982874475 Dec 24 12:30:16 PM PST 23 Dec 24 12:30:39 PM PST 23 31005798 ps
T51 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2475128192 Dec 24 12:30:25 PM PST 23 Dec 24 12:30:50 PM PST 23 30377692 ps
T52 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2163789951 Dec 24 12:30:07 PM PST 23 Dec 24 12:30:33 PM PST 23 30936821 ps
T15 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3062200149 Dec 24 12:30:30 PM PST 23 Dec 24 12:30:57 PM PST 23 30192056 ps
T53 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2686447598 Dec 24 12:30:22 PM PST 23 Dec 24 12:30:45 PM PST 23 31826823 ps
T54 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3799426211 Dec 24 12:30:25 PM PST 23 Dec 24 12:30:50 PM PST 23 29700645 ps
T55 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3309468216 Dec 24 12:30:34 PM PST 23 Dec 24 12:31:01 PM PST 23 29333333 ps
T34 /workspace/coverage/sync_alert/5.prim_sync_alert.2825046193 Dec 24 12:48:04 PM PST 23 Dec 24 12:48:06 PM PST 23 9349654 ps
T35 /workspace/coverage/sync_alert/8.prim_sync_alert.1220274272 Dec 24 12:47:58 PM PST 23 Dec 24 12:48:01 PM PST 23 8149564 ps
T24 /workspace/coverage/sync_alert/7.prim_sync_alert.1691953681 Dec 24 12:48:00 PM PST 23 Dec 24 12:48:03 PM PST 23 10024175 ps
T25 /workspace/coverage/sync_alert/6.prim_sync_alert.679698160 Dec 24 12:48:07 PM PST 23 Dec 24 12:48:11 PM PST 23 9533133 ps
T26 /workspace/coverage/sync_alert/18.prim_sync_alert.2740269798 Dec 24 12:48:07 PM PST 23 Dec 24 12:48:11 PM PST 23 8820259 ps
T27 /workspace/coverage/sync_alert/19.prim_sync_alert.1945884876 Dec 24 12:48:09 PM PST 23 Dec 24 12:48:12 PM PST 23 8441790 ps
T28 /workspace/coverage/sync_alert/4.prim_sync_alert.700551002 Dec 24 12:48:01 PM PST 23 Dec 24 12:48:04 PM PST 23 10246769 ps
T29 /workspace/coverage/sync_alert/12.prim_sync_alert.907081133 Dec 24 12:48:13 PM PST 23 Dec 24 12:48:15 PM PST 23 9822214 ps
T30 /workspace/coverage/sync_alert/10.prim_sync_alert.828061483 Dec 24 12:48:06 PM PST 23 Dec 24 12:48:09 PM PST 23 9010375 ps
T31 /workspace/coverage/sync_alert/2.prim_sync_alert.2347004203 Dec 24 12:48:05 PM PST 23 Dec 24 12:48:07 PM PST 23 9944074 ps
T32 /workspace/coverage/sync_alert/9.prim_sync_alert.616668674 Dec 24 12:48:06 PM PST 23 Dec 24 12:48:08 PM PST 23 9425401 ps
T33 /workspace/coverage/sync_alert/13.prim_sync_alert.3568545668 Dec 24 12:48:10 PM PST 23 Dec 24 12:48:13 PM PST 23 9585714 ps
T56 /workspace/coverage/sync_alert/0.prim_sync_alert.916529727 Dec 24 12:47:35 PM PST 23 Dec 24 12:47:38 PM PST 23 8306580 ps
T57 /workspace/coverage/sync_alert/3.prim_sync_alert.2226154092 Dec 24 12:48:14 PM PST 23 Dec 24 12:48:16 PM PST 23 9346294 ps
T58 /workspace/coverage/sync_alert/1.prim_sync_alert.3763332472 Dec 24 12:47:33 PM PST 23 Dec 24 12:47:37 PM PST 23 8291931 ps
T59 /workspace/coverage/sync_alert/17.prim_sync_alert.1546672875 Dec 24 12:48:05 PM PST 23 Dec 24 12:48:07 PM PST 23 8878935 ps
T12 /workspace/coverage/sync_alert/15.prim_sync_alert.1629836072 Dec 24 12:48:14 PM PST 23 Dec 24 12:48:16 PM PST 23 9125674 ps
T60 /workspace/coverage/sync_alert/11.prim_sync_alert.2954769929 Dec 24 12:48:22 PM PST 23 Dec 24 12:48:24 PM PST 23 8832348 ps
T61 /workspace/coverage/sync_alert/14.prim_sync_alert.380913577 Dec 24 12:48:07 PM PST 23 Dec 24 12:48:10 PM PST 23 10096273 ps
T62 /workspace/coverage/sync_alert/16.prim_sync_alert.475432166 Dec 24 12:47:58 PM PST 23 Dec 24 12:48:00 PM PST 23 10517615 ps
T63 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3348886051 Dec 24 12:30:07 PM PST 23 Dec 24 12:30:32 PM PST 23 26796484 ps
T64 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1597927677 Dec 24 12:30:18 PM PST 23 Dec 24 12:30:41 PM PST 23 26846901 ps
T5 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3264658010 Dec 24 12:30:28 PM PST 23 Dec 24 12:30:53 PM PST 23 28547302 ps
T65 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3808745848 Dec 24 12:30:06 PM PST 23 Dec 24 12:30:32 PM PST 23 28295158 ps
T66 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1229148831 Dec 24 12:29:49 PM PST 23 Dec 24 12:30:12 PM PST 23 29140473 ps
T67 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2893627996 Dec 24 12:30:17 PM PST 23 Dec 24 12:30:40 PM PST 23 29188689 ps
T68 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2154871022 Dec 24 12:30:20 PM PST 23 Dec 24 12:30:42 PM PST 23 24400696 ps
T69 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3270712176 Dec 24 12:30:18 PM PST 23 Dec 24 12:30:40 PM PST 23 28064815 ps
T70 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1262124408 Dec 24 12:30:22 PM PST 23 Dec 24 12:30:45 PM PST 23 27632182 ps
T6 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3296990427 Dec 24 12:29:54 PM PST 23 Dec 24 12:30:20 PM PST 23 27877315 ps
T71 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2871673936 Dec 24 12:29:55 PM PST 23 Dec 24 12:30:21 PM PST 23 27445809 ps
T72 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2698266375 Dec 24 12:30:22 PM PST 23 Dec 24 12:30:45 PM PST 23 27942202 ps
T73 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2444061444 Dec 24 12:29:58 PM PST 23 Dec 24 12:30:25 PM PST 23 27844486 ps
T74 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.340344359 Dec 24 12:29:54 PM PST 23 Dec 24 12:30:20 PM PST 23 28549191 ps
T75 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3925457 Dec 24 12:30:27 PM PST 23 Dec 24 12:30:52 PM PST 23 25352873 ps
T76 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2000886839 Dec 24 12:29:57 PM PST 23 Dec 24 12:30:24 PM PST 23 27511483 ps
T77 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1639039620 Dec 24 12:30:12 PM PST 23 Dec 24 12:30:36 PM PST 23 27527152 ps
T78 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3724949527 Dec 24 12:29:48 PM PST 23 Dec 24 12:30:18 PM PST 23 26961329 ps
T79 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1868626768 Dec 24 12:30:08 PM PST 23 Dec 24 12:30:33 PM PST 23 27812669 ps
T80 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3181761767 Dec 24 12:30:02 PM PST 23 Dec 24 12:30:28 PM PST 23 28417173 ps

Test location /workspace/coverage/default/2.prim_async_alert.3602209227
Short name T2
Test name
Test status
Simulation time 11774106 ps
CPU time 0.37 seconds
Started Dec 24 12:31:13 PM PST 23
Finished Dec 24 12:31:35 PM PST 23
Peak memory 145328 kb
Host smart-9547f8db-2f21-4b9e-bf36-f7b2844f6920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602209227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3602209227
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2825046193
Short name T34
Test name
Test status
Simulation time 9349654 ps
CPU time 0.38 seconds
Started Dec 24 12:48:04 PM PST 23
Finished Dec 24 12:48:06 PM PST 23
Peak memory 144964 kb
Host smart-b07ccf31-dfbc-4fba-ab98-6473e0925eb0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2825046193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2825046193
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.646837177
Short name T4
Test name
Test status
Simulation time 29961034 ps
CPU time 0.4 seconds
Started Dec 24 12:30:32 PM PST 23
Finished Dec 24 12:30:59 PM PST 23
Peak memory 145580 kb
Host smart-fd432eb2-32ae-4d0c-aadf-4a77964658ab
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=646837177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.646837177
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.1571575405
Short name T11
Test name
Test status
Simulation time 11293892 ps
CPU time 0.45 seconds
Started Dec 24 12:30:34 PM PST 23
Finished Dec 24 12:31:01 PM PST 23
Peak memory 143868 kb
Host smart-fa1e1843-aad6-49ba-88ae-887baaa45f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571575405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1571575405
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.1629836072
Short name T12
Test name
Test status
Simulation time 9125674 ps
CPU time 0.38 seconds
Started Dec 24 12:48:14 PM PST 23
Finished Dec 24 12:48:16 PM PST 23
Peak memory 144908 kb
Host smart-cd0f6e84-3f57-492a-9205-79d834dc07fd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1629836072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1629836072
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.3382488960
Short name T44
Test name
Test status
Simulation time 12053006 ps
CPU time 0.38 seconds
Started Dec 24 12:29:56 PM PST 23
Finished Dec 24 12:30:22 PM PST 23
Peak memory 145428 kb
Host smart-f9f17176-df2c-45aa-a4f5-66bbca6bc867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382488960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3382488960
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.341655432
Short name T7
Test name
Test status
Simulation time 11690281 ps
CPU time 0.38 seconds
Started Dec 24 12:29:55 PM PST 23
Finished Dec 24 12:30:20 PM PST 23
Peak memory 145424 kb
Host smart-af1f8f62-3398-4206-b7f0-4a18349e1a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341655432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.341655432
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.3766455803
Short name T13
Test name
Test status
Simulation time 12299369 ps
CPU time 0.38 seconds
Started Dec 24 12:30:18 PM PST 23
Finished Dec 24 12:30:40 PM PST 23
Peak memory 145420 kb
Host smart-d1c74326-b790-4257-be40-c096f8d49dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766455803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3766455803
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.3387517739
Short name T8
Test name
Test status
Simulation time 11113442 ps
CPU time 0.38 seconds
Started Dec 24 12:29:54 PM PST 23
Finished Dec 24 12:30:20 PM PST 23
Peak memory 145428 kb
Host smart-be1714ba-057b-4506-bde2-828fa38ec5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387517739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3387517739
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2670001686
Short name T22
Test name
Test status
Simulation time 10499491 ps
CPU time 0.46 seconds
Started Dec 24 12:29:57 PM PST 23
Finished Dec 24 12:30:24 PM PST 23
Peak memory 145600 kb
Host smart-d8186973-d7d8-4122-9379-5b316f5af18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670001686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2670001686
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.1120240892
Short name T46
Test name
Test status
Simulation time 11488218 ps
CPU time 0.38 seconds
Started Dec 24 12:30:18 PM PST 23
Finished Dec 24 12:30:40 PM PST 23
Peak memory 145440 kb
Host smart-86e713b3-4241-436c-b334-d7a442f001a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120240892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1120240892
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.3973941537
Short name T21
Test name
Test status
Simulation time 11552175 ps
CPU time 0.39 seconds
Started Dec 24 12:29:48 PM PST 23
Finished Dec 24 12:30:11 PM PST 23
Peak memory 145428 kb
Host smart-dc1027d3-89f8-4abc-bef4-64854de7279d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973941537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3973941537
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.1384285602
Short name T20
Test name
Test status
Simulation time 10848234 ps
CPU time 0.38 seconds
Started Dec 24 12:30:13 PM PST 23
Finished Dec 24 12:30:37 PM PST 23
Peak memory 145324 kb
Host smart-a681c236-c4f1-4468-86a5-e9d2270cb6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384285602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1384285602
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2177642253
Short name T19
Test name
Test status
Simulation time 10738137 ps
CPU time 0.37 seconds
Started Dec 24 12:30:12 PM PST 23
Finished Dec 24 12:30:36 PM PST 23
Peak memory 145308 kb
Host smart-67991119-72e8-4137-91e6-fce0d949a4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177642253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2177642253
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2382238553
Short name T16
Test name
Test status
Simulation time 10912564 ps
CPU time 0.38 seconds
Started Dec 24 12:31:01 PM PST 23
Finished Dec 24 12:31:22 PM PST 23
Peak memory 145356 kb
Host smart-b24d39c7-4ca5-47aa-ab66-8a5cb52c6435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382238553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2382238553
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.305906123
Short name T10
Test name
Test status
Simulation time 10975665 ps
CPU time 0.38 seconds
Started Dec 24 12:29:53 PM PST 23
Finished Dec 24 12:30:20 PM PST 23
Peak memory 145436 kb
Host smart-78ba6a58-0cb2-4459-87bf-c14be2062aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305906123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.305906123
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.395262963
Short name T45
Test name
Test status
Simulation time 11883577 ps
CPU time 0.37 seconds
Started Dec 24 12:31:16 PM PST 23
Finished Dec 24 12:31:39 PM PST 23
Peak memory 145328 kb
Host smart-5cdccb28-2412-4e23-9454-1af911419468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395262963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.395262963
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.3632885356
Short name T17
Test name
Test status
Simulation time 12592903 ps
CPU time 0.54 seconds
Started Dec 24 12:30:34 PM PST 23
Finished Dec 24 12:31:01 PM PST 23
Peak memory 143892 kb
Host smart-b1a350b5-d9e8-41a9-b792-a892570f9c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632885356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3632885356
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.1811302505
Short name T9
Test name
Test status
Simulation time 11231048 ps
CPU time 0.38 seconds
Started Dec 24 12:30:20 PM PST 23
Finished Dec 24 12:30:42 PM PST 23
Peak memory 145320 kb
Host smart-e09030c8-9397-4544-8bc7-4d2ca559c9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811302505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1811302505
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3663422930
Short name T3
Test name
Test status
Simulation time 10782962 ps
CPU time 0.38 seconds
Started Dec 24 12:29:37 PM PST 23
Finished Dec 24 12:29:54 PM PST 23
Peak memory 145272 kb
Host smart-e3ae28d1-664b-44a6-8768-37156cd2b7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663422930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3663422930
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.4043482866
Short name T18
Test name
Test status
Simulation time 11798814 ps
CPU time 0.38 seconds
Started Dec 24 12:29:43 PM PST 23
Finished Dec 24 12:30:04 PM PST 23
Peak memory 145360 kb
Host smart-290b18f1-125c-4e6b-bcfb-653fb96d32e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043482866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.4043482866
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.1551372192
Short name T1
Test name
Test status
Simulation time 10849097 ps
CPU time 0.37 seconds
Started Dec 24 12:30:03 PM PST 23
Finished Dec 24 12:30:29 PM PST 23
Peak memory 145460 kb
Host smart-7c02a8b0-ba83-4e61-a78b-bdb2d37e08d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551372192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1551372192
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.764856618
Short name T47
Test name
Test status
Simulation time 10998082 ps
CPU time 0.43 seconds
Started Dec 24 12:30:03 PM PST 23
Finished Dec 24 12:30:29 PM PST 23
Peak memory 145584 kb
Host smart-0327c05f-f91d-4a7c-bc2a-c32e4a7c6ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764856618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.764856618
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3332034464
Short name T43
Test name
Test status
Simulation time 30712169 ps
CPU time 0.44 seconds
Started Dec 24 12:29:36 PM PST 23
Finished Dec 24 12:29:53 PM PST 23
Peak memory 144528 kb
Host smart-e1bbe988-151f-468b-8b66-f88925cfcd64
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3332034464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3332034464
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2686447598
Short name T53
Test name
Test status
Simulation time 31826823 ps
CPU time 0.39 seconds
Started Dec 24 12:30:22 PM PST 23
Finished Dec 24 12:30:45 PM PST 23
Peak memory 145488 kb
Host smart-6bbd8c4c-57ad-4f3c-8dce-e8d40b62f7d3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2686447598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2686447598
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2163789951
Short name T52
Test name
Test status
Simulation time 30936821 ps
CPU time 0.41 seconds
Started Dec 24 12:30:07 PM PST 23
Finished Dec 24 12:30:33 PM PST 23
Peak memory 145588 kb
Host smart-dbb484af-bd85-4b9c-88ba-23a39c50c188
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2163789951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2163789951
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1379103102
Short name T36
Test name
Test status
Simulation time 30671754 ps
CPU time 0.41 seconds
Started Dec 24 12:30:13 PM PST 23
Finished Dec 24 12:30:37 PM PST 23
Peak memory 145440 kb
Host smart-3bf49b06-e6ca-4773-9770-24018eec57a6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1379103102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1379103102
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2072902484
Short name T14
Test name
Test status
Simulation time 31376235 ps
CPU time 0.4 seconds
Started Dec 24 12:30:24 PM PST 23
Finished Dec 24 12:30:48 PM PST 23
Peak memory 145512 kb
Host smart-dfd207fe-c328-48b3-b80f-1a853b828fe7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2072902484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2072902484
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2810244632
Short name T49
Test name
Test status
Simulation time 29248231 ps
CPU time 0.4 seconds
Started Dec 24 12:30:26 PM PST 23
Finished Dec 24 12:30:51 PM PST 23
Peak memory 145332 kb
Host smart-f72d6506-6245-4f0d-81cf-eb68b2a02253
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2810244632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2810244632
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1018181445
Short name T23
Test name
Test status
Simulation time 26818864 ps
CPU time 0.39 seconds
Started Dec 24 12:30:25 PM PST 23
Finished Dec 24 12:30:50 PM PST 23
Peak memory 145496 kb
Host smart-45a551ec-d95c-4b48-9216-1a628e570112
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1018181445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1018181445
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3626995841
Short name T42
Test name
Test status
Simulation time 31148019 ps
CPU time 0.4 seconds
Started Dec 24 12:30:24 PM PST 23
Finished Dec 24 12:30:47 PM PST 23
Peak memory 145360 kb
Host smart-93756778-0ccd-459a-a50f-e65b676a0469
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3626995841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3626995841
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2001762522
Short name T41
Test name
Test status
Simulation time 29994887 ps
CPU time 0.41 seconds
Started Dec 24 12:29:47 PM PST 23
Finished Dec 24 12:30:11 PM PST 23
Peak memory 145640 kb
Host smart-8612af74-036a-40a5-a3f6-1f290b8289d7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2001762522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2001762522
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3799426211
Short name T54
Test name
Test status
Simulation time 29700645 ps
CPU time 0.43 seconds
Started Dec 24 12:30:25 PM PST 23
Finished Dec 24 12:30:50 PM PST 23
Peak memory 145588 kb
Host smart-a44c4291-d8cc-401d-8ad3-5d23bc3f93af
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3799426211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3799426211
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3309468216
Short name T55
Test name
Test status
Simulation time 29333333 ps
CPU time 0.44 seconds
Started Dec 24 12:30:34 PM PST 23
Finished Dec 24 12:31:01 PM PST 23
Peak memory 145600 kb
Host smart-6177c4d2-4aa9-4779-9eeb-896f84d3122c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3309468216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3309468216
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1982874475
Short name T50
Test name
Test status
Simulation time 31005798 ps
CPU time 0.4 seconds
Started Dec 24 12:30:16 PM PST 23
Finished Dec 24 12:30:39 PM PST 23
Peak memory 145572 kb
Host smart-1f757c45-51f9-4541-b333-25ed185a7988
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1982874475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1982874475
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1490617169
Short name T37
Test name
Test status
Simulation time 30921410 ps
CPU time 0.39 seconds
Started Dec 24 12:30:00 PM PST 23
Finished Dec 24 12:30:26 PM PST 23
Peak memory 145428 kb
Host smart-55bfe9d5-3109-437b-91f4-7b7d5bdd2575
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1490617169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1490617169
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1432536276
Short name T40
Test name
Test status
Simulation time 31119474 ps
CPU time 0.42 seconds
Started Dec 24 12:30:06 PM PST 23
Finished Dec 24 12:30:31 PM PST 23
Peak memory 145472 kb
Host smart-4ca437af-1d72-4de3-909d-eec1eba0f1f6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1432536276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1432536276
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2475128192
Short name T51
Test name
Test status
Simulation time 30377692 ps
CPU time 0.39 seconds
Started Dec 24 12:30:25 PM PST 23
Finished Dec 24 12:30:50 PM PST 23
Peak memory 145512 kb
Host smart-5d5b5db4-ead8-4b18-a588-b03878014e5d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2475128192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2475128192
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.956400147
Short name T39
Test name
Test status
Simulation time 31310590 ps
CPU time 0.4 seconds
Started Dec 24 12:30:11 PM PST 23
Finished Dec 24 12:30:36 PM PST 23
Peak memory 145396 kb
Host smart-e7759d1f-f8b2-4ed9-8cae-5a5ec0b1a70e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=956400147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.956400147
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3062200149
Short name T15
Test name
Test status
Simulation time 30192056 ps
CPU time 0.4 seconds
Started Dec 24 12:30:30 PM PST 23
Finished Dec 24 12:30:57 PM PST 23
Peak memory 145528 kb
Host smart-9ad090a9-4c76-434a-844c-e2034d10de40
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3062200149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3062200149
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.882486595
Short name T38
Test name
Test status
Simulation time 28088090 ps
CPU time 0.39 seconds
Started Dec 24 12:30:19 PM PST 23
Finished Dec 24 12:30:42 PM PST 23
Peak memory 145440 kb
Host smart-1244142d-d039-4869-9d10-b728d4e8955e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=882486595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.882486595
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.365799665
Short name T48
Test name
Test status
Simulation time 29867892 ps
CPU time 0.4 seconds
Started Dec 24 12:30:05 PM PST 23
Finished Dec 24 12:30:30 PM PST 23
Peak memory 145488 kb
Host smart-3eda1620-4127-4a7b-870b-850c466a9880
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=365799665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.365799665
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.916529727
Short name T56
Test name
Test status
Simulation time 8306580 ps
CPU time 0.38 seconds
Started Dec 24 12:47:35 PM PST 23
Finished Dec 24 12:47:38 PM PST 23
Peak memory 144896 kb
Host smart-f07f1bc5-ba4b-430d-b378-4f3b22ccf034
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=916529727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.916529727
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3763332472
Short name T58
Test name
Test status
Simulation time 8291931 ps
CPU time 0.37 seconds
Started Dec 24 12:47:33 PM PST 23
Finished Dec 24 12:47:37 PM PST 23
Peak memory 144964 kb
Host smart-d05d47ee-7feb-44aa-aac7-713a8a5a7f54
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3763332472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3763332472
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.828061483
Short name T30
Test name
Test status
Simulation time 9010375 ps
CPU time 0.38 seconds
Started Dec 24 12:48:06 PM PST 23
Finished Dec 24 12:48:09 PM PST 23
Peak memory 145104 kb
Host smart-d50d6cdd-3b19-40cb-bf9e-4e60516220a8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=828061483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.828061483
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.2954769929
Short name T60
Test name
Test status
Simulation time 8832348 ps
CPU time 0.38 seconds
Started Dec 24 12:48:22 PM PST 23
Finished Dec 24 12:48:24 PM PST 23
Peak memory 144976 kb
Host smart-088a7ec5-1ff5-4cfb-b78b-bc6290aae83f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2954769929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2954769929
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.907081133
Short name T29
Test name
Test status
Simulation time 9822214 ps
CPU time 0.39 seconds
Started Dec 24 12:48:13 PM PST 23
Finished Dec 24 12:48:15 PM PST 23
Peak memory 144908 kb
Host smart-2ee569b3-0c64-499b-9cf4-8efbf1820939
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=907081133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.907081133
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3568545668
Short name T33
Test name
Test status
Simulation time 9585714 ps
CPU time 0.39 seconds
Started Dec 24 12:48:10 PM PST 23
Finished Dec 24 12:48:13 PM PST 23
Peak memory 145000 kb
Host smart-ca04aa86-48ce-4988-bccc-e74286ceb60f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3568545668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3568545668
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.380913577
Short name T61
Test name
Test status
Simulation time 10096273 ps
CPU time 0.4 seconds
Started Dec 24 12:48:07 PM PST 23
Finished Dec 24 12:48:10 PM PST 23
Peak memory 144868 kb
Host smart-e6256b6b-80c3-41b6-bd00-55804b2d910d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=380913577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.380913577
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.475432166
Short name T62
Test name
Test status
Simulation time 10517615 ps
CPU time 0.4 seconds
Started Dec 24 12:47:58 PM PST 23
Finished Dec 24 12:48:00 PM PST 23
Peak memory 144968 kb
Host smart-a042a880-7deb-4afe-98dc-f3b8d274c435
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=475432166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.475432166
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1546672875
Short name T59
Test name
Test status
Simulation time 8878935 ps
CPU time 0.39 seconds
Started Dec 24 12:48:05 PM PST 23
Finished Dec 24 12:48:07 PM PST 23
Peak memory 145016 kb
Host smart-ac374f23-8bd4-4f31-920d-32c0fd05359c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1546672875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1546672875
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2740269798
Short name T26
Test name
Test status
Simulation time 8820259 ps
CPU time 0.4 seconds
Started Dec 24 12:48:07 PM PST 23
Finished Dec 24 12:48:11 PM PST 23
Peak memory 145004 kb
Host smart-5ffcb78a-6177-41b2-923b-fe202c8624ae
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2740269798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2740269798
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.1945884876
Short name T27
Test name
Test status
Simulation time 8441790 ps
CPU time 0.39 seconds
Started Dec 24 12:48:09 PM PST 23
Finished Dec 24 12:48:12 PM PST 23
Peak memory 144896 kb
Host smart-14e97e28-34cd-481d-a368-52441d296e81
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1945884876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1945884876
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.2347004203
Short name T31
Test name
Test status
Simulation time 9944074 ps
CPU time 0.39 seconds
Started Dec 24 12:48:05 PM PST 23
Finished Dec 24 12:48:07 PM PST 23
Peak memory 144916 kb
Host smart-8528725d-fb15-4736-aba9-62aa9b81fee9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2347004203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2347004203
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.2226154092
Short name T57
Test name
Test status
Simulation time 9346294 ps
CPU time 0.38 seconds
Started Dec 24 12:48:14 PM PST 23
Finished Dec 24 12:48:16 PM PST 23
Peak memory 144996 kb
Host smart-9c716d2c-ee73-4aaf-9f7e-eed8bfe5ad9a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2226154092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2226154092
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.700551002
Short name T28
Test name
Test status
Simulation time 10246769 ps
CPU time 0.37 seconds
Started Dec 24 12:48:01 PM PST 23
Finished Dec 24 12:48:04 PM PST 23
Peak memory 144932 kb
Host smart-90090f7c-9a5c-4190-ae78-ba4fda70f332
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=700551002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.700551002
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.679698160
Short name T25
Test name
Test status
Simulation time 9533133 ps
CPU time 0.38 seconds
Started Dec 24 12:48:07 PM PST 23
Finished Dec 24 12:48:11 PM PST 23
Peak memory 145024 kb
Host smart-bca1ec30-f6be-4f3d-92e7-3db530da3f03
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=679698160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.679698160
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1691953681
Short name T24
Test name
Test status
Simulation time 10024175 ps
CPU time 0.44 seconds
Started Dec 24 12:48:00 PM PST 23
Finished Dec 24 12:48:03 PM PST 23
Peak memory 144936 kb
Host smart-eebd9d6c-bfd2-4bed-a383-614416aef3cc
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1691953681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1691953681
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.1220274272
Short name T35
Test name
Test status
Simulation time 8149564 ps
CPU time 0.4 seconds
Started Dec 24 12:47:58 PM PST 23
Finished Dec 24 12:48:01 PM PST 23
Peak memory 144896 kb
Host smart-4d51a01a-ffce-4066-bdd7-e928cc01748a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1220274272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1220274272
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.616668674
Short name T32
Test name
Test status
Simulation time 9425401 ps
CPU time 0.39 seconds
Started Dec 24 12:48:06 PM PST 23
Finished Dec 24 12:48:08 PM PST 23
Peak memory 144928 kb
Host smart-eecb6e51-57ec-4a83-98cf-dc9c0694d318
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=616668674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.616668674
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3348886051
Short name T63
Test name
Test status
Simulation time 26796484 ps
CPU time 0.39 seconds
Started Dec 24 12:30:07 PM PST 23
Finished Dec 24 12:30:32 PM PST 23
Peak memory 144936 kb
Host smart-98fa48b1-a4fb-40a0-9de9-8e9b28b07861
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3348886051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3348886051
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1262124408
Short name T70
Test name
Test status
Simulation time 27632182 ps
CPU time 0.38 seconds
Started Dec 24 12:30:22 PM PST 23
Finished Dec 24 12:30:45 PM PST 23
Peak memory 144932 kb
Host smart-909b3fdb-e962-4456-9b18-aa01771c8233
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1262124408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1262124408
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3724949527
Short name T78
Test name
Test status
Simulation time 26961329 ps
CPU time 0.39 seconds
Started Dec 24 12:29:48 PM PST 23
Finished Dec 24 12:30:18 PM PST 23
Peak memory 144928 kb
Host smart-ac6556d8-78bb-4b91-9e47-a575a39a62a7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3724949527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3724949527
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3181761767
Short name T80
Test name
Test status
Simulation time 28417173 ps
CPU time 0.39 seconds
Started Dec 24 12:30:02 PM PST 23
Finished Dec 24 12:30:28 PM PST 23
Peak memory 144972 kb
Host smart-5f2f5028-9fe1-4f21-a353-a337f0226eec
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3181761767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3181761767
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1229148831
Short name T66
Test name
Test status
Simulation time 29140473 ps
CPU time 0.39 seconds
Started Dec 24 12:29:49 PM PST 23
Finished Dec 24 12:30:12 PM PST 23
Peak memory 145024 kb
Host smart-739ffec5-ab11-43ca-b6df-fdcb018d637e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1229148831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1229148831
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3270712176
Short name T69
Test name
Test status
Simulation time 28064815 ps
CPU time 0.39 seconds
Started Dec 24 12:30:18 PM PST 23
Finished Dec 24 12:30:40 PM PST 23
Peak memory 144996 kb
Host smart-61d2b47e-04b5-450f-8dd8-4827902ca7f5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3270712176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3270712176
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.340344359
Short name T74
Test name
Test status
Simulation time 28549191 ps
CPU time 0.39 seconds
Started Dec 24 12:29:54 PM PST 23
Finished Dec 24 12:30:20 PM PST 23
Peak memory 145024 kb
Host smart-47ae92d1-7d96-4838-ae55-8946fc6fa591
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=340344359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.340344359
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3925457
Short name T75
Test name
Test status
Simulation time 25352873 ps
CPU time 0.39 seconds
Started Dec 24 12:30:27 PM PST 23
Finished Dec 24 12:30:52 PM PST 23
Peak memory 144948 kb
Host smart-10c00fb4-b88d-4532-8bf5-b41f810d320f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3925457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3925457
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2444061444
Short name T73
Test name
Test status
Simulation time 27844486 ps
CPU time 0.43 seconds
Started Dec 24 12:29:58 PM PST 23
Finished Dec 24 12:30:25 PM PST 23
Peak memory 144892 kb
Host smart-097c3dbc-c113-4593-ba43-ae297d716d9b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2444061444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2444061444
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1868626768
Short name T79
Test name
Test status
Simulation time 27812669 ps
CPU time 0.38 seconds
Started Dec 24 12:30:08 PM PST 23
Finished Dec 24 12:30:33 PM PST 23
Peak memory 144916 kb
Host smart-19ce0274-9ffb-40a0-ba77-76b7b6f2bcbd
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1868626768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1868626768
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2154871022
Short name T68
Test name
Test status
Simulation time 24400696 ps
CPU time 0.39 seconds
Started Dec 24 12:30:20 PM PST 23
Finished Dec 24 12:30:42 PM PST 23
Peak memory 145000 kb
Host smart-d364e707-5e1c-4715-8e9b-2a16267c0208
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2154871022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2154871022
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2871673936
Short name T71
Test name
Test status
Simulation time 27445809 ps
CPU time 0.4 seconds
Started Dec 24 12:29:55 PM PST 23
Finished Dec 24 12:30:21 PM PST 23
Peak memory 144996 kb
Host smart-62fd8ee5-b68b-4b23-90b7-63efa7cbef59
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2871673936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2871673936
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3296990427
Short name T6
Test name
Test status
Simulation time 27877315 ps
CPU time 0.44 seconds
Started Dec 24 12:29:54 PM PST 23
Finished Dec 24 12:30:20 PM PST 23
Peak memory 144924 kb
Host smart-a0c0a2bb-96f1-4bb4-9344-45329115510c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3296990427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3296990427
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3264658010
Short name T5
Test name
Test status
Simulation time 28547302 ps
CPU time 0.39 seconds
Started Dec 24 12:30:28 PM PST 23
Finished Dec 24 12:30:53 PM PST 23
Peak memory 144932 kb
Host smart-e8f43f22-8335-4e82-8c29-7ebb8a76142b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3264658010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3264658010
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2000886839
Short name T76
Test name
Test status
Simulation time 27511483 ps
CPU time 0.39 seconds
Started Dec 24 12:29:57 PM PST 23
Finished Dec 24 12:30:24 PM PST 23
Peak memory 144924 kb
Host smart-47778ad8-33f8-42ea-8926-1f46995fbe2b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2000886839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2000886839
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1597927677
Short name T64
Test name
Test status
Simulation time 26846901 ps
CPU time 0.39 seconds
Started Dec 24 12:30:18 PM PST 23
Finished Dec 24 12:30:41 PM PST 23
Peak memory 144932 kb
Host smart-ca1a3a9c-e1c5-485b-9569-6e92a483900e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1597927677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1597927677
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2698266375
Short name T72
Test name
Test status
Simulation time 27942202 ps
CPU time 0.41 seconds
Started Dec 24 12:30:22 PM PST 23
Finished Dec 24 12:30:45 PM PST 23
Peak memory 144912 kb
Host smart-f0f67225-ace5-4f03-961d-a0cd8def6ae2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2698266375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2698266375
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1639039620
Short name T77
Test name
Test status
Simulation time 27527152 ps
CPU time 0.44 seconds
Started Dec 24 12:30:12 PM PST 23
Finished Dec 24 12:30:36 PM PST 23
Peak memory 145028 kb
Host smart-3f577f68-2399-4174-9c74-a1a3b4ec3c07
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1639039620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1639039620
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2893627996
Short name T67
Test name
Test status
Simulation time 29188689 ps
CPU time 0.39 seconds
Started Dec 24 12:30:17 PM PST 23
Finished Dec 24 12:30:40 PM PST 23
Peak memory 144924 kb
Host smart-3ab27691-f5c3-4b8b-947e-7d52dda97f61
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2893627996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2893627996
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3808745848
Short name T65
Test name
Test status
Simulation time 28295158 ps
CPU time 0.39 seconds
Started Dec 24 12:30:06 PM PST 23
Finished Dec 24 12:30:32 PM PST 23
Peak memory 145012 kb
Host smart-d3b10978-ff19-460b-8a24-398700c1acb6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3808745848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3808745848
Directory /workspace/9.prim_sync_fatal_alert/latest
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