Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.32 88.32 100.00 100.00 91.67 91.67 96.43 96.43 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/8.prim_async_alert.1188398011
91.45 3.13 100.00 0.00 91.67 0.00 96.43 0.00 85.71 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/1.prim_sync_alert.3333712619
94.15 2.70 100.00 0.00 93.75 2.08 100.00 3.57 89.29 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.720429555
94.50 0.35 100.00 0.00 95.83 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/default/12.prim_async_alert.1378601991
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3353130641
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/8.prim_sync_alert.3353836733

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.1403883464
/workspace/coverage/default/1.prim_async_alert.2798680088
/workspace/coverage/default/10.prim_async_alert.3094239799
/workspace/coverage/default/11.prim_async_alert.3327530812
/workspace/coverage/default/13.prim_async_alert.2692187593
/workspace/coverage/default/14.prim_async_alert.240392855
/workspace/coverage/default/15.prim_async_alert.3799114563
/workspace/coverage/default/16.prim_async_alert.3861470189
/workspace/coverage/default/17.prim_async_alert.1995262164
/workspace/coverage/default/18.prim_async_alert.3393055763
/workspace/coverage/default/19.prim_async_alert.254614498
/workspace/coverage/default/2.prim_async_alert.3982994586
/workspace/coverage/default/3.prim_async_alert.1495843778
/workspace/coverage/default/4.prim_async_alert.195433384
/workspace/coverage/default/5.prim_async_alert.3809576042
/workspace/coverage/default/6.prim_async_alert.3739914451
/workspace/coverage/default/7.prim_async_alert.1114495061
/workspace/coverage/default/9.prim_async_alert.171865528
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.373777585
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2523668667
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3204866993
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.308099358
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1544172487
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1116483321
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1345886486
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2655625821
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1545683543
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1557983685
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1757599877
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.410467333
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.164345657
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1687847065
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3451079139
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.969930225
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4186128617
/workspace/coverage/sync_alert/0.prim_sync_alert.386730299
/workspace/coverage/sync_alert/10.prim_sync_alert.1161765607
/workspace/coverage/sync_alert/11.prim_sync_alert.80430619
/workspace/coverage/sync_alert/12.prim_sync_alert.2783251800
/workspace/coverage/sync_alert/13.prim_sync_alert.86602066
/workspace/coverage/sync_alert/14.prim_sync_alert.19914934
/workspace/coverage/sync_alert/15.prim_sync_alert.1407713198
/workspace/coverage/sync_alert/16.prim_sync_alert.1915994817
/workspace/coverage/sync_alert/17.prim_sync_alert.2737883647
/workspace/coverage/sync_alert/18.prim_sync_alert.3601296656
/workspace/coverage/sync_alert/19.prim_sync_alert.549744836
/workspace/coverage/sync_alert/2.prim_sync_alert.3431682192
/workspace/coverage/sync_alert/3.prim_sync_alert.882405660
/workspace/coverage/sync_alert/4.prim_sync_alert.3173631193
/workspace/coverage/sync_alert/5.prim_sync_alert.1645639492
/workspace/coverage/sync_alert/6.prim_sync_alert.1877901011
/workspace/coverage/sync_alert/7.prim_sync_alert.2105452416
/workspace/coverage/sync_alert/9.prim_sync_alert.1449283376
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1204727154
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2955344280
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2815170062
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4024409456
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2731130971
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.561685143
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2383246617
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2482693020
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2539970460
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3814180000
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.685837636
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1851263574
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3092535609
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3616457615
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1791934949
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4184495898
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3254481700
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2649023525
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1143122298
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3819991259



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/10.prim_async_alert.3094239799 Dec 27 12:45:32 PM PST 23 Dec 27 12:45:40 PM PST 23 10898669 ps
T2 /workspace/coverage/default/2.prim_async_alert.3982994586 Dec 27 12:45:49 PM PST 23 Dec 27 12:45:57 PM PST 23 11887350 ps
T3 /workspace/coverage/default/19.prim_async_alert.254614498 Dec 27 12:45:18 PM PST 23 Dec 27 12:45:27 PM PST 23 11644022 ps
T18 /workspace/coverage/default/18.prim_async_alert.3393055763 Dec 27 12:45:38 PM PST 23 Dec 27 12:45:47 PM PST 23 11255197 ps
T12 /workspace/coverage/default/15.prim_async_alert.3799114563 Dec 27 12:46:00 PM PST 23 Dec 27 12:46:12 PM PST 23 11762750 ps
T13 /workspace/coverage/default/3.prim_async_alert.1495843778 Dec 27 12:45:46 PM PST 23 Dec 27 12:45:54 PM PST 23 12518579 ps
T7 /workspace/coverage/default/0.prim_async_alert.1403883464 Dec 27 12:45:31 PM PST 23 Dec 27 12:45:39 PM PST 23 10799551 ps
T20 /workspace/coverage/default/8.prim_async_alert.1188398011 Dec 27 12:45:45 PM PST 23 Dec 27 12:45:54 PM PST 23 11064083 ps
T23 /workspace/coverage/default/9.prim_async_alert.171865528 Dec 27 12:45:45 PM PST 23 Dec 27 12:45:54 PM PST 23 10480593 ps
T9 /workspace/coverage/default/6.prim_async_alert.3739914451 Dec 27 12:45:49 PM PST 23 Dec 27 12:45:57 PM PST 23 11172762 ps
T8 /workspace/coverage/default/11.prim_async_alert.3327530812 Dec 27 12:45:49 PM PST 23 Dec 27 12:45:57 PM PST 23 11356569 ps
T24 /workspace/coverage/default/17.prim_async_alert.1995262164 Dec 27 12:45:28 PM PST 23 Dec 27 12:45:35 PM PST 23 11110895 ps
T19 /workspace/coverage/default/1.prim_async_alert.2798680088 Dec 27 12:45:39 PM PST 23 Dec 27 12:45:47 PM PST 23 11737887 ps
T14 /workspace/coverage/default/7.prim_async_alert.1114495061 Dec 27 12:45:30 PM PST 23 Dec 27 12:45:38 PM PST 23 11688217 ps
T21 /workspace/coverage/default/13.prim_async_alert.2692187593 Dec 27 12:45:53 PM PST 23 Dec 27 12:46:03 PM PST 23 11570679 ps
T44 /workspace/coverage/default/12.prim_async_alert.1378601991 Dec 27 12:45:35 PM PST 23 Dec 27 12:45:45 PM PST 23 11108217 ps
T22 /workspace/coverage/default/5.prim_async_alert.3809576042 Dec 27 12:45:31 PM PST 23 Dec 27 12:45:39 PM PST 23 12111770 ps
T25 /workspace/coverage/default/16.prim_async_alert.3861470189 Dec 27 12:45:34 PM PST 23 Dec 27 12:45:43 PM PST 23 11115842 ps
T45 /workspace/coverage/default/4.prim_async_alert.195433384 Dec 27 12:45:30 PM PST 23 Dec 27 12:45:38 PM PST 23 11264355 ps
T26 /workspace/coverage/default/14.prim_async_alert.240392855 Dec 27 12:45:32 PM PST 23 Dec 27 12:45:41 PM PST 23 11015725 ps
T27 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1116483321 Dec 27 12:40:20 PM PST 23 Dec 27 12:41:15 PM PST 23 29109605 ps
T15 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.720429555 Dec 27 12:40:28 PM PST 23 Dec 27 12:41:25 PM PST 23 29627338 ps
T38 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1544172487 Dec 27 12:40:20 PM PST 23 Dec 27 12:41:14 PM PST 23 29002069 ps
T37 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2655625821 Dec 27 12:40:27 PM PST 23 Dec 27 12:41:23 PM PST 23 30152254 ps
T39 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3451079139 Dec 27 12:40:27 PM PST 23 Dec 27 12:41:23 PM PST 23 29439744 ps
T4 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3353130641 Dec 27 12:40:36 PM PST 23 Dec 27 12:41:36 PM PST 23 28100770 ps
T40 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1345886486 Dec 27 12:40:27 PM PST 23 Dec 27 12:41:23 PM PST 23 30610934 ps
T41 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.969930225 Dec 27 12:40:29 PM PST 23 Dec 27 12:41:26 PM PST 23 29859476 ps
T42 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2523668667 Dec 27 12:40:27 PM PST 23 Dec 27 12:41:23 PM PST 23 30507495 ps
T43 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3204866993 Dec 27 12:40:44 PM PST 23 Dec 27 12:41:45 PM PST 23 30711773 ps
T46 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.373777585 Dec 27 12:40:15 PM PST 23 Dec 27 12:41:07 PM PST 23 28531564 ps
T47 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1757599877 Dec 27 12:40:28 PM PST 23 Dec 27 12:41:24 PM PST 23 29002626 ps
T48 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.164345657 Dec 27 12:40:21 PM PST 23 Dec 27 12:41:15 PM PST 23 30164985 ps
T16 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.410467333 Dec 27 12:40:28 PM PST 23 Dec 27 12:41:24 PM PST 23 31240890 ps
T49 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1557983685 Dec 27 12:40:40 PM PST 23 Dec 27 12:41:42 PM PST 23 30411058 ps
T50 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.308099358 Dec 27 12:40:35 PM PST 23 Dec 27 12:41:36 PM PST 23 32305032 ps
T51 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1545683543 Dec 27 12:40:28 PM PST 23 Dec 27 12:41:24 PM PST 23 30427337 ps
T52 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1687847065 Dec 27 12:40:46 PM PST 23 Dec 27 12:41:48 PM PST 23 30942317 ps
T53 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4186128617 Dec 27 12:40:41 PM PST 23 Dec 27 12:41:42 PM PST 23 28960905 ps
T28 /workspace/coverage/sync_alert/18.prim_sync_alert.3601296656 Dec 27 12:29:46 PM PST 23 Dec 27 12:30:39 PM PST 23 9338715 ps
T29 /workspace/coverage/sync_alert/13.prim_sync_alert.86602066 Dec 27 12:29:21 PM PST 23 Dec 27 12:30:17 PM PST 23 10015110 ps
T10 /workspace/coverage/sync_alert/8.prim_sync_alert.3353836733 Dec 27 12:29:21 PM PST 23 Dec 27 12:30:16 PM PST 23 8422756 ps
T30 /workspace/coverage/sync_alert/11.prim_sync_alert.80430619 Dec 27 12:29:08 PM PST 23 Dec 27 12:30:03 PM PST 23 8257779 ps
T31 /workspace/coverage/sync_alert/15.prim_sync_alert.1407713198 Dec 27 12:29:55 PM PST 23 Dec 27 12:30:48 PM PST 23 9546520 ps
T32 /workspace/coverage/sync_alert/16.prim_sync_alert.1915994817 Dec 27 12:29:47 PM PST 23 Dec 27 12:30:39 PM PST 23 8770472 ps
T33 /workspace/coverage/sync_alert/1.prim_sync_alert.3333712619 Dec 27 12:29:04 PM PST 23 Dec 27 12:29:59 PM PST 23 9821507 ps
T34 /workspace/coverage/sync_alert/12.prim_sync_alert.2783251800 Dec 27 12:29:22 PM PST 23 Dec 27 12:30:17 PM PST 23 9082979 ps
T35 /workspace/coverage/sync_alert/19.prim_sync_alert.549744836 Dec 27 12:29:34 PM PST 23 Dec 27 12:30:32 PM PST 23 7390897 ps
T36 /workspace/coverage/sync_alert/10.prim_sync_alert.1161765607 Dec 27 12:29:19 PM PST 23 Dec 27 12:30:14 PM PST 23 9324753 ps
T54 /workspace/coverage/sync_alert/6.prim_sync_alert.1877901011 Dec 27 12:31:54 PM PST 23 Dec 27 12:32:40 PM PST 23 8537077 ps
T55 /workspace/coverage/sync_alert/0.prim_sync_alert.386730299 Dec 27 12:31:51 PM PST 23 Dec 27 12:32:37 PM PST 23 10224076 ps
T56 /workspace/coverage/sync_alert/7.prim_sync_alert.2105452416 Dec 27 12:31:57 PM PST 23 Dec 27 12:32:43 PM PST 23 9639809 ps
T57 /workspace/coverage/sync_alert/14.prim_sync_alert.19914934 Dec 27 12:29:54 PM PST 23 Dec 27 12:30:46 PM PST 23 9288648 ps
T58 /workspace/coverage/sync_alert/2.prim_sync_alert.3431682192 Dec 27 12:29:12 PM PST 23 Dec 27 12:30:06 PM PST 23 10142407 ps
T59 /workspace/coverage/sync_alert/4.prim_sync_alert.3173631193 Dec 27 12:31:54 PM PST 23 Dec 27 12:32:40 PM PST 23 8941688 ps
T17 /workspace/coverage/sync_alert/5.prim_sync_alert.1645639492 Dec 27 12:29:14 PM PST 23 Dec 27 12:30:09 PM PST 23 10431048 ps
T60 /workspace/coverage/sync_alert/9.prim_sync_alert.1449283376 Dec 27 12:29:23 PM PST 23 Dec 27 12:30:19 PM PST 23 9872512 ps
T61 /workspace/coverage/sync_alert/17.prim_sync_alert.2737883647 Dec 27 12:29:23 PM PST 23 Dec 27 12:30:18 PM PST 23 9007947 ps
T62 /workspace/coverage/sync_alert/3.prim_sync_alert.882405660 Dec 27 12:29:24 PM PST 23 Dec 27 12:30:19 PM PST 23 10115317 ps
T63 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2731130971 Dec 27 12:30:20 PM PST 23 Dec 27 12:31:16 PM PST 23 28169667 ps
T5 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2482693020 Dec 27 12:32:18 PM PST 23 Dec 27 12:33:02 PM PST 23 26925954 ps
T64 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3814180000 Dec 27 12:29:04 PM PST 23 Dec 27 12:29:59 PM PST 23 27536642 ps
T65 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4184495898 Dec 27 12:28:57 PM PST 23 Dec 27 12:29:52 PM PST 23 27422573 ps
T66 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2649023525 Dec 27 12:29:26 PM PST 23 Dec 27 12:30:20 PM PST 23 27509597 ps
T67 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2815170062 Dec 27 12:31:45 PM PST 23 Dec 27 12:32:34 PM PST 23 27724879 ps
T68 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.685837636 Dec 27 12:29:20 PM PST 23 Dec 27 12:30:16 PM PST 23 26038927 ps
T69 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.561685143 Dec 27 12:30:17 PM PST 23 Dec 27 12:31:12 PM PST 23 29332094 ps
T11 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2539970460 Dec 27 12:31:56 PM PST 23 Dec 27 12:32:42 PM PST 23 27622175 ps
T70 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3819991259 Dec 27 12:31:23 PM PST 23 Dec 27 12:32:14 PM PST 23 28089407 ps
T71 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1143122298 Dec 27 12:29:15 PM PST 23 Dec 27 12:30:09 PM PST 23 27218307 ps
T72 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2955344280 Dec 27 12:30:28 PM PST 23 Dec 27 12:31:25 PM PST 23 27576911 ps
T73 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3616457615 Dec 27 12:30:33 PM PST 23 Dec 27 12:31:30 PM PST 23 26224411 ps
T74 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1791934949 Dec 27 12:31:10 PM PST 23 Dec 27 12:31:59 PM PST 23 29003411 ps
T75 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3254481700 Dec 27 12:32:07 PM PST 23 Dec 27 12:32:52 PM PST 23 26761322 ps
T76 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1204727154 Dec 27 12:29:40 PM PST 23 Dec 27 12:30:34 PM PST 23 27128740 ps
T77 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3092535609 Dec 27 12:29:05 PM PST 23 Dec 27 12:29:59 PM PST 23 26442033 ps
T6 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4024409456 Dec 27 12:29:13 PM PST 23 Dec 27 12:30:08 PM PST 23 24833945 ps
T78 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1851263574 Dec 27 12:30:50 PM PST 23 Dec 27 12:31:44 PM PST 23 29554095 ps
T79 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2383246617 Dec 27 12:29:30 PM PST 23 Dec 27 12:30:24 PM PST 23 27523781 ps

Test location /workspace/coverage/default/8.prim_async_alert.1188398011
Short name T20
Test name
Test status
Simulation time 11064083 ps
CPU time 0.39 seconds
Started Dec 27 12:45:45 PM PST 23
Finished Dec 27 12:45:54 PM PST 23
Peak memory 145388 kb
Host smart-44b7f189-59cc-4681-ba50-3b141e4099d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188398011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1188398011
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3333712619
Short name T33
Test name
Test status
Simulation time 9821507 ps
CPU time 0.37 seconds
Started Dec 27 12:29:04 PM PST 23
Finished Dec 27 12:29:59 PM PST 23
Peak memory 144896 kb
Host smart-8b2e5a4c-f7c3-4428-9e49-01bb9ea30de3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3333712619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3333712619
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.720429555
Short name T15
Test name
Test status
Simulation time 29627338 ps
CPU time 0.39 seconds
Started Dec 27 12:40:28 PM PST 23
Finished Dec 27 12:41:25 PM PST 23
Peak memory 145576 kb
Host smart-c513515c-a8cb-4f0f-92bf-ccf1c5030fc3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=720429555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.720429555
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.1378601991
Short name T44
Test name
Test status
Simulation time 11108217 ps
CPU time 0.38 seconds
Started Dec 27 12:45:35 PM PST 23
Finished Dec 27 12:45:45 PM PST 23
Peak memory 145276 kb
Host smart-6b3beff1-3941-4417-9e7e-0fdeb9d32bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378601991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1378601991
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3353130641
Short name T4
Test name
Test status
Simulation time 28100770 ps
CPU time 0.4 seconds
Started Dec 27 12:40:36 PM PST 23
Finished Dec 27 12:41:36 PM PST 23
Peak memory 145608 kb
Host smart-f75606e3-380c-409f-a645-c916b0d58119
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3353130641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3353130641
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.3353836733
Short name T10
Test name
Test status
Simulation time 8422756 ps
CPU time 0.37 seconds
Started Dec 27 12:29:21 PM PST 23
Finished Dec 27 12:30:16 PM PST 23
Peak memory 144872 kb
Host smart-75eb336f-4b4b-47ee-a8bf-1ec3a9a57bdd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3353836733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3353836733
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.1403883464
Short name T7
Test name
Test status
Simulation time 10799551 ps
CPU time 0.38 seconds
Started Dec 27 12:45:31 PM PST 23
Finished Dec 27 12:45:39 PM PST 23
Peak memory 145344 kb
Host smart-b70f6327-e390-4c3f-906a-6ce5cb0adcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403883464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1403883464
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2798680088
Short name T19
Test name
Test status
Simulation time 11737887 ps
CPU time 0.36 seconds
Started Dec 27 12:45:39 PM PST 23
Finished Dec 27 12:45:47 PM PST 23
Peak memory 145324 kb
Host smart-805c3cb6-7ead-46b8-aeb6-31c8afe175d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798680088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2798680088
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3094239799
Short name T1
Test name
Test status
Simulation time 10898669 ps
CPU time 0.37 seconds
Started Dec 27 12:45:32 PM PST 23
Finished Dec 27 12:45:40 PM PST 23
Peak memory 145276 kb
Host smart-40882454-3722-4c34-ba47-3d44c7f7ea01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094239799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3094239799
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.3327530812
Short name T8
Test name
Test status
Simulation time 11356569 ps
CPU time 0.38 seconds
Started Dec 27 12:45:49 PM PST 23
Finished Dec 27 12:45:57 PM PST 23
Peak memory 145380 kb
Host smart-cde3440f-0daf-4b6f-849b-e65cd9bb8313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327530812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3327530812
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2692187593
Short name T21
Test name
Test status
Simulation time 11570679 ps
CPU time 0.38 seconds
Started Dec 27 12:45:53 PM PST 23
Finished Dec 27 12:46:03 PM PST 23
Peak memory 145380 kb
Host smart-4ef1e585-c96e-4e16-90d8-59c655b1b71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692187593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2692187593
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.240392855
Short name T26
Test name
Test status
Simulation time 11015725 ps
CPU time 0.37 seconds
Started Dec 27 12:45:32 PM PST 23
Finished Dec 27 12:45:41 PM PST 23
Peak memory 145392 kb
Host smart-32361f5c-5a1c-4d8c-af27-df519f1e611b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240392855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.240392855
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.3799114563
Short name T12
Test name
Test status
Simulation time 11762750 ps
CPU time 0.38 seconds
Started Dec 27 12:46:00 PM PST 23
Finished Dec 27 12:46:12 PM PST 23
Peak memory 145276 kb
Host smart-c398fe61-d086-47a5-91c9-99a4103d1a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799114563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3799114563
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3861470189
Short name T25
Test name
Test status
Simulation time 11115842 ps
CPU time 0.38 seconds
Started Dec 27 12:45:34 PM PST 23
Finished Dec 27 12:45:43 PM PST 23
Peak memory 145276 kb
Host smart-c77f437c-df32-4b41-b02d-40410fb567ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861470189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3861470189
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1995262164
Short name T24
Test name
Test status
Simulation time 11110895 ps
CPU time 0.36 seconds
Started Dec 27 12:45:28 PM PST 23
Finished Dec 27 12:45:35 PM PST 23
Peak memory 145316 kb
Host smart-b6f0ea59-8356-4388-9a0b-de33c7a544dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995262164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1995262164
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.3393055763
Short name T18
Test name
Test status
Simulation time 11255197 ps
CPU time 0.4 seconds
Started Dec 27 12:45:38 PM PST 23
Finished Dec 27 12:45:47 PM PST 23
Peak memory 145352 kb
Host smart-a2d21386-9d1d-4649-b33a-744d6fee87f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393055763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3393055763
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.254614498
Short name T3
Test name
Test status
Simulation time 11644022 ps
CPU time 0.38 seconds
Started Dec 27 12:45:18 PM PST 23
Finished Dec 27 12:45:27 PM PST 23
Peak memory 145472 kb
Host smart-4ac82297-accd-4cbb-92fb-47059d8be385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254614498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.254614498
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3982994586
Short name T2
Test name
Test status
Simulation time 11887350 ps
CPU time 0.38 seconds
Started Dec 27 12:45:49 PM PST 23
Finished Dec 27 12:45:57 PM PST 23
Peak memory 145336 kb
Host smart-0dcc94cb-7fb5-4fa4-b024-fa8f42727176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982994586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3982994586
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1495843778
Short name T13
Test name
Test status
Simulation time 12518579 ps
CPU time 0.41 seconds
Started Dec 27 12:45:46 PM PST 23
Finished Dec 27 12:45:54 PM PST 23
Peak memory 145344 kb
Host smart-c7f4fddf-4fe8-42cb-ba8b-8abe3a7dc220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495843778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1495843778
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.195433384
Short name T45
Test name
Test status
Simulation time 11264355 ps
CPU time 0.38 seconds
Started Dec 27 12:45:30 PM PST 23
Finished Dec 27 12:45:38 PM PST 23
Peak memory 145344 kb
Host smart-a62a2c7b-31f8-4afe-b834-5932d29b76ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195433384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.195433384
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3809576042
Short name T22
Test name
Test status
Simulation time 12111770 ps
CPU time 0.36 seconds
Started Dec 27 12:45:31 PM PST 23
Finished Dec 27 12:45:39 PM PST 23
Peak memory 145336 kb
Host smart-a185897f-5e46-4dca-bfb0-88ddd000f1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809576042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3809576042
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3739914451
Short name T9
Test name
Test status
Simulation time 11172762 ps
CPU time 0.44 seconds
Started Dec 27 12:45:49 PM PST 23
Finished Dec 27 12:45:57 PM PST 23
Peak memory 145380 kb
Host smart-2c0e2216-afe0-44f6-86de-98497c2a103d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739914451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3739914451
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1114495061
Short name T14
Test name
Test status
Simulation time 11688217 ps
CPU time 0.37 seconds
Started Dec 27 12:45:30 PM PST 23
Finished Dec 27 12:45:38 PM PST 23
Peak memory 145460 kb
Host smart-74287507-c79b-47a1-9ef8-32d73ada90a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114495061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1114495061
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.171865528
Short name T23
Test name
Test status
Simulation time 10480593 ps
CPU time 0.37 seconds
Started Dec 27 12:45:45 PM PST 23
Finished Dec 27 12:45:54 PM PST 23
Peak memory 145440 kb
Host smart-e9a31b9b-0ae2-43a5-b4f0-cca8b185fc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171865528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.171865528
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.373777585
Short name T46
Test name
Test status
Simulation time 28531564 ps
CPU time 0.39 seconds
Started Dec 27 12:40:15 PM PST 23
Finished Dec 27 12:41:07 PM PST 23
Peak memory 145432 kb
Host smart-21aa2c8d-0b24-4196-aa41-b19c01f27bac
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=373777585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.373777585
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2523668667
Short name T42
Test name
Test status
Simulation time 30507495 ps
CPU time 0.39 seconds
Started Dec 27 12:40:27 PM PST 23
Finished Dec 27 12:41:23 PM PST 23
Peak memory 145416 kb
Host smart-86212234-30db-4368-a11a-1244dfae52ff
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2523668667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2523668667
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3204866993
Short name T43
Test name
Test status
Simulation time 30711773 ps
CPU time 0.39 seconds
Started Dec 27 12:40:44 PM PST 23
Finished Dec 27 12:41:45 PM PST 23
Peak memory 145536 kb
Host smart-4bd0e35c-ea32-498f-b4af-d45b362789b4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3204866993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3204866993
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.308099358
Short name T50
Test name
Test status
Simulation time 32305032 ps
CPU time 0.4 seconds
Started Dec 27 12:40:35 PM PST 23
Finished Dec 27 12:41:36 PM PST 23
Peak memory 145436 kb
Host smart-ef4dd8b0-f3df-4200-a2ed-868b5cd9cfd2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=308099358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.308099358
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1544172487
Short name T38
Test name
Test status
Simulation time 29002069 ps
CPU time 0.38 seconds
Started Dec 27 12:40:20 PM PST 23
Finished Dec 27 12:41:14 PM PST 23
Peak memory 145504 kb
Host smart-55be9e69-fc92-490c-bedc-4474e5897c7d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1544172487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1544172487
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1116483321
Short name T27
Test name
Test status
Simulation time 29109605 ps
CPU time 0.44 seconds
Started Dec 27 12:40:20 PM PST 23
Finished Dec 27 12:41:15 PM PST 23
Peak memory 145560 kb
Host smart-f60b47c3-66d5-48fc-958a-70cf4ec25472
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1116483321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1116483321
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1345886486
Short name T40
Test name
Test status
Simulation time 30610934 ps
CPU time 0.38 seconds
Started Dec 27 12:40:27 PM PST 23
Finished Dec 27 12:41:23 PM PST 23
Peak memory 145608 kb
Host smart-fe65b169-b11d-4122-944b-13a8e94cf8a6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1345886486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1345886486
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2655625821
Short name T37
Test name
Test status
Simulation time 30152254 ps
CPU time 0.39 seconds
Started Dec 27 12:40:27 PM PST 23
Finished Dec 27 12:41:23 PM PST 23
Peak memory 145500 kb
Host smart-0afe391c-b99f-48b7-ab4e-a62fb538790f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2655625821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2655625821
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1545683543
Short name T51
Test name
Test status
Simulation time 30427337 ps
CPU time 0.38 seconds
Started Dec 27 12:40:28 PM PST 23
Finished Dec 27 12:41:24 PM PST 23
Peak memory 145500 kb
Host smart-47c8bc42-be95-43ae-8cac-ced643d63172
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1545683543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1545683543
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1557983685
Short name T49
Test name
Test status
Simulation time 30411058 ps
CPU time 0.41 seconds
Started Dec 27 12:40:40 PM PST 23
Finished Dec 27 12:41:42 PM PST 23
Peak memory 145516 kb
Host smart-6cc08d83-6625-49d2-8767-c35ff18efb1e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1557983685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1557983685
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1757599877
Short name T47
Test name
Test status
Simulation time 29002626 ps
CPU time 0.4 seconds
Started Dec 27 12:40:28 PM PST 23
Finished Dec 27 12:41:24 PM PST 23
Peak memory 145464 kb
Host smart-0c6eb316-2882-4f7d-8f30-a952da8ba298
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1757599877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1757599877
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.410467333
Short name T16
Test name
Test status
Simulation time 31240890 ps
CPU time 0.4 seconds
Started Dec 27 12:40:28 PM PST 23
Finished Dec 27 12:41:24 PM PST 23
Peak memory 145432 kb
Host smart-2a546b7e-d51d-4472-ac5b-3d9d748a879c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=410467333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.410467333
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.164345657
Short name T48
Test name
Test status
Simulation time 30164985 ps
CPU time 0.39 seconds
Started Dec 27 12:40:21 PM PST 23
Finished Dec 27 12:41:15 PM PST 23
Peak memory 145524 kb
Host smart-5cb8f915-757e-4c4f-8cd3-4e0e8df67f95
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=164345657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.164345657
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1687847065
Short name T52
Test name
Test status
Simulation time 30942317 ps
CPU time 0.4 seconds
Started Dec 27 12:40:46 PM PST 23
Finished Dec 27 12:41:48 PM PST 23
Peak memory 145544 kb
Host smart-79943f08-23a2-4983-aeb5-0a13e508d05e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1687847065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1687847065
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3451079139
Short name T39
Test name
Test status
Simulation time 29439744 ps
CPU time 0.38 seconds
Started Dec 27 12:40:27 PM PST 23
Finished Dec 27 12:41:23 PM PST 23
Peak memory 145480 kb
Host smart-08699a75-9451-41e7-8e32-cfafdc6c5754
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3451079139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3451079139
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.969930225
Short name T41
Test name
Test status
Simulation time 29859476 ps
CPU time 0.39 seconds
Started Dec 27 12:40:29 PM PST 23
Finished Dec 27 12:41:26 PM PST 23
Peak memory 145540 kb
Host smart-ed2db608-0e5f-4441-bcc3-fbca35ebba33
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=969930225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.969930225
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4186128617
Short name T53
Test name
Test status
Simulation time 28960905 ps
CPU time 0.39 seconds
Started Dec 27 12:40:41 PM PST 23
Finished Dec 27 12:41:42 PM PST 23
Peak memory 145476 kb
Host smart-2d70309e-f610-481c-8236-054729d2753e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4186128617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.4186128617
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.386730299
Short name T55
Test name
Test status
Simulation time 10224076 ps
CPU time 0.37 seconds
Started Dec 27 12:31:51 PM PST 23
Finished Dec 27 12:32:37 PM PST 23
Peak memory 144568 kb
Host smart-cf38d572-c47a-45b0-816e-490f0abeda65
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=386730299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.386730299
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1161765607
Short name T36
Test name
Test status
Simulation time 9324753 ps
CPU time 0.37 seconds
Started Dec 27 12:29:19 PM PST 23
Finished Dec 27 12:30:14 PM PST 23
Peak memory 144960 kb
Host smart-db437752-cd9e-4181-b4cb-8d9f1e60e1c5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1161765607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1161765607
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.80430619
Short name T30
Test name
Test status
Simulation time 8257779 ps
CPU time 0.38 seconds
Started Dec 27 12:29:08 PM PST 23
Finished Dec 27 12:30:03 PM PST 23
Peak memory 145000 kb
Host smart-90b094f7-77e7-4428-9a20-c0ea5577956a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=80430619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.80430619
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.2783251800
Short name T34
Test name
Test status
Simulation time 9082979 ps
CPU time 0.37 seconds
Started Dec 27 12:29:22 PM PST 23
Finished Dec 27 12:30:17 PM PST 23
Peak memory 144952 kb
Host smart-41d8419a-d231-4f84-b4bc-a09b9236efc6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2783251800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2783251800
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.86602066
Short name T29
Test name
Test status
Simulation time 10015110 ps
CPU time 0.37 seconds
Started Dec 27 12:29:21 PM PST 23
Finished Dec 27 12:30:17 PM PST 23
Peak memory 144992 kb
Host smart-74534361-42ed-4e35-ac32-987c979b73a9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=86602066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.86602066
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.19914934
Short name T57
Test name
Test status
Simulation time 9288648 ps
CPU time 0.36 seconds
Started Dec 27 12:29:54 PM PST 23
Finished Dec 27 12:30:46 PM PST 23
Peak memory 144928 kb
Host smart-d335922c-0691-4ca9-9432-96c66fe435d8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=19914934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.19914934
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.1407713198
Short name T31
Test name
Test status
Simulation time 9546520 ps
CPU time 0.37 seconds
Started Dec 27 12:29:55 PM PST 23
Finished Dec 27 12:30:48 PM PST 23
Peak memory 144936 kb
Host smart-47d26afc-522c-43df-b0d3-fbadd9738f8d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1407713198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1407713198
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.1915994817
Short name T32
Test name
Test status
Simulation time 8770472 ps
CPU time 0.37 seconds
Started Dec 27 12:29:47 PM PST 23
Finished Dec 27 12:30:39 PM PST 23
Peak memory 144844 kb
Host smart-97c501ab-0769-40fe-a6ae-93f9c87e6fed
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1915994817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1915994817
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.2737883647
Short name T61
Test name
Test status
Simulation time 9007947 ps
CPU time 0.38 seconds
Started Dec 27 12:29:23 PM PST 23
Finished Dec 27 12:30:18 PM PST 23
Peak memory 144976 kb
Host smart-74135596-24c8-4db2-86a6-ed279f617e89
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2737883647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2737883647
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.3601296656
Short name T28
Test name
Test status
Simulation time 9338715 ps
CPU time 0.37 seconds
Started Dec 27 12:29:46 PM PST 23
Finished Dec 27 12:30:39 PM PST 23
Peak memory 144924 kb
Host smart-506200c7-0e17-4311-869b-40fb9c03e323
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3601296656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3601296656
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.549744836
Short name T35
Test name
Test status
Simulation time 7390897 ps
CPU time 0.37 seconds
Started Dec 27 12:29:34 PM PST 23
Finished Dec 27 12:30:32 PM PST 23
Peak memory 144904 kb
Host smart-886dcc32-7dc0-4190-8850-d4825489f697
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=549744836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.549744836
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3431682192
Short name T58
Test name
Test status
Simulation time 10142407 ps
CPU time 0.36 seconds
Started Dec 27 12:29:12 PM PST 23
Finished Dec 27 12:30:06 PM PST 23
Peak memory 144880 kb
Host smart-f4a29380-bb16-4f6b-8fc8-145312c6e2cc
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3431682192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3431682192
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.882405660
Short name T62
Test name
Test status
Simulation time 10115317 ps
CPU time 0.38 seconds
Started Dec 27 12:29:24 PM PST 23
Finished Dec 27 12:30:19 PM PST 23
Peak memory 145008 kb
Host smart-c487504b-dfb3-46ed-8b1e-f5764f2d9db2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=882405660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.882405660
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3173631193
Short name T59
Test name
Test status
Simulation time 8941688 ps
CPU time 0.36 seconds
Started Dec 27 12:31:54 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 144584 kb
Host smart-0a148cb8-3fec-4373-844f-b47cc570d74a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3173631193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3173631193
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1645639492
Short name T17
Test name
Test status
Simulation time 10431048 ps
CPU time 0.38 seconds
Started Dec 27 12:29:14 PM PST 23
Finished Dec 27 12:30:09 PM PST 23
Peak memory 144988 kb
Host smart-387e10ff-a259-4a01-b511-1297c4b53cec
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1645639492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1645639492
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1877901011
Short name T54
Test name
Test status
Simulation time 8537077 ps
CPU time 0.36 seconds
Started Dec 27 12:31:54 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 144564 kb
Host smart-30cbde29-bc8f-42e6-aa83-aad2447d3a78
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1877901011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1877901011
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.2105452416
Short name T56
Test name
Test status
Simulation time 9639809 ps
CPU time 0.37 seconds
Started Dec 27 12:31:57 PM PST 23
Finished Dec 27 12:32:43 PM PST 23
Peak memory 144584 kb
Host smart-de2a423c-fd60-45c5-9a3d-54052e130032
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2105452416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2105452416
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1449283376
Short name T60
Test name
Test status
Simulation time 9872512 ps
CPU time 0.37 seconds
Started Dec 27 12:29:23 PM PST 23
Finished Dec 27 12:30:19 PM PST 23
Peak memory 144856 kb
Host smart-44497a56-5914-4fda-bc86-49f093bb7e2d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1449283376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1449283376
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1204727154
Short name T76
Test name
Test status
Simulation time 27128740 ps
CPU time 0.38 seconds
Started Dec 27 12:29:40 PM PST 23
Finished Dec 27 12:30:34 PM PST 23
Peak memory 144932 kb
Host smart-171dceb8-96d9-42a4-8e0e-03b083cfdff6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1204727154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1204727154
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2955344280
Short name T72
Test name
Test status
Simulation time 27576911 ps
CPU time 0.39 seconds
Started Dec 27 12:30:28 PM PST 23
Finished Dec 27 12:31:25 PM PST 23
Peak memory 144944 kb
Host smart-9903164d-efa9-4983-9164-e5c2d9be7f58
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2955344280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2955344280
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2815170062
Short name T67
Test name
Test status
Simulation time 27724879 ps
CPU time 0.4 seconds
Started Dec 27 12:31:45 PM PST 23
Finished Dec 27 12:32:34 PM PST 23
Peak memory 144580 kb
Host smart-1f68f380-2b5c-4c20-896c-21fe0af6aed4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2815170062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2815170062
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4024409456
Short name T6
Test name
Test status
Simulation time 24833945 ps
CPU time 0.38 seconds
Started Dec 27 12:29:13 PM PST 23
Finished Dec 27 12:30:08 PM PST 23
Peak memory 144908 kb
Host smart-69d2d329-ce64-4bff-9acd-924e3ca9bff7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4024409456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.4024409456
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2731130971
Short name T63
Test name
Test status
Simulation time 28169667 ps
CPU time 0.41 seconds
Started Dec 27 12:30:20 PM PST 23
Finished Dec 27 12:31:16 PM PST 23
Peak memory 145048 kb
Host smart-60abfd68-109a-4116-b1c2-61e355478819
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2731130971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2731130971
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.561685143
Short name T69
Test name
Test status
Simulation time 29332094 ps
CPU time 0.4 seconds
Started Dec 27 12:30:17 PM PST 23
Finished Dec 27 12:31:12 PM PST 23
Peak memory 144936 kb
Host smart-50ca9070-0e6b-48e0-a17e-166a89d9ca88
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=561685143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.561685143
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2383246617
Short name T79
Test name
Test status
Simulation time 27523781 ps
CPU time 0.39 seconds
Started Dec 27 12:29:30 PM PST 23
Finished Dec 27 12:30:24 PM PST 23
Peak memory 144916 kb
Host smart-b36e74e6-1d8e-4f02-ad29-6cb8f7ef082a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2383246617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2383246617
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2482693020
Short name T5
Test name
Test status
Simulation time 26925954 ps
CPU time 0.43 seconds
Started Dec 27 12:32:18 PM PST 23
Finished Dec 27 12:33:02 PM PST 23
Peak memory 144848 kb
Host smart-96b89400-db12-4868-a7f4-71db55a41e74
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2482693020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2482693020
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2539970460
Short name T11
Test name
Test status
Simulation time 27622175 ps
CPU time 0.38 seconds
Started Dec 27 12:31:56 PM PST 23
Finished Dec 27 12:32:42 PM PST 23
Peak memory 144580 kb
Host smart-f3249534-6674-425a-8d3c-d72ca4f9213a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2539970460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2539970460
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3814180000
Short name T64
Test name
Test status
Simulation time 27536642 ps
CPU time 0.38 seconds
Started Dec 27 12:29:04 PM PST 23
Finished Dec 27 12:29:59 PM PST 23
Peak memory 145012 kb
Host smart-82a3faec-66f3-4dbb-93f1-46d6b59acd5b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3814180000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3814180000
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.685837636
Short name T68
Test name
Test status
Simulation time 26038927 ps
CPU time 0.39 seconds
Started Dec 27 12:29:20 PM PST 23
Finished Dec 27 12:30:16 PM PST 23
Peak memory 144912 kb
Host smart-af7843fb-b67b-4491-93d2-262875b0112f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=685837636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.685837636
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1851263574
Short name T78
Test name
Test status
Simulation time 29554095 ps
CPU time 0.39 seconds
Started Dec 27 12:30:50 PM PST 23
Finished Dec 27 12:31:44 PM PST 23
Peak memory 144880 kb
Host smart-0628e0d4-6fdc-4a93-af48-49752f47a8b7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1851263574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1851263574
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3092535609
Short name T77
Test name
Test status
Simulation time 26442033 ps
CPU time 0.39 seconds
Started Dec 27 12:29:05 PM PST 23
Finished Dec 27 12:29:59 PM PST 23
Peak memory 144912 kb
Host smart-e0a842b7-e05a-4709-83e7-8da6280cec2b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3092535609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3092535609
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3616457615
Short name T73
Test name
Test status
Simulation time 26224411 ps
CPU time 0.39 seconds
Started Dec 27 12:30:33 PM PST 23
Finished Dec 27 12:31:30 PM PST 23
Peak memory 144876 kb
Host smart-432c1f11-254a-4fd3-87a0-59df8d170605
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3616457615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3616457615
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1791934949
Short name T74
Test name
Test status
Simulation time 29003411 ps
CPU time 0.39 seconds
Started Dec 27 12:31:10 PM PST 23
Finished Dec 27 12:31:59 PM PST 23
Peak memory 144952 kb
Host smart-cf6748ad-390d-4b16-b1d6-19f6d26c22c4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1791934949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1791934949
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4184495898
Short name T65
Test name
Test status
Simulation time 27422573 ps
CPU time 0.38 seconds
Started Dec 27 12:28:57 PM PST 23
Finished Dec 27 12:29:52 PM PST 23
Peak memory 144876 kb
Host smart-8d3e4cc7-5160-43d7-9ddd-be052671f47f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4184495898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.4184495898
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3254481700
Short name T75
Test name
Test status
Simulation time 26761322 ps
CPU time 0.37 seconds
Started Dec 27 12:32:07 PM PST 23
Finished Dec 27 12:32:52 PM PST 23
Peak memory 144584 kb
Host smart-e76b83af-76bd-48de-8a0f-d6e240c84da4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3254481700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3254481700
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2649023525
Short name T66
Test name
Test status
Simulation time 27509597 ps
CPU time 0.39 seconds
Started Dec 27 12:29:26 PM PST 23
Finished Dec 27 12:30:20 PM PST 23
Peak memory 144928 kb
Host smart-83b7d82f-0927-44a5-a33f-55145e1d550b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2649023525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2649023525
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1143122298
Short name T71
Test name
Test status
Simulation time 27218307 ps
CPU time 0.4 seconds
Started Dec 27 12:29:15 PM PST 23
Finished Dec 27 12:30:09 PM PST 23
Peak memory 144860 kb
Host smart-9b32f277-8100-4308-b90b-5a54adc3a1d1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1143122298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1143122298
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3819991259
Short name T70
Test name
Test status
Simulation time 28089407 ps
CPU time 0.46 seconds
Started Dec 27 12:31:23 PM PST 23
Finished Dec 27 12:32:14 PM PST 23
Peak memory 143756 kb
Host smart-f09c195d-bfe5-4389-90db-81e85e8ec6cf
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3819991259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3819991259
Directory /workspace/9.prim_sync_fatal_alert/latest
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